JP2013258543A - D/a converter and clock delay control circuit for use in the d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A converter that reduces the effect of noise on electronic components mounted on an electronic apparatus.SOLUTION: A sampling circuit 150 comprises a continuous section 150a for transmitting a continuous signal, a digital section for transmitting a sampled and quantized signal, and a sample-and-hold section 150b for transmitting a sampled and non-quantized signal. The sample-and-hold section 150b includes a plurality of capacitors for storing charges caused by an input signal, and a plurality of switches for storing charges in each of the capacitors, respectively. The D/A converter further includes a clock delay control circuit for controlling a delay generated by a clock delay conversion section for generating a plurality of clock signals different in operation timing from each other from a second clock signal for driving at least the plurality of switches.

Description

  The present invention relates to a D / A converter and a clock delay control circuit used for the D / A converter, and more specifically, D that can reduce the influence of noise received by an electronic component mounted on an electronic device. The present invention relates to a / A converter and a clock delay control circuit used for the D / A converter.

  Currently, the demand for downsizing of electronic devices is increasing, electronic parts mounted on electronic devices are downsized, and electronic parts are arranged closer to each other. If electronic components are arranged close to each other, noise generated in the electronic components may be transmitted to other electronic components directly or via a mounting board or wiring, and may interfere with normal operation of the other electronic components. For this reason, recent electronic devices are required to be reduced in size and to suppress the influence of noise (hereinafter also referred to as noise countermeasures).

In order to prevent the noise generated by electronic components from affecting other electronic components, it is generally necessary to place electronic components apart so that the effect of noise is reduced, or when manufacturing electronic components. In the process, it is conceivable to devise arrangement and separation of elements. It is also conceivable to provide input / output terminals separately for each electronic component.
However, it is not preferable to dispose the electronic components apart from each other in order to prevent downsizing of the electronic device described above. Further, in order to prevent noise from affecting the outside due to the process of the electronic component, an advanced process technique is required, which is not preferable because the manufacturing cost increases. Further, separating the input terminal and output terminal of the electronic component is disadvantageous in reducing the size of the electronic component due to the increase in the number of pins of the electronic device.

Incidentally, there is a D / A converter as an electronic component mounted on an electronic device. The D / A converter is an electronic component that is often used for an audio function of an electronic device, and particularly an electronic component that requires countermeasures against noise.
As a conventional technique for noise suppression of a D / A converter, for example, there is one described in Patent Document 1. The device described in Patent Document 1 adds jitter to a synchronization signal (control clock signal) of an input signal of a D / A converter. According to such a D / A converter described in Patent Document 1, the radiation of beat noise caused by the synchronization signal (conversion clock signal) for outputting the output signal and the control clock signal is diffused. Is possible.

  Such prior art is based on the idea of reducing radiation noise generated by a D / A converter and reducing the influence of noise on other devices.

JP 62-6536 A

However, as in the prior art, even if the radiation noise generated by the D / A converter is reduced, the influence of noise generated from outside the D / A converter on the D / A converter is sufficiently reduced. Can not.
Further, since the prior art adds jitter only to the digital part, it is not possible to diffuse periodic noise caused by the inrush current of the analog part. For this reason, the diffusion effect of the prior art is limited.

  In order to reduce the influence of radiation noise generated by individual electronic components directly or indirectly on the D / A converter using the conventional technology, a plurality of other components mounted in the electronic device are used. A circuit for inputting jitter must be provided for these components. In such a configuration, it is necessary to provide a large number of circuits for inputting jitter, and it is considered that miniaturization of electronic devices is hindered.

  The present invention has been made in view of such a problem, and an object of the present invention is to be mounted on an electronic device while preventing downsizing of electronic components and avoiding advancement of process technology. An object of the present invention is to provide a D / A converter and a clock delay control circuit used for the D / A converter that can reduce the influence of noise applied to an electronic component.

The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to a digital part (150c in FIG. 11) for inputting a digital signal and a digital part inputted by the digital part. A sample and hold unit (150b in FIG. 10) that samples an input signal based on the signal, holds and transfers the sampled input signal, and outputs the signal transferred by the sample and hold unit as an analog signal A sampling circuit (150 in FIGS. 10 and 11) having a continuous unit (150a in FIG. 10), a first clock signal is supplied to the continuous unit, and a first clock signal is supplied to the sample and hold unit. A clock signal supply unit (159 in FIGS. 10 and 11) that supplies two clock signals and at least the second clock signal. A clock delay conversion unit (141 in FIG. 11) that generates a plurality of clock signals having different operation timings, and a clock delay control circuit (171 in FIG. 11) that controls a delay amount generated by the clock delay conversion unit, The sample and hold unit includes a plurality of capacitive elements (111_1 and 111_2 in FIG. 10) for accumulating charges generated by the input signal, and transfers the charges accumulated in the plurality of capacitive elements to the continuous unit, respectively. And a plurality of switching elements (101_1, 101_2, 102_1, 102_2). (Fig. 10)
According to a second aspect of the present invention, in the first aspect of the present invention, the clock delay control circuit uses the frequency characteristics of the input signal supplied to the sample and hold unit to change the sampled input signal. A detector (170 in FIG. 11) that detects the peak frequency of the mixed noise has a peak, and a delay amount converter (in FIG. 11) that converts the peak frequency of the noise detected by the detector into an arbitrary delay amount. 141).

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the sample and hold unit includes a plurality of capacitive elements that accumulate charges generated by the input signal, and the plurality of capacitive elements. A plurality of switching elements for transferring the accumulated charges to the continuous unit, and the plurality of switching elements are turned on / off based on the plurality of second clock signals supplied with different operation timings. It is characterized by doing.

  According to a fourth aspect of the present invention, there is provided a clock delay control circuit (171) used in the D / A converter according to the first, second or third aspect, wherein the input is supplied to the sample and hold unit. From the frequency characteristics of the signal, a detector that detects the peak frequency of the noise mixed in the sampled input signal, and converts it to an arbitrary delay amount with respect to the peak frequency of the noise detected by the detector And a clock delay conversion unit (141).

  According to the present invention, a sampling circuit capable of reducing the influence of noise received by an electronic component mounted on an electronic device, a D / A converter provided with the sampling circuit, and the D / A converter are used. A clock delay control circuit can be realized. Such an effect is obtained by operating the continuous unit based on the first clock signal operating at a single operation timing, and the sample hold unit based on the second clock signal group having two or more different operation timings. Therefore, downsizing of electronic components is not hindered. Moreover, it is not necessary to upgrade process technology.

Moreover, since the radiation noise resulting from the inrush current of the analog part can be diffused, the radiation noise can be effectively suppressed.
Furthermore, by matching the zero point of the FIR filter obtained by the sampling operation with a plurality of operation timings in the sample and hold unit to the noise frequency peak detected by the detector, the noise can be effectively suppressed and the desired frequency can be suppressed. Optimal characteristics can be obtained in a band (for example, in-band band).

It is a circuit block diagram for demonstrating the sampling circuit in the D / A converter which concerns on this invention. (A)-(e) is a figure for demonstrating operation | movement when there is no periodic noise in the reference signal Vref of the sampling circuit shown in FIG. (A)-(c) is a figure for demonstrating the signal output from the capacitor shown in FIG. (A)-(e) is a figure for demonstrating operation | movement when there exists periodic noise in the reference signal Vref of the sampling circuit shown in FIG. (A)-(c) is a figure for demonstrating the periodic noise shown in FIG. (A)-(c) is a figure for demonstrating the signal output from the capacitor shown to Fig.5 (a). (A)-(e) is a figure for demonstrating operation | movement when there exists periodic noise in the reference signal Vref of the sampling circuit shown in FIG. (A)-(c) is a figure for demonstrating the relationship between the noise and frequency in the sampling circuit which concerns on this invention. (A)-(c) is a figure for demonstrating further the signal shown to Fig.8 (a). It is a circuit block diagram for demonstrating one Embodiment of the D / A converter which concerns on this invention. It is a functional block diagram of a D / A converter concerning the present invention. It is a circuit block diagram for demonstrating the clock delay control circuit shown in FIG. FIG. 13 is a circuit diagram of a transistor level as an example of the delay element illustrated in FIG. 12. It is a circuit block diagram which shows an example of the delay controller shown in FIG.

Prior to the description of the embodiments of the present invention, first, the concept of the sampling circuit constituting the present invention will be described. In the following description, a D / A converter using a sampling circuit is taken as an example.
Hereinafter, the digital unit is composed of a general digital circuit, and means that a quantized and sampled signal is transmitted. The sample and hold unit is composed of a general switched capacitor circuit (SC circuit), and means that a sampled signal is transmitted without being quantized. The continuous part is composed of a general continuous signal circuit (continuous circuit; continuous circuit), and means that a signal that is not quantized and is not sampled is transmitted.

Note that the above-mentioned “transmission” of a signal means that the signal is output to another circuit. In this specification, sampling means so-called sampling processing in which continuous signals (analog signals) are divided in time, and quantization means processing in which signals are divided by amplitude values.
FIG. 1 is a circuit configuration diagram for explaining a sampling circuit in a D / A converter according to the present invention. The sampling circuit 150 includes a digital unit 150c (see FIG. 11), a sample / hold unit 150b, and a continuous unit 150a. The digital unit 150c is configured by a general digital circuit and transmits a quantized and sampled signal. The sample and hold unit 150b is configured by a general switched capacitor circuit (SC circuit), and is configured to transmit a sampled signal without being quantized. The continuous unit 150a is configured by a general continuous signal circuit (Continuous circuit), and transmits a signal that is not quantized and is not sampled.

In FIG. 1, the digital unit 150c that handles a digital signal is not shown in the configuration described above, and a continuous unit 150a and a sample / hold unit 150b are shown. The digital unit 150c is provided further upstream of the sample and hold unit 150b shown in FIG.
The sample and hold unit 150b includes switches 101_1, 101_2, 102_1, and 102_2, and capacitors 111_1 and 111_2. The switch 101_1, the capacitor 111_1, and the switch 102_1 are connected in series, and the switch 101_2, the capacitor 111_2, and the switch 102_2 are connected in series. The switches 101_1 and 101_2 constitute the switch unit 101, and the switches 102_1 and 102_2 constitute the switch unit 102.

  The continuous portion 150a includes a switch 104_1 connected in series with the capacitor 111_1, a switch 104_2 connected in series with the capacitor 111_2, an operational amplifier 121 connected to one end of the switches 104_1 and 104_2, and an operational amplifier 121. , The switch 103_1 connected between the switch 101_1 and the capacitor 111_1, the output terminal of the operational amplifier 121 and the switch 103_2 connected between the switch 101_2 and the capacitor 111_2, and the output terminal of the operational amplifier 121 and the inverting input. And a capacitor 112 connected between the terminals. The switches 103_1 and 103_2 constitute the switch unit 103, and the switches 104_1 and 104_2 constitute the switch unit 104.

  By including the capacitor 112, an LPF (Low-pass filter) is formed in the continuous portion 150a, and the cutoff frequency of the LPF is determined by the capacitance ratio of the capacitor 112 and the capacitors 111_1 and 111_2 and the switching frequency. Such a capacitor 112 is not an essential component for the sampling circuit according to the present invention.

The sampling circuit 150 includes a capacitor 113. The capacitor 113 accumulates the charge generated by the analog output signal Aout on the feedback paths 158_1 and 158_2 for inputting the analog output signal Aout of the operational amplifier 121 to the inverting input terminal.
The output terminal of the operational amplifier 121 is connected to the terminal 106, and the analog signal VAout is output from the terminal 106. A reference signal Vcom1 using a common mode voltage is supplied to the non-inverting input terminal and the inverting input terminal of the operational amplifier 121 directly or via the switches 102_1, 102_2, 104_1, and 104_2.

Further, in the sampling circuit 150 shown in FIG. 1, the sample-and-hold unit 150b and the continuous unit 150a share the capacitors 111_1 and 111_2. That is, the capacitors 111_1 and 111_2 function as both the sample and hold unit 150b and the continuous unit 150a.
The reference signal Vref is input from the terminal 105 to the sampling circuit 150 described above. The reference signal Vref is sampled by the switches 101_1 and 102_1. Charges are accumulated in the capacitor 111_1 by sampling. Further, the reference signal Vref is sampled by the switches 101_2 and 102_2, and charges are accumulated in the capacitor 111_2. The reference signal Vref sampled by the switches 101_1, 101_2, 102_2, and 102_2 is referred to as an input signal Vin.

The charges accumulated in the capacitors 111_1 and 111_2 are input to the inverting input terminal of the operational amplifier 121 in accordance with switching of the switches 101_1, 102_1, and 104_1, and 101_2, 102_2, and 104_2. The operational amplifier 121 receives the reference voltage signal Vcom1 from the non-inverting input terminal and outputs an analog output signal VAout.
In the sampling circuit 150 shown in FIG. 1 described above, a plurality (two in the example shown in FIG. 1) of capacitors 111_1 and 111_2 of the sample and hold unit 150b are provided. The number of switches included in the switch units 103 and 104 of the continuous unit 150a corresponds to the number of capacitors 111_1 and 111_2. The amount of charge accumulated in the capacitor 111_1 is determined by the switches 103_1 and 104_1. Further, the amount of charge accumulated in the capacitor 111_2 is determined by the switches 103_2 and 104_2.

Note that the number of capacitors 111_1 and 111_2 in the sample and hold unit 150b is not limited to two as a matter of course, and may be a natural number M. At this time, each of the switch units 103 and 104 of the continuous unit 150a includes M switches.
In the sampling circuit 150 shown in FIG. 1, as the number M of capacitors 111_1 and 111_2 increases, the number of switches included in the switch units 103 and 104 similarly increases. When the number of capacitors 111_1 and 111_2 is increased, the configuration of the continuous unit 150a is not changed from the configuration illustrated in FIG. 1 except that the number of switches included in the switch units 103 and 104 is increased.

  In the sampling circuit 150 shown in FIG. 1, as the number M of the capacitors 111_1 and 111_2 increases, the number of switches included in the switch units 101 and 102 increases in the same manner. When the number of capacitors 111_1 and 111_2 increases, the configuration of the sample and hold unit 150b may be changed from the configuration illustrated in FIG. 1 except that the number of switches included in the switch units 101 and 102 increases. Absent.

  Further, when a capacitor is further added to the continuous unit 150a illustrated in FIG. 1, the total capacitance of the added capacitor is made equal to the total capacitance of the capacitors 111_1 and 111_2. By doing so, an analog FIR (Finite Impulse Response) filter is formed that appropriately distributes the magnitude of the capacitors 111_1 and 111_2 and the operation timing and lowers the gain of a specific frequency included in the output signal VAout. be able to.

  Further, the switch 101_1 and the switch 101_2 are driven by different clock signals, and the switch 102_1 and the switch 102_2 are driven by different clock signals. Further, the switches 103_1 and 103_2 and the switches 104_1 and 104_2 are driven by a clock signal φI different from any of the switches 101_1 and 101_2.

Hereinafter, the operation of the circuit configuration shown in FIG. 1 will be described. That is, even when periodic noise (noise caused by an inrush current to a circuit that processes an analog signal: hereinafter, also simply referred to as noise) is superimposed on the input signal, the sampling circuit 150 shown in FIG. A description will be given of obtaining an effect of reducing noise generated by the used D / A converter.
In the following description, in order to facilitate understanding of the effect of the present embodiment, first, the switch 101_1 and the switch 101_2 of the sampling circuit 150 illustrated in FIG. 1 are driven by the clock signals of the same timing, and the switch 102_1 and the switch 102_2 Are driven by the same timing clock signal, the switch 103_1 and the switch 103_2 are driven by the same timing clock signal, and the switch 104_1 and the switch 104_2 are driven by the same timing clock signal (hereinafter referred to as “general clock signal The case of “driving” will be described.

Hereinafter, the output signal VAout when the sampling circuit 150 shown in FIG. 1 is driven by a general clock signal is used when the periodic noise is not superimposed on the reference signal Vref and when the periodic noise is superimposed. This will be explained separately.
In the sampling circuit 150 shown in FIG. 1, when periodic noise is superimposed on the reference signal Vref and the reference signal Vcom1, the periodic noise appears in the output waveform with a gain of 0 dB, so that the sampling circuit 150 has the highest sensitivity to noise. . In the present embodiment, a case where periodic noise is superimposed on the reference signal Vref will be described, but the same consideration can be applied even when periodic noise is superimposed on other than the reference signal Vref. An example of a signal in which periodic noise is superimposed in addition to the reference signal Vref is the reference signal Vcom1. As the noise mixing path, a sampling operation path can be considered, and the path is not limited to the reference signal Vref and the reference signal Vcom1.

(I) When Periodic Noise is not Overlaid FIGS. 2A to 2E are diagrams for explaining the operation of the sampling circuit shown in FIG. 1 when there is no periodic noise in the reference signal Vref. FIG. 3 is a diagram for explaining the operation of the sampling circuit 150 shown in FIG. 1 when there is no periodic noise in the reference signal Vref. FIG. 2A shows a clock signal φS1 for driving the switch 101_1 and the switch 102_1. The clock signal φS1 coincides with the sampling timing of the reference signal Vref in the capacitor 111_1. FIG. 2B shows a clock signal φS2 that drives the switch 101_2 and the switch 102_2. The clock signal φS2 coincides with the sampling timing of the reference signal Vref in the capacitor 111_2. Since the clock signal φS1 and the clock signal φS2 illustrated in FIG. 2 are equal, in the sampling circuit 150 illustrated in FIG. 1, the capacitor 111_1 and the capacitor 111_2 operate at the same timing.

  FIG. 2C shows a clock signal φI that drives the switches included in the switch units 103 and 104. The clock signal φI coincides with the timing at which the capacitors 111_1 and 111_2 hold and release charges accumulated by the input signal Vin, respectively. The clock signal φI is a non-overlapping signal that does not simultaneously become High (hereinafter referred to as H) with any of the clock signals φS1 and φS2.

  FIG. 2D shows the reference signal Vref which is a DC voltage, and FIG. 2E shows the output signal VAout which is an analog signal output from the operational amplifier 121. In FIG. 2E, the signal indicated by the solid line is the input signal Vin generated by the charges transferred from the capacitors 111_1 and 111_2, and the sampling circuit 150 generates the output signal VAout indicated by the broken line by feedback. The

  3A to 3C are diagrams for explaining signals output from the capacitor shown in FIG. The graph shown in FIG. 3A is a diagram for explaining signals output from the capacitors 111_1 and 111_2 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 3B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitors 111_1 and 111_2 hold and discharge the charges accumulated by the input signal Vin into the frequency axis by Fourier transformation. The graph shown in FIG. 3C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 3A to 3C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by the arrow in the graphs of FIGS. 3A to 3C indicates the frequency reference (“0”).

  As shown in FIG. 3, the signals output from the capacitors 111_1 and 111_2 (indicated by spectrum p in the figure) have a constant frequency. The spectrum q shows the noise shaped floor noise in the input signal Vin. When the spectra p and q are sampled, held, and emitted by the switches 101_1 and 102_1 and 101_2 and 102_2, respectively, the output signal VAout shown in FIG. 3C is generated by convolution. In the output signal VAout, the spectra p and q are mirrored symmetrically.

(Ii) Case where periodic noise is superimposed Next, a case where periodic noise is present in the reference signal Vref will be described. Even in this case, the switches 101_1 and 101_2 are driven by clock signals having the same timing, the switches 102_1 and 102_2 are driven by clock signals having the same timing, and the switches 103_1 and 103_2 are driven by clock signals having the same timing. The switches 104_1 and 104_2 are driven by clock signals having the same timing.

4A to 4E are diagrams for explaining the operation of the sampling circuit shown in FIG. 1 when there is periodic noise in the reference signal Vref. In the sampling circuit 150 shown in FIG. It is a figure for demonstrating operation | movement of a D / A converter when there exists periodic noise in the signal Vref.
FIG. 4A shows the sampling timing of the reference signal Vref in the capacitor 111_1. FIG. 4B shows the sampling timing of the reference signal Vref in the capacitor 111_2. FIG. 4C shows the timing at which the capacitors 111_1 and 111_2 hold and release the charges accumulated by the reference signal Vref, respectively. FIG. 4D shows the reference signal Vref which is a DC voltage. e) shows an output signal VAout that is an analog signal output from the operational amplifier 121. Here, FIG. 4A and FIG. 4B operate at the same timing. As is clear from FIGS. 4D and 4E, when the periodic noise N1 is superimposed on the reference signal Vref shown in FIG. 4D, the D / A converter adds the output signal VAout to the output signal VAout. In this case, the periodic noise N2 corresponding to the periodic noise N1 is generated. Next, the periodic noise shown in FIGS. 4 (d) and 4 (e) will be described with reference to FIGS. 5 (a) to 5 (c).

  5A to 5C are diagrams for explaining the periodic noise shown in FIG. 4, and the graph shown in FIG. 5A is output from the capacitors 111_1 and 111_2 shown in FIG. It is a figure for demonstrating a signal, and shows the spectrum which converted the input signal Vin into the frequency axis by Fourier transformation. The graph shown in FIG. 5B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitors 111_1 and 111_2 hold and discharge the charges accumulated by the input signal Vin into the frequency axis by Fourier transformation, respectively. The graph shown in c) shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 5A to 5C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow line in the graphs of FIGS. 5A to 5C indicates the frequency reference (“0”).

  When the spectrum shown in FIG. 5A is sampled, held, and emitted by the switches 101_1, 102_1, 101_2, and 102_2 shown in FIG. 1, the periodic noise N2 is folded, and the periodic noise N2 ′ is near DC. appear. Then, as shown in the graph of FIG. 5C, the periodic noise N2 'is mirrored symmetrically by convolution to generate the output signal VAout. When the D / A converter is used in an audio device, for example, the periodic noise N2 'appears in a frequency region (hereinafter also referred to as in-band) used for output sound.

In the present embodiment, by providing a plurality of different clock signals for operating a device such as a sampling circuit, periodic noise appearing in the in-band is diffused by a signal output from another device, and a signal of an output signal such as sound This is based on the technical idea of preventing the quality from being impaired.
FIGS. 6A to 6C are diagrams for explaining signals output from the capacitor shown in FIG. Here, signals output from the capacitors 111_1 and 111_2 shown in FIG. 5A will be further described with reference to FIGS. The graph shown in FIG. 6A is a frequency characteristic of the reference signal Vref shown in FIG. 4D, and shows a spectrum obtained by converting Vref superimposed with periodic noise into the frequency axis by Fourier transform. The frequency indicated by the broken line in FIG. 6A represents the Nyquist frequency, which is half the sampling operation frequency. The graph shown in FIG. 6B shows a spectrum in which the capacitors 111_1 and 111_2 store the input signal Vin and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency f1 indicated by a broken line in FIG. 6B represents a Nyquist frequency, which is half the sampling operation frequency. The frequency characteristic (F characteristic) indicated by the broken line Lb1 in FIG. 6B is the frequency characteristic of the FIR filter obtained by the sampling operation.

  Here, since the sampling operation is performed by one clock signal, the frequency characteristic of the FIR filter is an all-pass filter (no gain suppression effect for all frequencies). The graph shown in FIG. 6C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 6A to 6C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by an arrow in the graphs of FIGS. 6A to 6C indicates the frequency reference (“0”).

As shown in FIG. 6C, the filter effect by the FIR filter cannot be obtained in the sampling operation of the capacitors 111_1 and 111_2 in FIG. For this reason, the spectrum of the periodic noise N2 is folded as it is to become the periodic noise N2 ′.
The present embodiment has been made paying attention to the fact that in-band signal quality can be improved by dispersing the above-described periodic noise N2 ′. For this reason, the sample and hold unit of the sampling circuit 150 is operated by a plurality of clock signals. Hereinafter, a plurality of clock signals of this embodiment will be described.

  FIGS. 7A to 7E are diagrams for explaining the operation in the sampling circuit 150 shown in FIG. 1 when the reference signal Vref has periodic noise. FIG. 7A shows the clock signal φS3 input to the switches 101_1 and 102_1 of the sampling circuit 150 shown in FIG. The clock signal φS3 is equal to the sampling timing of the reference signal Vref in the capacitor 111_1. FIG. 7B shows the clock signal φS4 input to the switches 101_2 and 102_2 of the sampling circuit 150 shown in FIG. The clock signal φS4 is equal to the sampling timing of the reference signal Vref in the capacitor 111_2.

FIG. 7C shows the timing at which the capacitors 111_1 and 111_2 hold and release the charges accumulated by the reference signal Vref, and FIG. 7D shows the reference signal Vref which is a DC voltage. 7 (e) shows an output signal VAout that is an analog signal output from the operational amplifier 121.
In the present embodiment, as shown in FIGS. 7A and 7B, the clock signal φS3 and the clock signal φS4 are switched from H to Low (hereinafter referred to as L) or from L to H at different timings. This timing difference occurs when the clock signal φS4 is switched with a delay from the clock signal φ3. In the present embodiment, the delay amount T of the clock signal φS4 with respect to the clock signal φS3 is 10 ns. As a matter of course, the delay amount of the clock signal φS4 of the present embodiment is not limited to 10 ns, and can be set arbitrarily.

  When the periodic noise N1 shown in FIG. 7D is superimposed on the reference signal Vref, in the D / A converter using the sampling circuit 150 according to the present invention, the output signal VAout also has a period corresponding to the periodic noise N1. Noise N3 is superimposed. However, since the sampling circuit 150 is driven by the clock signal φS3 and the clock signal φS4 that is delayed with respect to the clock signal φS3, the sampling circuit 150 has two sampling timings. Therefore, as apparent from comparison with the periodic noise N2 in FIG. 4, the periodic noise N3 is averaged and its value is suppressed.

  FIGS. 8A to 8C are diagrams for explaining the relationship between noise and frequency in the sampling circuit according to the present invention, and for explaining the relationship between noise N3 and frequency in the sampling circuit according to the present invention. FIG. The graph shown in FIG. 8A is a diagram for explaining signals output from the capacitors 111_1 and 111_2 shown in FIG. 1, and shows a spectrum obtained by converting the input signal Vin into the frequency axis by Fourier transform. The graph shown in FIG. 8B shows a spectrum obtained by converting the clock signal that regulates the timing at which the capacitors 111_1 and 111_2 hold and discharge the charges accumulated by the input signal Vin into the frequency axis by Fourier transformation, respectively. The graph of c) shows the spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 8A to 8C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by the arrow in the graphs of FIGS. 8A to 8C indicates the frequency reference (“0”).

  As shown in FIG. 8A, since the sampling circuit 150 shown in FIG. 1 has a plurality of sampling timings of the sample and hold unit 150b, it can diffuse periodic noise caused by the inrush current of the analog unit. For this reason, in this embodiment, the peak of the spectrum of the periodic noise N3 can be made smaller than the peak of the spectrum of the periodic noise N2 shown in FIG.

  Also in this embodiment, the periodic noise N3 is folded back to generate the periodic noise N3 '. However, in the present embodiment having a plurality of sampling timings, the filter effect by the FIR filter is applied at the time of folding, and the spectrum of the periodic noise N3 'is further smaller than the spectrum of the periodic noise N3. From this, this embodiment can reduce the periodic noise which generate | occur | produces in in-band rather than the sampling circuit 150 which operate | moves with a general clock signal.

  9A to 9C are diagrams for further explaining the signals shown in FIG. The graph shown in FIG. 9A is a diagram showing the frequency characteristics of the noise N3 superimposed on the reference signal Vref shown in FIG. 7D, and Vref on which the periodic noise N3 is superimposed is obtained by Fourier transform. The spectrum converted to the frequency axis is shown. The frequency indicated by the broken line in FIG. 9A represents the Nyquist frequency, which is half the sampling operation frequency.

  The graph shown in FIG. 9B shows a spectrum in which the capacitors 111_1 and 111_2 store the input signal Vin and the clock signal that regulates the sampling timing is converted to the frequency axis by Fourier transform. A frequency f2 indicated by a broken line in FIG. 9B represents a Nyquist frequency, which is half the sampling operation frequency. The frequency characteristic indicated by the broken line Lb2 in FIG. 9B is the frequency characteristic of the FIR filter obtained by the sampling operation.

In the present embodiment, the sampling operation is performed by the clock signal φS4 having a delay of 10 ns with respect to the clock signal φ3 and the clock signal φS3. For this reason, the frequency characteristic fc of the FIR filter of this embodiment is represented by the following formula (1).
fc = 1 / (2 × T) + X / T (Hz) (1)
However, X in the formula (1) is an integer. Here, in this embodiment, the delay time T is 10 ns, so fc = 50 MHz + 100 × X MHz (in FIG. 9, only fc = 50 MHz which is a solution at X = 0) An FIR filter having a zero point is formed.

The graph shown in FIG. 9C shows a spectrum obtained by converting the output signal VAout to the frequency axis by Fourier transform. In any of the graphs shown in FIGS. 9A to 9C, the vertical axis indicates the intensity of the signal spectrum, and the horizontal axis indicates the frequency. The position of the vertical axis indicated by the arrow line in the graphs of FIGS. 9A to 9C indicates the frequency reference (“0”).
As shown in FIG. 9A, noise components are suppressed at the time of sampling by the filter effect by the FIR filter in the sampling operation to the capacitors 111_1 and 111_2 in FIG. 1, and the spectrum of the periodic noise N3 is attenuated and turned back, and the periodic noise N3 ′. It becomes.

  According to the present embodiment, since a filter effect is obtained in the modulation from the periodic noise N3 to the periodic noise N3 ′ shown in FIG. 8A, the D / A converter generates in-band. Periodic noise can be reduced. Such periodic noise is generated not only in the D / A converter but also in, for example, an A / D converter mounted on the same substrate as the D / A converter. For this reason, the sampling circuit 150 of this embodiment has a remarkable effect in reducing the periodic noise of the electronic component, particularly when applied to the electronic component in which the periodic noise affects the operation. Such an embodiment is advantageous in reducing the size and configuration of the electronic device.

Next, an embodiment of the present invention based on the above-described concept will be described.
FIG. 10 is a circuit configuration diagram for explaining an embodiment of the D / A converter according to the present invention, in which the sampling circuit 150 shown in FIG. 1 and a clock signal for driving the sampling circuit 150 are shown. A control circuit (clock signal supply unit) 159 that outputs φS3, φS4, and φI, and a detector 170 are shown. In FIG. 10, the same reference numerals are given to the same components as those shown in FIG. 1, and the description thereof is partially omitted.

  The sampling circuit 150 in the D / A converter of the present invention samples a digital part (150c in FIG. 11 described later) for inputting a digital signal and an input signal based on the digital signal input by the digital part, and performs sampling. A sample-and-hold unit 150b that holds and transfers the received input signal, and a continuous unit 150a that outputs the signal transferred by the sample-and-hold unit 150b as an analog signal.

The clock signal supply unit 159 supplies a first clock signal to the continuous unit 150a and a second clock signal to the sample and hold unit 150b.
The sample-and-hold unit 150b also includes a plurality of capacitor elements 111_1 and 111_2 that store charges generated by an input signal, and a plurality of switching units that transfer the charges stored in the plurality of capacitor elements 111_1 and 111_2, respectively, to the continuous unit 150a. The plurality of switching elements 101_1, 101_2, 102_1, and 102_2 are turned on / off based on a plurality of second clock signals supplied with different operation timings. .

That is, as described in FIG. 1, the sampling circuit 150 includes a digital unit (not shown), a continuous unit 150a, and a sample / hold unit 150b.
The control circuit 159 generates and outputs the clock signals φS3, φS4, and φI shown in FIGS. The clock signal φI is input to the continuous unit 150a, and the clock signal φS3 is input to the switches 101_1 and 102_1 of the sample and hold unit 150b. The clock signal φS4 is input to the switches 101_2 and 102_2 of the sample and hold unit 150b. The clock signals φS3, φS4, and φI all drive the switches so that the switches are turned on when they are H and the switches are turned off when they are L.

  The detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref, which is a noise mixing path, and matches the zero point of the FIR filter obtained by the sampling operation with a plurality of operation timings of the sample and hold unit 150b with the noise peak frequency. The control circuit 159 changes the amount of clock delay added. In the present embodiment, the configuration shown in FIG. 10 is configured as a semiconductor integrated circuit, but the detector 170 may be provided outside the semiconductor integrated circuit. When the detector 170 is provided outside the semiconductor generation circuit, the detector 170 is realized by, for example, a spectrum analyzer.

  FIG. 11 is a functional block diagram of a D / A converter (DAC) according to the present invention. As shown in FIG. 11, the D / A converter of this embodiment includes a digital part (referred to as a digital part in the figure) 150c, a sample / hold part (referred to as an S / H part in the figure) 150b, and a continuous part (shown in the figure). And a control circuit 159. The sampling circuit 150 includes 150a).

The clock delay conversion unit 141 generates a plurality of clock signals having different operation timings relative to at least the second clock signal. The clock delay control circuit 171 controls a delay amount generated by the clock delay conversion unit 141.
The clock delay control circuit 171 includes a detector 170 for detecting a peak frequency at which noise mixed in the sampled input signal has a peak, from the frequency characteristic of the input signal supplied to the sample and hold unit 150b, A delay amount conversion unit 141 that converts the peak frequency of the noise detected by the detector 170 into an arbitrary delay amount;

  The control circuit 159 includes a clock signal generation unit 143 that generates clock signals φS3 and φI, and a clock delay conversion unit that generates a clock signal φS4 delayed from the clock signal φS3 generated by the clock signal generation unit 143 (FIG. 11). 141) and clock signals φS3, φS4, φI are selected, the clock signals φS3, φS4 are selected and output to the sample and hold unit 150b, and the clock signal φI is selected and output to the continuous unit 150a And a clock signal selection unit 162 that performs the operation. The clock signal selection unit 162 may select one of the clock signals φS3, φS4, and φI and output the selected signal to the digital unit 150c. The digital unit 150c is driven by the selected clock signal.

  Note that the present embodiment is not limited to the configuration including the clock signal selection unit 162, and can be configured without the clock signal selection unit 162. In the case where the clock signal selection unit 162 is not provided, the present embodiment directly outputs the clock signals φS3 and φS4 from the clock delay conversion unit 141 to the sample and hold unit 150b. The clock signal generation unit 143 outputs the clock signal φI directly to the continuous unit 150a. The clock delay conversion unit 141 or the clock signal generation unit 143 directly outputs any one of the clock signals φS3, φS4, and φI to the digital unit 150c.

  The detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref which is a noise mixing path. The clock delay conversion unit 141 generates a clock signal with a delay added based on the control signal output from the detector 170. The clock delay amount is changed so that the noise peak frequency superimposed on the reference signal Vref matches the zero point of the FIR filter. In the present embodiment, the detector 170 and the clock delay conversion unit 141 function as the clock delay control circuit 171 of the present embodiment.

  FIG. 12 is a circuit configuration diagram for explaining the clock delay control circuit shown in FIG. 11, and specifically shows the configuration of the clock delay conversion unit 141. The clock delay conversion unit 141 includes a delay element 144 and a clock delay controller 148. The clock signal φS3 output from the clock signal generation unit 143 illustrated in FIG. 11 is input to the delay element 144, and is output from the clock delay conversion unit 141 as the clock signal φS4.

  FIG. 13 is a circuit diagram of a transistor level as an example of the delay element shown in FIG. The delay element 144 includes a delay amount control CMOS inverter including a CMOS inverter 144_1, a PMOS transistor 144_2 connected in series to the VDD side of the CMOS inverter, and an NMOS transistor 144_3 connected in series to the VSS side of the CMOS inverter. Two-stage cascade connection. The input signal VBP of the delay element 144 is a control signal of a PMOS transistor connected in series to the CMOS inverter VDD side, and the input signal VBN is a control signal of an NMOS transistor connected in series to the VSS side of the CMOS inverter. . The PMOS transistor 144_2 and the NMOS transistor 144_3 function as constant current sources according to the voltage levels of the control signals VBP and VBN, and perform current control of the CMOS inverter. The control signal VBP controls the delay amount of the rising edge of the clock signal, and the control signal VBN controls the delay amount of the falling edge of the clock signal. The reference signal Vref is input to the detector 170, and the detector 170 detects the frequency characteristic of the noise peak of the reference signal Vref. A control signal 173 is output from the detector 170 based on the detected frequency characteristic. The control signal 173 is input to the delay controller 148.

  FIG. 14 is a circuit configuration diagram showing an example of the delay controller shown in FIG. The delay controller 148 outputs control signals VBP and VBN for controlling the delay amount of the delay element 144 based on the control signal 173. The delay controller 148 includes resistance element groups 145_1 and 145_2 connected in series and switch groups 146_1 to 146_4 and 147_1 to 147_4. The switch groups 146_1 to 146_4 and 147_1 to 147_4 are resistance elements connected in series. Connected to a group. In the switch groups 146_1 to 146_4 and the switch groups 147_1 to 147_4, according to the control signal 173, only one signal is always selected and becomes H, and the remaining three signals become L. As a matter of course, the switch groups 146_1 to 146_4 and the switch groups 147_1 to 147_4 of the present embodiment are not limited to four and can be arbitrarily set.

Note that the above-described configurations of FIGS. 12, 13, and 14 are examples, and other configurations may be used as long as the same effects can be obtained.
According to this embodiment, the sample and hold unit 150b transmits the sampled signal to the continuous unit 150a. Since the transmitted signal component is a DC component, even if the sample and hold unit 150b has a plurality of operation clocks, the component is not attenuated by averaging. However, periodic noise generated by the D / A converter itself or periodic noise mixed from other electronic devices is an AC component. For this reason, when the sample and hold unit 150b has a plurality of operation clocks, the periodic noise component is attenuated by averaging. For this reason, in the D / A converter of this embodiment, the effect of suppressing periodic noise can be obtained. In other words, in this embodiment, the STF (Signal Transfer Function) is not changed, and it can be said that the attenuation coefficient by averaging can be applied only to the NTF (Noise Transfer Function).

  Further, according to the present embodiment, when periodic noise having a peak of 50 MHz is superimposed on the reference signal Vref, the delay amount added to the clock signal in the clock delay conversion unit 141 by the detector 170 is set to 10 ns, for example. According to such setting, the D / A converter performs the sampling operation by the clock signal φS3 and the clock signal φS4 having a delay of 10 ns with respect to the clock signal φS3. For this reason, since the delay time of the frequency characteristic fc of the FIR filter of this embodiment is 10 ns, an FIR filter having a zero point at fc = 50 MHz + 100 × X MHz is formed. Therefore, the present embodiment can efficiently suppress periodic noise superimposed on the D / A converter.

In this embodiment, periodic noise mixed in the output signal of the D / A converter can be efficiently separated from the signal component. For this reason, this embodiment can average only the noise in in-band, and can reduce the spectrum, without adding noise to the signal which should be transmitted.
The present embodiment described above can not only reduce noise generated from devices in the vicinity of the D / A converter, but also enhance resistance to noise of the D / A converter itself. For this reason, the influence of noise on the D / A converter can be reduced by changing only the D / A converter without changing the configuration of other devices around the D / A converter.

  The present embodiment can be realized only by adding a circuit for generating a plurality of clock signals. This eliminates the need for advanced semiconductor process technology and the increase in the number of pins on the chip, thereby preventing an increase in cost of the D / A converter. Furthermore, according to the present embodiment, since the D / A converter can be disposed in close proximity to other devices without considering the influence of noise, the size of the device including the D / A converter can be reduced. There is an effect.

Further, in the present embodiment, it is possible to reduce the noise suppression requirement for a decoupling capacitor that is generally provided for the purpose of reducing noise generated from devices around the D / A converter. At this time, if a sufficient effect of noise reduction is obtained, the decoupling capacitor itself may be unnecessary.
Further, the present embodiment is not limited to the configuration described above. That is, in the present embodiment, the case where the delay amount added by the clock delay conversion unit 141 is generated by one delay element has been described, but this is a configuration in the case of having one zero of the FIR filter shown in FIG. Yes, as a matter of course, the number is not limited to one and may be a natural number M.

  When there are M zero points of the FIR filter, in the sampling circuit 150 shown in FIG. 10, the number of switches included in the switch units 103 and 104 of the sample and hold unit 150b increases as the number M of the capacitors 111_1 and 111_2 increases. Similarly increases. In addition, the number of switches included in the switch units 101 and 102 of the continuous unit 150a also increases. At this time, the configuration of the clock delay conversion unit 141 shown in FIG. 12 is not changed except that the number of delay elements 144 is increased to M and the delay elements 144 are cascaded. Even in such a case, the present embodiment can obtain the same effect.

  In this embodiment, when the D / A converter has a single configuration, the control circuit 159 shown in FIG. 10 is provided in association with one sampling circuit. In this embodiment, the D / A converter control circuit 159 may be provided outside the D / A converter. Furthermore, in this embodiment, when the sampling circuit of the D / A converter shown in FIG. 1 is configured as another device, the control circuit 159 may be provided outside the device.

Next, consider a CODEC in which the D / A converter of this embodiment and an existing A / D converter are mounted together.
The D / A converter of the present embodiment has the same configuration as that of the A / D converter and the D / A converter even when the sampling frequencies of the A / D converter and the D / A converter are the same (operating frequency difference 0 on the horizontal axis). Even when the sampling frequency with the / A converter has a difference of about ± 25 Hz, the distortion of the output signal is small. In this embodiment, the output signal is distorted both in an asynchronous operation in which the A / D converter and the D / A converter operate with different clock signals, and in a synchronous operation in which the same clock signal operates. Can be reduced.

  The above effect of the present embodiment is obtained when the operation clock signals of the sample / hold unit of the D / A converter are operated by four different clock signals.

  The present invention can be used for all D / A converters and electronic devices having the D / A conversion function.

101, 102, 103, 104 Switch unit 101_1, 101_2, 102_1, 102_2, 103_1, 103_2, 104_1, 104_2 Switch 105, 106 Terminal 111_1, 111_2, 112, 113 Capacitor 121 Operational amplifier 141 Clock delay converter 143 Clock signal generator 144 Delay element 144_1 CMOS inverter 144_2 PMOS transistor 144_3 NMOS transistor 145_1, 145_2 Resistive element group 146_1-146_4, 147_1-147_4 Switch group 148 Clock delay controller 150a Continuous unit 150b Sample / hold unit 150c Digital unit Clock signal 159 Control circuit Part)
150 sampling circuit 158_1, 158_2 feedback path 162 clock signal selection unit 170 detector 171 clock delay control circuit 1391, 1591 clock signal generation unit 1392, 1392 clock signal selection unit

Claims (4)

A digital unit for inputting a digital signal; a sample-and-hold unit for sampling an input signal based on the digital signal input by the digital unit; and holding and transferring the sampled input signal; and the sample-and-hold unit A sampling circuit including a continuous unit that outputs the signal transferred by the analog signal;
A clock signal supply unit that supplies a first clock signal to the continuous unit and a second clock signal to the sample and hold unit;
A clock delay conversion unit that generates a plurality of clock signals having operation timings different from each other at least with respect to the second clock signal;
A clock delay control circuit for controlling a delay amount generated by the clock delay conversion unit,
The sample-and-hold unit includes a plurality of capacitive elements that accumulate charges generated by the input signal, and a plurality of switching elements that transfer the charges accumulated in the plurality of capacitive elements to the continuous unit, respectively. A D / A converter characterized by the above.   The clock delay control circuit includes: a detector for detecting a peak frequency at which noise mixed in the sampled input signal has a peak from a frequency characteristic of the input signal supplied to the sample and hold unit; and the detector 2. The D / A converter according to claim 1, further comprising: a delay amount conversion unit that converts a peak frequency of the noise detected by step 1 into an arbitrary delay amount.   The sample-and-hold unit includes a plurality of capacitive elements that accumulate charges generated by the input signal, and a plurality of switching elements that transfer the charges accumulated in the plurality of capacitive elements to the continuous unit, respectively. The D / A converter according to claim 1, wherein the switching element performs an on / off operation based on the plurality of second clock signals having different operation timings supplied thereto. A clock delay control circuit used in the D / A converter according to claim 1, 2 or 3,
A detector for detecting a peak frequency at which noise mixed in the sampled input signal has a peak from a frequency characteristic of the input signal supplied to the sample and hold unit, and a peak frequency of the noise detected by the detector A clock delay control circuit for use in a D / A converter, comprising: a clock delay conversion unit that converts the signal into an arbitrary delay amount.

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