JP5667602B2 - Sampling circuit, integrating circuit and A / D converter - Google Patents

Description

  The present invention relates to a sampling circuit, an integration circuit, and an A / D converter.

Currently, there is an increasing demand for downsizing electronic devices, and electronic components mounted on electronic devices are downsized, and electronic components are arranged closer to each other.
When electronic components are arranged close to each other, noise generated in the electronic components may be transmitted to other electronic components directly or via a mounting substrate or wiring, and may interfere with normal operation of the other electronic components. For this reason, recent electronic devices are required to be reduced in size and to suppress the influence of noise (hereinafter also referred to as noise countermeasures).

In order to prevent the noise generated by electronic components from affecting other electronic components, it is generally necessary to place electronic components apart so that the effect of noise is reduced, or when manufacturing electronic components. In the process, it is conceivable to devise arrangement and separation of elements. It is also conceivable to provide input / output terminals separately for each electronic component.
However, it is not preferable to dispose the electronic components apart from each other because it prevents the electronic device from being downsized. Further, in order to prevent noise from affecting the outside due to the process of the electronic component, an advanced process technique is required, which is not preferable because the manufacturing cost increases. Further, separating the input terminal and output terminal of the electronic component is disadvantageous in reducing the size of the electronic component due to the increase in the number of pins of the electronic device.

Incidentally, an A / D converter is an electronic component mounted on an electronic device. The A / D converter is an electronic component that is frequently used for an audio function of an electronic device, and particularly an electronic component that requires countermeasures against noise.
In recent A / D converters, a sampling circuit is often used, but in order to prevent noise from being mixed due to aliasing in the sampling circuit, it is necessary to suppress the high-frequency component of the input signal in advance. Generally, a front CR filter or the like is provided to remove the high-frequency component.

As a conventional technique for noise suppression of an A / D converter, for example, there is an invention described in Patent Document 1.
The invention described in Patent Document 1 includes an A / D converter 1004, an analog moving average filter 1002, and a digital moving average filter 1006 as shown in FIG. By applying the zero point of the digital moving average filter 1006 to the frequency band, a high frequency attenuation effect is obtained over a wide frequency range.

Japanese Patent Laying-Open No. 2003-46390 (FIG. 1)

  However, when the high-frequency component of the input signal is suppressed using the method of the prior art, it is necessary to provide the analog moving average filter 1002 and the digital moving average filter 1006 separately from the A / D converter 1004, and the area (circuit Scale)-Increased power consumption is inevitable. In addition, since the analog moving average filter 1002 generates noise, the noise suppression request to the A / D converter 1004 is further increased.

Further, for example, since the radiated noise caused by the inrush current generated with the sampling operation of the A / D converter 1004 is not reduced, in addition to a circuit element for radiating noise countermeasures, an analog moving average filter 1002 and a digital The moving average filter 1006 is provided and cannot contribute to downsizing of the electronic device.
The present invention has been made in view of the above-described points, and does not hinder downsizing of electronic components, and can suppress high-frequency components of an input signal while avoiding advancement of process technology. An object of the present invention is to provide a sampling circuit, an integration circuit including this circuit, and an A / D converter.

In order to achieve the above object, a sampling circuit of one embodiment of the present invention includes a first capacitor element portion including a plurality of capacitor elements for accumulating charges generated by an input signal, and charges generated by the input signal. A second capacitor element section including a plurality of capacitor elements for storing the charge, and a plurality of switching elements for storing charges in each of the plurality of capacitor elements of the first capacitor element section and transferring the charges. A first switching element unit; and a second switching element unit including a plurality of switching elements for storing charges in each of the plurality of capacitor elements of the second capacitor element unit and transferring the charges. switching element section and Ri us the second switching element section so as to operate alternately, the first switching element section, the second scan Sampling for accumulating the electric charge in a plurality of capacitive elements included in the first capacitive element portion in a second switching element portion non-accumulating period which is a period excluding a period in which the charge element portion accumulates electric charges in the capacitive element. In accordance with a plurality of clock signals set at different timings, an operation of accumulating the electric charge in the capacitive element included in the first capacitive element unit is performed, and the second switching element unit performs the first switching Sampling timing for accumulating the charge in a plurality of capacitive elements included in the second capacitive element portion in a first switching element portion non-accumulating period that is a period excluding a period in which the element portion accumulates charges in the capacitive element In accordance with a plurality of clock signals set to be different from each other, the capacitive element included in the second capacitive element section. Wherein performs an operation of storing charges, characterized in that it jitter is applied to at least one of rising or falling of the clock signal to.

Integrating circuit according to one embodiment of the present invention, a sampling circuit of the upper Symbol one embodiment, the first switching element section non-storage period, the accumulated charge is transferred to the first capacitor element portion, the second An integration capacitor to which the charge accumulated in the second capacitor element unit is transferred during the non-accumulation period of the switching element unit; and an operational amplifier, the operational amplifier including the first capacitor element unit and the second capacitor An input terminal to which charges accumulated in the element portion are supplied and an output terminal for outputting an output signal, and the integration capacitor is provided between the input terminal and the output terminal of the operational amplifier. Features.

One aspect of the A / D converter of the present invention is characterized in that it comprises an integrating circuit the one state-like, and a digital circuit that outputs a signal transferred as a digital signal by the integration circuit.

  According to the present invention described above, it is possible to provide a sampling circuit that can suppress high-frequency components of an input signal, and an A / D converter including this circuit. Since such an effect is obtained by providing a plurality of capacitive elements and operating them based on two or more different operation timings, the increase in area is suppressed without increasing power consumption, and noise. It is not accompanied by an increase. Furthermore, since the radiation noise caused by the inrush current of the analog part can be diffused, the radiation noise can be effectively suppressed.

It is an example of the integration circuit provided with the sampling circuit in 1st Embodiment of this invention. 2 is a timing chart showing an example of a clock signal supplied to the sampling circuit of FIG. 1. It is a figure for demonstrating the frequency characteristic obtained by capacity division in the sampling circuit of FIG. It is an example of the frequency characteristic obtained by using the clock signal represented with the timing chart of FIG. It is a timing chart which shows the other example of a clock signal. It is an example of the frequency characteristic obtained by using the clock signal represented with the timing chart of FIG. It is a timing chart which shows the other example of a clock signal. It is an example of the frequency characteristic obtained by using the clock signal represented by the timing chart of FIG. It is a timing chart which shows the other example of a clock signal. FIG. 5 is an example of frequency characteristics when the sampling capacitors used in FIG. 4 have different capacitance ratios of sampling capacitors. FIG. 7 is an example of frequency characteristics when the sampling capacitors used in FIG. 6 have different capacitance ratios of sampling capacitors. It is a timing chart which shows an example of the clock signal which applied the jitter in 2nd Embodiment of this invention. It is an example of the frequency characteristic obtained by using the clock signal represented with the timing chart of FIG. In the sampling circuit of FIG. 1, it is an example of the frequency characteristic obtained by dividing capacitance and applying jitter to the sampling edge. It is a block diagram which shows an example of the A / D converter using the sampling circuit of FIG. It is an example of the integration circuit provided with the conventional sampling circuit. It is an example of the clock signal supplied to the conventional sampling circuit. It is a block diagram for demonstrating the filtering method in the conventional A / D converter.

Hereinafter, first to third embodiments of the present invention will be described.
(First embodiment)
(Sampling circuit)
First, the sampling circuit of the first embodiment will be described.
(Circuit configuration)
FIG. 1 is a diagram for explaining a sampling circuit according to the first embodiment, and is a circuit diagram showing an example of an integrating circuit 1 including a sampling circuit 2 according to the present invention.

The integrating circuit 1 shown in FIG. 1 includes a sampling circuit 2, an integrating capacitor 106, and an operational amplifier 107.
The sampling circuit 2 includes sampling capacitors 105A_1, 105A_2, 105B_1, 105B_2, switches 101A_1, 101A_2, 101B_1, 101B_2, 102A_1, 102A_2, 102B_1, 102B_2, 103A_1, 103A_2, 103B_1, 103B_2, 104A_1, 104A, 104A_1 Is included.

The switch 101A_1, the sampling capacitor 105A_1, and the switch 102A_1 are connected in series with each other, and the switch 101A_2, the sampling capacitor 105A_2, and the switch 102A_2 are connected in series with each other.
The switch 103A_1, the sampling capacitor 105A_1, and the switch 104A_1 are connected in series with each other, and the switch 103A_2, the sampling capacitor 105A_2, and the switch 104A_2 are connected in series with each other.

The switch 101B_1, the sampling capacitor 105B_1, and the switch 102B_1 are connected in series with each other, and the switch 101B_2, the sampling capacitor 105B_2, and the switch 102B_2 are connected in series with each other.
The switch 103B_1, the sampling capacitor 105B_1, and the switch 104B_1 are connected in series with each other, and the switch 103B_2, the sampling capacitor 105B_2, and the switch 104B_2 are connected in series with each other.

  The switch 103A_1 and the switch 103A_2 constitute a switch unit 103A, the switch 103B_1 and the switch 103B_2 constitute a switch unit 103B, the switch 104A_1 and the switch 104A_2 constitute a switch unit 104A, and the switch 104B_1 and the switch 104B_2 constitute a switch unit 104B. To do.

  The switches 101A_1, 101A_2, 101B_1, and 101B_2 are each connected to an input terminal 111 to which an analog input signal Ain is input. The switches 102A_1, 102A_2, 102B_1, 102B_2, 103A_1, 103A_2, 103B_1, and 103B_2 are each connected to a terminal 113 to which an analog reference voltage Vcom is supplied.

The switches 104A_1, 104A_2, 104B_1, and 104B_2 are connected to one end of the integrating capacitor 106 and the inverting input terminal 107n of the operational amplifier 107 as outputs of the sampling circuit 2, respectively.
The integrating capacitor 106 is connected between the inverting input terminal 107n and the output terminal 107out of the operational amplifier 107, and the output terminal 107out is connected to the output terminal 112 of the integrating circuit 1.

The non-inverting input terminal 107p of the operational amplifier 107 is connected to a terminal 113 to which an analog reference voltage Vcom is supplied.
Each of the switches is driven by a clock signal supplied from a control circuit (not shown) and performs an on / off operation.
In FIG. 1, the circuit configuration composed of the circuit elements described with the symbol A added and the circuit configuration composed of the circuit elements described with the symbol B added are the same circuit configuration.

In FIG. 1, it is desirable that the sampling capacitor 105A_1 and the sampling capacitor 105A_2 have the same capacitance. Similarly, it is desirable that the sampling capacitor 105B_1 and the sampling capacitor 105B_2 have the same capacitance.
The analog input signal Ain is input from the input terminal 111 to the sampling circuit 2 having the above configuration.

The analog input signal Ain is sampled by the switch 102A_1. By this sampling, charges are accumulated in the sampling capacitor 105A_1. The analog input signal Ain is sampled by the switch 102A_2. By this sampling, charges are accumulated in the sampling capacitor 105A_2.
Similarly, the analog input signal Ain is sampled by the switch 102B_1. By this sampling, electric charges are accumulated in the sampling capacitor 105B_1. The analog input signal Ain is sampled by the switch 102B_2. By this sampling, charges are accumulated in the sampling capacitor 105B_2.

  Charges accumulated in the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 are switched to the switches 101A_1, 101A_2, 101B_1, 101B_2, 102A_1, 102A_2, 102B_1, 102B_2, 103A_1, 103A_2, 103B_1, 103B_2, 104A_1, 104B_1 Is input to the inverting input terminal 107n of the operational amplifier 107.

  The charges accumulated in the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 are stored in the switches 101A_1, 101A_2, 101B_1, 101B_2, 102A_1, 102A_2, 102B_1, 102B_2, 103A_1, 103A_2, 103B_1, 103B_2, 104A_1, 104A_1 The charge is transferred to the integration capacitor 106 according to the switching.

The operational amplifier 107 inputs the reference voltage signal Vcom1 to the non-inverting input terminal 107p, and outputs an analog output signal Vout from the output terminal 107out.
In the sampling circuit 2 shown in FIG. 1 described above, a plurality of sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 (four in the example shown in FIG. 1) are provided.

The amount of charge accumulated in the sampling capacitor 105A_1 is determined by the switching operation of the switches 101A_1 and 102A_1. The amount of charge accumulated in the sampling capacitor 105A_2 is determined by the switching operation of the switches 101A_2 and 102A_2.
Further, the amount of charge accumulated in the sampling capacitor 105B_1 is determined by the switching operation of the switches 101B_1 and 102B_1. The amount of charge accumulated in the sampling capacitor 105B_2 is determined by the switching operation of the switches 101B_2 and 102B_2.

Note that the number of sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 in the sampling circuit 2 of the first embodiment is not limited to four as a matter of course, and may be a natural number M × 2.
In the sampling circuit 2 shown in FIG. 1, as the number of sampling capacitors M × 2 increases, the number of switches similarly increases. Further, as the number of sampling capacitors M × 2 increases, the number of phases of the clock signal that drives the switch similarly increases. When the number of sampling capacitors increases, the configuration other than the sampling circuit 2 is not changed from the configuration shown in FIG.

  Further, when a sampling capacitor is further added to the sampling circuit 2 shown in FIG. 1, the total capacity of the added sampling capacitors is made equal to the total capacity of the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2. . Thus, the total value of the capacitors is configured to be equal, and by appropriately allocating the size of the sampling capacitor included in the sampling circuit 2 including the added sampling capacitor and the operation timing, the output signal Vout is distributed. An analog FIR (Finite Impulse Response) filter that lowers the gain of a specific frequency included can be formed.

  In the first embodiment, as shown in FIG. 1, the switches 101A_1 and 102A_1 are driven by the clock signal ΦS1A, the switches 101A_2 and 102A_2 are driven by the clock signal ΦS2A, and the switches 101B_1 and 102B_1 are driven by the clock signal ΦS1B. The switches 101B_2 and 102B_2 are driven by the clock signal ΦS2B. The switches 103A_1, 103A_2, 104A_1, and 104A_2 are driven by the clock signal ΦIA, and the switches 103B_1, 103B_2, 104B_1, and 104B_2 are driven by the clock signal ΦIB.

  These clock signals ΦS1A, ΦS2A, ΦIA, ΦS1B, ΦS2B, and ΦIB change on and off at the timing shown in the timing chart of FIG. 2, (a) is the clock signal ΦS1A, (b) is the clock signal ΦS2A, (c) is the clock signal ΦIA, (d) is the clock signal ΦS1B, (e) is the clock signal ΦS2B, (f) is Represents the clock signal ΦIB.

  As shown in FIG. 2, the clock signal ΦS1A (a), the clock signal ΦS2A (b), the clock signal ΦS1B (d), and the clock signal ΦS2B (e) are at the H level for the same time, and the clock signals ΦS1A, ΦS2A , ΦS1B and ΦS2B are signals that sequentially become H level one by one. Specifically, as shown in FIG. 2, these clock signals are repeatedly at the H level in the order of ΦS1A, ΦS2A, ΦS1B, ΦS2B, ΦS1A, ΦS2A,... That is, the sampling timings of the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2, which are determined by the falling edges of the clock signals ΦS1A, ΦS2A, ΦS1B (d), and ΦS2B, are set to repeatedly occur at equal intervals.

  The clock signal ΦIA is a signal that is at the H level during a period from the falling edge of the clock signal ΦS2A to the next rising edge of the clock signal ΦS1A (first switching element portion non-accumulation period). This clock signal ΦIA is a period from the falling edge of the clock signal ΦS2A to the next rising edge of the clock signal ΦS1A during the integration timing, which is the timing for transferring the charges accumulated in the sampling capacitors 105A_1 and 105A_2 to the integration capacitor 106 Is set to occur.

  Similarly, the clock signal ΦIB is a signal that becomes H level during a period from the falling edge of the clock signal ΦS2B to the next rising edge of the clock signal ΦS1B (second switching element unit non-accumulation period). This clock signal ΦIB is a period from the falling edge of the clock signal ΦS2B to the next rising edge of the clock signal ΦS1B, during which the integration timing, which is the timing to transfer the charges accumulated in the sampling capacitors 105B_1 and 105B_2 to the integration capacitor 106 Is set to occur.

(Function)
Next, the operation of the first embodiment having the above-described configuration will be described. A high-frequency component and periodic noise (noise caused by an inrush current to a circuit that processes an analog signal: hereinafter simply referred to as noise) will be described in the analog input signal Ain. ) Is superimposed, it will be described that the effect that the noise generated by the integration circuit 1 including the sampling circuit 2 of the present invention shown in FIG. 1 can be reduced can be obtained.
In this description, in order to facilitate understanding of the effects of the first embodiment, first, the operation of the conventional sampling circuit 4 shown in FIG. 16 will be described.

The integration circuit 3 shown in FIG. 16 has the same circuit configuration as that of the integration circuit 1 shown in FIG.
The sampling circuit 4 includes a sampling capacitor 905 and switches 901, 902, 903, and 904. The switch 901, the sampling capacitor 905, and the switch 902 are connected in series with each other. The switch 903, the sampling capacitor 905, and the switch 904 are connected in series with each other.

The other end of the switch 901 is connected to the input terminal 111 of the analog input signal Ain. The other ends of the switches 902 and 903 are connected to a terminal 113 to which an analog reference voltage Vcom is supplied. The other end of the switch 904 is connected to one end of the integration capacitor 106 and the inverting input terminal 107 n of the operational amplifier 107 as an output of the sampling circuit 4.
The integration capacitor 106 is connected between the inverting input terminal 107n and the output terminal 107out of the operational amplifier 107. The output terminal 107out of the operational amplifier 107 is connected to the output terminal 112 of the integrating circuit 3, and the output signal Vout is output from the output terminal 112.

The non-inverting input terminal 107p of the operational amplifier 107 is connected to a terminal 113 to which an analog reference voltage Vcom is supplied.
Each of the switches is driven by clock signals ΦS and ΦI (not shown) supplied from a control circuit (not shown) to perform an on / off operation.
The analog input signal Ain is input from the input terminal 111 to the sampling circuit 4 having the above configuration. The analog input signal Ain is sampled by the switch 902. Charges are accumulated in the sampling capacitor 905 by this sampling.

The electric charge accumulated in the sampling capacitor 905 is input to the inverting input terminal 107n of the operational amplifier 107 in accordance with switching of the switches 901, 902, 903, and 904. The operational amplifier 107 inputs the reference voltage signal Vcom1 to the non-inverting input terminal 107p and outputs an output signal Vout.
FIG. 17 is a timing chart showing the operation timing of the clock signal supplied to each switch shown in FIG.

The switches 901 and 902 are driven by the clock signal ΦS, and the switches 903 and 904 are driven by the clock signal ΦI.
In FIG. 17, (a) represents the clock signal ΦS, and (b) represents the clock signal ΦI.
As shown in FIG. 17, both the clock signal ΦS (FIG. 17A) and the clock signal ΦI (FIG. 17B) are non-overlapping clock signals that do not become H level.
In the sampling circuit 4 shown in FIG. 16, the sampling timing is only the sampling operation timing of the sampling capacitor 905, and the FIR filter characteristics cannot be obtained.

Next, the operation of the sampling circuit 2 in the first embodiment of the present invention shown in FIG. 1 will be described.
As shown in FIG. 1, the sampling circuit 2 in the first embodiment has a configuration in which the sampling capacitor 905 is divided into a plurality of parts in the conventional sampling circuit 4 shown in FIG. As an example, when the sampling capacitor 905 is divided into a natural number M, the analog FIR filter characteristic can be obtained by the sampling circuit 2 of FIG.

The zero point is formed by the analog FIR filter, and the frequency at which the zero point enters is expressed by the following equation (1).
F0 = FS × (k / M) (1)
k = 1, 2,..., M−1, M + 1,... 2 × M−1, 2 × M + 1,.
Here, in the expression (1), FS represents a sampling frequency, and k represents an integer excluding an integer multiple of M.

  As an example, FIG. 3 shows an analog FIR filter characteristic when the number M of sampling capacitors is M = 16. In FIG. 3, the horizontal axis represents frequency and the vertical axis represents Gain. FS is a sampling frequency.

  When the clock signals to the switches corresponding to the M = 16 sampling capacitors are ΦS1A to ΦS16A and the clock signals ΦS1B to ΦS16B, these clock signals are the clock signal ΦS1A as in the timing chart shown in FIG. .About..PHI.S16A and clock signals .PHI.S1B.about..PHI.S16B are clock signals that are equally spaced and at the same time H level, and sampling timings determined by falling edges of the respective clock signals are arranged at equally spaced intervals. In addition, the capacitance ratio of the 16 sampling capacitors is assumed to be sampling capacitors 105A_1: 105A_2:...: 105A_16 = 1: 1:...: 1, sampling capacitors 105B_1: 105B_2:.

  In the sampling circuit 2 in the first embodiment shown in FIG. 1, the sampling capacitor 4 is divided into a plurality of sampling capacitors 905 in the sampling circuit 4 shown in FIG. The analog FIR filter characteristics can be obtained by performing the time interleave operation of these two sets of circuits. That is, the circuit composed of the elements with A in FIG. 1 and the circuit composed of the elements with B in FIG. 1 have the same configuration, and obtain an analog FIR characteristic by alternately performing sampling operations. be able to. Note that FIG. 1 illustrates the case where M = 2.

  The sampling capacitor 905 is not limited to being equally divided into M as illustrated. By arbitrarily adjusting the size of the M sampling capacitors, the frequency characteristics of the obtained analog FIR characteristics can be arbitrarily adjusted.

(Specific example 1 of analog FIR characteristics)
FIG. 2 is a timing chart showing an example of the clock signal supplied to each switch in FIG. 1 as described above. The period of the supplied clock signal is T (= 1 / FS). 2A to 2F are clock signals that do not include jitter.
In the example shown in FIG. 2, the clock signal ΦS1A (a), the clock signal ΦS2A (b), the clock signal ΦS1B (d), and the clock signal ΦS2B (e) are equally spaced and have the same time at the H level. It is said. That is, the sampling timings of the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2, which are determined by the falling edges of the clock signals ΦS1A, ΦS2A, ΦS1B (d), and ΦS2B, are set at equal intervals.

  FIG. 4 shows analog FIR characteristics obtained when the clock signal shown in the timing chart of FIG. 2 is supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 of the integrating circuit 1 shown in FIG. Note that the sampling capacitors 105A_1: 105A_2 = 1: 1 and the sampling capacitors 105B_1: 105B_2 = 1: 1.

  In FIG. 4, the horizontal axis represents frequency and the vertical axis represents Gain. As shown in FIG. 4, it can be seen that the gain (Gain) steeply becomes substantially zero at the sampling frequency FS. That is, an analog FIR characteristic having a large attenuation effect at the sampling frequency FS can be obtained.

(Specific example 2 of analog FIR characteristics)
Here, each clock signal is not limited to the timing shown in the timing chart shown in FIG. The clock signal ΦS1A (a) or the clock signal ΦS2A (b) and the clock signal ΦIA (c) are non-overlapping clock signals that do not simultaneously become the H level, and the clock signal ΦS1B (d) or the clock signal ΦS2B ( e) and the clock signal ΦIB (f) are non-overlapping clock signals that do not simultaneously become the H level, and the relationship between the clock signal ΦS1A (a), the clock signal ΦS2A (b), and the clock signal ΦIA (c) By arbitrarily setting the sampling timing interval within a range that satisfies the condition that the relationship between the clock signal ΦS1B (d), the clock signal ΦS2B (e), and the clock signal ΦIB (f) is the same, The FIR filter characteristics can be arbitrarily adjusted.

  As an example, in the timing chart of FIG. 2, the sampling period of the clock signal ΦS1A (a) and the clock signal ΦS1B (d) is halved, and the sampling timing of the clock signal ΦS1A (a) and the clock signal ΦS1B (d) is ¼. FIG. 5 shows a timing chart when the cycle is advanced. As in FIG. 2, in FIG. 5, (a) is the clock signal ΦS1A, (b) is the clock signal ΦS2A, (c) is the clock signal ΦIA, (d) is the clock signal ΦS1B, and (e) is the clock signal. ΦS2B, (f) represents the clock signal ΦIB.

  FIG. 6 shows analog FIR characteristics obtained when the clock signal shown in the timing chart of FIG. 5 is supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 of the integration circuit 1 shown in FIG. Note that the sampling capacitors 105A_1: 105A_2 = 1: 1 and the sampling capacitors 105B_1: 105B_2 = 1: 1.

  In FIG. 6, the horizontal axis represents frequency and the vertical axis represents Gain. As shown in FIG. 6, at a frequency lower than the sampling frequency FS and a frequency “2FS” that is twice the sampling frequency FS, the gain (Gain) becomes steeply substantially zero, and the analog FIR characteristic having a large attenuation effect is obtained. Can be obtained.

(Specific example 3 of analog FIR characteristics)
As another example, in the timing chart of FIG. 2, the sampling period of the clock signal ΦS1A (a), the clock signal ΦS2A (b), the clock signal ΦS1B (d), and the clock signal ΦS2B (e) is 1.5 times. And a timing chart when the sampling timing of the clock signal ΦS1A (a) and the clock signal ΦS1B (d) is delayed by ¼ period and the integration timing of the clock signals ΦIA (c) and ΦIB (f) is delayed by ½ period. Is shown in FIG. 2, (a) is the clock signal ΦS1A, (b) is the clock signal ΦS2A, (c) is the clock signal ΦIA, (d) is the clock signal ΦS1B, and (e) is the clock signal. ΦS2B, (f) represents the clock signal ΦIB.

  FIG. 8 shows analog FIR characteristics obtained when the clock signal shown in the timing chart of FIG. 7 is supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 of the integration circuit 1 shown in FIG. Note that the sampling capacitors 105A_1: 105A_2 = 1: 1 and the sampling capacitors 105B_1: 105B_2 = 1: 1.

  In FIG. 8, the horizontal axis represents frequency and the vertical axis represents Gain. As shown in FIG. 8, the gain (Gain) is relatively large at the sampling frequency FS, and the gain is substantially zero at the frequency “2FS” that is twice the sampling frequency FS, so that an analog FIR characteristic having a large attenuation effect can be obtained.

(Specific example 4 of analog FIR characteristics)
As another example, in the timing chart of FIG. 2, the sampling period of the clock signal ΦS1A (a), the clock signal ΦS2A (b), the clock signal ΦS1B (d), and the clock signal ΦS2B (e) is 1.5 times. The sampling timing of the clock signal ΦS1A (a) and the clock signal ΦS1B (d) is delayed by ¼ period, and the integration timing of the clock signal ΦIA (c) and the clock signal ΦIB (f) is advanced by ½ period, A timing chart of the clock signal is shown in FIG. Like FIG. 2, in FIG. 9, (a) is the clock signal ΦS1A, (b) is the clock signal ΦS2A, (c) is the clock signal ΦIA, (d) is the clock signal ΦS1B, and (e) is the clock signal. ΦS2B, (f) represents the clock signal ΦIB.

  Here, the sampling timing (that is, the falling edges of the clock signals ΦS1A (a), ΦS2A (b), ΦS1B (d), and ΦS2B (e)) according to the timing chart shown in FIG. The timing is the same as the sampling timing of each sampling capacitor (that is, the falling edges of the clock signals ΦS1A (a), ΦS2A (b), ΦS1B (d), and ΦS2B (e)). In FIG. 1, the sampling capacitors 105A_1: 105A_2 = 1: 1 and the sampling capacitors 105B_1: 105B_2 = 1: 1.

  Therefore, the analog FIR characteristics obtained when the clock signal shown in the timing chart of FIG. 9 is supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 of the integration circuit 1 shown in FIG. 1 are the same as those in FIG. Become.

(Specific example 5 of analog FIR characteristics)
Further, as described above, when the sampling capacitor 905 of FIG. 16 is divided into a plurality of parts, the number of divisions is not limited to being equally divided into M as illustrated. By arbitrarily adjusting the size of the divided M sampling capacitors, the frequency characteristics of the obtained analog FIR characteristics can be arbitrarily adjusted.

  As an example, the capacitance ratio of each sampling capacitor of the integrating circuit 1 shown in FIG. 1 is set to sampling capacitors 105A_1: 105A_2 = 3: 1 and sampling capacitors 105B_1: 105B_2 = 3: 1. FIG. 10 shows analog FIR characteristics obtained when the clock signals shown in the timing chart of FIG. 2 are supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 having such a capacitance ratio.

  In FIG. 10, the horizontal axis represents frequency and the vertical axis represents Gain. As shown in FIG. 10, the gain changes in a sine wave shape as the frequency increases, the gain (Gain) becomes minimum near the sampling frequency FS, and becomes maximum near the frequency “2FS” that is twice the sampling frequency FS. It can be seen that analog FIR characteristics can be obtained.

(Specific example 6 of analog FIR characteristics)
As another example, the capacitance ratio of each sampling capacitor of the integration circuit 1 shown in FIG. 1 is set to sampling capacitors 105A_1: 105A_2 = 3: 1 and sampling capacitors 105B_1: 105B_2 = 3: 1. FIG. 11 shows analog FIR characteristics obtained when the clock signals shown in the timing chart of FIG. 5 are supplied to the sampling capacitors 105A_1, 105A_2, 105B_1, and 105B_2 having such a capacitance ratio.

  In FIG. 11, the horizontal axis represents frequency and the vertical axis represents Gain. As shown in FIG. 11, the gain changes in a sine wave shape as the frequency increases, and the gain (Gain) is minimized in the vicinity of a frequency slightly lower than the sampling frequency FS and a frequency “2FS” that is twice the sampling frequency FS. Thus, an analog FIR characteristic can be obtained in which the frequency is zero and becomes maximum in the vicinity of a frequency slightly higher than the sampling frequency FS.

(Summary)
Thus, in the analog FIR filter obtained by the integration circuit 1 in the first embodiment, the zero point frequency formed is analog to the sampling capacitors 105A_1, 105A_2,... And the sampling capacitors 105B_1, 105B_2,. It depends on each interval of the sampling timing at which the input signal Ain is sampled.

  When the sampling capacitors 105A_1, 105A_2,... And the sampling capacitors 105B_1, 105B_2,... Are sampled at intervals of the sampling timing at which the analog input signal Ain is sampled (ie, short on the time axis), that is, FIG. As shown in the timing chart, the interval between the falling edge of the clock signal ΦS1A and the falling edge of the clock signal ΦS2A, and the interval between the falling edge of the clock signal ΦS1B and the falling edge of the clock signal ΦS2B are shown in FIG. , The interval between the falling edge of the clock signal ΦS1A and the falling edge of the clock signal ΦS2A when the clock signals ΦS1A, ΦS2A, ΦS1B, and ΦS2B are arranged at equal intervals. If narrow compared to the spacing between the trailing edge and the falling edge of the clock signal ΦS2B of No. Faiesu1B, the zero point is formed on the high frequency side as shown in FIG.

  Conversely, when the sampling timings at which the analog input signal Ain is sampled in the sampling capacitors 105A_1, 105A_2,... And the sampling capacitors 105B_1, 105B_2,. As shown in the timing chart, the interval between the falling edge of the clock signal ΦS1A and the falling edge of the clock signal ΦS2A, and the interval between the falling edge of the clock signal ΦS1B and the falling edge of the clock signal ΦS2B are shown in FIG. 2, when the clock signals ΦS1A, ΦS2A, ΦS1B, and ΦS2B are arranged at equal intervals, the interval between the falling edge of the clock signal ΦS1A and the falling edge of the clock signal ΦS2A, and the clock signal If longer than the interval between the falling edge and the falling edge of the clock signal ΦS2B of Faiesu1B, the zero point is formed on the low frequency side as shown in FIG.

  Further, as shown in FIG. 1, by dividing the sampling capacitor 905 into a plurality of parts in FIG. 16 and having two sets of circuits (multiple times conventional) having a plurality of sampling timings, a time interleave operation is performed. Rather than dividing only in the sample phase and sampling a plurality of “between half phases”, a plurality of samplings can be performed “between all phases”. For this reason, the sampling capacitors 105A_1, 105A_2,... And the sampling capacitors 105B_1, 105B_2,. A zero point can be formed, and a cut-off point can be formed in a low band.

  Note that the sampling period, the integration timing, and the period do not affect the analog FIR characteristics. Only the sampling interval affects the analog FIR characteristics.

(effect)
As shown in FIG. 1, by using a sampling circuit 2 in which a sampling capacitor is divided into a plurality of parts, for example, when 16 sampling capacitors are provided, an analog FIR characteristic as shown in FIG. 3 can be obtained. By adjusting the sampling timing of a plurality of sampling capacitors and the capacitance ratio of the sampling capacitors, the analog FIR characteristics can be arbitrarily adjusted as shown in FIGS. 4, 6, 8, 10, and 11, for example. Can do.

Therefore, by adjusting the analog FIR characteristic of the sampling circuit 2, a high frequency component such as 1/2 or more of the sampling frequency of the sampling circuit 2 can be suppressed, that is, sampling having a frequency characteristic that provides a high frequency suppression effect. Circuit 2 can be realized.
In addition, a circuit composed of a sampling element with “A” added to the code and a circuit made of an element added with “B” to the code are provided, and the sampling capacitors included in these two sets of circuits are sampled alternately. By operating, as shown in FIG. 2, in one circuit (for example, a circuit made of an element having “A” added to the reference numeral), a sampling capacitor is performing a sampling operation in parallel. Thus, charge transfer to the integration capacitor 106 is performed in the other circuit (for example, a circuit including an element having a symbol “B”). Therefore, for example, in a circuit including an element with “A” as a reference, as shown in FIG. 2, the clock signal ΦIA is between the falling timing of the clock signal ΦS2A and the rising timing of the clock signal ΦS1A. Thus, the charge transfer to the integration capacitor 106 may be performed, so that the degree of freedom in setting the timing of the charge transfer to the integration capacitor 106 can be increased.

  Moreover, since the radiation noise resulting from the inrush current of the analog part can be diffused, the radiation noise can be effectively suppressed. This is because the sampling capacitor itself is provided with the frequency characteristic of the analog FIR filter by providing the sampling capacitor twice and performing the time division operation. That is, it is not necessary to provide an analog unit such as an analog circuit for obtaining the frequency characteristics of the analog FIR filter.

Further, in order to obtain the above-described effect, it can be realized only with an increase in sampling circuits and without an increase in area (circuit scale), noise, etc., and cost reduction can be achieved.
Further, as described above, in the sampling circuit 2, since the generation of noise by the analog unit can be suppressed by adjusting the operation timing and capacitance of each sampling capacitor, advanced process technology is required. It can be realized without.
Further, by adjusting the specifications of the sampling circuit 2 in this way, the integration circuit using the sampling circuit 2 can be reduced in size because it can be realized without increasing the area (circuit scale) and noise. Interfering can be suppressed.

(Second Embodiment)
(Sampling circuit)
Next, the sampling circuit of the second embodiment will be described.
(Circuit configuration)
The sampling circuit of the second embodiment has the same circuit configuration as the sampling circuit 2 of the first embodiment shown in FIG.
In the second embodiment, as in the first embodiment, as shown in FIG. 1, the switches 101A_1 and 102A_1 are driven by the clock signal ΦS1A, the switches 101A_2 and 102A_2 are driven by the clock signal ΦS2A, and the switches 101B_1 and 102B_1 Is driven by the clock signal ΦS1B, the switches 101B_2 and 102B_2 are driven by the clock signal ΦS2B, the switches 103A_1, 103A_2, 104A_1 and 104A_2 are driven by the clock signal ΦIA, and the switches 103B_1, 103B_2, 104B_1 and 104B_2 are driven by the clock signal ΦIB. Is done. However, in the second embodiment, these clock signals are turned on / off according to the timing chart shown in FIG.

(Function)
Here, first, the operation of the above-described configuration of the second embodiment will be described, and the sampling circuit 2 in the second embodiment will rush into the analog input signal Ain with a high frequency component and periodic noise (a circuit for processing an analog signal). Even when noise due to current (hereinafter also simply referred to as noise) is superimposed, noise generated by the integration circuit using the sampling circuit 2 shown in FIG. The point that the effect of attenuating the component can be obtained will be described.

  FIG. 12 shows an example of a timing chart of a clock signal supplied to each switch having the above-described configuration according to the second embodiment. 12 (a) to 12 (f) are clock signals to which jitter is applied, (a) is the clock signal ΦS1A, (b) is the clock signal ΦS2A, (c) is the clock signal ΦIA, and (d) is the clock signal ΦS1B. , (E) represents the clock signal ΦS2B, and (f) represents the clock signal ΦIB. Jitter is applied to the rising and falling edges of each clock signal.

  In the example shown in FIG. 12, the clock signals (a) ΦS1A, (b) ΦS2A, (d) ΦS1B, and (e) ΦS2B are shown as clock signals that are at the same time and at the same time H level. As with one embodiment, the present invention is not limited to being equally spaced. The sampling end time of the clock signals (a) ΦS1A, (b) ΦS2A, (d) ΦS1B, and (e) ΦS2B is the sampling time of the analog input signal Ain, and this cycle is arbitrarily set as in the first embodiment. By doing so, the analog FIR filter characteristics can be arbitrarily adjusted.

  FIG. 12 shows an example in which jitter is also applied to the clock signals (c) ΦIA and (f) ΦIB. However, no jitter is applied to the clock signals (c) ΦIA and (f) ΦIB. Clock signals similar to the clock signals (c) ΦIA and (f) ΦIB shown may be used. At this time, even if no jitter is applied to the clock signals (c) ΦIA and (f) ΦIB, the sampling time of the analog input signal Ain is not affected, and therefore the analog FIR filter characteristics are not affected at all.

In order to facilitate understanding of the effects of the second embodiment, first, in the conventional clock signal timing chart shown in FIG. 17, a case where jitter is applied to the clock signal, that is, a case where jitter is applied to the sampling timing will be described.
Applying jitter to the sampling timing means that the operation timing is dynamically changed in the timing chart of FIG.

By applying jitter to the sampling timing, frequency modulation can be applied in the sampling operation.
By this frequency modulation, a zero point can be formed in the frequency characteristic by the jitter amplitude (the absolute value on the time axis at which the sampling edge changes in FIG. 12).
The zero point frequency FJ formed in frequency modulation by applying jitter to the sampling timing is expressed by the following equation (2).
FJ = (1 / d) × I (I = natural number) (2)

  Here, d represents the jitter amplitude. As an example, FIG. 13 shows frequency characteristics by frequency modulation by applying jitter to the sampling timing when d = (1 / FS) × (1 / M) (M is the number of sampling capacitors). In FIG. 13, the horizontal axis represents frequency, and the vertical axis represents Gain. FIG. 13 shows frequency characteristics when jitter is applied to the sampling timing in the sampling circuit 2 shown in FIG. 1 having 16 sampling capacitors (M = 16).

  As shown in FIG. 13, a zero point can be formed at a frequency of 1 / d, and the frequency at which this zero point can be formed is inversely proportional to the jitter amplitude. For example, if the jitter amplitude d is set large, the zero point moves to the low frequency side, and if the jitter amplitude d is set small, the zero point moves to the high frequency side.

Next, the operation of the second embodiment will be described.
In the configuration of the second embodiment, as shown in the sampling circuit 2 of FIG. 1, in the sampling circuit 4 shown in FIG. 16, the sampling capacitor 905 is divided into a plurality of parts. Further, as shown in FIG. In this configuration, jitter is applied to the first and second jitters.
In FIG. 16, the effects of both the analog FIR filter characteristic (Equation (1)) obtained by dividing the sampling capacitor 905 and the frequency characteristic (Equation (2)) by frequency modulation by applying jitter to the sampling timing are obtained. The frequency characteristics are as shown in FIG.

  In FIG. 14, the horizontal axis represents frequency and the vertical axis represents Gain. The characteristic line L1 represents the analog FIR filter characteristic (formula (1)), the characteristic line L2 represents the frequency characteristic by frequency modulation (formula (2)), and the characteristic line L3 represents the division of the sampling capacitor 905 and It represents an analog FIR filter characteristic (that is, a combination of the analog FIR filter characteristic (L1) and the frequency characteristic (L2) by frequency modulation) obtained by performing frequency modulation by applying jitter together.

  Sampling is performed by appropriately adjusting the amplitude of jitter for a transmission band of “0 dB” that appears in an integral multiple of the sampling frequency FS, which cannot be attenuated by the analog FIR filter characteristics obtained by dividing the sampling capacitor 905. By frequency modulation accompanying the application of jitter to the timing, a zero point of the frequency characteristic can be formed, and a frequency characteristic that attenuates the high frequency component in a wider band as shown in FIG. 14 can be obtained.

(effect)
By dividing the sampling capacitor into a plurality of parts and applying jitter to the sampling timing, it is possible to provide a frequency characteristic that can obtain a high frequency suppression effect as shown in FIG. 14, and furthermore, radiation due to the inrush current of the analog part Since noise can be diffused, radiation noise can be effectively suppressed. This is because the sampling capacitor itself is provided with the frequency characteristic of the analog FIR filter by providing the sampling capacitor twice and performing the time division operation.

Further, in order to obtain such an effect, only the sampling circuit is increased, and the area noise is not increased.
Furthermore, the zero point of the frequency characteristic due to frequency modulation by applying jitter to the sampling timing by appropriately adjusting the amplitude of the jitter with respect to the 0 dB transmission band that appears in an integral multiple of the sampling frequency FS that cannot be attenuated by the analog FIR filter characteristics. As shown in FIG. 14, it is possible to obtain a frequency characteristic that attenuates a high frequency in a wider band.

  In the second embodiment, the case where jitter is applied to both the rising edge and the falling edge of the sampling clock signal has been described. However, the present invention is not limited to this. Even when jitter is applied only to the falling edge of the sampling clock signal, frequency modulation can be performed, that is, a zero point of frequency characteristics can be formed. Even when jitter is applied only to the rising edge of the sampling clock signal, the radiation noise caused by the inrush current of the analog portion can be diffused, that is, the radiation noise can be effectively suppressed.

  In the first and second embodiments, as described above, in the sampling circuit 2, the sampling timing and the capacitance ratio of the sampling capacitors are made different, and the jitter is applied to the sampling timing, so that the frequency characteristics are improved. Can be changed. Therefore, the sampling circuit 2 having a desired frequency characteristic can be easily obtained by changing the sampling timing or the like according to the use of the sampling circuit 2.

(Modification)
Note that the sampling circuit of the present invention is not limited to the one configured as the integration circuit 1 as described above, and can also be applied to the A / D converter 200 as shown in FIG. . For example, it can be used for a charge pump or the like.
In FIG. 15, 201 is a digital circuit that inputs the output of the integrating circuit 1, and 202 is a control circuit that outputs the clock signals ΦS1A and ΦS2A to the sampling circuit 2 at a predetermined timing.
In addition, the scope of the present invention is not limited to the exemplary embodiments shown and described above, but includes all embodiments that bring about effects equivalent to those intended by the present invention.

Further, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but is defined by any desired combination of particular features among all the disclosed features. sell.
Here, in the above embodiment, the sampling capacitors 105A_1 and 105A_2 correspond to the first capacitor element section, 105B_1 and 105B_2 correspond to the second capacitor element section, and the switches 101A_1, 101A_2, 102A_1 and 102A_2 are the first switching element section. The switches 101B_1, 101B_2, 102B_1, and 102B_2 correspond to the second switching element portion.

  The present invention can be used for all electronic devices having an A / D conversion function in addition to a sampling circuit, an A / D converter, and an integration circuit.

DESCRIPTION OF SYMBOLS 1 Integration circuit 2 Sampling circuit 101A_1, 101A_2, 101B_1, 101B_2 Switch 102A_1, 102A_2, 102B_1, 102B_2 Switch 103A_1, 103A_2, 103B_1, 103B_2 Switch 104A_1, 104A_2, 104B_1, 104B_1, 104B_2 105_1, 104B_2 105_1 107 operational amplifier 111 input terminal 112 output terminal

Claims (3)

A first capacitive element portion including a plurality of capacitive elements for accumulating charges generated by an input signal that is input;
A second capacitive element portion including a plurality of capacitive elements for accumulating charges generated by the input signal;
A first switching element unit including a plurality of switching elements for storing charges in each of the plurality of capacitor elements of the first capacitor element unit and transferring the charges;
A second switching element unit including a plurality of switching elements for accumulating charges in each of the plurality of capacitor elements of the second capacitor element unit and transferring the charges,
Ri Contact adapted to operate alternately said first switching element section and the second switching element section,
The first switching element unit is included in the first capacitor element unit in a second switching element unit non-accumulation period that is a period excluding a period in which the second switching element unit accumulates charges in the capacitor element. In accordance with a plurality of clock signals set so that the sampling timings for accumulating the charges in a plurality of capacitive elements are different from each other, an operation for accumulating the charges in the capacitive elements included in the first capacitive element portion is performed.
The second switching element unit is included in the second capacitor element unit in a first switching element unit non-storage period that is a period excluding a period in which the first switching element unit stores charges in the capacitor element. In accordance with a plurality of clock signals set so that the sampling timings for accumulating the charges in a plurality of capacitive elements are different from each other, an operation for accumulating the charges in the capacitive elements included in the second capacitive element section is performed.
A sampling circuit , wherein jitter is added to at least one of the rising edge and falling edge of the clock signal . A sampling circuit according to claim 1 ;
The charge accumulated in the first capacitor element portion is transferred during the first switching element portion non-accumulation period, and the charge accumulated in the second capacitor element portion during the second switching element portion non-accumulation period. Integration capacity to be transferred,
An operational amplifier,
The operational amplifier has an input terminal to which charges accumulated in the first capacitor element part and the second capacitor element part are supplied, and an output terminal for outputting an output signal,
The integration circuit, wherein the integration capacitor is provided between the input terminal and the output terminal of the operational amplifier. An integrating circuit according to claim 2 ;
A digital circuit that outputs the signal transferred by the integration circuit as a digital signal;
An A / D converter comprising:

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