JP2013069770A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which prevents variation among transistors in a height of a silicon film formed on an upper part of a silicon pillar by epitaxial growth when an active region is provided on the upper part of the silicon pillar of the transistor in a semiconductor device to equalize an implantation depth of a conductive dopant to the silicon film.SOLUTION: A semiconductor device manufacturing method comprises: a silicon pillar formation process of forming a columnar silicon pillar on a principal surface of a substrate; a first insulation film formation process of forming a first insulation film so as to cover the silicon pillar; a first insulation film removal process of removing the first insulation film from a top face to expose the top face and lateral faces of an upper part of the silicon pillar; and a silicon film formation process of forming a silicon film on the tip face and the lateral faces of the upper part of the silicon pillar by an epitaxial growth method.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a vertical transistor and a manufacturing method thereof.

  In recent years, miniaturization of semiconductor devices has been progressing rapidly due to progress in microfabrication technology. Even in a transistor which is one of semiconductor devices, the surface area of a semiconductor substrate that can be used as an active region is gradually reduced. When the active region is reduced, the channel length and the channel width are reduced in the planar transistor, and a short channel effect or the like occurs. In order to avoid such problems as the short channel effect and cope with the reduction of the active region, a vertical transistor has been proposed.

  In a vertical transistor, columnar silicon pillars are formed on the main surface of a semiconductor substrate such as a silicon substrate (hereinafter referred to as a substrate), and diffusion regions into which conductive dopants are implanted are provided above and below the silicon pillar, respectively. It has been. Usually, these diffusion regions function as source / drain regions of the transistor. A gate electrode is provided on the side wall of the silicon pillar between the upper diffusion region and the lower diffusion region via a gate insulating film. The upper and lower diffusion regions functioning as the source / drain regions of the transistor can be connected to other elements through contact plugs or the like. For example, when such a vertical transistor is applied as a DRAM (dynamic random access memory) selection transistor, the lower diffusion layer is connected to a bit line (or the diffusion layer itself is a bit line), and a contact plug is connected to the upper diffusion layer. A memory cell (hereinafter referred to as a cell) can be configured by connecting to the capacitor via the.

Such a vertical transistor can be increased in density without increasing the area of the substrate. In addition, a vertical transistor can easily form a semiconductor element having a fully depleted structure or a partially depleted structure, and has excellent characteristics such as a high-speed device and a semiconductor element with low power consumption.
Regarding such vertical transistors, vertical transistors having various structures and manufacturing methods thereof (see Patent Documents 1 to 3) have been proposed depending on the shape and arrangement of semiconductor elements.

For example, Patent Document 1 discloses a pillar-type pillar-type silicon MIS (metal-insulator-semiconductor) transistor in which both side walls are sandwiched between two gate electrodes.
In the pillar type MIS transistor, a diffusion region of an impurity semiconductor is formed in each of a lower portion and an upper portion of a silicon pillar formed on a substrate, a source / drain region is disposed, and a gate electrode is formed on a side wall of the silicon pillar via a gate insulating film. Is a vertical structure MIS transistor. The pillar type MIS transistor having such a structure can reduce the occupied area per transistor as compared with the planar type MIS transistor in which the gate electrode formed in a plane with respect to the substrate and the diffusion region is disposed on the lower side thereof.
Patent Document 2 discloses an SGT (Surrounding Gate Transistor) having a structure in which a gate electrode surrounds a columnar silicon.

However, in the transistor having the above-described structure, the volume and surface area of the diffusion region formed on the silicon pillar are reduced by the miniaturization of the transistor, and the resistance of the contact plug connected to the diffusion region and the diffusion region is increased. End up.
In particular, in a DRAM cell transistor, if the concentration of an impurity implanted into the diffusion region is increased in order to reduce the resistance of the diffusion region, the junction electric field in the diffusion region becomes stronger and the leakage current increases. As a result, the refresh characteristics of the DRAM deteriorate and the performance of the DRAM product is degraded.

  In Patent Document 3, in order to solve such a problem, in the step of forming a pillar-type transistor, the upper surface of the silicon pillar is exposed from the interlayer insulating film, and epitaxial growth using the upper surface of the silicon pillar as a seed is performed. A method for manufacturing a semiconductor device in which a diffusion layer to be a source / drain region is formed at the top is disclosed.

US Patent Application Publication No. 2006/0017088 US Patent Application Publication No. 2006/0081884 JP 2010-135592 A

  However, when the epitaxial growth is performed using the upper surface of the silicon pillar as a seed as in the conventional method of manufacturing a semiconductor device, the height of the formed silicon film varies from transistor to transistor. As a result, in the formation of the diffusion region above the silicon pillar performed after the silicon film is formed, there is a problem in that the implantation depth of the conductive dopant into the silicon film varies from transistor to transistor.

  The semiconductor device manufacturing method of the present invention includes a silicon pillar forming step of forming columnar silicon pillars on the main surface of the substrate, a first insulating film forming step of forming a first insulating film so as to cover the silicon pillars, A first insulating film removing step of removing the first insulating film from the upper surface to expose the upper surface and side surfaces of the upper portion of the silicon pillar; and a silicon film forming step of forming a silicon film on the upper surface and side surfaces of the upper portion of the silicon pillar by epitaxial growth. It is characterized by having.

  The semiconductor device of the present invention is filled with a silicon pillar formed in a pillar shape on the main surface of the substrate and a lower portion of the first groove formed simultaneously with the silicon pillar, and is formed so as to expose the upper portion of the silicon pillar. And a silicon film formed by epitaxial growth on an upper surface and a side surface of the upper part of the silicon pillar.

  According to the semiconductor device manufacturing method of the present invention, the upper part of the silicon pillar protrudes from the upper surface of the surrounding insulating film (first insulating film), and the silicon film formed by the epitaxial growth method is formed using the side surface as a seed in addition to the upper surface of the silicon pillar. It is formed. This method requires less epitaxial growth than conventional silicon film formation methods. Therefore, variation in the height of the silicon film formed by epitaxial growth for each transistor can be reduced. Further, when forming the diffusion region above the silicon pillar, the implantation depth of the conductive dopant can be made substantially uniform. As a result, a semiconductor device with little variation in electrical characteristics between transistors can be manufactured.

It is sectional drawing which shows the structure of the principal part of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 1st Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 2nd Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 3rd Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 4th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 4th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 4th Embodiment of this invention. It is a top view which shows the structure of the principal part of the semiconductor device of 5th Embodiment of this invention. It is sectional drawing which shows the structure of the principal part of the semiconductor device of 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is a top view which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention. It is sectional drawing which shows one manufacturing process of the semiconductor device in 5th Embodiment of this invention.

  Hereinafter, a semiconductor device to which the present invention is applied and a manufacturing method thereof will be described in detail with reference to the drawings. In the drawings used in the following description, the dimensional ratios of the components are not always the same as the actual ones. In addition, the materials and the like exemplified in the following description are merely examples, and the present invention is not limited to them, and can be appropriately modified and implemented without changing the gist thereof.

(First embodiment)
FIG. 1 is a sectional view showing the main part of a semiconductor device 200 according to the first embodiment of the present invention.
As shown in FIG. 1, the semiconductor device 200 includes a substrate 1, a p-type well 20a and an n-type well 20b formed in the surface of the substrate 1, a silicon pillar 2 formed in connection with these wells, p STI (shallow trench isolation) film 16 formed between type well 20a and n type well 20b, lower diffusion region (second diffusion region) 7 formed on the main surface of the well, and lower diffusion region 7 and a substrate insulating film (third insulating film) 30 formed on the STI film 16, a gate insulating film 5 formed on the sidewall of the silicon pillar 2, a gate electrode 6 formed around the gate insulating film 5, and a gate An interlayer insulating film (first insulating film) 8 filling the space between the electrodes, an upper diffusion region (first diffusion region) 10 formed on the silicon pillar 2, and an upper diffusion region 10 are embedded. Interlayer insulating film (second insulating film) 12 formed, first upper wiring 18 and second upper wiring 19 formed on interlayer insulating film 12, upper diffusion region 10 and first upper wiring 18 And a second contact plug 14 for connecting the lower diffusion region 10 and the second upper wiring 19 to each other.
In the semiconductor device 200, a region including the p-type well 20a functions as the n-channel transistor 101a, and a region including the n-type well 20b functions as the p-channel transistor 101b.

  As the substrate 1, for example, a silicon substrate can be used. Specifically, a p-type silicon substrate can be used. In the following description, it is assumed that a p-type silicon substrate (silicon wafer) is used as the substrate 1.

The p-type well 20 a is an impurity diffusion region formed by implanting p-type impurities into the substrate 1. Similarly, the n-type well 20b is an impurity diffusion region formed by implanting an n-type impurity into the substrate 1. These wells are formed for the purpose of lowering the contact resistance when a metal or the like serving as a wiring layer is bonded to the source / drain regions or the terminals of the source / drain regions.
The silicon pillar 2 connected to the p-type well 20a and the n-type well 20b has the same type (p-type or n-type) conductivity as the respective wells.
Note that FIG. 1 shows a twin-well configuration in which a p-type well and an n-type well are provided in the region of the n-channel transistor 101a and the region of the p-channel transistor 101b, respectively. A single-well or triple-well configuration may be used instead.

  The STI film 16 is formed by filling a trench formed in the boundary surface between the p-type well 20a and the n-type well 20b with an insulating film. For example, silicon oxide can be used for the STI film 16.

  The lower diffusion region 7 is a region containing an impurity of an n-type semiconductor or a p-type semiconductor, and is formed on the upper surfaces of the p-type well 20a and the n-type well 20b excluding the silicon pillar 2 portion. An n-type semiconductor is implanted as an impurity into the lower diffusion region 7a on the main surface of the p-type well 20a, and the lower diffusion region 7a is made n-type conductive. A p-type semiconductor is implanted as an impurity into the lower diffusion region 7b on the main surface of the n-type well 20b, and the lower diffusion region 7b is made p-type conductive. Examples of the n-type semiconductor include arsenic and phosphorus. Examples of the p-type semiconductor include aluminum, arsenic, and indium. The lower diffusion region 10 functions as a source / drain region of the transistor.

  The substrate insulating film 30 is formed on the surface of the p-type well 20a, the n-type well 20b, and the STI film 16. As the substrate insulating film 30, for example, silicon oxide can be used. In the present embodiment, a case where a silicon oxide film is used as the substrate insulating film 30 will be described as an example.

The gate insulating film 5 is formed so as to cover a part of the lower diffusion region 7 and the side wall of the silicon pillar 2. As the gate insulating film 5, for example, a silicon oxide film can be used. In the present embodiment, description will be made assuming that a silicon oxide film is used as the gate insulating film 5.
The gate electrode 6 is provided so as to cover the upper surface of the substrate insulating film 30 and the gate insulating film 5. For the gate electrode 6, impurity-doped silicon (first impurity-doped semiconductor) can be used. Specifically, arsenic doped silicon or the like can be used.

  The interlayer insulating film 8 is formed so as to cover the insulating film 30, the gate electrode 6, and the exposed silicon pillar 2. The upper surface of the interlayer insulating film 8 is a flat surface. For example, a silicon oxide film or a silicon nitride film can be used as the interlayer insulating film 8. In the present embodiment, a case where a silicon oxide film is used as the interlayer insulating film 8 will be described as an example.

  The upper diffusion region 10 includes a silicon pillar upper portion 22 and a silicon film 24 formed in contact with the silicon pillar upper portion 22, and is formed on the silicon pillar 2. The silicon pillar upper portion 22 and the silicon film 10 contain impurities of an n-type semiconductor or a p-type semiconductor. An n-type semiconductor is implanted as an impurity into the silicon pillar upper portion 22a and the silicon film 24a of the upper diffusion region 10a of the p-type well 20a region, and the upper diffusion region 10a is made n-type conductive. A p-type semiconductor is implanted as an impurity into the silicon pillar upper portion 22b and the silicon film 24b of the upper diffusion region 10b of the n-type well 20b region, and the upper diffusion region 10b is made p-type conductive. The upper diffusion region 10 functions as a source / drain region of the transistor.

  The interlayer insulating film 12 is provided on the upper surface of the interlayer insulating film 8 so as to cover the upper diffusion region 10. For example, a silicon oxide film can be used as the interlayer insulating film 12. In the present embodiment, a case where a silicon oxide film is used as the interlayer insulating film 12 will be described as an example.

  The first upper wiring 18 is provided on the upper surface of the interlayer insulating film 12 and is in contact with the upper end of the first contact plug 13. The first contact plug 13 is formed through the interlayer insulating film 12 so as to be in contact with the upper surface of the upper diffusion region 10. As the conductive film (first conductive film) for forming the first upper wiring 18 and the first contact plug 13, a metal film can be used. The first upper wiring 18 is electrically connected to the upper diffusion region 10 via the first contact plug 13.

  The second upper wiring 19 is provided on the upper surface of the interlayer insulating film 12 and is connected to the upper end of the second contact plug 14. The second contact plug 14 is formed so as to penetrate the insulating film 30, the interlayer insulating film 8, and the interlayer insulating film 12 and to be in contact with the upper surface of the lower diffusion region 7 and the bottom surface of the second upper wiring 19. Has been. A metal film can be used as the conductive film (second conductive film) for forming the second upper wiring 19 and the second contact plug 14. As a result, the second upper wiring 19 is electrically connected to the lower diffusion region 7 via the second contact plug 14.

The semiconductor device 200 having such a configuration operates as a pillar type MIS transistor. A voltage is applied to the first upper wiring 18 and the second upper wiring 19 from a peripheral circuit or the like of the semiconductor device 200 (not shown), and a voltage is separately applied to the gate electrode 6. The amount of application of these voltages is controlled by a control unit provided in the peripheral circuit.
When a voltage is applied to the gate electrode 6, a channel region of the transistor is formed in the extending direction of the silicon pillar central portion 23 in contact with the gate electrode 6 through the gate insulating film 5. As a result, electrons flow from the lower diffusion region 7 to the upper diffusion region 10 so that the first upper wiring 18 and the second upper wiring 19 can be electrically connected. Therefore, the semiconductor device 200 activates the switch function by controlling the voltage in the control unit.
Further, another semiconductor device is provided on the interlayer insulating film 12, and the wiring of the semiconductor device can be connected to the first upper wiring and the second upper wiring of the semiconductor device 200.

  Next, a method for manufacturing the semiconductor device 200 of this embodiment will be described with reference to FIGS. 2 to 9 are cross-sectional views showing each manufacturing process of the semiconductor device according to the embodiment of the present invention. 2-9, the same code | symbol is attached | subjected to the component same as the semiconductor device 200 shown in FIG.

  First, the STI film 16 is formed on the substrate 1. The formation position of the STI film 16 is a boundary portion between the p-type well and the n-type well formed in the next step. The depth of the STI film 16 from the surface of the substrate 1 is preferably set in accordance with the depths of the p-type well and the n-type well.

<Diffusion region forming process in substrate>
Next, impurities are implanted into the surface of the substrate 1 between the STI films 16. At this time, in the region where the n-channel transistor is formed, high concentration ions of p-type impurities are implanted into the substrate 1 as channel ions from above the surface of the substrate 1. In the region where the p-channel transistor is formed, high concentration ions of n-type impurities are implanted into the substrate 1 as channel ions from above the surface of the substrate 1. Through this step, a p-type well 20a, an n-type well 20b, and an STI film 16 are formed on the substrate 1 as shown in FIG.

  Next, the surface of the substrate 1 is oxidized to form a silicon oxide film 3 on the substrate 1. Subsequently, a silicon nitride film 4 as a hard mask for forming silicon pillars is formed on the silicon oxide film 3. Further, a resist film is formed on the silicon nitride film 4, and the silicon oxide film 3 and the silicon nitride film 4 are patterned and post-processed using the resist film as a mask. By this step, only the silicon oxide film 3 and the silicon nitride film 4 above the substrate 1 that will later become the silicon pillar 2 remain.

<Silicon pillar formation process>
Next, using the silicon oxide film 3 and the silicon nitride film 4 as a mask, the substrate 1 is patterned as shown in FIG. 2 to form the silicon pillar 2.

  Next, a silicon oxide film 25 is formed so as to cover the surfaces of the p-type well 20a and the n-type well 20b, the side walls of the silicon pillar 2, and the side surfaces and the upper surface of the silicon nitride film 4. The silicon oxide film 25 can be formed by an ISSG (in situ stream generation) method.

  Next, a silicon nitride film is filled in the groove between the silicon pillars 2. Subsequently, the silicon nitride film is etched back to form sidewall spacers 26 shown in FIG. 3 on the silicon oxide film 25.

<Third insulating film forming step>
Next, the exposed upper surface of the p-type well 20a and the upper surface of the n-type well 20b are oxidized by thermal oxidation to form a substrate insulating film 30 made of a silicon oxide film as shown in FIG.

<Second diffusion region forming step>
Next, high-concentration ions of an n-type semiconductor as a conductive dopant are implanted into the p-type well 20a from above the silicon oxide film 30 on the p-type well 20a. As a result, a lower diffusion region 7a, which is an impurity diffusion region of the n-type semiconductor, is formed at the interface between the p-type well 20a and the substrate insulating film 30.
Similarly, high-concentration ions of a p-type semiconductor as a conductive dopant are implanted into the n-type well 20b from above the silicon oxide film 30 on the n-type well 20b. As a result, a lower diffusion region 7b which is an impurity diffusion region of a p-type impurity is formed at the interface between the n-type well 20b and the substrate insulating film 30.
Thereafter, the silicon oxide film 25 and the sidewall spacer 26 are removed.

<Gate insulation film formation process>
Next, a gate insulating film 5 made of a silicon oxide film is formed so as to cover the exposed lower diffusion region 7, silicon pillar 2, silicon oxide film 3, and silicon nitride film 4. The silicon oxide film of the gate insulating film 5 can be formed by the ISSG method.

<Gate electrode formation process>
Next, a gate electrode film made of impurity-doped silicon is formed so as to fill the gate insulating film 5 and the substrate insulating film 30 in the silicon pillar central portion 23. Subsequently, the gate electrode film is etched back to form a gate electrode 6 as shown in FIG.

<First insulating film forming step>
Next, an interlayer insulating film 8 made of a silicon oxide film as shown in FIG. 4 is formed so as to bury the upper portion of the silicon pillar 2, the gate electrode 6, and the substrate insulating film 30.

<First insulating film removal step>
Next, as shown in FIG. 5, the upper surface of the interlayer insulating film 8 is removed until the upper surface of the silicon nitride film 4 is exposed. The interlayer insulating film 8 can be removed by CMP (chemical mechanical polishing) or etch back.
Subsequently, the silicon nitride film 4 and the gate insulating film 5 on the side surface of the silicon nitride film 4 are removed by wet etching using hot phosphoric acid. By this step, as shown in FIG. 6, the silicon oxide film 3 formed on the silicon pillar 2 is exposed.
Thereafter, as shown in FIG. 7, the interlayer insulating film 8 is etched back downward, and the upper part of the silicon pillar 2 (the upper part of the silicon pillar 22) is protruded from the upper surface of the interlayer insulating film 8. Further, the silicon oxide film 3 and the gate insulating film 5 on the exposed side wall of the silicon pillar upper portion 22 are removed. By this step, the silicon pillar 2 upper portion 22 protrudes from the interlayer insulating film 8 and is exposed (FIG. 7).

<Silicon film formation process>
Next, as shown in FIG. 8, a silicon film 24 is formed so as to cover the silicon pillar upper portion 22 by epitaxial growth using the upper surface and side surfaces of the silicon pillar upper portion 22 as seeds.
In this step, since the silicon film 24 is formed on the silicon pillar upper part 22 whose upper surface and side surfaces protrude from the interlayer insulating film 8, the amount of epitaxial growth can be reduced. Therefore, variation in the thickness of the silicon film 24 for each silicon pillar 2 can be reduced.

<Second insulating film forming step>
Next, the interlayer insulating film 12 made of a silicon oxide film is formed so as to bury the silicon film 24 on the interlayer insulating film 8.

<First contact hole forming step>
Next, the upper surface of the interlayer insulating film 12 is polished by CMP. Thereafter, the interlayer insulating film 12 is patterned so that the upper surface of the silicon film 24 is exposed. As a result, a first contact hole 32 penetrating the interlayer insulating film 12 is formed on the silicon film 24.

<First diffusion region forming step>
Next, high-concentration ions of an n-type semiconductor as a conductive dopant are implanted into the silicon pillar upper portion 22a and the silicon film 24a from above the upper surface of the silicon film 24a on the p-type well 20a. Thus, an upper diffusion region 10a which is an n-type semiconductor impurity diffusion region is formed on the silicon pillar 2a connected to the p-type well 20a.
Similarly, high-concentration ions of a p-type semiconductor as a conductive dopant are implanted into the silicon pillar upper portion 22b and the silicon film 24b from above the upper surface of the silicon film 24b on the n-type well 20b. As a result, an upper diffusion region 10b which is an impurity diffusion region of the p-type semiconductor is formed on the silicon pillar 2b connected to the n-type well 20b.
By such a process, an upper diffusion region 10 as shown in FIG. 9 is formed.
In this step, as described above, since the variation in the thickness of the silicon film 24 for each silicon pillar 2 is small, the variation in the ion implantation depth (range) of the conductive dopant for each silicon pillar 2 is also small.

<First contact plug formation step>
Next, a conductive film is embedded in the first contact hole 32 formed on the upper diffusion region 10 to form the first contact plug 13. The first contact plug 13 is formed so that the upper surface thereof is flush with the upper surface of the interlayer insulating film 12. As the conductive film, a metal film such as a tungsten film or a titanium film can be used.

<First upper wiring formation process>
Next, a first upper wiring 18 for energizing the upper diffusion region 10 is formed on the first contact plug 13. As a material of the first upper wiring 18, a metal film similar to that of the first contact plug 13 can be used. Through this step, the first upper wiring 18 is electrically connected to the upper diffusion region 10 through the first contact plug 13.

<Second contact hole forming step>
Next, a second contact hole 34 that penetrates through the interlayer insulating film 12, the interlayer insulating film 8, and the insulating film 30 and exposes the upper surface of the lower diffusion region 7 is formed by a combination of photolithography and dry etching. Form.

<Second contact plug formation step>
Next, a conductive film is embedded in the second contact hole 34 to form the second contact plug 14. The second contact plug 14 is formed so that the upper surface thereof is flush with the upper surfaces of the interlayer insulating film 12 and the first contact plug 13. As the conductive film, a metal film such as a tungsten film or a titanium film can be used.

<Second upper wiring formation process>
Next, a second upper wiring 19 for energizing the lower diffusion region 7 is formed on the second contact plug 14. As a material of the second upper wiring 19, a metal film similar to that of the second contact plug 14 can be used. Through this step, the second upper wiring 18 is electrically connected to the lower diffusion region 7 through the second contact plug 14.
Depending on the wiring, as shown in FIG. 1, the first upper wiring 18 is connected to the plurality of first contact plugs 13, or the second upper wiring 19 is connected to the plurality of second contact plugs 14. May be.

The semiconductor device 200 shown in FIG. 1 is completed by the above manufacturing process.
According to the method for manufacturing a semiconductor device of the present embodiment, the upper part of the silicon pillar protrudes from the first interlayer insulating film in the step before the silicon film forming the upper diffusion region is formed by the epitaxial growth method, and the upper surface of the silicon pillar is formed. In addition, a part of the side surface is exposed from the first interlayer insulating film. Thereby, the amount of epitaxial growth can be reduced as compared with the case where the silicon film is formed by the epitaxial growth method using the silicon pillar exposed only on the upper surface as a seed.
Therefore, the upper diffusion region is formed with a substantially constant thickness, and variations in the epitaxially grown film thickness of the silicon film can be reduced. As a result, variation in electrical characteristics due to non-uniform shape in the pillar-type MIS transistor of the semiconductor device can be reduced.

In the semiconductor device manufacturing method of the present embodiment, after a silicon film is formed on the upper side of the silicon pillar by epitaxial growth, impurities are introduced into the upper side of the silicon pillar and the silicon film by ion implantation from the upper side of the silicon pillar. Form a region. As described above, since the variation of the epitaxially grown film thickness of the silicon film is reduced, the variation of the ion implantation depth for each silicon pillar is reduced.
As a result, variation in the distance (offset amount or overlap amount) between the upper end of the gate electrode of the pillar type MIS transistor and the upper diffusion region can be suppressed, and variation in element characteristics such as threshold voltage for each pillar type MIS transistor can be suppressed. This can reduce the productivity of the semiconductor device.

(Second Embodiment)
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device completed by this manufacturing method includes the same components as those of the semiconductor device 200 of the first embodiment.
FIG. 10 is a cross-sectional view showing each manufacturing process of the semiconductor device according to the embodiment of the present invention. 10, the same components as those of the semiconductor device 200 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In the manufacturing method of the semiconductor device of this embodiment, the same manufacturing process is performed until the silicon film forming step in the manufacturing method of the semiconductor device of the first embodiment. Following the silicon film forming step, the following steps are performed.

<First diffusion region forming step>
As shown in FIG. 10, n-type semiconductor high-concentration ions as a conductive dopant are implanted into the silicon pillar upper portion 22a and the silicon film 24a from the top of the silicon film 24a on the p-type well 20a. Thus, an upper diffusion region 10a which is an n-type semiconductor impurity diffusion region is formed on the silicon pillar 2a connected to the p-type well 20a.
Similarly, high concentration ions of a p-type semiconductor as a conductive dopant are implanted into the silicon pillar upper portion 22b and the silicon film 24b from the top of the silicon film 24b on the n-type well 20b. As a result, an upper diffusion region 10b, which is a p-type semiconductor impurity diffusion region, is formed on the silicon pillar 2b connected to the n-type well 20b.

<Second insulating film forming step>
Next, an interlayer insulating film 12 made of a silicon oxide film is formed so as to bury the upper diffusion region 10 on the interlayer insulating film 8.

<First contact hole forming step>
Next, the interlayer insulating film 12 is patterned so that the upper surface of the upper diffusion region 10 is exposed. Thereby, the first contact hole 32 is formed on the upper diffusion region 10. Note that the upper surface of the interlayer insulating film 12 may be polished by CMP before patterning the interlayer insulating film 12.

Thereafter, in the manufacturing method of the semiconductor device of the present embodiment, the same manufacturing process as that after the first contact plug forming process in the manufacturing method of the semiconductor device of the first embodiment is performed. And
After the second wiring formation step, the semiconductor device 200 shown in FIG. 1 is completed.

According to the method of manufacturing a semiconductor device of this embodiment, as in the first embodiment, the silicon film covers the upper portion of the silicon pillar by epitaxial growth using the sidewall portion of the upper portion of the silicon pillar protruding from the interlayer insulating film as a seed. Formed. Therefore, the epitaxially grown film thickness can be reduced, and as a result, variations in the film thickness of the silicon film for each silicon pillar can be reduced.
Further, the variation in the thickness of the silicon film due to the epitaxial growth method is reduced, so that the variation in the depth of ion implantation into the upper portion of the silicon pillar and the silicon film in the first diffusion region forming process is reduced. As a result, it is possible to further reduce variation in electrical characteristics of each pillar type MIS transistor in the semiconductor device.

(Third embodiment)
Next, with reference to FIG. 11, a method for manufacturing the semiconductor device of this embodiment will be described. The semiconductor device completed by this manufacturing method has the same configuration as the semiconductor device 200 of the first embodiment.
FIG. 11 is a sectional view showing each manufacturing process of the semiconductor device according to the embodiment of the present invention. 11, the same components as those of the semiconductor device 200 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In the manufacturing method of the semiconductor device of this embodiment, the same manufacturing process is performed until the silicon film forming step in the manufacturing method of the semiconductor device of the first embodiment. Following the silicon film forming step, the following steps are performed.

<First diffusion region forming step>
Subsequently, as shown in FIG. 11, high concentration ions of n-type semiconductor as a conductive dopant are obliquely implanted into the silicon pillar upper portion 22a and the silicon film 24a from the side surface of the silicon film 24a on the p-type well 20a. Thus, an upper diffusion region 10a which is an n-type semiconductor impurity diffusion region is formed on the silicon pillar 2a connected to the p-type well 20a.
Similarly, high-concentration ions of a p-type semiconductor as a conductive dopant are obliquely implanted into the silicon pillar upper portion 22b and the silicon film 24b from the side surface of the silicon film 24a on the n-type well 20b. As a result, an upper diffusion region 10b, which is a p-type semiconductor impurity diffusion region, is formed on the silicon pillar 2b connected to the n-type well 20b.

Thereafter, in the method for manufacturing the semiconductor device of the present embodiment, the same manufacturing steps as those after the second insulating film forming step in the method for manufacturing the semiconductor device of the second embodiment are performed. In the semiconductor device manufacturing method of this embodiment, the interlayer insulating film 12 is formed after the upper diffusion region 10 forming step so as not to prevent oblique implantation of high-concentration ions into the silicon pillar upper portion 22 and the silicon film 24.
After the second wiring formation step, the semiconductor device 200 shown in FIG. 1 is completed.

By the manufacturing process described above, the silicon film can be thinned by the epitaxial growth method as in the semiconductor device manufacturing method of the first embodiment and the second embodiment, and the silicon film film for each silicon pillar can be reduced. Variations in thickness can be reduced.
In addition, according to the method for manufacturing a semiconductor device of this embodiment, channeling to the channel region in the upper diffusion region is suppressed by performing oblique ion implantation on the silicon pillar upper portion and the silicon film in the first diffusion region forming step. Is done. Thereby, the ion implantation depth of the upper diffusion region is stabilized, and the variation of the ion implantation depth for each silicon pillar is further reduced. As a result, variations in element characteristics such as threshold voltage for each pillar type MIS transistor in the semiconductor device can be extremely reduced. As a result, variations in element characteristics such as threshold voltage for each pillar type MIS transistor in the semiconductor device can be reliably reduced. In addition, the productivity of the semiconductor device can be further increased.

(Fourth embodiment)
Next, with reference to FIGS. 12 to 14, a method for manufacturing the semiconductor device of this embodiment will be described. The semiconductor device 201 completed by this manufacturing method is formed such that the silicon film 10 is in contact with only the side surface of the silicon pillar upper portion 22 in the structure of the semiconductor device 200 of the first embodiment shown in FIG.
12 to 14 are cross-sectional views illustrating each manufacturing process of the semiconductor device 201 according to the embodiment of the present invention. 12 to 14, the same components as those of the semiconductor device 200 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

In the manufacturing method of the semiconductor device of this embodiment, the same manufacturing process is performed until the first insulating film forming step in the manufacturing method of the semiconductor device of the first embodiment.
Following the first insulating film forming step, the following steps are performed.

<First insulating film removal step>
Next, as shown in FIG. 12, the upper surface of the interlayer insulating film 8 is removed until the silicon oxide film 3, the silicon nitride film 4, and the silicon pillar upper portion 22 are exposed. The interlayer insulating film 8 can be removed by CMP or etch back.
In this embodiment, as shown in FIG. 12, the silicon oxide film 3 and the silicon nitride film 4 which is a mask insulating film are left on the silicon pillar 2, so that the upper surface of the silicon pillar 2 is covered with the mask insulating film. Put it in a state.

<Silicon film formation process>
Next, as shown in FIG. 13, silicon films 24 are formed on both side surfaces of the silicon pillar upper portion 22 by epitaxial growth using the exposed side surface of the silicon pillar upper portion 22 as a seed.
In this step, with the silicon oxide film 3 and the silicon nitride film 4 left on the silicon pillar 2, the silicon film 24 is formed by epitaxial growth in a direction perpendicular to the side surface of the silicon pillar 2 (left and right in FIG. 13). Is formed. Therefore, in the upper diffusion region forming process to be performed later, the silicon film does not grow in the direction in which ions of the conductive dopant are implanted into the silicon film 24 and the silicon pillar upper portion 22. That is, the height of the upper surface of the silicon pillar upper portion 22 and the upper surface of the silicon film 24 are substantially aligned. Therefore, when viewed from the ion implantation direction of the conductive dopant, the variation in the thickness of the silicon film 24 for each silicon pillar 2 is removed.

  Subsequently, the silicon oxide film 3 and the silicon nitride film 4 on the silicon pillar upper portion 22 are removed. At this time, the silicon pillar upper portion 22 and the silicon film 24 are exposed on the interlayer insulating film 8.

<Second insulating film forming step>
Next, an interlayer insulating film 12 made of a silicon oxide film is formed on the interlayer insulating film 8 and between the side surfaces of the silicon film 24.

<First diffusion region forming step>
Next, as shown in FIG. 14, from the upper surface of the silicon pillar 22a on the p-type well 20a and the upper surface of the silicon film 24a, high-concentration ions of an n-type semiconductor as a conductive dopant are applied to the silicon pillar upper portion 22a and the silicon film 24a. Inject. Thus, an upper diffusion region 10a which is an n-type semiconductor impurity diffusion region is formed on the silicon pillar 2a connected to the p-type well 20a.
Similarly, high-concentration ions of p-type semiconductor as a conductive dopant are implanted into the silicon pillar upper portion 22b and the silicon film 24b from the upper surface of the silicon pillar 22b and the upper surface of the silicon film 24b on the n-type well 20b. As a result, an upper diffusion region 10b, which is a p-type semiconductor impurity diffusion region, is formed on the silicon pillar 2b connected to the n-type well 20b.

  Subsequently, an interlayer insulating film 12 ′ (not shown) is formed so as to cover the interlayer insulating film 12 and the upper diffusion region 10. As this interlayer insulating film 12 ′, an insulating film made of the same material as that of the interlayer insulating film 12 can be used. In the manufacturing method of the semiconductor device of this embodiment, the interlayer insulating film 12 and the interlayer insulating film 12 ′ are combined, assuming that the same insulating film such as a silicon oxide film is used for the interlayer insulating film 12 and the interlayer insulating film 12 ′. Thus, the interlayer insulating film 12 is obtained.

<First contact hole forming step>
Next, the upper surface of the interlayer insulating film 12 is polished by CMP. Thereafter, the interlayer insulating film 12 is patterned so that the upper surface of the upper diffusion region 10 is exposed. As a result, a first contact hole 32 is formed on the silicon film 24.

Thereafter, in the manufacturing method of the semiconductor device of the present embodiment, the same manufacturing process as that after the first contact plug forming process in the manufacturing method of the semiconductor device of the first embodiment is performed. And
After the second wiring formation step, the semiconductor device 201 (not shown) is completed.

  According to the method for manufacturing a semiconductor device of this embodiment, a silicon film is formed by epitaxial growth using only the side surface of the upper portion of the silicon pillar protruding from the interlayer insulating film as a seed. For this reason, the silicon film does not grow in the direction in which the ions of the first conductivity type dopant are implanted after the silicon film forming step. Therefore, the variation in the epitaxial growth film thickness can be remarkably reduced in the upper surface of the upper part of the silicon pillar of the first conductivity type dopant and the ion implantation direction into the silicon film. As a result, the variation of the ion implantation depth into the silicon pillar upper part and the silicon film in the first diffusion region forming process for each silicon pillar is further reduced.

(Fifth embodiment)
15 and 16 are cross-sectional views showing the main part of another semiconductor device 205 according to an embodiment of the present invention. The semiconductor device 205 is an example of a DRAM to which the present invention is applied. 15 is a plan view of a cell portion of the semiconductor device 205 in which a plurality of memory cells are formed, and FIG. 16 is a cross-sectional view taken along the line AA ′ shown in FIG. However, the illustration of the interlayer insulating film is omitted in FIG.

  The semiconductor device 205 is provided with a cell portion and a peripheral circuit portion. A plurality of vertical cell transistors are formed in the cell portion. In the peripheral circuit portion, a circuit for performing control for controlling a voltage applied to the bit line or the word line, a vertical transistor, and the like are formed.

Next, the configuration of the vertical cell transistor in the cell portion of the semiconductor device 205 to which the present invention is applied will be described.
The cell portion includes a substrate 50, a groove portion (first groove) 51 extending in the X direction (first direction), and a groove portion (third groove) 53 extending in the Y direction (second direction). Between the silicon pillar 71 formed on the main surface of the substrate 1, the buried bit line (second diffusion region) 57 formed on the main surface of the substrate 1, and the side surface parallel to the X direction of the silicon pillar 71. A substrate insulating film (fifth insulating film) 61 formed on the buried bit line 57, a gate insulating film 64 formed on the side surface of the silicon pillar 2, and a gate electrode formed on the gate insulating film 64. 67, a groove portion (second groove) 52 extending in the Y direction so as to divide the buried bit line 57 into a plurality in the X direction, and a groove portion 51 and an interlayer formed so as to fill the groove portion 52 Filling the insulating film (fourth insulating film) 62 and the groove 53 The formed interlayer insulating film (sixth insulating film) 65, the upper diffusion region (first diffusion region) 70 formed on the silicon pillar 2, and the capacitor contact (first contact) formed on the upper diffusion region 70 1 contact plug) 73, an interlayer insulating film (second insulating film) 66 formed on the side of the upper diffusion region 70 and the capacitor contact 73, and a capacitor conpad (first contact plug) formed on the capacitor contact 73. 1 upper wiring) 78 and a capacitor 79 formed on the capacitor conpad 78.

  As the substrate 50, for example, a silicon substrate can be used. Specifically, a p-type silicon substrate can be used. In the semiconductor device manufacturing method of the embodiment described below, a p-type silicon substrate (silicon wafer) is used as the substrate 1 and will be described.

As shown in FIG. 16, a buried bit line 57 extending in the X direction is formed in the semiconductor device 205. The buried bit line 57 can be formed by implanting ions of a conductive dopant (second conductive dopant) into the substrate 50. The formation of the buried bit line 57 is not limited to this method, and the buried bit line 57 may be formed of a silicon film doped with a conductive dopant.
When the substrate 50 is made p-type conductive, the buried bit line 57 is made n-type conductive. That is, the bit line diffusion region 57 is reversely conductive with the substrate 50 forming the silicon pillar 71.
A well may be provided in the substrate 50 below the buried bit line 57. In that case, the buried bit line 57 in the p-type well region is made to be n-type and the buried bit line 57 in the n-type well region is made to be p-type, and an insulating film is provided between the wells of different conductivity types. It is done.
The embedded bit line 57 having such a structure functions as a bit line of a transistor. The portion below the bottom surface of the silicon pillar 2 functions as a source / drain region of the transistor.

  A part of the upper surface of the buried bit line 57 is in contact with the bottom surface of the silicon pillar 71. However, the buried bit line 57 is not limited to such a configuration, and the buried bit line 58 is buried between the buried bit line 58 and the silicon pillar 71 in accordance with the mutual formation position relationship between the buried bit line 58 and the silicon pillar 71. A bit line contact for connecting the bit line 58 and the silicon pillar 71 may be provided.

The gate electrode 67 extends in the Y direction so as to intersect the buried bit line 58 extending in the X direction, and is provided so as to be positioned above the buried bit line 58. As the gate electrode 67, impurity-doped silicon can be used. Moreover, arsenic, phosphorus, etc. can be used as this impurity.
The gate electrode 67 is composed of a pair of gate electrode wirings 67 a and 67 b, and each gate electrode wiring 67 a and 67 b is provided on the side wall in the X direction of the silicon pillar 71 through the gate insulating film 64. The gate electrode 67 is shared between transistors arranged side by side in the Y direction, and functions as a word line of the DRAM. A silicon oxide film can be used for the gate insulating film 64.

  The interlayer insulating film 65 is formed on the side surface of the silicon pillar 2 in the Y direction, and the gate insulating film 64 is formed on the side surface in the X direction as described above, and the gate electrode 67 including the gate electrode wirings 67a and 67b is formed on the outer side. ing.

The interlayer insulating film 62 extends in the Y direction, forms the silicon pillar 71 in the Y direction, and is an insulating film for isolating the buried bit line 57. The interlayer insulating film 65 is an insulating film for separating adjacent gate electrode wirings 6b and 6a in the X direction.
Examples of the material of the interlayer insulating films 62 and 65 include a silicon oxide film. In the method of manufacturing the semiconductor device according to the present embodiment, a silicon oxide film is used as the interlayer insulating films 62 and 65.

The upper diffusion region 70 includes a silicon pillar upper portion 72 and a silicon film 69 formed so as to cover the silicon pillar upper portion 72. A second conductivity type dopant is implanted into the silicon pillar upper portion 72 and the silicon film 69. The second conductivity type dopant is an n-type semiconductor or a p-type semiconductor, and is an impurity having a conductivity type opposite to that of the substrate 50 forming the silicon pillar 71. In the method for manufacturing the semiconductor device of this embodiment, an n-type impurity is used as the second conductivity type dopant.
As described above, when the p-type well or the n-type well is formed in the substrate, the silicon pillar upper portion 72 of the upper diffusion region 70 and the silicon film 69 formed on the silicon pillar 71 of each well region are formed. Are implanted with a second conductivity type dopant having a conductivity type opposite to that of each well. The upper diffusion region 70 functions as a source or drain region of the transistor.

  The interlayer insulating film 66 is provided above the interlayer insulating film 62 and the interlayer insulating film 65 so as to cover the upper diffusion region 70. As the interlayer insulating film 66, for example, a silicon oxide film can be used. In this embodiment, a silicon oxide film is used as the interlayer insulating film 66.

  A capacitor conpad (first upper wiring) 75 is formed on the capacitor contact 73. The capacitor contact 73 is formed through the interlayer insulating film 66 so as to connect the upper surface of the upper diffusion region 70 and the bottom surface of the capacitor conpad 75. As the capacitor conpad 75 and the capacitor contact 73, a metal film (first conductive film) can be used. Thereby, the capacitor conpad 75 is electrically connected to the upper diffusion region 70 via the capacitor contact 73.

The capacitor 79 is provided above the capacitor conpad 75 and functions as a DRAM capacitor. The capacitor 79 includes a lower electrode 81, a capacitor film 82, and an upper electrode 83, as shown in FIG. With this configuration, the capacitor 79 is electrically connected to the upper diffusion region 70 via the capacitor conpad 75 and the capacitor contact 73. Titanium nitride can be used as a material for the lower electrode 81 and the upper electrode 83. As a material for the capacitor film 82, a metal film such as zirconium oxide, hafnium oxide, and aluminum oxide, or a laminated film of these metals can be used.
Note that the capacitor contact 73 and the capacitor 79 may be directly connected. In that case, the capacitor compad 73 is not formed.

The voltages of the embedded bit line 57 and the gate electrode 67 of the semiconductor device 205 having such a configuration are controlled by the control circuit in the peripheral circuit portion.
When a voltage is applied to the gate electrode 67, a channel region of the vertical transistor is formed inside the silicon pillar 71 in contact with the gate electrode 67 through the gate insulating film 64. As a result, electrons flow from the buried bit line 57 as the lower diffusion region to the upper diffusion region 70.

In the semiconductor device 205 operating as a DRAM, one memory cell is configured by one vertical transistor and one capacitor.
In the cell portion, when the potential of the gate electrode 67 rises and the potential of the buried bit line 57 rises with the vertical transistor conducting, the channel region and the upper diffusion region 70 formed in the silicon pillar 71 of the vertical transistor. Through this, the capacitor 79 is charged by the current flowing from the embedded bit line 57. On the other hand, when the potential of the buried bit line 57 is lowered while the potential of the gate electrode 67 is raised, the charge of the capacitor 79 is discharged to the buried bit line 57 through the vertical transistor. By such an operation, charging and discharging of the capacitor 79 of each memory are controlled.

  Next, a method for manufacturing the semiconductor device 205 of this embodiment will be described with reference to FIGS. 17 to 43 are cross-sectional views illustrating each manufacturing process of the semiconductor device according to the embodiment of the present invention.

  First, impurity ions are implanted into the substrate 50 to form a conductive well. However, in FIGS. 17 to 43, illustration of the conductive well is omitted.

Next, the surface of the substrate 50 is oxidized to form a silicon oxide film 54. A silicon nitride film 56 serving as a hard mask is formed on the silicon oxide film 54. In addition, a silicon oxide film 55 is formed on the silicon nitride film 56.
Thereafter, the silicon oxide film 54, the silicon nitride film 56, and the silicon oxide film 55 are patterned by lithography and etching.

<Silicon fin formation process>
Next, a groove 51 extending in the X direction is formed in the substrate 50 by dry etching using the hard mask film as a mask. Formation of the groove 51 forms a silicon fin 90 extending in the Y direction on the main surface of the substrate 50.

<Second diffusion region forming step>
Next, a silicon oxide film 58 is formed so as to cover the silicon oxide film 55, the silicon nitride film 56, the silicon fin 90, and the main surface of the substrate 50. Thereafter, a silicon nitride film is filled so as to fill the space between the silicon fins 90. By etching back the silicon nitride film and part of the silicon oxide film 58, sidewall spacers 68 made of a silicon nitride film as shown in FIG. 19 are formed on the silicon oxide film 58. At this time, a part of the surface of the substrate 50 is exposed between the sidewall spacers 68.
Subsequently, conductive dopant ions of an n-type semiconductor for forming a buried bit line are implanted into the substrate 50 from above the exposed surface of the substrate 50. Further, by performing the annealing treatment, ions of the conductive dopant are diffused into the surface of the substrate 50 below the silicon fin 90 and the sidewall spacer 68 as shown in FIGS. By this step, an n-type conductive bit line diffusion region 57 ′ is formed on the main surface of the substrate 50 that is conductive to the p-type.

<Second groove forming step>
Next, as shown in FIGS. 20 to 22, using the sidewall spacer 68 as a mask, the groove 52 is formed in the exposed bit line diffusion region 57 ′.
By this step, the bit line diffusion region 57 ′ is separated, and the buried bit line 57 shown in FIG. 22 is formed.

<Fourth insulating film forming step>
Next, the sidewall spacer 68 is removed, and an interlayer insulating film 62 made of a silicon oxide film is formed so as to fill the groove 51 and the groove 52. Thereafter, as shown in FIGS. 23 to 25, the interlayer insulating film 62 is etched back by CMP until the silicon oxide film 55 is removed and the silicon nitride film 56 is exposed.

<Silicon pillar formation process>
Next, a resist film 95 is formed on the upper surface of the interlayer insulating film 62 and the exposed silicon nitride film 56 so as to extend in the Y direction intersecting the silicon fin 90 and the buried bit line 57 as shown in FIG. The resist film 95 is patterned. Subsequently, using the resist film 95 as a mask, the silicon nitride film 56, the silicon oxide film 55, and a part of the silicon fin 90 are sequentially removed by dry etching. Through this step, the silicon pillar 71 as shown in FIGS. 26 to 28 is formed on the buried bit line 57. Thereafter, the resist film 95 is removed.

<Fifth insulating film forming step>
Subsequently, the surface of the silicon pillar 71 is oxidized to form a protective film (not shown). A sidewall film (not shown) made of a silicon nitride film is formed thereon and etched back.
Next, a substrate insulating film 61 as shown in FIG. 30 is formed on the bottom surface of the trench 53, that is, on the exposed surface of the buried bit line 57 by thermal oxidation. Thereafter, the sidewall film and the silicon nitride film are removed.

<Gate insulation film formation process>
Next, a gate insulating film 64 is formed on the exposed side surfaces of the silicon pillar 2 and the silicon nitride film 56 in the X direction and on the exposed buried bit line 57 by the ISSG method.

<Gate electrode formation process>
Next, impurity-doped silicon is buried in the trench 53 as a conductive film for the gate electrode 67. The height of the upper surface of the impurity-doped silicon from the upper surface of the substrate insulating film 61 is preferably approximately the same as the height of the target gate electrode 67.
Subsequently, the impurity-doped silicon on the substrate insulating film 61 is removed by etch back. Thus, as shown in FIGS. 29 and 30, a gate electrode 67 made of impurity-doped silicon is provided on the gate insulating film 64 on the lower side surface of the silicon pillar 71.

<Sixth insulating film forming step>
Next, an interlayer insulating film 65 is formed so as to cover the trench 53 and the gate insulating film 64. Thereafter, as shown in FIG. 31, the interlayer insulating film 65 is removed by CMP or etch back until the upper surface of the gate insulating film 64 is exposed. Further, a part of the gate insulating film 64 covering the silicon nitride film 56 and the silicon nitride film 56 are sequentially removed by hot phosphoric acid wet etching as shown in FIGS.

<Sixth insulating film removing step>
Next, the interlayer insulating film 65 is etched back so that the upper part of the silicon pillar 71 (the upper part of the silicon pillar 72) protrudes. Thereafter, a part of the gate insulating film 64 covering the protruding silicon pillar upper portion 72 is removed using a chemical solution or the like. By this step, as shown in FIGS. 35 to 37, the upper surface and side surfaces of the silicon pillar upper portion 72 are exposed.

<Silicon film formation process>
Next, as shown in FIGS. 38 to 40, a silicon film 69 is formed by epitaxial growth using the exposed upper surface and side surfaces of the upper silicon pillar 72 as seeds.

<Third insulating film forming step>
Next, an interlayer insulating film 66 for forming capacitor contacts is formed on the interlayer insulating film 62 and the interlayer insulating film 65 so as to cover the silicon film 69. The upper surface of the interlayer insulating film 66 is removed and planarized by CMP.

<First contact hole forming step>
Subsequently, the interlayer insulating film 66 is patterned so that the upper surface of the silicon film 69 is exposed. By this step, a first contact hole 74 that penetrates the interlayer insulating film 66 is formed on the silicon film 24.

<First diffusion region forming step>
Next, as shown in FIGS. 41 to 43, high-concentration ions of a conductive dopant are implanted from above the upper surface of the silicon film 69 through the first contact hole 74. As the conductive dopant, an impurity semiconductor having a conductivity type opposite to that in the silicon pillar 71 below the silicon pillar upper portion 72 is used. As a result, an upper diffusion region 70 composed of a silicon film 69 and a silicon pillar upper portion 72 having a conductivity type opposite to the inside of the silicon pillar 2 is formed.

<First contact plug formation step>
Next, a capacitor contact 73 is formed by embedding a conductive film in the first contact hole 74. The upper surface of the capacitor contact 73 is flush with the upper surface of the interlayer insulating film 66. If necessary, the upper surfaces of the capacitor contact 73 and the interlayer insulating film 66 may be polished by a CMP method.

<First upper wiring formation process>
Subsequently, a capacitor conpad 75 for connecting the capacitor contact 73 and a capacitor 79 to be formed later is formed on the capacitor contact 73.

<Capacitor formation process>
Next, a stopper film 76 made of silicon nitride is formed on the interlayer insulating film 66. Further, a sacrificial oxide film is formed, and a capacitor cylinder hole is formed by lithography and dry etching. The sacrificial oxide film and the cylinder hole are not shown.
Subsequently, a lower electrode 81 made of titanium nitride is formed on the inner wall of the cylinder hole. Further, a capacitor film 82 such as zirconium oxide is formed on the lower electrode 81. Then, an upper electrode 83 made of titanium nitride is formed so as to cover the capacitor film 82. Through such a process, a capacitor 79 including a lower electrode 81, a capacitor film 82, and an upper electrode 83 is provided on the semiconductor device 205.

Subsequently, an impurity-doped silicon film 85 is formed so as to bury the upper electrode 83.
The semiconductor device 205 shown in FIGS. 15 and 16 is completed by the above manufacturing process.

According to the method of manufacturing a semiconductor device of this embodiment, a silicon film is formed in order to form an upper diffusion region functioning as a source / drain region of a vertical transistor in a cell portion of a DRAM having the structure shown in FIGS. Prior to epitaxial growth, the upper portion of the silicon pillar is exposed from the interlayer insulating film. Then, not only the upper surface of the silicon pillar but also the side surface is used as a seed for silicon film formation by the epitaxial growth method. Thereby, the epitaxial growth film thickness for forming the upper diffusion region of the target thickness can be reduced as compared with the conventional method of forming a silicon film. Therefore, in the silicon film constituting the upper diffusion region, the variation in the epitaxial growth film thickness for each vertical transistor can be reduced. As a result, variations in characteristics of the vertical transistors in the DRAM can be reduced.
Further, after a silicon film is formed on the silicon pillar, an impurity of a conductive dopant is introduced by ion implantation from the upper side of the silicon pillar to form an upper diffusion region. At this time, as described above, since the epitaxial growth film thickness of the silicon film has little variation, the variation of the ion implantation depth for each silicon pillar can be reduced. Therefore, variation in the distance (offset amount or overlap amount) between the upper end portion of the gate electrode of the vertical transistor constituting the DRAM and the upper diffusion region can be reduced.

According to the semiconductor device manufacturing method of the above embodiment, a semiconductor device in which variations in transistor characteristics due to variations in ion implantation depth in the upper diffusion region are reduced is provided. Further, the productivity of a semiconductor device to which the present invention is applied, such as a vertical MIS transistor or a DRAM, is improved.
The application range of the present invention is not limited to the above-described vertical MIS transistor and DRAM. Any semiconductor device including a transistor as a constituent element may be used.

DESCRIPTION OF SYMBOLS 1,50 ... Substrate, 2,71 ... Silicon pillar, 3 ... Silicon oxide film, 4 ... Silicon nitride film, 5, 64 ... Gate insulating film, 6, 67 ... Gate electrode, 7 ... Bit line diffusion region (second Diffusion region), 8 ... Interlayer insulating film (first insulating film), 10, 70 ... Upper diffusion region (first diffusion region), 12, 66 ... Interlayer insulating film (second insulating film), 13 ... First 1 contact plug, 14 ... second contact plug, 16 ... STI film, 18 ... first upper wiring, 19 ... second upper wiring, 20a ... p-type well, 20b ... n-type well, 22, 72 ... Upper part of silicon pillar, 23 ... center part of silicon pillar, 24, 69 ... silicon film, 25 ... silicon oxide film, 26 ... side wall spacer, 30 ... substrate insulating film (third insulating film), 32 ... first contact hole , 34 ... second contact , 51... Groove (first groove), 52... Groove (second groove), 53... Groove (third groove), 54, 55, 58... Silicon oxide film, 56. ... buried bit line (second diffusion region), 57 '... bit line diffusion region, 61 ... substrate insulation film (fifth insulation film), 62 ... interlayer insulation film (second insulation film), 65 ... interlayer insulation Film (fifth insulating film), 67a, 67b ... gate electrode wiring, 68 ... sidewall spacer, 73 ... capacitor contact (first contact plug), 74 ... first contact hole, 75 ... capacitor compad (first 1, upper wiring 1), 76, stopper film, 78, upper insulating film, 79, capacitor, 81, lower electrode, 82, capacitor film, 83, upper electrode, 85, impurity-doped silicon film, 90, silicon fin, 95,. Regis , 101a... N-channel transistor, 101b... P-channel transistor, 200, 201, 205.

Claims (21)

A silicon pillar forming step of forming columnar silicon pillars on the main surface of the substrate;
A first insulating film forming step of forming a first insulating film so as to cover the silicon pillar;
Removing the first insulating film from the upper surface and exposing the upper surface and side surfaces of the upper portion of the silicon pillar; and
A silicon film forming step of forming a silicon film on the upper and side surfaces of the upper portion of the silicon pillar by an epitaxial growth method;
A method for manufacturing a semiconductor device, comprising: After the silicon film forming step,
A second insulating film forming step of forming a second insulating film on the first insulating film so as to cover an upper surface and a side surface of the silicon film;
A first contact hole forming step of forming a first contact hole by removing a part of the second insulating film so that an upper surface of the silicon film is exposed;
A first diffusion region forming step of forming a first diffusion region by implanting a first conductivity type dopant from above the first contact hole;
The method of manufacturing a semiconductor device according to claim 1, wherein: After the silicon film forming step,
A first diffusion region forming step of forming a first diffusion region by implanting a first conductivity type dopant from the upper surface of the silicon film;
A second insulating film forming step for forming the second insulating film on the first insulating film so as to cover the diffusion region;
A first contact hole forming step of forming a first contact hole by removing a part of the second insulating film so that an upper surface of the silicon film is exposed;
The method of manufacturing a semiconductor device according to claim 1, wherein: After the silicon film forming step,
A first diffusion region forming step of forming a first diffusion region by obliquely implanting a first conductivity type dopant from a side surface of the silicon film;
A second insulating film forming step for forming the second insulating film on the first insulating film so as to cover the diffusion region;
A first contact hole forming step of forming a first contact hole by removing a part of the second insulating film so that an upper surface of the silicon film is exposed;
The method of manufacturing a semiconductor device according to claim 1, wherein: In the silicon pillar forming step,
Forming the mask insulating film on the substrate and then etching the substrate to form the silicon pillar;
In the first insulating film forming step and the first insulating film removing step,
By leaving the mask insulating film, the upper surface of the silicon pillar remains covered with the mask insulating film,
In the silicon film forming step,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon film is formed only on a side surface of the upper portion of the silicon pillar by an epitaxial growth method. After the silicon film forming step,
A mask insulating film removing step for removing the mask insulating film;
A second insulating film forming step of forming a second insulating film on the first insulating film so as to cover the silicon film and the upper surface of the silicon pillar;
A first contact hole forming step of forming a first contact hole by removing a part of the second insulating film so that the upper surfaces of the silicon film and the silicon pillar are exposed;
A first diffusion region forming step of forming a first diffusion region by implanting a first conductivity type dopant from above the first contact hole;
The method of manufacturing a semiconductor device according to claim 5, wherein: After the first contact hole forming step,
A first contact plug forming step of forming a first contact plug by embedding a first conductive film on the silicon film in the first contact hole;
A first upper wiring forming step of forming a first upper wiring on the first contact plug;
The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is manufactured as follows. Before the first insulating film forming step,
A third insulating film forming step of forming a third insulating film on the substrate main surface;
A second diffusion region forming step of forming a second diffusion region by injecting a second conductivity type dopant into the substrate from above the third insulating film;
Forming a gate insulating film on the side wall of the silicon pillar; and
Forming a gate electrode made of a first impurity-doped semiconductor around the gate insulating film; and
The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a silicon fin by forming a first groove extending in a first direction relative to the main surface of the substrate;
A second diffusion region forming step of forming a second diffusion region by injecting a second conductivity type dopant into the substrate surface from above the bottom of the first groove;
A second groove step for forming a second groove extending in a first direction and dividing the first diffusion region on the main surface of the substrate between the silicon fins;
A fourth insulating film forming step of forming a fourth insulating film filling the first groove and the second groove;
Formation of a silicon pillar that divides the silicon fin into a plurality of silicon pillars by forming a third groove that extends in a second direction intersecting the first direction and exposes the first diffusion region Process,
The method for manufacturing a semiconductor device according to claim 1, wherein: After the silicon pillar forming step,
A fifth insulating film forming step of forming a fifth insulating film on the surface of the second diffusion region;
Forming a gate insulating film on a side surface of the silicon pillar exposed by forming the third groove;
Forming a gate electrode made of a first impurity-doped semiconductor covering the gate insulating film in the third trench and extending along the third trench;
A sixth insulating film forming step of forming a sixth insulating film filling the gate insulating film in the third trench;
The method of manufacturing a semiconductor device according to claim 9, wherein:   11. The method of manufacturing a semiconductor device according to claim 7, further comprising a capacitor forming step of forming a capacitor on the first upper wiring.   11. The semiconductor device according to claim 2, wherein the first diffusion region and a portion below the first diffusion region portion of the silicon pillar are made to be semiconductors of opposite conductivity type to each other. A method of manufacturing a semiconductor device according to claim. A silicon pillar formed in a pillar shape on the main surface of the substrate;
A first insulating film formed to fill a lower portion of a first groove formed simultaneously with the silicon pillar and to expose the upper portion of the silicon pillar;
A silicon film formed by epitaxial growth on the top and side surfaces of the top of the silicon pillar;
A semiconductor device comprising:   The semiconductor device according to claim 13, wherein the silicon film is formed only on a side surface of the upper portion of the silicon pillar.   15. The semiconductor device according to claim 13, further comprising a first diffusion region formed by implanting a first conductivity type dopant into the silicon film. A second insulating film formed on the first insulating film so as to cover the first diffusion region;
The first contact hole formed in the second insulating film so that the upper surface of the first diffusion region is exposed is filled with a first conductive film. Contact plugs,
A first upper wiring formed on the first contact plug;
16. The semiconductor device according to claim 15, further comprising: A third insulating film formed on the substrate surface between the silicon pillars;
A second diffusion region formed in the substrate below the third insulating film by implanting a second conductivity type dopant from above the third insulating film;
A gate insulating film formed on a side wall of the silicon pillar;
A gate electrode made of first impurity-doped silicon formed around the gate insulating film;
The semiconductor device according to claim 13, comprising: Silicon formed in a columnar shape on the main surface of the substrate by a first groove extending in the first direction of the substrate and a third groove extending in a second direction intersecting the first direction With pillars,
A second diffusion region formed by injecting a second conductivity type dopant into the substrate surface from above the bottom of the first groove;
A fourth insulating film filled in the second groove extending in the first direction and provided to divide the first diffusion region between the first groove and the silicon pillar;
The semiconductor device according to claim 13, comprising: A fifth insulating film formed on the surface of the second diffusion region;
A gate insulating film formed on a side surface of the silicon pillar exposed by forming the third groove;
A gate electrode made of a first impurity-doped semiconductor and covering the gate insulating film and extending along the third groove;
A sixth insulating film filled on the gate insulating film in the third trench;
The semiconductor device according to claim 18, comprising:   20. The semiconductor device according to claim 16, further comprising a capacitor formed on the first upper wiring.   21. The semiconductor device according to claim 14, wherein the first diffusion region and a portion below the first diffusion region portion of the silicon pillar are semiconductors of opposite conductivity type to each other. The semiconductor device according to claim.

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