JP2012221443A - Controller, electronic apparatus and image processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide one method of operating an electronic apparatus in a power-saving state.SOLUTION: A controller that includes a memory controller and a memory controlled by a memory PHY and is operable in a normal mode and a power-saving mode, includes: a block A to be powered off in the power-saving mode; and a block B not to be powered off in the power-saving mode. The block A includes the memory, the memory controller, and a first CPU which sends a request to the memory controller. The block B includes the memory PHY, a second CPU, and a command conversion section which issues a command to the memory when receiving a request from the second CPU. The second CPU monitors generation of an external request or an internal request during the power-saving mode, and starts return processing to the normal mode when the external request or the internal request is generated.

Description

The present invention relates to a controller, an electronic apparatus, and an image processing apparatus, and more particularly to power saving control.

In recent years, electronic devices including image processing apparatuses such as printers are required to operate with lower power consumption. For example, there is an electronic device having a normal mode in which a normal operation is performed and a power saving mode in which some operations are stopped. As a method for the power saving operation, for example, SoC (System on Chip) and ASIC (Application Specific Integra) which are main elements of an electronic device are used.
multiple devices (such as ted Circuit) and LSI (Large Scale Integration)
For example, CPU, RAM, ROM, various processing circuits, etc.) are divided into a plurality of blocks,
A method of turning off the power of some blocks is known.

Patent Document 1 describes a method of providing a power control target block and stopping or starting power supply to the block.

JP 2006-4108 A

By the way, the circuit scale of an electronic device and the degree of power saving differ depending on how the various devices are arranged in a block in which the power is turned off in the power saving mode and a block in which the power is not turned off.

  An object of the present invention is to provide a method for operating an electronic device with power saving.

One aspect of the present invention for solving the above problems is a controller that includes a memory controller and a memory controlled by the memory PHY, and that can operate in a normal mode and a power saving mode. A first block that is turned off and a second block that is not powered off, the first block comprising the memory, the memory controller, and a first CPU that sends a request to the memory controller, The two blocks include the memory PHY, a second CPU, and a command conversion unit that issues a command to the memory in response to a request from the second CPU.
The second CPU monitors the occurrence of an external request or an internal request during the power saving mode, and starts a return process to the normal mode when the external request or the internal request occurs.

Here, the power of the first block and the second block is turned on in the normal mode,
A power supply unit for turning off the power of the first block in the power saving mode;
The PU may be characterized by instructing the power supply unit to power on the first block when an external request or an internal request occurs during the power saving mode.

The second CPU executes at least a part of the processing corresponding to the external request or the internal request before the first CPU returns after the return processing to the normal mode is started. Also good.

The second CPU may send an instruction for returning the memory from the self-refresh state to the normal access state to the command conversion unit after the start of the return processing to the normal mode.

The first CPU monitors a request for shifting to the power saving mode during the normal mode, and notifies the second CPU when there is a request for shifting to the power saving mode. ,
In response to the notification from the first CPU, the process of shifting to the power saving mode may be started.

  Moreover, an electronic apparatus provided with one of the said controllers may be sufficient.

  Moreover, a printing apparatus provided with one of the said controllers may be sufficient.

1 is a block diagram illustrating a schematic configuration of a printer according to an example of an embodiment of the present disclosure. It is a block diagram which shows schematic structure of SoC which concerns on an example of one Embodiment of this invention. It is a list of arrangement | positioning of the component in SoC. It is a block diagram explaining SoC (arrangement A) which does not have the feature of one embodiment of the present invention. It is a block diagram explaining SoC (arrangement B) concerning an example of one embodiment of the present invention. It is a block diagram explaining SoC (arrangement C) which does not have the feature of one embodiment of the present invention. It is a flowchart which shows the transfer process to the power saving mode which concerns on an example of one Embodiment of this invention. It is a flowchart which shows the transfer (returning from a power saving mode) process to the normal mode which concerns on an example of one Embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

In the present embodiment, a printer that is an image processing apparatus will be described as an example of the electronic apparatus. Of course, the electronic apparatus is not limited to a printer, and may be an image processing apparatus such as a multifunction machine, a copier, or a scanner. Further, the image processing apparatus is not limited to other types of electronic devices.

FIG. 1 is a block diagram illustrating a schematic configuration of a printer according to an example of an embodiment of the invention.

The printer 1 is a device that receives print data and performs printing on a print medium based on the print data. The printer 1 is, for example, a laser type page printer. Of course, an inkjet method or a serial printer may be used.

The printer 1 includes a controller 10 that controls the printer 1 in an integrated manner, a print engine 60 that performs printing on a print medium, and an operation panel 70 that displays various types of information and accepts input of user operations.

The controller 10 controls the SDRAM 40 to perform processing according to various programs, a power supply unit 30 that supplies power to the SoC 20, and an SDRAM (Synchronous DRAM) 40 that stores various programs and data in a volatile manner. And a ROM 50 such as a flash ROM for storing various programs and data in a nonvolatile manner.

In the present embodiment, the SDRAM 40 is, for example, DDR (Double Data Rate) -SDRA.
M. The SDRAM 40 has a self-refresh function. SDRAM 40
As described later, access control to the SDRAM 40 is performed by a memory controller and a memory PHY (Phys.
ical Interface) and SSTL I / O (Stub Series Termination Logic I / O).

The print engine 60 is a unit that performs printing on a print medium based on print data under the control of the controller 10. The print engine 60 is, for example, a laser engine having a toner cartridge, a photosensitive drum, a laser light irradiation mechanism, a transfer mechanism, a paper feed mechanism, a paper supply / discharge mechanism, and the like. Of course, the print engine 60 is not limited to the laser system, and may be an inkjet system.

The operation panel 70 is an input / output interface between the printer 1 and the user. The operation panel 70 includes, for example, a display such as a liquid crystal display or an organic EL display (Electro-Luminescence Display), a touch panel that functions as an input device, a hard switch, and the like.

The configuration of the printer 1 described above is not limited to the above because the main configuration has been described in describing the features of the present invention. In addition, other configurations included in a general printer are not excluded. For example, the SoC 20 may be composed of one or more ASICs.

  FIG. 2 is a block diagram showing a schematic configuration of the SoC according to an example of the embodiment of the present invention.

The SoC 20 includes a main CPU 201, a processing circuit 202, and a memory controller 2
03, signal level holding cell 204, sub CPU 205, power management circuit 206, network I / F (interface) 207, USB I / F 208, external I / F
209, command conversion circuit 210, memory PHY 211, SSTL I / O 21
2 is provided.

In the present embodiment, the SoC 20 includes a block A in which the power is turned off in the power saving mode,
And a block B that is always powered on. Each device of the SoC 20 is separated into a block A and a block B. The block A includes a main CPU 201, a processing circuit 202, and a memory controller 203. The block B includes a signal level holding cell 204, a sub CPU 205, a power management circuit 206, and a network I / F (
Interface) 207, USB I / F 208, external I / F 209, command conversion circuit 210, memory PHY 211, and SSTL I / O 212.

The power supply unit 30 supplies or stops power to the block A according to a signal output from the power management circuit 206. That is, the power OFF enable
While the signal is input, the power to the block A is stopped, and when the power OFF enable signal is stopped, the power to the block A is supplied. The power supply unit 30 always supplies power to the block B in both the normal mode and the power saving mode.

The main CPU 201 is an arithmetic device that executes a predetermined program to realize the main functions of the printer 1. The main CPU 201 basically operates when the printer 1 is in the normal mode. The main CPU 201 is connected to the SDRAM via the memory controller 203.
40 can be accessed.

When the printer 1 is in the normal mode, the main CPU 201 monitors whether or not there is a request for shifting to the power saving mode. If there is a request to switch to the power saving mode, sub-C
Notify the PU 205.

The processing circuit 202 is a circuit that performs predetermined processing. Although one processing circuit 202 is shown in the figure, a plurality of processing circuits 202 are provided. The processing circuit 202 is, for example, a circuit that performs various image processing and data processing. The processing circuit 202 can access the SDRAM 40 via the memory controller 203.

The sub CPU 205 is a computing device that executes a predetermined program and realizes functions related to the power saving mode of the printer 1. The sub CPU 205 basically operates in both the normal mode and the power saving mode of the printer 1. The sub CPU 205 can access the SDRAM 40 via the command conversion circuit 210. The SDRAM 40 may be accessed via the memory controller 203.

When the sub CPU 205 receives a notification from the main CPU 201 regarding a transition request to the power saving mode, the sub CPU 205 starts a transition process. For example, the power management circuit 206 is instructed to cause the power supply unit 30 to output a power OFF enable signal.

Further, the sub CPU 205 monitors a request from the outside of the printer 1 or a request from the inside of the printer 1 while the printer 1 is in the power saving mode. If there is a request, the sub CPU 205 starts a restoration process. For example, the power management circuit 206 is instructed to stop outputting the power OFF enable signal to the power supply unit 30.

The memory controller 203 receives requests from masters such as the main CPU 201 and the processing circuit 202, and issues commands to the SDRAM 40. The memory controller 203 outputs the generated command or the like to the memory PHY 211 via the signal level holding cell 204.

The memory PHY 211 controls the physical layer for the SDRAM 40. Memory PH
Y211 performs, for example, phase control and timing control on the signal output from the memory controller 203 or the command conversion circuit 210, and outputs it to the SDRAM 40.

The SSTL I / O 212 is connected to the memory PHY 211 and the SDRAM 40, and SD
This is an interface circuit for transferring a signal to the RAM 40 at a high speed and with a low signal amplitude.

The command conversion circuit 210 receives a request from the sub CPU 205 without going through the memory controller 203, and issues a command to the SDRAM 40. The command conversion circuit 210 outputs the generated command or the like to the memory PHY 211. Note that the command conversion circuit 210 only needs to be able to issue a command necessary for processing executed by the sub CPU 205, and thus realizes at least a part of the functions of the memory controller 203.

The power management circuit 206 is a circuit that outputs a signal to the power supply unit 30. The power management circuit 206 starts or stops outputting the power OFF enable signal to the power supply unit 30 in accordance with an instruction from the sub CPU 205.

A network I / F 207 is an interface circuit that is connected to a network such as a LAN (Local Area Network) and controls transmission / reception of data. USB I / F208 is
It is an interface circuit that is connected to a USB host and controls data transmission / reception via USB. The external I / F 209 is an interface circuit that controls data transmission / reception with devices such as the ROM 50 and the operation panel 70. When receiving a request from the outside, these circuits notify the sub CPU 205.

The signal level holding cell 204 fixes all signals output from the block A to a predetermined level (high or low) in the power saving mode (when the power of the block A is OFF).
In the present embodiment, the plurality of output signals from the memory controller 203 are fixed at predetermined levels so that, for example, the SDRAM 40 can maintain a self-refresh state so that various devices in the block B do not malfunction. Various input / output signals are fixed at predetermined levels so that no current flows from block B to block A or vice versa. The signal level holding cell 204 passes various input / output signals as they are in the normal mode.

Although not shown, the main CPU 201 and the processing circuit 2 are included in the block A of the SoC 20.
An arbitration circuit that arbitrates requests from 02 to the memory controller 203 may be provided.

Note that the configuration of the SoC 20 described above is not limited to the above because the main configuration has been described in describing the features of the present invention. In addition, other configurations included in a general SoC are not excluded. For example, the SoC 20 may have an ASIC that includes one or more devices.

Next, the characteristics of the SoC according to an example of this embodiment will be described more clearly with reference to FIGS.

FIG. 3 is a list of component arrangements in the SoC. As shown in the figure, as the arrangement of the components in the SoC, for example, a conventional arrangement and arrangements A to C are conceivable. Here, a main CPU, a processing circuit group, a memory controller, and a memory PHY are exemplified as main components.

In the conventional arrangement, the main CPU, the processing circuit group, the memory controller, and the memory PHY are arranged in the block B. In the arrangement A, the main CPU and the processing circuit group are arranged in the block A, and the memory controller and the memory PHY are arranged in the block B. In the arrangement B (this embodiment), the main CPU, the processing circuit group, and the memory controller are arranged in the block A, and the memory PHY is arranged in the block B (FIG. 2).
reference). In the arrangement C, the processing circuit group, the memory controller, and the memory PHY are arranged in the block A.

More specifically, the arrangement A is as shown in FIG. 4, for example. That is, the signal level holding cell 204 is provided between the main CPU 201 and the plurality of processing circuits 202 included in the block A and the memory controller 203 included in the block B. The signal level holding cell 204 has cells corresponding to output signals from the main CPU 201 and the plurality of processing circuits 202, respectively. For example, each output signal is fixed to a predetermined level so that the SDRAM 40 can maintain the self-refresh state in the power saving mode.
As the number of the main CPU 201 and the plurality of processing circuits 202 increases, the number of cells increases accordingly.

Accordingly, in the arrangement A, since it is necessary to provide the signal level holding cell 204 between the memory controller 203, the main CPU 201, and each processing circuit 202, the circuit scale becomes larger than the arrangements B and C. The memory controller 203 is connected to the main C
Since the PU 201 and each processing circuit 202 are arranged in the block A, the power saving performance is higher than the conventional arrangement, but the power saving performance is lower than the arrangement B and C.

An arbitration circuit that arbitrates requests from the main CPU 201 and the processing circuit 202 to the memory controller 203 may be provided between the signal level holding cell 204 and the memory controller 203.

More specifically, the arrangement B (this embodiment) is as shown in FIG. 5, for example. That is, the signal level holding cell 204 is provided between the memory controller 203 included in the block A and the memory PHY 211 included in the block B. The signal level holding cell 204 has a cell corresponding to each output signal (for example, a control signal, a data signal, a setting signal, etc.) from the memory controller 203. For example, in the power saving mode, SDR
Each output signal is fixed to a predetermined level so that the AM 40 can maintain the self-refresh state.

The signal between the memory controller 203 and the memory PHY 211 is sent to the main CPU 20
There are fewer signals than between the one and multiple processing circuits 202 and the memory controller 203. Even if the number of the main CPU 201 and the plurality of processing circuits 202 increases, the number of signals between the memory controller 203 and the memory PHY 211 does not change, so the number of cells does not change.

Therefore, in the arrangement B, regardless of the number of output signals of the main CPU 201 and each processing circuit 202, depending on the number of output signals from the memory controller 203 smaller than that number,
A signal level holding cell may be provided. Therefore, the circuit scale is smaller than that of the arrangement A. Further, since the memory controller 203 is arranged in the block A, the power saving performance is high as compared with the conventional arrangement and arrangement A.

In the arrangement B, since the memory PHY 211 is arranged in the block B, the memory PHY 211 can be operated even in the power saving mode, and can be operated anytime even immediately after returning from the power saving mode to the normal mode. Further, the memory PHY 211 has a sub CPU 205.
Can control the SDRAM 40 via the command conversion circuit 210 (see FIG. 2).
Even before the power saving mode returns to the normal mode (even when the main CPU 201 is stopped), the SDRAM 40 can be returned from the self-refresh state to the normal access state.

An arbitration circuit that arbitrates requests from the main CPU 201 and the processing circuit 202 to the memory controller 203 may be provided between the main CPU 201 and the processing circuit 202 and the memory controller 203. Also from the point that the arbitration circuit belongs to the block A, the arrangement B has higher power saving performance than the conventional arrangement and the arrangement A.

More specifically, the arrangement C is as shown in FIG. 6, for example. That is, the signal level holding cell 204 is provided between the memory PHY 211 included in the block A and the SSTL I / O 212 included in the block B. The signal level holding cell 204 is stored in the memory P
A cell is provided corresponding to each output signal (for example, a control signal, a data signal, etc.) from the HY 211. For example, each output signal is fixed to a predetermined level so that the SDRAM 40 can maintain the self-refresh state in the power saving mode.

The signal between the memory PHY 211 and the SSTL I / O 212 is less than the signal between the memory controller 203 and the memory PHY 211. Even if the number of the main CPU 201 and the plurality of processing circuits 202 increases, the number of signals between the memory PHY 211 and the SSTL I / O 212 does not change, so the number of cells does not change.

Therefore, in the arrangement C, signal level holding cells may be provided according to the number of output signals from the memory PHY 211 that is smaller than the number of output signals of the main CPU 201 and each processing circuit 202. Therefore, the circuit scale is smaller than those of the arrangements A and B.
Further, since the memory controller 203 and the memory PHY 211 are arranged in the block A, the power saving performance is higher than the conventional arrangement and arrangement A.

However, in the arrangement C, the power of the memory PHY 211 is turned off in the power saving mode. Therefore, the SDRAM 40 cannot be returned from the self-refresh state to the normal access state before returning from the power saving mode to the normal mode.
Recovery is delayed. In addition, since the memory PHY 211 and the SSTL I / O 212 are arranged apart from each other, circuit design for stabilizing the analog signal is required, which leads to an increase in cost. In addition, since the signal level holding cell 204 is arranged in the vicinity of the SSTL I / O 212, there is a possibility that the frequency of the signal is difficult to increase. Compared with the arrangements A and B,
Performance is degraded.

An arbitration circuit that arbitrates requests from the main CPU 201 and the processing circuit 202 to the memory controller 203 may be provided between the main CPU 201 and the processing circuit 202 and the memory controller 203.

  From the above, the arrangement B is selected in the present embodiment.

  Next, a characteristic operation of the SoC according to an example of this embodiment will be described.

FIG. 7 is a flowchart showing a transition process to the power saving mode according to an example of the embodiment of the present invention. This flow is started while the printer 1 is operating in the normal mode, for example.

In S10, a request for shifting to the power saving mode is monitored. Specifically, the main CPU 20
1 monitors whether there is a request to shift to the power saving mode. For example, the main CPU 201 should shift to the power saving mode when a request is not input from any of the network I / F (interface) 207, the USB I / F 208, and the external I / F 209 for a predetermined time. Can be determined. Further, for example, when there is a user operation for instructing a shift to the power saving mode via the operation panel 70, it can be determined that the mode should be shifted to the power saving mode. When there is a request to shift to the power saving mode (S10: YE)
S), the main CPU 201 notifies the sub CPU 205, and the process proceeds to S20. If there is no request for shifting to the power saving mode (S10: NO), the monitoring is continued.

In S20, the SDRAM 40 is shifted to the self-refresh state. Specifically, the main CPU 201 (which may be the sub CPU 205) instructs the memory controller 203 to issue a predetermined command, and shifts the SDRAM 40 to the self-refresh state. Then, the process proceeds to S30. The main CPU 2 arranged in the block A
01, the processing circuit 202, and the memory controller 203 are, for example, the SDRAM 40
For example, a preparatory process for turning off the power may be executed such as storing the program state.

In S30, output of the power OFF Enable signal is started. Specifically, sub C
Upon receiving the notification from the main CPU 201, the PU 205 instructs the power management circuit 206 to cause the power supply unit 30 to output a power OFF enable signal. And
The process proceeds to S40.

In S40, power supply to the block A is stopped. Specifically, the power supply unit 3
0 receives the input of the power OFF enable signal and stops the power supply to the block A.
Then, the process proceeds to S50.

In S <b> 50, the levels of various signals are held by the signal level holding cell 204. Specifically, the plurality of output signals from the memory controller 203 are fixed to predetermined levels so that, for example, the SDRAM 40 can maintain a self-refresh state so that various devices in the block B do not malfunction. Various input / output signals are fixed at predetermined levels so that no current flows from block B to block A or vice versa. Then, this flow ends.

  As described above, the transition from the normal mode to the power saving mode is performed.

FIG. 8 is a flowchart showing the transition to the normal mode (return from the power saving mode) processing according to an example of the embodiment of the present invention. This flow is started, for example, while the printer 1 is operating in the power saving mode.

In S110, a request for shifting to the normal mode is monitored. Specifically, the sub CPU 205
Monitors whether there is a request for transition to the normal mode. The sub CPU 205 is, for example,
Network I / F (interface) 207, USB I / F 208, and external I / F
When an external request is input from any one of F209, it can be determined that the transition to the normal mode should be performed. Further, for example, when an internal request such as an interrupt by a timer (not included in the block A) occurs, it can be determined that the transition to the normal mode should be performed. When there is a request for transition to the normal mode (S110: YES), the process is S
Proceed to 120. When there is no normal mode transition request (S110: NO), monitoring is continued.

In S120, the return mode is determined. Specifically, the sub CPU 205 determines the return mode. In the present embodiment, there are basically a first return mode in which return processing is performed by the main CPU 201 and a second return mode in which return processing is basically performed by the sub CPU 205. As the return mode, for example, any mode is preset in the ROM 50 or the like as a default setting. Of course, for example, the user may be able to change the setting from the host PC via the network I / F 207 or from the operation panel 70 via the external I / F 209. When the return mode is the first return mode (S120: first return mode), the process proceeds to S130. When the return mode is the second return mode (S120: second return mode), the process proceeds to S210.

In S130, the output of the power OFF Enable signal is stopped. Specifically, the sub CPU 205 instructs the power management circuit 206 to supply power to the power supply unit 30.
The output of the FF enable signal is terminated. Thereby, power supply to the block A is started. Then, the process proceeds to S140.

In S140, the return of the main CPU 201 is awaited. Specifically, the main CPU 20
1 performs a return from the power OFF state to the normal operation state. Note that the processing circuit 202 and the memory controller 203 arranged in the block A also return to the normal operation state. Then, after returning, the process proceeds to S150.

In S150, an instruction to return the SDRAM 40 from the self-refresh state is issued. Specifically, the main CPU 201 instructs the memory controller 203 to execute the SDRA.
A predetermined command for shifting M40 from the self-refresh state to the normal access state is issued. Then, the process proceeds to S160.

In S160, the SDRAM 40 is awaited to return from the self-refresh state. Specifically, the SDRAM 40 receives the input of a signal corresponding to a predetermined command to shift to the normal access state, and shifts to the normal access state. After returning, the process is S170.
Proceed to

In S170, it is determined whether or not the return is due to an external request. Specifically, when there is an external request in S110, the main CPU 201 determines that the return is due to the external request (S170: YES), and the process proceeds to S180. In S110, for example, when there is an internal request such as a timer interrupt, it is determined that the return is not due to an external request (S170: NO), and this flow ends. Note that the sub CPU 205 has S
In 110, the contents of the request may be stored in the ROM 50, the internal RAM, or the like.

In S180, the main CPU 201 processes the request. Specifically, the main CPU 201 executes processing corresponding to the request accepted in S110. Then, this flow ends. In S180, for example, the main CPU 201 performs pre-processing such as request acceptance processing, and executes the main processing according to the request after the end of the main flow (after the end of the normal mode transition processing). The external request is, for example, print data received via the network I / F 207, and this processing according to the external request is, for example, print processing based on the print data.

In S190, the main CPU 201 performs timer interruption processing. Specifically, the main CPU 201 executes processing corresponding to the timer interrupt generated in S110. Then, this flow ends. In S190, the main CPU 201 performs pre-processing such as canceling the execution of the timer, for example, and this processing corresponding to the timer interrupt is executed after the end of this flow (after the normal mode transition processing is completed). To do. This process in response to the timer interrupt is, for example, a calibration process for the print engine 60.

S210 is the same as S130. In S220, the SDRAM 40 is instructed to return from the self-refresh state. Specifically, the sub CPU 205 instructs the command conversion circuit 210 to issue a predetermined command for shifting the SDRAM 40 from the self-refresh state to the normal access state. Then, the process proceeds to S230.

S230 is the same as S160. In S240, it is determined whether or not the return is due to an external request. Specifically, when there is an external request in S110, the sub CPU 205 determines that the return is due to the external request (S240: YES), and the process is S
Proceed to 250. In S110, for example, when there is an internal request such as a timer interrupt, it is determined that the return is not due to an external request (S240: NO), and the process is S290.
Proceed to

In S250, it is determined whether or not the sub-CPU 205 processes an external request. Specifically, the sub CPU 205 determines whether or not the sub CPU 205 can process at least a part of the processing corresponding to the external request based on the content of the request and a predetermined standard. For example, the predetermined reference may be associated with information indicating whether or not a process that cannot be executed by the sub CPU 205 is included for each request content. Of course, this determination method is an example, and other determination methods may be used. When the sub CPU 205 can execute at least a part of the process corresponding to the external request (S250: YES), the process proceeds to S2.
Proceed to 60. When the sub CPU 205 cannot process the external request (S250: NO)
The process proceeds to S270.

In S260, the sub CPU 205 processes the request. Specifically, sub C
The PU 205 executes processing corresponding to the request accepted in S110. However, the sub CPU 205 executes at least some executable processes among the processes corresponding to the request. For example, in S260, the sub CPU 205 performs an executable process among the pre-processes corresponding to the request. Processing that cannot be executed is performed by the main CPU 201 in S280. Then, the process proceeds to S270.

S270 is the same as S140. In S280, the main CPU 201 processes the request. Specifically, the main CPU 201 executes all of the pre-processing according to the external request or the pre-processing not executed by the sub CPU 205 in S260.
When the sub CPU 205 executes all the preprocessing corresponding to the request in S260, the main CPU 201 does not need to perform the processing. Then, this flow ends. Note that this process according to the request is executed by the main CPU 201 after the end of this flow (after the end of the normal mode transition process).

In S290, the sub CPU 205 performs timer interrupt processing. Specifically, the sub CPU 205 executes processing corresponding to the timer interrupt generated in S110. Then, this flow ends. In S290, the sub CPU 205 performs preprocessing such as canceling the execution of the timer, for example. This process in response to the timer interrupt is executed by the main CPU 201 after the end of this flow (after the end of the normal mode transition process).

  S300 is the same as S140.

As described above, the transition from the power saving mode to the normal mode is performed. In the second return mode, before the main CPU 201 returns, the sub CPU 205 recovers the SDRAM,
At least a part of processing corresponding to the request is executed. Therefore, the main CPU 20
The process can proceed before 1 returns, and the time for returning to the normal mode is further shortened. Since the restoration of the SDRAM is performed by the sub CPU 205, the main CPU 201 can use the SDRAM immediately after the restoration.

Note that the first return mode may not be executed (that is, S110, S2).
10 to S300 are executed).

Each of the processing units in FIGS. 7 and 8 is divided according to the main processing contents in order to facilitate understanding of the processing of the printer 1. The present invention is not limited by the way of dividing the processing unit or the name. The processing of the printer 1 can be divided into more processing units according to the processing content. Moreover, it can also divide | segment so that one process unit may contain many processes.

Heretofore, an example of an embodiment of the present invention has been described. According to the present embodiment, the electronic device can be operated with lower power consumption. Further, it is possible to operate with power saving while suppressing the circuit scale as much as possible. Further, by performing the return process by the sub CPU, the return from the power saving mode can be made earlier.

The above embodiments of the present invention are intended to illustrate the gist and scope of the present invention, and are not intended to be limiting. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

1: Printer, 10: Controller, 20: SoC, 30: Power supply unit, 40
: SDRAM, 50: ROM, 60: Print engine, 70: Operation panel, 201: Main CPU, 202: Processing circuit, 203: Memory controller, 204: Signal level holding cell, 205: Sub CPU, 206: Power management circuit, 207: Network I / F, 20
8: USB I / F, 209: External I / F, 210: Command conversion circuit, 211: Memory PHY, 212: SSTL I / O

Claims (7)

A controller having a memory controller and a memory controlled by a memory PHY, and operable in a normal mode and a power saving mode,
In the power saving mode, including a first block that is powered off and a second block that is not powered off,
In the first block,
The memory;
The memory controller;
A first CPU for sending a request to the memory controller;
In the second block,
The memory PHY;
A second CPU;
A command conversion unit that issues a command to the memory in response to a request from the second CPU,
The second CPU monitors the occurrence of an external request or an internal request during the power saving mode, and when an external request or an internal request occurs, starts a return process to the normal mode.
A controller characterized by that. The controller of claim 1,
A power supply unit for turning on the power of the first block and the second block in the normal mode and turning off the power of the first block in the power saving mode;
The second CPU instructs the power supply unit to turn on the first block when an external request or an internal request occurs during the power saving mode.
A controller characterized by that. The controller according to claim 1 or 2,
The second CPU executes at least a part of a process corresponding to an external request or an internal request after the start of the return process to the normal mode and before the first CPU returns.
A controller characterized by that. The controller according to any one of claims 1 to 3,
The second CPU sends an instruction for returning the memory from a self-refresh state to a normal access state to the command conversion unit after starting the return processing to the normal mode.
A controller characterized by that. The controller according to any one of claims 1 to 4,
The first CPU monitors a request to shift to the power saving mode during the normal mode, and if there is a request to shift to the power saving mode, notifies the second CPU,
The second CPU receives the notification from the first CPU and starts the process of shifting to the power saving mode.
A controller characterized by that.   An electronic device comprising the controller according to claim 1.   A printing apparatus comprising the controller according to claim 1.

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