JP2012182702A - Reset circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output an initial value of a logic circuit to be initialized to a logic circuit in the subsequent stage even in a clock-gating state.SOLUTION: A reset circuit, which resets a logic circuit operating in synchronization with a clock, includes an output selection unit that receives an output signal from the logic circuit and outputs any of an initial value of an output signal when the logic circuit is reset and the output signal received from the logic circuit; and a control unit that receives a reset signal for resetting the logic circuit and controls the output selection unit so that the initial value is output from the output selection unit in response to the reset signal.

Description

  The present invention relates to a reset circuit and a semiconductor device.

  An LSI includes a plurality of functional blocks (IP (Intellectual Property) macros) as it is highly integrated and multifunctional. This type of LSI initializes the logic circuit of the functional block by soft reset (for example, Patent Document 1). For example, some logic circuits of the LSI are initialized by soft reset. In general, the soft reset is performed in synchronization with the clock of the logic circuit to be initialized.

  In recent LSIs, low power consumption is required. For this reason, the LSI reduces power consumption by, for example, stopping the clock supply to the logic circuit of the functional block that is not used (clock gating).

JP 2008-118179 A

  In a logic circuit that is reset in synchronization with a clock, when the clock supply to the logic circuit to be initialized is stopped before the reset is performed, the reset is not performed. In this case, the output of the logic circuit may not be reset to the initial value. When the output of the initialization target logic circuit is not reset to the initial value, the initialization target logic circuit cannot output the initial value to the subsequent logic circuit. For this reason, a malfunction may occur in the operation of the subsequent logic circuit.

  An object of the present invention is to output an initial value of a logic circuit to be initialized to a subsequent logic circuit even in a clock gating state.

  In one embodiment of the present invention, a reset circuit that resets a logic circuit that operates in synchronization with a clock receives an output signal of the logic circuit and receives an initial value of the output signal when the logic circuit is reset and the logic circuit. An output selection unit that outputs one of the output signals and a reset signal for resetting the logic circuit are received, and the output selection unit is controlled so that an initial value is output in response to the reset signal from the output selection unit And a control unit.

  Even in the clock gating state, the initial value of the logic circuit to be initialized can be output to the subsequent logic circuit.

3 shows an example of a reset circuit in one embodiment. An example of a reset circuit in another embodiment is shown. 3 shows an example of the operation of the reset circuit shown in FIG. 3 shows an example of a semiconductor device on which the reset circuit shown in FIG. 2 is mounted. An example of a reset circuit in another embodiment is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a reset circuit 10 in one embodiment. For example, the reset circuit 10 resets the logic circuit 20 that operates in synchronization with the clock CLK1. The reset circuit 10 and the logic circuit 20 form at least a part of the semiconductor device. For example, the reset circuit 10 is mounted on an LSI or the like including the logic circuit 20.

  The reset circuit 10 includes an input selection unit ISEL, an output selection unit OSEL, and a control unit CNT. For example, the reset circuit 10 receives the soft reset signal RST and the input signal DIN, and outputs the output signal DOUT to the logic circuit at the subsequent stage of the logic circuit 20. The soft reset signal RST is a reset signal for resetting the logic circuit 20, for example, and is output from a CPU or the like that controls the operation of the semiconductor device. The input signal DIN is, for example, an input signal that is input to the logic circuit 20 during a normal operation in which the soft reset signal RST is not asserted, and is output from the logic circuit in the previous stage of the logic circuit 20. Note that the clock CLK1 received by the logic circuit 20 is output from, for example, a clock control circuit that controls supply and stop of the clock of the semiconductor device.

  The input selection unit ISEL receives the input signal DIN and outputs either a predetermined value for resetting the logic circuit 20 or the input signal DIN to the logic circuit 20. For example, the input selection unit ISEL outputs either a predetermined value or the input signal DIN to the logic circuit 20 according to the control of the control unit CNT. Here, for example, the input selection unit ISEL may generate a predetermined value using a control signal received from the control unit CNT, or may receive a predetermined value from the control unit CNT. Alternatively, the input selection unit ISEL may hold a predetermined value in advance.

  The output selection unit OSEL receives the output signal of the logic circuit 20 and outputs either the initial value of the output signal when the logic circuit 20 is reset or the output signal received from the logic circuit 20. For example, the output selection unit OSEL selects either the initial value of the output signal of the logic circuit 20 (hereinafter also simply referred to as the initial value) or the output signal received from the logic circuit 20 in accordance with the control of the control unit CNT. It is output as an output signal DOUT to the subsequent logic circuit.

  That is, the logic circuit at the subsequent stage of the logic circuit 20 receives the output signal DOUT of the reset circuit 10 as an output signal from the logic circuit 20. Here, for example, the output selection unit OSEL may generate an initial value using a control signal received from the control unit CNT, or may receive an initial value from the control unit CNT. Alternatively, the output selection unit OSEL may hold an initial value in advance.

  The control unit CNT receives the soft reset signal RST and the output signal of the logic circuit 20. Then, the control unit CNT controls the input selection unit ISEL and the output selection unit OSEL based on the soft reset signal RST and the output signal of the logic circuit 20. For example, the control unit CNT selects the output so that the initial value is output from the output selection unit OSEL in response to the soft reset signal RST even when the clock CLK1 stops before the reset timing based on the soft reset signal RST. Control part OSEL.

  That is, the output selection unit OSEL outputs the output signal DOUT indicating the initial value to the subsequent stage of the logic circuit 20 in response to the soft reset signal RST even when the clock CLK1 is stopped before the reset timing based on the soft reset signal RST. Output to the logic circuit. Thus, in this embodiment, the initial value of the initialization target logic circuit 20 can be output to the subsequent logic circuit regardless of the value of the output signal of the initialization target logic circuit 20 in the clock gating state.

  For example, the control unit CNT determines the output signal of the logic circuit 20 when the soft reset signal RST is asserted, and when the initial value matches the output signal of the logic circuit 20, the output signal of the logic circuit 20 May be output from the output selection unit OSEL. Alternatively, the control unit CNT may cause the output selection unit OSEL to output an initial value regardless of the value of the output signal of the logic circuit 20 when the soft reset signal RST is asserted.

  Further, for example, when the output signal of the logic circuit 20 is not reset to the initial value at the reset timing based on the soft reset signal RST, the control unit CNT is predetermined until the output signal of the logic circuit 20 is reset to the initial value. The input selection unit ISEL is controlled so that the value is output to the logic circuit 20.

  That is, the input selection unit ISEL has a predetermined value until the output signal of the logic circuit 20 is reset to the initial value when the output signal of the logic circuit 20 is not reset to the initial value at the reset timing based on the soft reset signal RST. Is output to the logic circuit 20. Therefore, the input of the logic circuit 20 is maintained at a predetermined value until the output signal of the logic circuit 20 is reset to the initial value. Thereby, the logic circuit 20 is reset, for example, when the supply of the clock CLK1 is resumed.

  Note that the configuration of the reset circuit 10 is not limited to this example. For example, the input selection unit ISEL may output either the predetermined value or the input signal DIN to the logic circuit 20 based on the soft reset signal RST. In this case, the input selection unit ISEL may receive the soft reset signal RST without going through the control unit CNT. In other words, the control unit CNT may not include a function for controlling the input selection unit ISEL.

  As described above, in this embodiment, the reset circuit 10 includes the output selection unit OSEL that outputs the initial value of the logic circuit 20 in accordance with the control of the control unit CNT. For example, even when the clock CLK1 is stopped, the output selection unit OSEL outputs the output signal DOUT indicating the initial value of the logic circuit 20 to the logic circuit subsequent to the logic circuit 20 in response to the soft reset signal RST. Thus, in this embodiment, the initial value of the initialization target logic circuit 20 can be output to the subsequent logic circuit regardless of the value of the output signal of the initialization target logic circuit 20 in the clock gating state. As a result, it is possible to prevent the operation of the logic circuit and the like subsequent to the logic circuit 20 from becoming unstable. That is, in this embodiment, it is possible to prevent the operation of the logic circuit and the like subsequent to the logic circuit 20 from becoming unstable while reducing power consumption by clock gating.

  FIG. 2 shows an example of the reset circuit 12 in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The reset circuit 12 resets the logic circuit 22 that operates in synchronization with the clock CLK1, for example. The reset circuit 12 and the logic circuit 22 form at least a part of the semiconductor device. For example, the reset circuit 12 is mounted on an LSI or the like including the logic circuit 22.

  The logic circuit 22 is, for example, a flip-flop circuit that becomes active when the enable signal en1 received at the enable terminal EN is “1” (high level). For example, when the enable signal en1 is “1”, the logic circuit 22 outputs the data signal d1 received at the terminal D from the terminal Q in synchronization with the clock CLK1 received at the terminal CK. The logic circuit 22 outputs, for example, “0” (low level) when reset. That is, in the example of FIG. 2, the initial value of the output signal q1 of the logic circuit 22 is “0”.

  The reset circuit 12 includes a control unit CNT2, an input selection unit ISEL2, and an output selection unit OSEL2. For example, the control unit CNT2, the input selection unit ISEL2, and the output selection unit OSEL2 correspond to the control unit CNT, the input selection unit ISEL, and the output selection unit OSEL shown in FIG.

  For example, the reset circuit 12 receives the soft reset signal RST, the clock CLK2, the input data DATA, the enable signal ENIN, and the output signal q1 of the logic circuit 22, and outputs the output signal DOUT to the logic circuit at the subsequent stage of the logic circuit 22. The input data DATA and the enable signal ENIN are, for example, input signals that are input to the logic circuit 22 during normal operation when the soft reset signal RST is not asserted, and correspond to the input signal DIN illustrated in FIG. The clocks CLK1 and CLK2 are output from, for example, a clock control circuit that controls supply and stop of the clock of the semiconductor device.

  Control unit CNT2 receives clock CLK2, soft reset signal RST, and output signal q1 of logic circuit 22. Then, the control unit CNT2 controls the input selection unit ISEL2 and the output selection unit OSEL2 based on the soft reset signal RST and the output signal q1 of the logic circuit 22.

  For example, when the output signal q1 of the logic circuit 22 is reset to the initial value at the reset timing based on the soft reset signal RST, the control unit CNT2 outputs the output signal q1 of the logic circuit 22 from the output selection unit OSEL2. The output selection unit OSEL2 is controlled. Then, when the output signal q1 of the logic circuit 22 is not reset to the initial value at the reset timing based on the soft reset signal RST, the control unit CNT2 outputs the initial value from the output selection unit OSEL2 To control. Note that when the soft reset signal RST is asserted, the control unit CNT2 may cause the output selection unit OSEL2 to output an initial value regardless of the value of the output signal q1 of the logic circuit 22.

  That is, for example, when the clock CLK1 is stopped before the reset timing based on the soft reset signal RST, the control unit CNT2 outputs an initial value from the output selection unit OSEL2 in response to the soft reset signal RST. The output selection unit OSEL2 is controlled. For example, when the output signal q1 of the logic circuit 22 is not reset to the initial value at the reset timing based on the soft reset signal RST, the control unit CNT2 sets the predetermined value until the output signal q1 is reset to the initial value. The input selection unit ISEL2 is controlled so as to be output to the logic circuit 22.

  The control unit CNT2 includes, for example, AND circuits AND1, AND2, AND3, OR circuits OR1, OR2, inverters INV1, INV2, and a flip-flop circuit FF1. The AND circuit AND1 outputs a logical product result (signal rstart) of the soft reset signal RST and the output signal q1 of the logic circuit 22 to the OR circuits OR1 and OR2. The inverter INV1 outputs an inverted signal of the output signal q1 to the AND circuit AND2.

  The AND circuit AND2 outputs a logical product result (signal lend) of the inverted signal of the output signal q1 and the output signal sel_out of the flip-flop circuit FF1 to the OR circuit OR1 and the inverter INV2. The OR circuit OR1 outputs a logical sum (enable signal en2) of the output signal rstart of the AND circuit AND1 and the output signal rend of the AND circuit AND2 to the enable terminal EN of the flip-flop circuit FF1.

  For example, when the enable signal en2 is “1”, the flip-flop circuit FF1 outputs the soft reset signal RST received at the terminal D from the terminal Q in synchronization with the clock CLK2 received at the terminal CK. The output signal sel_out of the flip-flop circuit FF1 is output to the AND circuit AND2, the OR circuit OR2, and the output selection unit OSEL2. That is, the soft reset signal RST is output as the output signal sel_out to the AND circuit AND2, the OR circuit OR2, and the output selection unit OSEL2 when the enable signal en2 is “1”.

  The OR circuit OR2 outputs a logical sum result of the output signal rstart of the AND circuit AND1 and the output signal sel_out of the flip-flop circuit FF1 to the AND circuit AND3. The inverter INV2 outputs an inverted signal of the output signal rend of the AND circuit AND2 to the AND circuit AND3. The AND circuit AND3 outputs a logical product result (signal sel_in) of the inverted signal of the output signal rend of the AND circuit AND2 and the output signal of the OR circuit OR2 to the input selection unit ISEL2.

  The input selection unit ISEL2 receives the input data DATA, the enable signal ENIN, and the output signal sel_in of the control unit CNT2, and outputs the data signal d1 and the enable signal en1 input to the logic circuit 22 to the logic circuit 22. For example, the input selection unit ISEL2 outputs either the predetermined value input data ("0") or the input data DATA for resetting the logic circuit 22 in accordance with the output signal sel_in of the control unit CNT2. Output to terminal D. Furthermore, the input selection unit ISEL2 outputs either an enable signal (“1”) having a predetermined value for resetting the logic circuit 22 or the enable signal ENIN in accordance with the output signal sel_in of the control unit CNT2. Output to enable terminal EN.

  For example, the input selection unit ISEL2 includes an inverter INV3, an AND circuit AND4, and an OR circuit OR3. The inverter INV3 outputs an inverted signal of the output signal sel_in of the control unit CNT2 to the AND circuit AND4. The AND circuit AND4 outputs a logical product result (data signal d1) of the inverted signal of the output signal sel_in and the input data DATA to the terminal D of the logic circuit 22. The OR circuit OR3 outputs the logical sum result (enable signal en1) of the output signal sel_in of the control unit CNT2 and the enable signal ENIN to the enable terminal EN of the logic circuit 22.

  The output selection unit OSEL2 receives the output signal q1 of the logic circuit 22 and the output signal sel_out of the control unit CNT2, and outputs the output signal DOUT to the logic circuit at the subsequent stage of the logic circuit 22. For example, the output selection unit OSEL2 selects either the initial value of the output signal q1 of the logic circuit 22 or the output signal q1 received from the logic circuit 22 in accordance with the output signal sel_out of the control unit CNT2. Is output as an output signal DOUT to the logic circuit. Thereby, the output selection unit OSEL2 responds to the soft reset signal RST with the initial value of the output signal q1 of the logic circuit 22 even when the clock CLK1 stops before the reset timing based on the soft reset signal RST, for example. Can output.

  For example, the output selection unit OSEL2 includes an inverter INV4 and an AND circuit AND5. The inverter INV4 outputs an inverted signal of the output signal sel_out of the control unit CNT2 to the AND circuit AND5. The AND circuit AND5 outputs a logical product result (output signal DOUT) of the inverted signal of the output signal sel_out and the output signal q1 of the logic circuit 22 to the logic circuit at the subsequent stage of the logic circuit 22. That is, the logic circuit at the subsequent stage of the logic circuit 22 receives the output signal DOUT of the reset circuit 12 as an output signal from the logic circuit 22.

  Note that the configuration of the reset circuit 12 is not limited to this example. For example, the reset circuit 12 only needs to be formed with a logic that matches an attribute such as an initial value of the logic circuit 22 to be initialized. For example, in the reset circuit 12 for resetting the plurality of logic circuits 22 corresponding to the plurality of bits of input data DATA, the control unit CNT2 may be provided in common by the plurality of logic circuits 22. In this case, even when the number of bits of the input data DATA increases, the number of control units CNT2 does not increase, so that it is possible to suppress an increase in power consumption of the reset circuit 12. The input selection unit ISEL2 and the output selection unit OSEL2 are provided corresponding to each of the plurality of logic circuits 22, for example.

  Further, the distinction between the control unit CNT2, the input selection unit ISEL2, and the output selection unit OSEL2 is not limited to this example. For example, the input selection unit ISEL2 may be defined including the AND circuit AND3, the OR circuit OR2, and the inverter INV2 of the control unit CNT2.

  FIG. 3 shows an example of the operation of the reset circuit 12 shown in FIG. FIG. 3 shows the operation of the reset circuit 12 when the clock CLK1 is stopped before the reset timing (time T1) based on the soft reset signal RST. The broken lines of the signals en1, d1, and q1 in FIG. 3 indicate a comparative example. In the comparative example, the control unit CNT2 and the output selection unit OSEL2 illustrated in FIG. 2 are omitted, and the soft reset signal RST is input to the input selection unit ISEL2 instead of the signal sel_in.

  In the example of FIG. 3, the output signal q1 of the logic circuit 22 immediately before the soft reset signal RST is asserted is “1” (high level). Further, the output signal sel_out of the control unit CNT2 immediately before the soft reset signal RST is asserted is “0” (low level). Therefore, the output signal DOUT immediately before the soft reset signal RST is asserted is “1”. The initial value of the output signal q1 is “0”. That is, when the logic circuit 22 is reset, the output signal q1 is initialized to “0”.

  First, in order to reset the logic circuit 22, the soft reset signal RST changes from “0” to “1” (FIG. 3A). The clock CLK1 stops before the reset timing (time T1) based on the soft reset signal RST. That is, the clock CLK1 stops before the logic circuit 22 is reset. As the soft reset signal RST changes from “0” to “1”, the signal rstart (the logical product of the soft reset signal RST and the output signal q1) changes from “0” to “1” (FIG. 3). (B)).

  As a result, the enable signal en2 of the flip-flop circuit FF1 (the logical sum of the signal rstart and the signal rend) changes from “0” to “1” (FIG. 3C). As a result, the output signal sel_out of the flip-flop circuit FF1 changes from “0” to “1” in synchronization with the rising edge of the clock CLK2 (FIG. 3D). As the output signal sel_out changes from “0” to “1”, the output signal DOUT changes from “1” to “0” (FIG. 3E). Note that the output signal q1 of the logic circuit 22 is maintained at “1” because the clock CLK1 is stopped before being reset.

  As described above, in this embodiment, even when the clock CLK1 is stopped before the logic circuit 22 is reset, in response to the soft reset signal RST, the initial value of the logic circuit 22 (an output signal indicating “0”). DOUT) can be output to the logic circuit downstream of the logic circuit 22. That is, in this embodiment, even when the clock CLK1 stops before the reset timing (time T1) based on the soft reset signal RST, the initial value of the logic circuit 22 is set in response to the soft reset signal RST. It can be output to the subsequent logic circuit. Therefore, in this embodiment, the initial value of the initialization target logic circuit 22 can be output to the subsequent logic circuit regardless of the value of the output signal q1 of the initialization target logic circuit 22 in the clock gating state.

  Also, when the soft reset signal RST changes from “0” to “1”, the signal rend is maintained at “0” because the output signal q1 is “1”. For this reason, the signal sel_in changes from “0” to “1” as the signal rstart changes from “0” to “1” (FIG. 3F). As a result, the enable signal en1 of the logic circuit 22 changes from “0” to “1” (FIG. 3G). Further, the data signal d1 to the logic circuit 22 changes from “1” to “0” (FIG. 3 (h)). In this way, the signals en1 and d1 received by the logic circuit 22 are set to predetermined values for resetting the logic circuit 22 in response to the soft reset signal RST.

  Then, when the soft reset signal RST changes from “1” to “0” (FIG. 3 (i)), the signal rstart changes from “1” to “0” (FIG. 3 (j)). As a result, the enable signal en2 of the flip-flop circuit FF1 changes from “1” to “0” (FIG. 3 (k)). For this reason, the output signal sel_out of the flip-flop circuit FF1 that has changed from “0” to “1” is maintained at “1” even when the soft reset signal RST has changed from “1” to “0” ( FIG. 3 (d, l)). Since the signal sel_out is maintained at “1”, the output signal DOUT that has changed from “1” to “0” becomes “0” even when the soft reset signal RST changes from “1” to “0”. Maintained (FIG. 3 (e, m)).

  Further, since the signal sel_out and the signal rend are maintained at “1” and “0”, respectively, the signal sel_in is also set to “1” even when the soft reset signal RST changes from “1” to “0”. Is maintained (FIG. 3 (n)). Thus, the enable signal en1 and the data signal d1 are maintained at “1” and “0”, respectively, even when the soft reset signal RST changes from “1” to “0” (FIG. 3 (o, p )).

  In the comparative example, the enable signal en1 and the data signal d1 change to “0” and “1”, respectively, when the soft reset signal RST changes from “1” to “0” (broken lines in FIG. 3). In the comparative example, since the output signal q1 (“1”) of the logic circuit 22 is output to the subsequent logic circuit, the initial value (“0”) of the logic circuit 22 is not output to the subsequent logic circuit. For this reason, in the comparative example, the operation of the logic circuit and the like subsequent to the logic circuit 22 becomes unstable. On the other hand, in this embodiment, since the initial value of the logic circuit 22 (the output signal DOUT indicating “0”) is output to the logic circuit at the subsequent stage of the logic circuit 22, It is possible to prevent the operation from becoming unstable.

  Next, supply of the clock CLK1 is resumed at time T2. At this time, since the enable signal en1 of the logic circuit 22 and the data signal d1 to the logic circuit 22 are maintained at “1” and “0”, respectively, the output signal q1 of the logic circuit 22 is changed from “1” to “0”. ("(Q) in FIG. 3)". Thus, since the signals en1 and d1 are maintained at the predetermined values for resetting the logic circuit 22, the logic circuit 22 is reset when the supply of the clock CLK1 is resumed.

  That is, when the output signal q1 of the logic circuit 22 is not reset to the initial value (“0”) at the reset timing (time T1) based on the soft reset signal RST, the signal is output until the output signal q1 is reset to the initial value. en1 and d1 are maintained at predetermined values. For example, when the output signal q1 of the logic circuit 22 is not reset to the initial value at the reset timing based on the soft reset signal RST, the input selection unit ISEL2 continues until the output signal q1 of the logic circuit 22 is reset to the initial value. A predetermined value is output to the logic circuit 22.

  In the comparative example, since the enable signal en1 and the data signal d1 are maintained at “0” and “1”, respectively, the output signal q1 of the logic circuit 22 is maintained at “1” (the broken line in FIG. 3). ). That is, in the comparative example, the logic circuit 22 is not reset even when the supply of the clock CLK1 is resumed. On the other hand, in this embodiment, since the signals en1 and d1 are maintained at predetermined values for resetting the logic circuit 22, the logic circuit 22 can be reset when the supply of the clock CLK1 is resumed.

  Further, since the signal sel_out is “1”, the signal rend changes from “0” to “1” when the output signal q1 changes from “1” to “0” (FIG. 3 (r)). . As a result, the enable signal en2 of the flip-flop circuit FF1 changes from “0” to “1” (FIG. 3 (s)).

  As the signal rend changes from “0” to “1”, the signal sel_in changes from “1” to “0” (FIG. 3 (t)). Thus, the enable signal ENIN and the input data DATA are input to the logic circuit 22 as the enable signal en1 and the data signal d1, respectively. For example, the enable signal en1 and the data signal d1 change to “0” and “1”, respectively (FIG. 3 (u)).

  As described above, the control unit CNT2 controls the input selection unit ISEL2 so that the enable signal ENIN and the input data DATA are output from the input selection unit ISEL2 to the logic circuit 22 after the output signal q1 is reset to the initial value. . Thereby, the logic circuit 22 can operate normally when the supply of the clock CLK1 is resumed.

  At time T3, the soft reset signal RST and the enable signal en2 of the flip-flop circuit FF1 are “0” and “1”, respectively. For this reason, the output signal sel_out of the flip-flop circuit FF1 changes from “1” to “0” in synchronization with the rising edge of the clock CLK2 (FIG. 3 (v)). As a result, the signal rend changes from “1” to “0” (FIG. 3 (w)). As a result, the enable signal en2 of the flip-flop circuit FF1 changes from “1” to “0” ((x) in FIG. 3). Therefore, the output signal sel_out of the flip-flop circuit FF1 that has changed from “1” to “0” is maintained at “0” (FIG. 3 (v, y)).

  Since the signal sel_out is maintained at “0” after time T3, the output signal q1 of the logic circuit 22 is output as an output signal DOUT to the logic circuit at the subsequent stage of the logic circuit 22. That is, after time T3, the logic circuit 22 returns to a normal operation in which the soft reset signal RST is not asserted. For example, when the enable signal ENIN changes to “1”, the output signal q1 of the logic circuit 22 changes from “0” to “1” in synchronization with the rising edge of the clock CLK1 (FIG. 3 (z)). As a result, the output signal DOUT changes from “0” to “1”.

  As described above, the control unit CNT2 controls the output selection unit OSEL2 so that the output signal q1 of the logic circuit 22 is output from the output selection unit OSEL2 when the logic circuit 22 operates in synchronization with the clock CLK1. . As a result, the logic circuit subsequent to the logic circuit 22 can operate normally when the supply of the clock CLK1 is resumed.

  Note that when the clock CLK1 is stopped after the reset timing (time T1) based on the soft reset signal RST, the output signal q1 of the logic circuit 22 is reset to “0”. To “0”.

  FIG. 4 shows an example of the semiconductor device 100 on which the reset circuit 12 shown in FIG. 2 is mounted. The semiconductor device 100 includes, for example, a reset circuit 12, a logic circuit 22, a CPU 110, a clock control circuit 120, and logic circuits 130 and 140. The minimum configuration of the semiconductor device 100 is the reset circuit 12 and the logic circuit 22.

  For example, the CPU 110 controls the operation of the semiconductor device 100. For example, the CPU 110 controls the clock control circuit 120 to control supply and stop of the clock CLK1. For example, the CPU 110 outputs the soft reset signal RST to the reset circuit 12 and asserts the soft reset signal RST when resetting the logic circuit 22.

  The clock control circuit 120 controls the supply and stop of the clocks CLK1, CLK2, CLK3, and CLK4, for example, according to the control of the CPU 110. For example, the clock control circuit 120 outputs clocks CLK1, CLK2, CLK3, and CLK4 to the logic circuit 22, the reset circuit 12, the logic circuit 130, and the logic circuit 140, respectively, during normal operation. Further, for example, when the power consumption is reduced by clock gating, the clock control circuit 120 stops the clock CLK1 supplied to the logic circuit 22 according to the control of the CPU 110.

  The logic circuit 130 is a preceding logic circuit of the logic circuit 22 and operates in synchronization with the clock CLK3. For example, the logic circuit 130 outputs the enable signal ENIN and the input data DATA to the reset circuit 12. The logic circuit 140 is a logic circuit subsequent to the logic circuit 22, and operates in synchronization with the clock CLK4. For example, the logic circuit 140 receives the output signal DOUT from the reset circuit 12.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. For example, the output selection unit OSEL2 of the reset circuit 12 outputs the initial value of the logic circuit 22 to the logic circuit 140 subsequent to the logic circuit 22 in response to the soft reset signal RST even when the clock CLK1 is stopped. Thereby, in this embodiment, the initial value of the initialization target logic circuit 22 can be output to the subsequent stage logic circuit 140 regardless of the value of the output signal q1 of the initialization target logic circuit 22 in the clock gating state. As a result, in this embodiment, it is possible to prevent the operation of the logic circuit 140 and the like from becoming unstable while reducing power consumption by clock gating.

  Further, for example, when the output signal q1 of the logic circuit 22 is not reset to the initial value at the reset timing based on the soft reset signal RST, the input selection unit ISEL2 of the reset circuit 12 sets the output signal q1 of the logic circuit 22 to the initial value. The predetermined value is output to the logic circuit 22 until it is reset to. Thereby, in this embodiment, when the supply of the clock CLK1 is resumed, the logic circuit 22 can be reset.

  FIG. 5 shows an example of the reset circuit 14 in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The reset circuit 14 of this embodiment has a control unit CNT4 instead of the control unit CNT2 shown in FIG. The input selection unit ISEL2 receives the soft reset signal RST instead of the output signal sel_in. Other configurations of the reset circuit 14 are the same as those in the embodiment described with reference to FIGS. For example, the reset circuit 14 is mounted on an LSI or the like including the logic circuit 22. The semiconductor device of this embodiment is the same as the embodiment described with reference to FIGS. 2 to 4 except that a reset circuit 14 is provided instead of the reset circuit 12.

  The reset circuit 14 receives, for example, the soft reset signal RST, the clock CLK2, the input data DATA, the enable signal ENIN, and the output signal q1 of the logic circuit 22, and outputs the output signal DOUT to the logic circuit subsequent to the logic circuit 22. For example, the reset circuit 14 includes a control unit CNT4, an input selection unit ISEL2, and an output selection unit OSEL2. The configuration of the input selection unit ISEL2 of the reset circuit 14 and the configuration of the output selection unit OSEL2 are the same as the input selection unit ISEL2 and the output selection unit OSEL2 of the reset circuit 12 shown in FIG.

  The input selection unit ISEL2 receives the input data DATA, the enable signal ENIN, and the soft reset signal RST, and outputs the data signal d1 and the enable signal en1 according to the soft reset signal RST. For example, when the soft reset signal RST is “1”, the input selection unit ISEL2 outputs a predetermined value (“0” data signal d1 and “1” enable signal en1) for the logic circuit 22 to reset the logic circuit 22. 22 to output. Further, for example, when the soft reset signal RST is “1”, the input selection unit ISEL2 outputs the enable signal en1 of “1” to the enable terminal EN of the flip-flop circuit FF1.

  For example, the control unit CNT4 receives the clock CLK2 and the soft reset signal RST, and controls the output selection unit OSEL2 based on the soft reset signal RST. For example, in the control unit CNT4, AND circuits AND1, AND2, AND3, OR circuits OR1, OR2, and inverters INV1, INV2 are omitted from the control unit CNT2 shown in FIG. That is, the control unit CNT4 has a flip-flop circuit FF1.

  The flip-flop circuit FF1 receives the soft reset signal RST at the terminal D, receives the logical sum result (enable signal en1) of the soft reset signal RST and the enable signal ENIN at the enable terminal EN, and receives the clock CLK2 at the terminal CK. For example, when the enable signal en1 is “1”, the flip-flop circuit FF1 outputs the soft reset signal RST as the output signal sel_out from the terminal Q to the output selection unit OSEL2 in synchronization with the clock CLK2.

  Thereby, the output selection unit OSEL2 responds to the soft reset signal RST with the initial value of the output signal q1 of the logic circuit 22 even when the clock CLK1 stops before the reset timing based on the soft reset signal RST, for example. Can output. That is, the logic circuit at the subsequent stage of the logic circuit 22 can receive the initial value of the logic circuit 22 from the reset circuit 14 even when the clock CLK1 is stopped before the reset timing based on the soft reset signal RST.

  When the supply of the clock CLK1 is resumed, the output signal sel_out of the flip-flop circuit FF1 changes to “0”, for example, when the enable signal ENIN for enabling the logic circuit 22 changes to “1”. As a result, the output signal q1 of the logic circuit 22 is output to the logic circuit subsequent to the logic circuit 22 as the output signal DOUT.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  10, 12, 14... Reset circuit; 20, 22, 130, 140 Logic circuit; 110 CPU; 120 Clock control circuit; CNT, CNT2, CNT4 Control unit; ISEL, ISEL2 Input selection unit; OSEL, OSEL2 Output selector

Claims (10)

A reset circuit that resets a logic circuit that operates in synchronization with a clock,
An output selection unit that receives an output signal of the logic circuit and outputs either the initial value of the output signal when the logic circuit is reset and the output signal received from the logic circuit;
A control unit that receives a reset signal for resetting the logic circuit and controls the output selection unit so that the initial value is output from the output selection unit in response to the reset signal. A featured reset circuit. The reset circuit further includes an input selection unit that receives an input signal and outputs either the predetermined value for resetting the logic circuit and the input signal to the logic circuit,
When the output signal is not reset to the initial value at the reset timing, the control unit outputs the predetermined value from the input selection unit to the logic circuit until the output signal is reset to the initial value. The reset circuit according to claim 1, wherein the input selection unit is controlled. The control unit controls the input selection unit so that the input signal is output from the input selection unit to the logic circuit after the output signal is reset to the initial value. 2. The reset circuit according to 2. The control unit controls the output selection unit so that the output signal of the logic circuit is output from the output selection unit when the logic circuit operates in synchronization with the clock. The reset circuit according to claim 1. The control unit controls the output selection unit so that the output signal of the logic circuit is output from the output selection unit when the output signal is reset to the initial value at the reset timing, 2. The reset circuit according to claim 1, wherein when the output signal is not reset to the initial value at a reset timing, the output selection unit is controlled so that the initial value is output from the output selection unit. . A logic circuit that operates in synchronization with the clock;
A reset circuit for resetting the logic circuit,
The reset circuit is
An output selection unit that receives an output signal of the logic circuit and outputs either the initial value of the output signal when the logic circuit is reset and the output signal received from the logic circuit;
A control unit that receives a reset signal for resetting the logic circuit and controls the output selection unit so that the initial value is output from the output selection unit in response to the reset signal. A featured semiconductor device. The reset circuit further includes an input selection unit that receives an input signal and outputs either the predetermined value for resetting the logic circuit and the input signal to the logic circuit,
When the output signal is not reset to the initial value at the reset timing, the control unit outputs the predetermined value from the input selection unit to the logic circuit until the output signal is reset to the initial value. The semiconductor device according to claim 6, wherein the input selection unit is controlled. The control unit controls the input selection unit so that the input signal is output from the input selection unit to the logic circuit after the output signal is reset to the initial value. 8. The semiconductor device according to 7. The control unit controls the output selection unit so that the output signal of the logic circuit is output from the output selection unit when the logic circuit operates in synchronization with the clock. The semiconductor device according to claim 6. The control unit controls the output selection unit so that the output signal of the logic circuit is output from the output selection unit when the output signal is reset to the initial value at the reset timing, The semiconductor device according to claim 6, wherein when the output signal is not reset to the initial value at a reset timing, the output selection unit is controlled such that the initial value is output from the output selection unit. .

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