JP2004069492A - Flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scan flip-flop circuit which can realize miniaturization of a circuit configuration and reduction of power consumption. <P>SOLUTION: The circuit comprises a scan data output part 22 which outputs scan data from a scan data output terminal Y when scan data input (SI) is selected by a selector 21 and locks output from the scan data output terminal Y when data input (D) is selected, and a delayed scan data input part 23 which allows delayed scan data input from a delayed scan data input terminal A when the scan data input (SI) is selected by the selector 21 and prohibits the delayed scan data input from the delayed scan data input terminal A when the when data input (D) is selected. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a flip-flop circuit used for a scan test.
[0002]
[Prior art]
FIG. 6 is a circuit diagram showing a scan flip-flop circuit connected during a conventional scan test. In the figure, reference numerals 1 and 2 denote scan flip-flop circuits, 3 denotes a logic circuit, and 4 denotes a delay circuit.
FIG. 7 is a circuit diagram showing a conventional scan flip-flop circuit. In the figure, reference numeral 11 denotes a two-input selector unit, D denotes a data input terminal, SI denotes a scan data input terminal, and SM denotes a scan mode input terminal. Reference numeral 12 denotes a D flip-flop unit, T denotes a clock input terminal, Q denotes a data output terminal, and QC denotes an inverted data output terminal.
[0003]
Next, the operation will be described.
The configuration of the scan flip-flop circuit at the time of the conventional scan test is to divide the output data into normal output data and scan test output data so that during normal operation the scan test output data is not output and no extra circuits are operated. However, in the case of this circuit configuration, it is necessary to add an AND gate for selecting one of the normal output data and the scan test output data.
[0004]
As another circuit configuration, when the output data of the scan flip-flop circuit 1 is not divided into the normal output data and the scan test output data as shown in FIG. Although the scan flip-flop circuit is small in size, the scan data input terminal SI becomes conductive as well as the data input terminal D of the scan flip-flop circuit 2 during normal operation, and extra power is consumed.
In particular, as shown in FIG. 6, when the delay circuit 4 is inserted to adjust the timing between the scan data input and the clock input, as the delay circuit 4 is inserted, the power consumption increases. I will.
[0005]
FIG. 7 shows details of the conventional scan flip-flop circuits 1 and 2.
Hereinafter, the operation of the scan flip-flop circuit will be described.
This scan flip-flop circuit has a circuit configuration in which a two-input selector unit 11 and a D flip-flop unit 12 are combined. In the two-input selector unit 11, a scan mode input from a scan mode input terminal SM is used. The data input from the data input terminal D or the scan data input from the scan data input terminal SI is selected. In addition, the D flip-flop unit 12 captures the data selected by the two-input selector unit 11 at the rise of the clock input from the clock input terminal T, and outputs the data from the data output terminal Q as an output synchronized with the clock input. At the same time, inverted data is output from the inverted data output terminal QC.
As shown in FIG. 6, this data output branches into a normal operation path having the logic circuit 3 and a scan test path having the delay circuit 4, and data is always propagated to both paths. That is, even during normal operation, data propagates to the delay circuit 4 on the scan test path, and the power consumption of the delay circuit 4 increases.
[0006]
[Problems to be solved by the invention]
Since the conventional scan flip-flop circuit is configured as described above, if the output data is divided into normal output data and scan test output data, and the scan test output data is not output during normal operation, It is necessary to add an AND gate for selecting one of the normal output data and the scan test output data, which increases the circuit configuration.
As another circuit configuration, when the output data of the scan flip-flop circuit 1 is not divided into the normal output data and the scan test output data as shown in FIG. Although the scan flip-flop circuit is small in size, the scan data input terminal SI becomes conductive similarly to the data input terminal D of the scan flip-flop circuit 2 during normal operation, and the power consumption is increased by the delay circuit 4, for example. There were challenges.
[0007]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a flip-flop circuit that achieves a smaller circuit configuration and lower power consumption.
[0008]
[Means for Solving the Problems]
A flip-flop circuit according to the present invention outputs scan data from a scan data output terminal when a scan data input is selected by a selector unit, and outputs an output of the scan data output terminal when a data input is selected by the selector unit. A scan data output section to be fixed, and when a scan data input is selected by the selector section, delayed scan data input (including no delay) from the delayed scan data input terminal is permitted, and data input is performed by the selector section. A delay scan data input section that inhibits delay scan data input from the delay scan data input terminal when selected, and a clock that uses the data input selected by the selector section or the delay scan data from the delay scan data input section as data. Synchronized data output That it is obtained by a D flip-flop unit.
[0009]
A flip-flop circuit according to the present invention includes a NOR gate having a scan data output unit to which a control signal and a scan data input from a selector unit are input, and a scan data output terminal connected to an output, and a delay scan data input unit. , And a transmission gate whose conduction is permitted and prohibited between the delay scan data input terminal and the input of the D flip-flop in response to a control signal from the selector.
[0010]
A flip-flop circuit according to the present invention is configured such that a scan data output unit includes a NAND gate having a control signal and a scan data input from a selector unit as inputs, and a scan data output terminal connected to an output, and a delay scan data input unit. , And a transmission gate whose conduction is permitted and prohibited between the delay scan data input terminal and the D flip-flop in response to a control signal from the selector.
[0011]
In a flip-flop circuit according to the present invention, in a scan data output unit, a first transmission gate in which conduction between a scan data input terminal and a scan data output terminal is enabled and disabled in response to a control signal from a selector unit; And a second transmission gate in which conduction between the control signal input from the selector unit and the scan data output terminal is enabled and disabled according to a control signal from the first transmission gate. In the delay scan data input unit, a third transmission gate is configured to enable and disable conduction between the delay scan data input terminal and the D flip-flop unit according to a control signal from the selector unit.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a scan flip-flop circuit according to a first embodiment of the present invention. In the figure, reference numeral 21 denotes a selector unit, D denotes a data input terminal, SI denotes a scan data input terminal, and SM denotes a scan mode input. Terminals, INV1 to INV3 are inverters, and TG4 is a transmission gate.
Reference numeral 22 denotes a scan data output unit, Y is a scan data output terminal, and NOR1 is a NOR gate.
23, a delay scan data input unit; A, a delay scan data input terminal; and TG3, a transmission gate (third transmission gate).
Reference numeral 12 denotes a D flip-flop unit, where D is a data input terminal, T is a clock input terminal, Q is a data output terminal, and QC is an inverted data output terminal.
FIG. 2 and FIG. 3 are circuit diagrams showing the symbolized scan flip-flop circuit.
[0013]
Next, the operation will be described.
1, this scan flip-flop circuit has a circuit configuration including a selector unit 21, a scan data output unit 22, a delay scan data input unit 23, and a D flip-flop unit 12.
First, as shown in FIG. 2 or FIG. 3, the scan data output terminal Y and the delay scan data input terminal A are directly connected or connected through a delay circuit. This delay circuit is provided to adjust the timing between the scan data input and the clock input, and is provided with a circuit that generates a desired delay amount according to the circuit configuration. In the selector section 21, when the scan mode input from the scan mode input terminal SM is at "H" level (= scan test mode), the output of the inverter INV1 becomes "L" level and the output of the inverter INV2 becomes "H" level. . As a result, the control signal of the "L" level is propagated to the NOR gate NOR1 of the scan data output unit 22, the transmission gate TG3 of the delay scan data input unit 23 is turned on, and the transmission gate TG4 of the selector unit 21 is turned off. .
As a result, scan data obtained by inverting the scan data input from the scan data input terminal SI is output from the NOR gate NOR1 to the scan data output terminal Y. Then, as shown in FIG. 2 or FIG. 3, delayed scan data is input to the delayed scan data input terminal A with or without delay. Further, since the transmission gate TG3 is on and the transmission gate TG4 is off, only the delayed scan data input through the transmission gate TG3 is input to the D flip-flop unit 12.
The D flip-flop unit 12 receives the delayed scan data input at the rising edge of the clock input from the clock input terminal T, outputs the data from the data output terminal Q as an output synchronized with the clock input, and outputs the inverted data output terminal QC To output inverted data.
[0014]
In the selector section 21, when the scan mode input from the scan mode input terminal SM is at the “L” level (= normal operation mode), the output of the inverter INV1 is at the “H” level, and the output of the inverter INV2 is at the “L” level. It becomes. As a result, an "H" level control signal is propagated to the NOR gate NOR1 of the scan data output unit 22, the transmission gate TG3 of the delay scan data input unit 23 is turned off, and the transmission gate TG4 of the selector unit 21 is turned on. .
As a result, the NOR gate NOR1 is logically fixed, and an "L" level fixed signal is output from the scan data output terminal Y. As a result, current does not flow through the delay circuit from the scan data output terminal Y to the delayed scan data input terminal A, and power consumption can be reduced.
Further, since the transmission gate TG3 is off and the transmission gate TG4 is on, only the data input from the data input terminal D is input to the D flip-flop unit 12, and the D flip-flop unit 12 similarly receives the clock input. At the rising edge of the clock input from the terminal T, the data input is taken in, the data is output from the data output terminal Q, and the inverted data is output from the inverted data output terminal QC.
[0015]
As described above, according to the first embodiment, if a delay circuit having a desired amount of delay is connected between scan data output terminal Y and delay scan data input terminal A, the desired delay can be achieved in scan test mode. In the normal operation mode, the scan data output unit 22 and the delay scan data input unit 23 are turned off, and the logic operation of the transistor is suppressed by the logic-fixed delay circuit. The power can be reduced.
Further, since the output data of the flip-flop circuit is not divided into the normal output data and the scan test output data, the circuit configuration can be reduced without providing a logic circuit such as an AND gate.
[0016]
Embodiment 2 FIG.
FIG. 4 is a circuit diagram showing a scan flip-flop circuit according to a second embodiment of the present invention. In the figure, reference numeral 31 denotes a scan data output unit, and NAND1 denotes a NAND gate. Other configurations are the same as those in FIG.
[0017]
Next, the operation will be described.
In the selector unit 21, when the scan mode input from the scan mode input terminal SM is at the “H” level (= scan test mode), the scan data input from the scan data input terminal SI to the scan data output terminal Y from the NAND gate NAND1. The inverted scan data is output. The delay scan data is input to the delay scan data input terminal A with or without delay, and the D flip-flop unit 12 receives the delay scan data input, outputs the data from the data output terminal Q, and outputs the inverted data. The inverted data is output from the terminal QC.
In the selector section 21, when the scan mode input from the scan mode input terminal SM is at the “L” level (= normal operation mode), the NAND gate NAND1 is logically fixed, and the “H” level is output from the scan data output terminal Y. A fixed signal is output. As a result, current does not flow through the delay circuit from the scan data output terminal Y to the delayed scan data input terminal A, and power consumption can be reduced. The D flip-flop unit 12 receives only the data input from the data input terminal D, outputs data from the data output terminal Q, and outputs inverted data from the inverted data output terminal QC.
[0018]
As described above, according to the second embodiment, the NOR gate NOR1 is used as the scan data output unit in the first embodiment, but the NAND gate NAND1 may be used, and the same effect can be obtained.
Although the output signal of the inverter INV2 is used as the control signal of the NOR gate NOR1 of the scan data output unit 31 from the selector unit 21, the scan mode signal may be directly used as the control signal.
[0019]
Embodiment 3 FIG.
FIG. 5 is a circuit diagram showing a scan flip-flop circuit according to Embodiment 3 of the present invention. In the figure, 32 is a scan data output unit, INV4 is an inverter, TG1 is a transmission gate (first transmission gate), TG2 is a transmission gate (second transmission gate). Other configurations are the same as those in FIG.
[0020]
Next, the operation will be described.
In the selector section 21, when the scan mode input from the scan mode input terminal SM is at the “H” level (= scan test mode), the transmission gate TG1 is turned on, the transmission gate TG2 is turned off, the transmission gate TG3 is turned on, and the transmission gate TG4 is turned on. Turns off. The scan data output terminal Y outputs the scan data obtained by inverting the scan data input from the scan data input terminal SI by the inverter INV4. The delay scan data is input to the delay scan data input terminal A with or without delay, and the D flip-flop unit 12 receives the delay scan data input, outputs the data from the data output terminal Q, and outputs the inverted data. The inverted data is output from the terminal QC.
In the selector section 21, when the scan mode input from the scan mode input terminal SM is at the “L” level (= normal operation mode), the transmission gate TG1 is off, the transmission gate TG2 is on, the transmission gate TG3 is off, and the transmission Gate TG4 turns on. A fixed signal is output from the scan data output terminal Y. As a result, current does not flow through the delay circuit from the scan data output terminal Y to the delayed scan data input terminal A, and power consumption can be reduced. The D flip-flop unit 12 receives only the data input from the data input terminal D, outputs data from the data output terminal Q, and outputs inverted data from the inverted data output terminal QC.
[0021]
As described above, according to the third embodiment, the NOR gate NOR1 is used as the scan data output unit in the first embodiment, but the inverter INV4, the transmission gate TG1, and the transmission gate TG2 may be used. The effect can be achieved.
[0022]
【The invention's effect】
As described above, according to the present invention, the scan data is output from the scan data output terminal when the scan data input is selected by the selector unit, and the scan data output terminal is output when the data input is selected by the selector unit. A scan data output section for fixing the output, and when the scan data input is selected by the selector section, delay scan data input (including no delay) from the delay scan data input terminal is permitted. A delay scan data input section that inhibits delay scan data input from the delay scan data input terminal when an input is selected, and a data input selected by the selector section or delay scan data from the delay scan data input section as data. D to output data synchronized with clock Since it is configured to have a flip-flop section, if a desired delay circuit is connected between the scan data output terminal and the delayed scan data input terminal, the timing between the delayed scan data input and the clock can be adjusted during the scan test. In addition, during normal operation, the output of the scan data output terminal is fixed, the input of the delay scan data input terminal is inhibited, and the transistor operation of the delay circuit is suppressed, so that power consumption can be reduced.
Further, since the output data of the flip-flop circuit is not divided into normal output data and scan test output data, there is an effect that the circuit configuration can be downsized without providing a logic circuit such as an AND gate.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a scan flip-flop circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a symbolized scan flip-flop circuit.
FIG. 3 is a circuit diagram illustrating a symbolized scan flip-flop circuit.
FIG. 4 is a circuit diagram showing a scan flip-flop circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a scan flip-flop circuit according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram showing a scan flip-flop circuit connected during a conventional scan test.
FIG. 7 is a circuit diagram showing a conventional scan flip-flop circuit.
[Explanation of symbols]
12 D flip-flop unit, 21 selector unit, 22, 31, 32 scan data output unit, 23 delay scan data input unit, A delay scan data input terminal, D data input terminal, INV1 to INV4 inverter, NAND1 NAND gate, NOR1 NOR gate, Q data output terminal, QC inverted data output terminal, SI scan data input terminal, SM scan mode input terminal, T clock input terminal, TG1 transmission gate (first transmission gate), TG2 transmission gate (second transmission gate), TG3 transmission gate (third transmission gate), TG4 transmission gate, Y scan data output terminal.

Claims (4)

A selector unit for selecting data input or scan data input according to the scan mode input,
A scan data output for outputting the scan data from the scan data output terminal when the scan data input is selected by the selector unit, and fixing the output of the scan data output terminal when the data input is selected by the selector unit Department and
When scan data input is selected by the selector unit, delayed scan data input (including no delay) from the delayed scan data input terminal is permitted, and when data input is selected by the selector unit, delayed scan data is input. A delayed scan data input section for inhibiting delayed scan data input from an input terminal;
A flip-flop circuit comprising: a D flip-flop unit that outputs data input selected by the selector unit or delayed scan data from the delayed scan data input unit as data in synchronization with a clock. The scan data output unit includes a NOR gate having a control signal and a scan data input from the selector unit as inputs, and a scan data output terminal connected to the output,
The delay scan data input unit is constituted by a transmission gate that enables and disables conduction between the delay scan data input terminal and the input of the D flip-flop unit according to a control signal from the selector unit. Item 2. The flip-flop circuit according to Item 1. The scan data output unit includes a NAND gate having a control signal and a scan data input from the selector unit as inputs, and a scan data output terminal connected to the output.
2. A delay gate according to claim 1, wherein said delay scan data input section comprises a transmission gate for permitting and prohibiting conduction between said delay scan data input terminal and said D flip-flop section in response to a control signal from said selector section. A flip-flop circuit as described. A scan data output unit, a first transmission gate for permitting and prohibiting conduction between the scan data input and scan data output terminals in response to a control signal from the selector unit;
In response to a control signal from the selector unit and with a logic contrary to the first transmission gate, conduction between the control signal input from the selector unit and the scan data output terminal is enabled and disabled. And a transmission gate.
The delay scan data input unit is characterized by comprising a third transmission gate for permitting and prohibiting conduction between the delay scan data input terminal and the D flip-flop unit according to a control signal from the selector unit. The flip-flop circuit according to claim 1.

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