Nothing Special   »   [go: up one dir, main page]

JP2012074660A - Semiconductor package substrate, and method of manufacturing the same - Google Patents

Semiconductor package substrate, and method of manufacturing the same Download PDF

Info

Publication number
JP2012074660A
JP2012074660A JP2010220344A JP2010220344A JP2012074660A JP 2012074660 A JP2012074660 A JP 2012074660A JP 2010220344 A JP2010220344 A JP 2010220344A JP 2010220344 A JP2010220344 A JP 2010220344A JP 2012074660 A JP2012074660 A JP 2012074660A
Authority
JP
Japan
Prior art keywords
insulating resin
resin layer
semiconductor package
package substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010220344A
Other languages
Japanese (ja)
Other versions
JP5640613B2 (en
Inventor
Jin Sato
尽 佐藤
Akihiro Hayashi
明宏 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2010220344A priority Critical patent/JP5640613B2/en
Publication of JP2012074660A publication Critical patent/JP2012074660A/en
Application granted granted Critical
Publication of JP5640613B2 publication Critical patent/JP5640613B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package substrate which improves the fluidity of underfill in mounting a semiconductor chip on the semiconductor package substrate and eliminates underfill void, and performs good connection between the semiconductor chip and the semiconductor package substrate, and to provide a method of manufacturing the same.SOLUTION: A light-shielding part 7c of a glass mask 7a arranged so as to be opposed to a surface of an uncured solder resist 7e is arranged at a position corresponding to a solder resist opening 7d of the uncured solder resist 7e. A gray-tone or half-tone part 7b having a light-shielding degree lower than that of the light-shielding part 7c is arranged around a position corresponding to the solder resist opening 7d of the uncured solder resist 7e and at a position corresponding to a part of the uncured solder resist 7e coating a solder connection terminal 7f. The uncured solder resist 7e is exposed and developed via the glass mask 7a to form a semiconductor package substrate A.

Description

本発明は、電子機器、電気機器、コンピューター、通信機器等に用いられる半導体パッケージ基板、特に、ＦＣ−ＢＧＡ基板（FC-BGA： Flip Cgip-Ball Grid Array）、ＣＳＰ基板（CSP： Chi Size Package）に用いる半導体パッケージ基板およびその製造方法に関する。   The present invention relates to semiconductor package substrates used in electronic devices, electrical devices, computers, communication devices, etc., in particular, FC-BGA substrates (FC-BGA: Flip Cgip-Ball Grid Array), CSP substrates (CSP: Chi Size Package). The present invention relates to a semiconductor package substrate used for manufacturing and a method for manufacturing the same.

半導体パッケージ基板の製造の際には、導体回路上を被覆する絶縁樹脂をロールコーター等により塗布し、露光、現像をすることで、絶縁樹脂膜を形成する。更に、露光、現像により設けた絶縁樹脂膜の開口部に半田を印刷等により形成することで半導体パッケージ基板となる。近年、高性能化、軽薄短小化の要求が進み、導体回路の細線化、半田接続端子（ランド、パッド等）の微細化に伴い、層間を電気的に接続するビアの小径化が進み、それらが多数存在する複雑な基板が形成されている。更に、ワイヤボンディング端子のないＦＣ−ＢＧＡやＣＳＰが開発され、高密度化に対応する為、急速に細線化、微細化が進んできている。   When manufacturing a semiconductor package substrate, an insulating resin that covers the conductor circuit is applied by a roll coater or the like, and exposed and developed to form an insulating resin film. Furthermore, a semiconductor package substrate is formed by forming solder by printing or the like in the opening of the insulating resin film provided by exposure and development. In recent years, there has been a demand for higher performance, lighter, thinner, and smaller conductors. As conductor circuits have become thinner and solder connection terminals (lands, pads, etc.) have become smaller, vias that electrically connect layers have become smaller in diameter. A complicated substrate in which a large number of is present is formed. In addition, FC-BGA and CSP without wire bonding terminals have been developed, and in order to cope with higher density, thinning and miniaturization are progressing rapidly.

半導体パッケージ基板における実装工程は、半導体パッケージ基板上の絶縁樹脂層の開口部と半導体チップ側の電極パッドを半田により接続し、半導体パッケージ基板と半導体チップの間隙をアンダーフィルにより充填する。アンダーフィルは毛細管現象により半導体パッケージ基板と半導体チップの間隙を流動するので、高密度化が進んだ半導体パッケージ基板では、回路、端子の細線化、微細化に伴いアンダーフィルが流動する間隙が狭くなる。このため、半導体チップ実装エリアの絶縁樹脂表面を平坦にしなくてはならない。   In the mounting process on the semiconductor package substrate, the opening of the insulating resin layer on the semiconductor package substrate and the electrode pad on the semiconductor chip side are connected by solder, and the gap between the semiconductor package substrate and the semiconductor chip is filled with underfill. Underfill flows through the gap between the semiconductor package substrate and the semiconductor chip due to a capillary phenomenon, and the semiconductor package substrate with higher density narrows the gap through which the underfill flows as the circuit and terminals become thinner and finer. . For this reason, the surface of the insulating resin in the semiconductor chip mounting area must be flattened.

例えば、特許文献１では、半導体パッケージ基板上に形成された導体回路を被覆する絶縁樹脂層の形成方法において、第一の絶縁樹脂層と第二の絶縁樹脂層からなり前記第一の樹脂層の表面を平坦にし、第二の絶縁樹脂層を形成する対策が提案されている。   For example, in Patent Document 1, in a method for forming an insulating resin layer that covers a conductor circuit formed on a semiconductor package substrate, the first resin layer includes a first insulating resin layer and a second insulating resin layer. A countermeasure for flattening the surface and forming the second insulating resin layer has been proposed.

また、特許文献２では、半導体パッケージ基板上に形成された絶縁樹脂を未硬化のまま過熱プレスして、その表面を平坦化し、露光・現像により開口部を形成することで、平坦な絶縁樹脂表面を得る対策が提案されている。   Further, in Patent Document 2, an insulating resin formed on a semiconductor package substrate is heated and pressed without being cured, the surface is flattened, and an opening is formed by exposure / development. Measures have been proposed.

特開２００４−１２８４０５号公報JP 2004-128405 A 特開２００１−２３７５４３号公報JP 2001-237543 A

上述した特許文献１に記載の発明では、第一の絶縁樹脂層を塗布、乾燥し、プレスにより平坦化した後に第二の絶縁樹脂層することで、平坦な樹脂表面を形成する。そして、第一、第二の絶縁樹脂層の形成後に露光、現像と硬化処理を実施する。   In the invention described in Patent Document 1 described above, the first insulating resin layer is applied, dried, flattened by pressing, and then the second insulating resin layer is formed to form a flat resin surface. Then, after forming the first and second insulating resin layers, exposure, development, and curing are performed.

また、特許文献２に記載の発明では、半導体パッケージ基板上に絶縁樹脂を形成した後に、金属板もしくは金属ロールを用いて、絶縁樹脂を押圧して平坦にする。   In the invention described in Patent Document 2, after an insulating resin is formed on a semiconductor package substrate, the insulating resin is pressed and flattened using a metal plate or a metal roll.

特許文献１の第一の絶縁樹脂層や特許文献２の絶縁樹脂層に対して、絶縁樹脂が未硬化のまま平坦化処置を施すと、導体回路部を被覆した絶縁樹脂部と導体回路部以外を被覆した絶縁樹脂部の絶縁樹脂層とが異なる厚みとなる。そのため、完全硬化後の絶縁樹脂層の硬化収縮量に差が生じ、導体回路部を被覆した絶縁樹脂部の高さが、導体回路部以外を被覆した絶縁樹脂部の高さより高くなる。これにより、硬化樹脂層の表面に凸部が複数形成される。凸部間のピッチは、半導体パッケージ基板に形成された導体回路の多層化やファインピッチ化に伴い、狭いものとなる。このように狭いピッチの凸部が硬化樹脂層の表面に多数形成されると、半導体チップを半導体パッケージ基板に実装し、アンダーフィルを充填する際に、アンダーフィルの毛細管現象による流動を絶縁樹脂表面の凸部が阻害する問題がある。   When the first insulating resin layer of Patent Document 1 and the insulating resin layer of Patent Document 2 are flattened while the insulating resin is uncured, other than the insulating resin part and the conductive circuit part covering the conductive circuit part The insulating resin layer of the insulating resin part coated with a different thickness. Therefore, a difference occurs in the amount of cure shrinkage of the insulating resin layer after complete curing, and the height of the insulating resin part covering the conductor circuit part becomes higher than the height of the insulating resin part covering other than the conductor circuit part. Thereby, a plurality of convex portions are formed on the surface of the cured resin layer. The pitch between the convex portions becomes narrow as the conductor circuit formed on the semiconductor package substrate becomes multilayered or fine pitched. When a large number of projections with such a narrow pitch are formed on the surface of the cured resin layer, when the semiconductor chip is mounted on the semiconductor package substrate and filled with the underfill, the flow caused by the capillary action of the underfill is prevented. There is a problem that the convex part of hinders.

本発明は、かかる従来技術の問題点に鑑み発明されたものであり、その目的は、半導体パッケージ基板に対する半導体チップの実装時のアンダーフィルの流動性が向上し、アンダーフィルボイドが解消され、半導体チップと半導体パッケージ基板が良好に接続される半導体パッケージ基板およびその製造方法を提供することを目的とする。   The present invention has been invented in view of the problems of the prior art, and the object thereof is to improve the fluidity of underfill when a semiconductor chip is mounted on a semiconductor package substrate, and to eliminate the underfill voids. It is an object of the present invention to provide a semiconductor package substrate in which a chip and a semiconductor package substrate are well connected and a method for manufacturing the same.

前記課題を解決する為の手段として、請求項１に記載の発明は、基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板において、前記絶縁樹脂層の前記半田接続端子を被覆した部分の表面高さが前記半田接続端子以外を被覆した部分の高さより０〜５μｍ低い位置にあることを特徴とする。   As a means for solving the above-mentioned problems, the invention according to claim 1 is characterized in that an opening for covering a conductor circuit formed on a substrate and a conductor circuit composed of a plurality of solder connection terminals and exposing the plurality of solder connection terminals is provided. In a semiconductor package substrate having an insulating resin layer having a portion formed from the surface side and a plurality of solder bumps for mounting a semiconductor chip formed by filling the opening with solder, the solder connection terminal of the insulating resin layer The surface height of the portion coated with is in a position lower by 0 to 5 μm than the height of the portion coated except for the solder connection terminals.

上記発明は、少なくとも半導体実装エリアに位置する前記半田接続端子を被覆した絶縁樹脂表面高さが前記半田接続端子以外を被覆した絶縁樹脂表面高さより０〜５μｍ低い位置であることを特徴とする半導体パッケージ基板である。絶縁樹脂とは半導体パッケージ基板上もしくは基板内に形成された導体回路を被覆する樹脂のことである。また、半導体実装エリアとは半導体パッケージ基板上に半導体チップを実装した際の半導体チップで覆われる領域のことである。
なお、前記各開口部は、前記半田接続端子側から前記絶縁樹脂層の表面側に向かうにつれて開口径が徐々に大きく広がる形状に形成されていてもよい。 The semiconductor according to the invention is characterized in that at least the insulating resin surface height covering the solder connection terminal located in the semiconductor mounting area is 0 to 5 μm lower than the insulating resin surface height covering other than the solder connection terminal. Package substrate. An insulating resin is a resin that covers a conductor circuit formed on or in a semiconductor package substrate. The semiconductor mounting area is an area covered with a semiconductor chip when the semiconductor chip is mounted on the semiconductor package substrate.
Each opening may be formed in a shape in which the opening diameter gradually widens from the solder connection terminal side toward the surface side of the insulating resin layer.

また、請求項３に記載の発明は、基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、前記絶縁樹脂層の表面に対向して配置したマスク部材の遮光部を、前記絶縁樹脂層の前記開口部に対応する箇所に配置し、前記遮光部よりも遮光度が低い半遮光部を、前記絶縁樹脂層の前記開口部に対応する箇所の周縁であって、かつ、前記絶縁樹脂層の前記半田接続端子を被覆した部分に対応する箇所に配置し、前記マスク部材を介して前記絶縁樹脂層の露光、現像を実施することにより形成したことを特徴とする半導体パッケージ基板の製造方法である。遮光部はクロム、エマルジョンを用いて形成することができる。ここで、クロム、エマルジョンとはガラスマスク上に形成するパターンの材質の種類のことであり、一般的にクロムのほうが、寸法精度が高い。また、グレートーンもしくはハーフトーン部によって半遮光部を構成することができる。ここで、グレートーンもしくはハーフトーンとは光を数〜数十％遮光するパターンを意味する。   According to a third aspect of the present invention, an opening is formed from the surface side so as to cover a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and to expose the plurality of solder connection terminals. A method of manufacturing a semiconductor package substrate having an insulating resin layer and a plurality of solder bumps for mounting a semiconductor chip formed by filling the opening with solder, and is disposed facing the surface of the insulating resin layer A light shielding portion of the mask member is disposed at a location corresponding to the opening of the insulating resin layer, and a semi-light shielding portion having a lower light shielding degree than the light shielding portion is provided at a location corresponding to the opening of the insulating resin layer. It was formed by performing exposure and development of the insulating resin layer through the mask member by disposing the peripheral resin at a location corresponding to the portion of the insulating resin layer covering the solder connection terminal. Special A semiconductor package substrate manufacturing method according to. The light shielding portion can be formed using chromium or an emulsion. Here, chrome and emulsion are the types of material of the pattern formed on the glass mask, and chrome generally has higher dimensional accuracy. In addition, the semi-light-shielding portion can be configured by the gray tone or the half-tone portion. Here, the gray tone or half tone means a pattern that blocks several to several tens of percent of light.

また、請求項４に記載の発明は、基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、前記絶縁樹脂層の表面を加熱プレスするプレス板に、突出高さが１〜４μｍの凸部を形成し、該凸部により、前記絶縁樹脂層の前記開口部に対応する箇所の周縁であって、かつ、前記絶縁樹脂層の前記半田接続端子を被覆した部分に対応する箇所を加熱プレスすると共に、前記プレス板の前記凸部以外の部分により、前記絶縁樹脂層の前記開口部に対応する箇所を加熱プレスすることにより形成したことを特徴とする半導体パッケージ基板の製造方法である。プレス板による加熱プレスの際には絶縁樹脂層の表面を保護フィルムにより予め被覆しておくことができる。保護フィルムとは、絶縁樹脂層の未硬化時に絶縁樹脂層表面にタック性がある場合の表面保護や露光による光硬化反応の酸素阻害防止のために設置されるもので、一般的にはポリエチレンテレフタレート（ＰＥＴ）にアクリル系の接着剤を設けた粘着ＰＥＴが用いられる。また、１〜４μｍの塗布部パターンを有するプレス板とは例えば、ＳＵＳ板を所望のパターンにフォトリソおよびエッチングを用いてパターニングしたものである。   According to a fourth aspect of the present invention, an opening is formed from the surface side so as to cover a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and to expose the plurality of solder connection terminals. A method of manufacturing a semiconductor package substrate having an insulating resin layer and a plurality of solder bumps for mounting a semiconductor chip formed by filling the opening with solder, wherein the press plate heat-presses the surface of the insulating resin layer A protrusion having a protrusion height of 1 to 4 μm, and the protrusion is a periphery of a portion corresponding to the opening of the insulating resin layer, and the solder connection terminal of the insulating resin layer. The portion corresponding to the portion coated with heat is heated and pressed, and the portion corresponding to the opening of the insulating resin layer is heated and pressed by a portion other than the convex portion of the press plate. A semiconductor package substrate manufacturing method according to. In the case of hot pressing with a press plate, the surface of the insulating resin layer can be previously coated with a protective film. Protective film is installed to protect the surface of the insulating resin layer when the insulating resin layer is uncured and to prevent oxygen inhibition of the photocuring reaction by exposure. Generally, polyethylene terephthalate Adhesive PET in which an acrylic adhesive is provided on (PET) is used. Moreover, the press plate having a coating part pattern of 1 to 4 μm is, for example, a SUS plate patterned in a desired pattern using photolithography and etching.

また、請求項５記載の発明は、請求項３又は４記載の発明において、前記絶縁樹脂層の表面を熱処理しながら平坦化処理し、硬化させた後に、前記開口部を形成したことを特徴とする半導体パッケージ基板の製造方法である。例えば、熱による硬化収縮が顕著に進む１００℃〜１５０℃の間の温度域のみ加熱プレスを実施し、硬化させながら、平坦化を実施し、硬化収縮による凹凸の発生を抑えることが可能となる。   The invention according to claim 5 is characterized in that, in the invention according to claim 3 or 4, the opening is formed after the surface of the insulating resin layer is planarized and cured while being heat-treated. A method for manufacturing a semiconductor package substrate. For example, it is possible to suppress the occurrence of unevenness due to curing shrinkage by performing heating pressing only in a temperature range between 100 ° C. and 150 ° C. where curing shrinkage due to heat is remarkable and curing. .

また、請求項６記載の発明は、基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、前記絶縁樹脂層の表面を熱処理しながら平坦化処理し、硬化させた後に、前記開口部を形成したことを特徴とする半導体パッケージ基板の製造方法である。請求項６記載の発明では、請求項５記載の発明と同様の効果を得ることができる。   According to a sixth aspect of the present invention, there is provided an insulation in which an opening for covering a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals on the substrate and exposing the plurality of solder connection terminals is formed from the surface side. A method of manufacturing a semiconductor package substrate having a resin layer and a plurality of solder bumps for mounting a semiconductor chip formed by filling the opening with solder, and planarizing the surface of the insulating resin layer while heat-treating it Then, the semiconductor package substrate manufacturing method is characterized in that the opening is formed after curing. In the invention described in claim 6, the same effect as that of the invention described in claim 5 can be obtained.

本発明によると半導体パッケージ基板の表面を被覆する絶縁樹脂層と半導体接続端子上を被覆した絶縁樹脂層の一部が開口し、半導体接続端子が露出した開口部からなり、半導体接続端子上に存在する絶縁樹脂層が半田接続端子以外を被覆した絶縁樹脂表面高さより０〜５μｍの位置である平坦部もしくは凹部の構造を有する絶縁樹脂表面を形成する。   According to the present invention, an insulating resin layer covering the surface of the semiconductor package substrate and a part of the insulating resin layer covering the semiconductor connection terminal are opened, and the semiconductor connection terminal is exposed to be present on the semiconductor connection terminal. An insulating resin surface having a structure of a flat portion or a concave portion at a position of 0 to 5 μm from the height of the surface of the insulating resin coating the insulating resin layer other than the solder connection terminals is formed.

その結果として、従来半導体接続端子上を被覆した絶縁樹脂層の硬化収縮の差による凸部分が平坦ないしは凹み構造となり、半導体チップ実装でのアンダーフィルの充填性が向上し、半導体パッケージ基板と半導体チップの実装歩留まりとか、その実装後の接続信頼性の向上とか微細化に伴う実装歩留まり、あるいは接続信頼性の低下を抑制できる絶縁樹脂層の表面形状の形成を実現できる。
また本発明によると、従来の設備での生産も可能となる。 As a result, the convex portion due to the difference in curing shrinkage of the insulating resin layer covering the conventional semiconductor connection terminal becomes a flat or concave structure, and the underfill filling property in the semiconductor chip mounting is improved, and the semiconductor package substrate and the semiconductor chip It is possible to realize the formation of the surface shape of the insulating resin layer that can suppress the mounting yield, the improvement of the connection reliability after the mounting, the mounting yield accompanying the miniaturization, or the decrease in the connection reliability.
Further, according to the present invention, it is possible to produce with conventional equipment.

本発明に係る絶縁樹脂層の表面形状の平坦部もしくは凹部は、加熱プレスの実施もしくは露光の実施により簡単に形成可能であり、絶縁樹脂層の表面を制御し、アンダーフィルの流動性を制御することで半導体パッケージ基板と半導体チップの接続信頼性を向上させるものである。   The flat portion or the concave portion of the surface shape of the insulating resin layer according to the present invention can be easily formed by performing hot pressing or exposure, and controls the surface of the insulating resin layer and controls the fluidity of the underfill. This improves the connection reliability between the semiconductor package substrate and the semiconductor chip.

また本発明は、半導体パッケージ基板だけに限って適用できるものではなく、絶縁樹脂材料を用いる部材を形成する際の表面形状の制御にも適用できる。   The present invention is not limited to the semiconductor package substrate, but can be applied to the control of the surface shape when forming a member using an insulating resin material.

一般的な半導体実装基板の半導体パッケージ基板と半導体チップの接続部を、従来の構造の要部拡大断面図と共に模式的な断面図で示す説明図である。It is explanatory drawing which shows the connection part of the semiconductor package board | substrate of a general semiconductor mounting board | substrate, and a semiconductor chip with typical sectional drawing with the principal part expanded sectional view of the conventional structure. 一般的な半導体パッケージ基板のコア層の一例を、模式的な断面図で示す説明図である。It is explanatory drawing which shows an example of the core layer of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板のビルドアップ層の製造方法の一例を、模式的な断面図で示す説明図である。It is explanatory drawing which shows an example of the manufacturing method of the buildup layer of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板の一例を、模式的な断面図で示す説明図である。It is explanatory drawing which shows an example of a common semiconductor package board | substrate with typical sectional drawing. 一般的な半導体パッケージ基板の絶縁樹脂層と半田による半導体接続端子の製造方法の一例を、模式的な断面図で示す説明図である。It is explanatory drawing shown in typical sectional drawing by an example of the manufacturing method of the semiconductor connection terminal by the insulating resin layer and solder of a common semiconductor package board | substrate. 本発明の一実施形態に係る半導体パッケージ基板の製造方法を、模式的な断面図で示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor package board | substrate which concerns on one Embodiment of this invention with typical sectional drawing. 本発明の他の実施形態に係る半導体パッケージ基板の製造方法を、模式的な断面図で示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor package board | substrate which concerns on other embodiment of this invention with typical sectional drawing. 一般的な製造方法により製造した半導体実装基板の不適切な構造の一例を、模式的な断面図で示す説明図である。It is explanatory drawing which shows an example of the unsuitable structure of the semiconductor mounting board manufactured with the general manufacturing method with typical sectional drawing. 本発明のさらに他の実施形態に係る半導体パッケージ基板の製造方法を、模式的な断面図で示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor package board | substrate which concerns on further another embodiment of this invention with typical sectional drawing. 本発明の実施形態に係る製造方法により製造した半導体パッケージ基板を、要部拡大断面図と共に模式的な断面図で示す説明図である。It is explanatory drawing which shows the semiconductor package board | substrate manufactured with the manufacturing method which concerns on embodiment of this invention with typical sectional drawing with the principal part expanded sectional view. 本発明の実施形態に係る製造方法により製造した半導体パッケージ基板を、要部拡大断面図と共に模式的な断面図で示す説明図である。It is explanatory drawing which shows the semiconductor package board | substrate manufactured with the manufacturing method which concerns on embodiment of this invention with typical sectional drawing with the principal part expanded sectional view.

本発明の実施の形態について、以下に図面を参照しながら説明する。
まず、本発明の実施形態の前提となる、一般的な半導体パッケージ基板と半導体チップの実装後の半田接続構造を図１に示す。半導体パッケージ基板Ａは内層回路２ａ（導体配線）と層間を電気的に接続するビアホール２ｂと半田接続端子２ｃと半田接続端子２ｃの一部以外を被覆した絶縁樹脂層２ｄおよび、絶縁樹脂層２ｄより露出した半田接続端子２ｃ上に半田バンプ２ｅを設けた構造である。実装時は半導体パッケージ基板Ａ側と半導体チップＢ側に半田が設けられているため、位置合わせによるマウント工程と、半田バンプ２ｅを溶融させて半導体パッケージ基板Ａと半導体チップＢを接続させるリフロー工程とにより、半導体パッケージ基板Ａと半導体チップＢとを接続する。また、上記工程を経て形成された、半導体パッケージ基板Ａと半導体チップＢとの間隙はアンダーフィル２ｆを充填することにより、半導体実装基板を得る。 Embodiments of the present invention will be described below with reference to the drawings.
First, FIG. 1 shows a solder connection structure after mounting a general semiconductor package substrate and a semiconductor chip, which is a premise of the embodiment of the present invention. The semiconductor package substrate A includes an insulating resin layer 2d covering the inner layer circuit 2a (conductor wiring) and a via hole 2b that electrically connects the layers, a solder connection terminal 2c, and a part other than the solder connection terminal 2c, and an insulating resin layer 2d. In this structure, solder bumps 2e are provided on the exposed solder connection terminals 2c. Since solder is provided on the semiconductor package substrate A side and the semiconductor chip B side at the time of mounting, a mounting process by alignment, a reflow process in which the solder bump 2e is melted and the semiconductor package substrate A and the semiconductor chip B are connected to each other. Thus, the semiconductor package substrate A and the semiconductor chip B are connected. Further, the gap between the semiconductor package substrate A and the semiconductor chip B formed through the above steps is filled with the underfill 2f, thereby obtaining a semiconductor mounting substrate.

一般的な製造工程により製造された従来の半導体パッケージ基板Ａと半導体チップＢとの接続部の拡大図を図１中に示す。従来の半導体パッケージ基板Ａの構造では、半導体パッケージ基板Ａ上に半田接続端子２ｃが存在する部分と存在しない部分とがあるために、後述する理由により、図１中の拡大図に示すように、半田接続端子２ｃ′の上に設けられた絶縁樹脂層２ｄ′の表面に凸の段差が形成される。そして、凸の段差が、アンダーフィル充填時の流動の妨げになる。よって、本発明では、予めこの段差を予想し、半田接続端子２ｃ′上の絶縁樹脂層２ｄ′の表面に凹構造を施し、意図的に完全硬化の硬化収縮により絶縁樹脂層２ｄの表面に平坦ないしは凹部を形成する。   FIG. 1 shows an enlarged view of a connection portion between a conventional semiconductor package substrate A and a semiconductor chip B manufactured by a general manufacturing process. In the structure of the conventional semiconductor package substrate A, since there are a portion where the solder connection terminal 2c is present and a portion where the solder connection terminal 2c is not present on the semiconductor package substrate A, as shown in an enlarged view in FIG. A convex step is formed on the surface of the insulating resin layer 2d 'provided on the solder connection terminal 2c'. And the convex level | step difference prevents the flow at the time of underfill filling. Therefore, in the present invention, this step is predicted in advance, and a concave structure is provided on the surface of the insulating resin layer 2d ′ on the solder connection terminal 2c ′, and the surface of the insulating resin layer 2d is intentionally flattened by complete curing and shrinkage. Or a recess is formed.

本発明では、平坦もしくは凹部の形成方法として、プレスによる形成と露光・現像による形成を提案する。
形成する凹みの量としては、絶縁樹脂層２ｄの硬化収縮量を考慮し、半田接続端子２ｃの導体厚みに対して５〜３０％の凹みを形成する。好ましくは絶縁樹脂層２ｄの硬化収縮率を予め測定し、完全硬化後に所望の平坦性、凹みを有するように形成する。
本発明の実施の形態の具体的な内容は、以下の、一般的な半導体パッケージ基板Ａの製造工程を説明した後で、詳細に説明する。 In the present invention, as a method for forming a flat or concave portion, formation by press and formation by exposure / development are proposed.
In consideration of the amount of cure shrinkage of the insulating resin layer 2d, the dent to be formed is 5 to 30% of the conductor thickness of the solder connection terminal 2c. Preferably, the curing shrinkage rate of the insulating resin layer 2d is measured in advance and formed so as to have desired flatness and dent after complete curing.
The specific contents of the embodiment of the present invention will be described in detail after the following manufacturing process of the general semiconductor package substrate A is described.

次に、一般的な半導体パッケージ基板Ａの製造工程について図を用いて説明する。半導体パッケージ基板Ａのコア層の構造を図２に示す。コア層３ａには、ガラスクロスにエポキシ樹脂等を含浸させた両面銅張り基板を用いており、ドリルによりスルーホール３ｂを形成し、パネルメッキとエッチングにより配線パターン３ｃを形成する。両面の導通はスルーホール形成後のパネルめっきにより確保する。   Next, a manufacturing process of a general semiconductor package substrate A will be described with reference to the drawings. The structure of the core layer of the semiconductor package substrate A is shown in FIG. For the core layer 3a, a double-sided copper-clad substrate in which a glass cloth is impregnated with an epoxy resin or the like is used, a through hole 3b is formed by a drill, and a wiring pattern 3c is formed by panel plating and etching. Conductivity on both sides is secured by panel plating after through-hole formation.

次いで、図３（ａ）にあるように、コア層４ａの両面に真空プレス機等を用いて、層間絶縁樹脂４ｂをラミネートする。次いで、図３（ｂ）に示すように、層間絶縁樹脂４ｂに埋め込まれた配線パターン４ｃをレーザーにより露出させビアホール４ｄを形成する。ここで、レーザーは炭酸ガスレーザー、ＵＶレーザー等が用いられる。次いで、図３（ｃ）に示すように、露出した配線パターン４ｃと層間絶縁樹脂４ｂ上に形成する半田接続端子４ｃ′（図３（ｅ）参照）とを電気的に接続する為に、無電解銅メッキ４ｅを形成し、感光性ドライフィルムレジスト４ｆを、層間絶縁樹脂４ｂの表面のうち半田接続端子４ｃ′（図３（ｅ）参照）が形成されない領域に設ける。   Next, as shown in FIG. 3A, an interlayer insulating resin 4b is laminated on both surfaces of the core layer 4a using a vacuum press or the like. Next, as shown in FIG. 3B, the wiring pattern 4c embedded in the interlayer insulating resin 4b is exposed by a laser to form a via hole 4d. Here, a carbon dioxide laser, a UV laser, or the like is used as the laser. Next, as shown in FIG. 3C, in order to electrically connect the exposed wiring pattern 4c and the solder connection terminal 4c '(see FIG. 3E) formed on the interlayer insulating resin 4b, The electrolytic copper plating 4e is formed, and the photosensitive dry film resist 4f is provided in the area of the surface of the interlayer insulating resin 4b where the solder connection terminal 4c ′ (see FIG. 3E) is not formed.

次いで、図３（ｄ）に示すように、各ビアホール４ｄと、隣り合う感光性ドライフィルムレジスト４ｆ、４ｆの間の空間とに、それぞれパターンメッキ４ｇを施して、半田接続端子４ｃ′を形成した後に、図３（ｅ）に示すように、感光性ドライフィルムレジスト４ｆを苛性ソーダ４ｈにより剥離する。次いで、図３（ｆ）に示すように、半田接続端子４ｃ′を形成しない領域の無電解銅メッキ４ｅをエッチングにより除去し、ビルドアップ層の１層分が完成する。この工程を所望の層数分繰り返し行い、図４に示す３次元配線基板Ｃを形成する。   Next, as shown in FIG. 3D, pattern plating 4g is applied to each via hole 4d and the space between adjacent photosensitive dry film resists 4f and 4f to form solder connection terminals 4c '. After that, as shown in FIG. 3E, the photosensitive dry film resist 4f is peeled off with caustic soda 4h. Next, as shown in FIG. 3F, the electroless copper plating 4e in the region where the solder connection terminal 4c ′ is not formed is removed by etching, and one build-up layer is completed. This process is repeated for the desired number of layers to form the three-dimensional wiring board C shown in FIG.

次いで、ソルダーレジスト層の形成を図５を用いて説明する。図４の３次元配線基板Ｃによって構成される半導体パッケージ基板Ａの最外層にロールコーターもしくはスクリーン印刷によりソルダーレジストを塗工し、乾燥することで、図５（ａ）に示すように、未硬化ソルダーレジスト６ａを形成する。また、ソルダーレジストが半硬化樹脂の場合は真空ラミネータ等により、ラミネートにて未硬化ソルダーレジスト６ａを形成する。次いで、図５（ｂ）に示すように、乾燥した未硬化ソルダーレジスト６ａ上に絶縁樹脂保護用フィルム６ｂを、ロールラミネーター等を用いて貼付する。   Next, the formation of the solder resist layer will be described with reference to FIG. As shown in FIG. 5 (a), a solder resist is applied to the outermost layer of the semiconductor package substrate A constituted by the three-dimensional wiring substrate C of FIG. 4 by a roll coater or screen printing, and is dried, as shown in FIG. A solder resist 6a is formed. When the solder resist is a semi-cured resin, the uncured solder resist 6a is formed by lamination using a vacuum laminator or the like. Next, as shown in FIG. 5B, the insulating resin protective film 6b is pasted onto the dried uncured solder resist 6a using a roll laminator or the like.

次いで、図５（ｃ）に示すように、半導体チップＢ用の接続端子を露出する為に、所望の露出部分をガラスマスク等の遮光パターン６ｃにてマスキングし、露光によりマスキング部以外の未硬化ソルダーレジスト６ａを光硬化させ、露光後に、図５（ｄ）に示すように、絶縁樹脂保護用フィルム６ｂを剥離して現像を行い、ソルダーレジスト開口部６ｄを形成する。現像に使用する現像液６ｆは通常１ｗｔ％のＮａ２ ＣＯ３ を用いる。 Next, as shown in FIG. 5C, in order to expose the connection terminals for the semiconductor chip B, a desired exposed portion is masked with a light shielding pattern 6c such as a glass mask, and the uncured portions other than the masking portion are exposed by exposure. The solder resist 6a is photocured, and after exposure, as shown in FIG. 5D, the insulating resin protective film 6b is peeled off and developed to form the solder resist opening 6d. As a developing solution 6f used for development, 1 wt% Na 2 CO 3 is usually used.

なお、未硬化ソルダーレジスト６ａを構成する絶縁樹脂としては熱硬化性樹脂か光硬化性樹脂もしくは両方の特性を有した樹脂を用いる。熱硬化性の樹脂としてはエポキシ樹脂、ポリイミド樹脂、フェノール樹脂、ポリエステル樹脂等を用いることができ、光硬化性樹脂としてはアクリル樹脂が用いることができる。あるいは、両方の特性を保持させる為に例えば、熱硬化樹脂の熱硬化機能を有する官能基をアクリル酸や、メタクリル酸などと反応させてアクリレート化する。即ち、半導体パッケージ基板Ａを被覆する絶縁樹脂としては、エポキシ樹脂もしくはポリイミド樹脂のアクリル化したものが好ましい。   As the insulating resin constituting the uncured solder resist 6a, a thermosetting resin, a photocurable resin, or a resin having both characteristics is used. An epoxy resin, a polyimide resin, a phenol resin, a polyester resin, or the like can be used as the thermosetting resin, and an acrylic resin can be used as the photocurable resin. Alternatively, in order to maintain both characteristics, for example, a functional group having a thermosetting function of a thermosetting resin is reacted with acrylic acid or methacrylic acid to acrylate. That is, the insulating resin that covers the semiconductor package substrate A is preferably an acrylated epoxy resin or polyimide resin.

乾燥後の未硬化ソルダーレジスト６ａの表面にはタックがある為、通常、図５（ｂ）に示す絶縁樹脂保護用フィルム６ｂを未硬化ソルダーレジスト６ａの表面に設ける。絶縁樹脂保護用フィルム６ｂは光透過性に優れたものであれば良く、例えば、ポリエチレン、ポリプロピレン、ポリブテン等のポリオレフィン、エチレン−ビニルアルコール共重合体、ポリスチレン、ポリエチレンテレフタレート、ポリエステル、ポリブチレンテレフタレート、ポリイミド等の樹脂からなるもの等が挙げられる。特に、透明性の高いフィルムである汎用のポリエチレンテレフタレート、ポリエチレン、ポリエチレンテレフタレート等が好ましい。絶縁樹脂保護用フィルム６ｂの基材フィルムの厚みは２〜５０μｍ、好ましくは４〜２０μｍが光透過性の観点から適している。   Since there is a tack on the surface of the uncured solder resist 6a after drying, an insulating resin protecting film 6b shown in FIG. 5B is usually provided on the surface of the uncured solder resist 6a. The insulating resin protecting film 6b may be any film having excellent light transmission properties, for example, polyolefins such as polyethylene, polypropylene, and polybutene, ethylene-vinyl alcohol copolymers, polystyrene, polyethylene terephthalate, polyester, polybutylene terephthalate, and polyimide. And the like made of a resin such as In particular, general-purpose polyethylene terephthalate, polyethylene, polyethylene terephthalate and the like, which are highly transparent films, are preferable. The thickness of the base film of the insulating resin protective film 6b is 2 to 50 μm, preferably 4 to 20 μm from the viewpoint of light transmittance.

次いで、図５（ｄ）の絶縁樹脂保護用フィルム６ｂが表面に形成された未硬化ソルダーレジスト６ａを完全硬化させるために、熱と光の２次処理を実施する。次いで、図５（ｅ）に示すように、ソルダーレジスト開口部６ｄに、印刷により半田インキを印刷し、リフローを実施することにより、図５（ｅ）に示す半田バンプ６ｅを形成する。これにより、半導体パッケージ基板Ａとなる。   Next, in order to completely cure the uncured solder resist 6a having the insulating resin protecting film 6b shown in FIG. 5D formed on the surface, a secondary heat and light treatment is performed. Next, as shown in FIG. 5 (e), solder bumps 6e shown in FIG. 5 (e) are formed by printing solder ink on the solder resist opening 6d by printing and performing reflow. As a result, the semiconductor package substrate A is obtained.

半導体パッケージ基板Ａ上に絶縁樹脂による未硬化ソルダーレジスト６ａの層を形成する方法としては、絶縁樹脂が液状の場合、スクリーン印刷法、スプレイコート法、ロールコート法等により塗布する。半導体パッケージ基板Ａにおいては基板の両面に同時塗布可能なロールコート法が好ましい。また、シート状のフィルムをラミネート法により形成しても良い。この場合、真空ロールラミネート法、真空プレス法等での形成方法がある。   As a method of forming an uncured solder resist 6a layer made of an insulating resin on the semiconductor package substrate A, when the insulating resin is liquid, it is applied by a screen printing method, a spray coating method, a roll coating method or the like. In the semiconductor package substrate A, a roll coating method capable of simultaneous application on both surfaces of the substrate is preferable. A sheet-like film may be formed by a laminating method. In this case, there are forming methods such as a vacuum roll laminating method and a vacuum pressing method.

インク塗布後の乾燥は５０〜１００℃の温度域で行われ、インクにより適宜乾燥温度と時間を設定する。   Drying after ink application is performed in a temperature range of 50 to 100 ° C., and the drying temperature and time are appropriately set depending on the ink.

図５で説明した製造方法の場合、半導体パッケージ基板Ａの半導体接続端子４ｃ′（図３（ｆ）参照）の存在する所と存在しない所とによる凹凸形状が存在する為、液状の絶縁樹脂を塗布する工程による未硬化ソルダーレジスト６ａの表面に凹凸が生じる。そのため、未硬化ソルダーレジスト６ａに対する熱と光の２次処理をする工程により、半導体接続端子４ｃ′（図３（ｆ）参照）を覆う未硬化ソルダーレジスト６ａの領域と半導体接続端子４ｃ′（図３（ｆ）参照）を覆っていない未硬化ソルダーレジスト６ａの領域とで、絶縁樹脂層４ｂの硬化収縮量の差が発生し、半導体接続端子４ｃ′（図３（ｆ）参照）の表面よりも更に凹凸が大きくなる。この凹凸が未硬化ソルダーレジスト６ａの表面に存在することは、半導体チップＢの実装に伴うアンダーフィルの充填時の流動性を低下させる要因となる。   In the case of the manufacturing method described with reference to FIG. 5, since there is an uneven shape depending on where the semiconductor connection terminal 4c ′ (see FIG. 3 (f)) of the semiconductor package substrate A is present, the liquid insulating resin is used. Concavities and convexities occur on the surface of the uncured solder resist 6a in the coating step. For this reason, the region of the uncured solder resist 6a covering the semiconductor connection terminal 4c ′ (see FIG. 3F) and the semiconductor connection terminal 4c ′ (see FIG. 3) are obtained by performing a secondary heat and light treatment on the uncured solder resist 6a. 3 (f)) and a region of the uncured solder resist 6a that does not cover the difference in curing shrinkage of the insulating resin layer 4b occurs from the surface of the semiconductor connection terminal 4c ′ (see FIG. 3 (f)). Will become even more uneven. The presence of the unevenness on the surface of the uncured solder resist 6a is a factor that lowers the fluidity when filling the underfill accompanying the mounting of the semiconductor chip B.

よって、以下に説明する本発明の実施形態では、未硬化ソルダーレジスト６ａを図５（ｃ）のように露光する場合、図６（ａ）に示すように、露光に使用するガラスマスク７ａの所望の位置を遮光部７ｃではなく、グレートーンもしくはハーフトーン７ｂとしている。ここでは、未硬化ソルダーレジスト６ａにソルダーレジスト開口部６ｄ（図５（ｄ）参照）を開口させるための遮光部７ｃの周囲、つまり遮光部７ｃを除いたガラスマスク７ａ上の領域が、光を数〜数十％遮光するグレートーンもしくはハーフトーン部７ｂとなっており、上記ガラスマスク７ａを用いて露光、現像することにより、図６（ｂ）に示すように、グレートーンもしくはハーフトーン部７ｂの領域で露光された部分が直接露光部分よりも凹んだ形状のソルダーレジスト開口部７ｄを形成することができる。次いで、半田接続端子７ｆを露出させるためのソルダーレジスト開口部７ｄに、印刷により半田インキを印刷し、リフローを実施することにより、半田バンプ（図示せず）を形成する。これにより、半導体パッケージ基板Ａとなる。
即ち、本実施形態では、未硬化ソルダーレジスト７ｅ（絶縁樹脂層）の表面に対向して配置したガラスマスク７ａ（マスク部材）の遮光部７ｃを、未硬化ソルダーレジスト７ｅのソルダーレジスト開口部７ｄ（開口部）に対応する箇所に配置し、遮光部７ｃよりも遮光度が低いグレートーンもしくはハーフトーン部７ｂ（半遮光部）を、未硬化ソルダーレジスト７ｅのソルダーレジスト開口部７ｄに対応する箇所の周縁であって、かつ、未硬化ソルダーレジスト７ｅの半田接続端子７ｆを被覆した部分に対応する箇所に配置し、ガラスマスク７ａを介して未硬化ソルダーレジスト７ｅの露光、現像を実施することにより、半導体パッケージ基板Ａを形成している。なお、現像に使用する現像液７ｇ（図６（ｂ）参照）は通常１ｗｔ％Ｎａ２ ＣＯ３ を用いる。 Therefore, in the embodiment of the present invention described below, when the uncured solder resist 6a is exposed as shown in FIG. 5C, the desired glass mask 7a used for exposure is shown in FIG. 6A. Is not gray shade 7c but gray tone or halftone 7b. Here, the area around the light shielding part 7c for opening the solder resist opening 6d (see FIG. 5D) in the uncured solder resist 6a, that is, the region on the glass mask 7a excluding the light shielding part 7c, transmits light. The gray tone or halftone portion 7b is shielded from several to several tens of percent. By exposing and developing using the glass mask 7a, the gray tone or halftone portion 7b is shown in FIG. 6B. It is possible to form a solder resist opening 7d having a shape in which a portion exposed in the region is recessed more than a directly exposed portion. Next, solder bumps (not shown) are formed by printing solder ink on the solder resist openings 7d for exposing the solder connection terminals 7f and performing reflow. As a result, the semiconductor package substrate A is obtained.
That is, in this embodiment, the light-shielding portion 7c of the glass mask 7a (mask member) disposed to face the surface of the uncured solder resist 7e (insulating resin layer) is replaced with the solder resist opening 7d ( The gray tone or the halftone portion 7b (semi-light-shielding portion) having a lower light-shielding degree than the light-shielding portion 7c is arranged at a location corresponding to the solder resist opening 7d of the uncured solder resist 7e. By placing the peripheral edge and corresponding to the portion of the uncured solder resist 7e covered with the solder connection terminal 7f, and exposing and developing the uncured solder resist 7e through the glass mask 7a, A semiconductor package substrate A is formed. Note that 1 wt% Na 2 CO 3 is usually used as a developer 7 g (see FIG. 6B) used for development.

また、ガラスマスク７ａによる露光に代えてプレスにより上記の形状のようなソルダーレジスト開口部８ｆ（図７（ｄ）参照）を形成する場合、図７（ａ）に示すように、絶縁樹脂保護用フィルム８ｄを介して、金属板８ａにより未硬化ソルダーレジスト８ｃをプレスするが、半田接続端子８ｂの上に設けられた未硬化ソルダーレジスト８ｃがプレスの際に凹形状に転写されるように、金属板８ａ上の所望の位置に凸部８ａ´を設ける。凸部８ａ´の形成方法としては、金型もしくはめっきにより作成する。コスト、生産性や精度を考慮するとめっきにより数μｍの凸部８ａ´を設けることが好ましい。次いで、図７（ｂ）に示すように、金属板８ａの凸部８ａ´により凹部８ｃ´が形成された乾燥した未硬化ソルダーレジスト８ｃ上に絶縁樹脂保護用フィルム８ｄを、ロールラミネーター等を用いて貼付する。
次いで、図７（ｃ）に示すように、半導体チップＢ用の接続端子を露出する為に、所望の露出部分をガラスマスク等の遮光パターン８ｅにてマスキングし、露光によりマスキング部以外の未硬化ソルダーレジスト８ｃを光硬化させ、露光後に、図７（ｄ）に示すように、絶縁樹脂保護用フィルム８ｄを剥離して現像を行い、半田接続端子８ｂを露出させるためのソルダーレジスト開口部８ｆを形成する。現像に使用する現像液８ｇは通常１ｗｔ％Ｎａ２ ＣＯ３ を用いる。
次いで、図７（ｅ）に示すように、ソルダーレジスト開口部８ｆに、印刷により半田インキを印刷し、リフローを実施することにより、図７（ｅ）に示す半田バンプ８ｈを形成する。これにより、半導体パッケージ基板Ａとなる。
即ち、本実施形態では、未硬化ソルダーレジスト８ｃ（絶縁樹脂層）の表面を加熱プレスする金属板８ａ（プレス板）に、突出高さが１〜４μｍの凸部８ａ´を形成し、この凸部８ａ´により、未硬化ソルダーレジスト８ｃのソルダーレジスト開口部８ｆに対応する箇所の周縁であって、かつ、未硬化ソルダーレジスト８ｃの半田接続端子８ｂを被覆した部分に対応する箇所を加熱プレスすると共に、金属板８ａの凸部８ａ´以外の部分により、未硬化ソルダーレジスト８ｃのソルダーレジスト開口部８ｆ（開口部）に対応する箇所を加熱プレスすることにより、半導体パッケージ基板Ａを形成している。 Further, when the solder resist opening 8f (see FIG. 7D) having the above shape is formed by pressing instead of exposure with the glass mask 7a, as shown in FIG. The uncured solder resist 8c is pressed by the metal plate 8a through the film 8d. The metal is so that the uncured solder resist 8c provided on the solder connection terminal 8b is transferred into a concave shape at the time of pressing. Protrusions 8a 'are provided at desired positions on the plate 8a. As a method of forming the convex portion 8a ', it is created by a mold or plating. In consideration of cost, productivity, and accuracy, it is preferable to provide the convex portion 8a ′ of several μm by plating. Next, as shown in FIG. 7B, an insulating resin protective film 8d is formed on the dried uncured solder resist 8c in which the concave portion 8c ′ is formed by the convex portion 8a ′ of the metal plate 8a, using a roll laminator or the like. Affix.
Next, as shown in FIG. 7C, in order to expose the connection terminals for the semiconductor chip B, a desired exposed portion is masked with a light shielding pattern 8e such as a glass mask, and the uncured portions other than the masking portion are exposed by exposure. The solder resist 8c is photocured, and after the exposure, as shown in FIG. 7D, the insulating resin protective film 8d is peeled off and developed, and the solder resist opening 8f for exposing the solder connection terminals 8b is formed. Form. As a developing solution 8g used for development, 1 wt% Na 2 CO 3 is usually used.
Next, as shown in FIG. 7E, a solder bump 8h shown in FIG. 7E is formed by printing solder ink on the solder resist opening 8f by printing and performing reflow. As a result, the semiconductor package substrate A is obtained.
That is, in the present embodiment, a protrusion 8a ′ having a protrusion height of 1 to 4 μm is formed on a metal plate 8a (press plate) that heat-presses the surface of the uncured solder resist 8c (insulating resin layer). The portion 8a ′ is heated and pressed at the periphery of the portion corresponding to the solder resist opening 8f of the uncured solder resist 8c and the portion corresponding to the portion of the uncured solder resist 8c covered with the solder connection terminal 8b. At the same time, the portion corresponding to the solder resist opening 8f (opening) of the uncured solder resist 8c is heated and pressed by a portion other than the convex portion 8a ′ of the metal plate 8a, thereby forming the semiconductor package substrate A. .

このプレスを実施することで、半導体パッケージ基板全体の絶縁樹脂層の厚みバラツキが抑制される効果もある。図８に示すように、半導体パッケージ基板Ａ内で配線パターン９ａの疎密が発生している為、絶縁樹脂層９ｂ（未硬化ソルダーレジスト）を塗布した際に、図中左側の配線パターン９ａが疎の部分は回路パターンがない隙間が多くあるため樹脂が流れ、膜厚が薄くなり、図中右側の配線パターン９ａが密の部分は樹脂が流れる隙間が少ない為、膜厚が厚くなる。そのため、アンダーフィル９ｃが充填される半導体パッケージ基板Ａと半導体チップＢの間隙にバラツキが生じ、アンダーフィル９ｃの充填性が低下し、実装信頼性が悪化することが懸念される。
図７に示す実施形態のようなプレスを実施することにより、半導体接続端子４ｃ′（図３（ｆ）参照）を覆う領域の未硬化ソルダーレジスト８ｃへの凹形状形成と同時に、半導体パッケージ基板Ａの絶縁樹脂層の回路パターン（半田接続端子４ｃ′のレイアウトパターン）により未硬化ソルダーレジスト８ｃの表面に図８のような凹凸が形成されるのを抑制することができる。これにより、半導体パッケージ基板Ａに半導体チップＢを実装する際に用いるアンダーフィルの充填時における流動性低下を抑制し、実装信頼性の更なる向上が期待できる。 By performing this pressing, there is also an effect of suppressing the thickness variation of the insulating resin layer of the entire semiconductor package substrate. As shown in FIG. 8, since the wiring pattern 9a is sparse and dense in the semiconductor package substrate A, when the insulating resin layer 9b (uncured solder resist) is applied, the wiring pattern 9a on the left side in the figure is sparse. Since there are many gaps without a circuit pattern in this part, the resin flows and the film thickness becomes thin. In the part where the wiring pattern 9a on the right side in the figure is dense, the resin flows there are few gaps and the film thickness becomes thick. For this reason, there is a concern that the gap between the semiconductor package substrate A and the semiconductor chip B filled with the underfill 9c is varied, the filling property of the underfill 9c is lowered, and the mounting reliability is deteriorated.
By performing pressing as in the embodiment shown in FIG. 7, the semiconductor package substrate A is formed simultaneously with the formation of the concave shape in the uncured solder resist 8c in the region covering the semiconductor connection terminal 4c ′ (see FIG. 3 (f)). 8 can be prevented from being formed on the surface of the uncured solder resist 8c by the circuit pattern of the insulating resin layer (layout pattern of the solder connection terminals 4c ′). Thereby, the fluidity | liquidity fall at the time of the filling of the underfill used when mounting the semiconductor chip B on the semiconductor package board | substrate A is suppressed, and the further improvement of mounting reliability can be anticipated.

また、絶縁樹脂層（未硬化ソルダーレジスト）の硬化と同時に平坦化する方法においては、半導体パッケージ基板Ａの絶縁樹脂層の現像後の硬化を実施する際に平板プレスにより熱をかけながら、プレスを実施する。図９に示すように、現像液１０ｆを用いて現像し、半田接続端子１０ｅを露出させるためのソルダーレジスト開口部１０ａを未硬化ソルダーレジスト１０ｄに設けた後に、平板熱プレス１０ｂにより未硬化ソルダーレジスト１０ｄの表面に対する加圧・加熱処理を行い、平坦な絶縁樹脂表面１０ｃを得る。次いで、ソルダーレジスト開口部１０ａに、印刷により半田インキを印刷し、リフローを実施することにより、半田接続端子１０ｅと電気的に導通する半田バンプ（図示せず）を形成する。これにより、半導体パッケージ基板Ａとなる。なお、現像に使用する現像液１０ｆ（図９（ａ）参照）は通常１ｗｔ％Ｎａ２ ＣＯ３ を用いる。 Further, in the method of flattening simultaneously with the curing of the insulating resin layer (uncured solder resist), when the insulating resin layer of the semiconductor package substrate A is cured after development, the press is applied while applying heat with a flat plate press. carry out. As shown in FIG. 9, after developing using the developing solution 10f and providing the solder resist opening 10a for exposing the solder connection terminal 10e in the uncured solder resist 10d, the uncured solder resist is applied by the flat plate heat press 10b. The surface of 10d is pressed and heated to obtain a flat insulating resin surface 10c. Next, solder bumps (not shown) that are electrically connected to the solder connection terminals 10e are formed by printing solder ink on the solder resist openings 10a by printing and performing reflow. As a result, the semiconductor package substrate A is obtained. Note that 1 wt% Na 2 CO 3 is usually used as the developing solution 10f (see FIG. 9A) used for development.

プレス時の温度は樹脂が硬化し始める１００℃以上で実施し、好ましくは、硬化が顕著に進む１００〜１５０℃の間でプレスを実施し、１５０℃以上では、圧力を開放し、温度上昇させ硬化する。最高到達温度は使用する絶縁樹脂により異なるが、１６０〜２００℃の間で行う。この際のプレス圧力は樹脂の特性により違う為、各々条件出しを実施する必要がある。
このような加圧・加熱処理は、図６や図７の製造方法によりソルダーレジスト開口部７ｄ、８ｆを形成した後の未硬化ソルダーレジスト７ｅ、８ｃの表面に対して行ってもよい。 The temperature at the time of pressing is 100 ° C. or higher at which the resin starts to harden, preferably, the pressing is performed between 100 to 150 ° C. where curing is significantly promoted, and at 150 ° C. or higher, the pressure is released and the temperature is increased. Harden. The maximum temperature reached varies between 160 and 200 ° C., depending on the insulating resin used. Since the pressing pressure at this time varies depending on the characteristics of the resin, it is necessary to determine the conditions for each.
Such pressurization / heating treatment may be performed on the surfaces of the uncured solder resists 7e and 8c after the solder resist openings 7d and 8f are formed by the manufacturing method of FIGS.

上記の図６や図７の製造方法によりソルダーレジスト開口部７ｄ、８ｆを形成した未硬化ソルダーレジスト７ｅ、８ｃの表面は、図１０の拡大図に示すように、半導体チップＢを接続する半田バンプ１ｄを形成する部分の周囲において、凹形状の絶縁樹脂表面１ｃを有する。また、図９の製造方法によりソルダーレジスト開口部１０ａを形成した未硬化ソルダーレジスト１０ｄの表面は、図１１の拡大図に示すように、半導体チップＢを実装する半田バンプ１ｄを形成する部分の周囲において、平坦な絶縁樹脂表面１ｃ´を有する。そこで、本発明の実施形態では、これらの製造方法により製造した半導体パッケージ基板Ａと半導体チップＢを、半田バンプ１ｄのマウント工程と半田接続のリフロー工程、アンダーフィルの充填工程を経て、図１０及び図１１に示す絶縁樹脂表面１ｃ、１ｃ´がそれぞれ凹形状および平坦に形成された半導体実装基板を得る。
本実施形態において、図１０や図１１の拡大図に示す絶縁樹脂表面１ｃ、１ｃ´は、半田接続端子１ｂを被覆した部分の高さ（厚み）が、半田接続端子１ｂ以外を被覆した部分の高さ（厚み）よりも０〜５μｍ低い位置にあるように形成される。５μｍを超えて低い位置にあるように形成されると、半田バンプが実装時に変形する恐れがあり実装信頼性の点で不利であること、また、半田接続端子上の絶縁樹脂層が薄いと硬化の際に内層回路が酸化されやすくなり、密着性、絶縁性の点で不利である。絶縁樹脂層の厚みは少なくとも５μｍ以上を必要とし、半田接続端子上の絶縁樹脂層の厚みは１０〜２０μｍ程度である。
また、図７の製造方法により未硬化ソルダーレジスト８ｃの表面にソルダーレジスト開口部８ｆを形成する際に用いる金属板８ａ上の所望の位置に形成する凸部８ａ´の高さは、この凸部８ａによって絶縁樹脂表面１ｃに形成する凹部が０〜５μｍの深さである場合、１〜４μｍとするのが好ましい。凸部８ａ´を１μｍ未満や４μｍを超える高さにすると、絶縁樹脂の硬化収縮率が最大で5%程度あり、硬化収縮後の凹部が５μｍを超える可能性がある為、実装信頼性の点で不利である。
絶縁樹脂表面１ｃ、１ｃ´の、半田接続端子１ｂを被覆した部分の高さ（厚み）を、半田接続端子１ｂ以外を被覆した部分の高さ（厚み）よりも０〜５μｍ低い位置とする結果、従来半導体接続端子上を被覆した絶縁樹脂層の硬化収縮の差による凸部分となっていたのが、平坦ないしは凹み構造となる。したがって、半導体チップＢを半導体パッケージ基板Ａに実装する際のアンダーフィル１ｅ（図１０、図１１）の充填性が向上し、半導体パッケージ基板Ａと半導体チップＢの実装歩留まりとか、その実装後の接続信頼性の向上とか微細化に伴う実装歩留まり、あるいは接続信頼性の低下を抑制できる絶縁樹脂層の表面形状の形成を実現できる。
また、上述した実施形態によると、従来の設備での生産も可能となる。
なお、図６や図７、あるいは、図９の製造方法により未硬化ソルダーレジスト７ｅ、８ｃ、１０ｄの表面に形成したソルダーレジスト開口部７ｄ、８ｆ、１０ａは、いずれも、半田接続端子７ｆ、８ｂ、１０ｅ側から未硬化ソルダーレジスト７ｅ、８ｃ、１０ｄの表面側に向かうにつれて開口径が徐々に大きく広がる形状とすることができる。これにより、ソルダーレジスト開口部７ｄ、８ｆ、１０ａに半田バンプを形成する際の半田ペーストの充填効率を良くすることができる。 The surfaces of the uncured solder resists 7e and 8c in which the solder resist openings 7d and 8f are formed by the manufacturing method shown in FIGS. 6 and 7 are solder bumps for connecting the semiconductor chip B as shown in the enlarged view of FIG. A concave insulating resin surface 1c is provided around the portion forming 1d. Further, as shown in the enlarged view of FIG. 11, the surface of the uncured solder resist 10d in which the solder resist opening 10a is formed by the manufacturing method of FIG. 9 is around the portion where the solder bump 1d for mounting the semiconductor chip B is formed. 1 has a flat insulating resin surface 1c ′. Therefore, in the embodiment of the present invention, the semiconductor package substrate A and the semiconductor chip B manufactured by these manufacturing methods are subjected to the mounting process of the solder bump 1d, the solder reflow process, and the underfill filling process, as shown in FIG. A semiconductor mounting substrate is obtained in which the insulating resin surfaces 1c and 1c 'shown in FIG.
In the present embodiment, the insulating resin surfaces 1c and 1c ′ shown in the enlarged views of FIG. 10 and FIG. 11 are the height (thickness) of the portion covering the solder connection terminal 1b. It is formed to be at a position 0 to 5 μm lower than the height (thickness). If it is formed at a low position exceeding 5 μm, solder bumps may be deformed during mounting, which is disadvantageous in terms of mounting reliability. Also, if the insulating resin layer on the solder connection terminal is thin, it will be cured. In this case, the inner layer circuit is easily oxidized, which is disadvantageous in terms of adhesion and insulation. The thickness of the insulating resin layer needs to be at least 5 μm, and the thickness of the insulating resin layer on the solder connection terminal is about 10 to 20 μm.
Further, the height of the convex portion 8a ′ formed at a desired position on the metal plate 8a used when the solder resist opening 8f is formed on the surface of the uncured solder resist 8c by the manufacturing method of FIG. When the recessed part formed in the insulating resin surface 1c by 8a is the depth of 0-5 micrometers, it is preferable to set it as 1-4 micrometers. If the height of the protrusion 8a 'is less than 1 μm or more than 4 μm, the curing shrinkage of the insulating resin is about 5% at the maximum, and the recess after curing shrinkage may exceed 5 μm. It is disadvantageous.
Result of setting the height (thickness) of the portion of the insulating resin surfaces 1c and 1c ′ covered with the solder connection terminal 1b to be 0 to 5 μm lower than the height (thickness) of the portion covering other than the solder connection terminal 1b. Conventionally, the convex portion due to the difference in curing shrinkage of the insulating resin layer covering the semiconductor connection terminal is a flat or concave structure. Therefore, the filling property of the underfill 1e (FIGS. 10 and 11) when the semiconductor chip B is mounted on the semiconductor package substrate A is improved, the mounting yield of the semiconductor package substrate A and the semiconductor chip B, and the connection after the mounting. It is possible to realize the formation of the surface shape of the insulating resin layer capable of suppressing the improvement in reliability, the mounting yield accompanying the miniaturization, or the decrease in the connection reliability.
Further, according to the above-described embodiment, it is possible to produce with conventional equipment.
The solder resist openings 7d, 8f, and 10a formed on the surfaces of the uncured solder resists 7e, 8c, and 10d by the manufacturing method of FIGS. 6, 7, and 9 are all solder connection terminals 7f, 8b. The opening diameter can be gradually widened from the 10e side toward the surface side of the uncured solder resists 7e, 8c, and 10d. Thereby, the filling efficiency of the solder paste when forming solder bumps in the solder resist openings 7d, 8f, 10a can be improved.

本発明に使用する半導体パッケージ基板は上記工程により作成し、効果の確認をしたものである。効果の確認のため、露光、プレスそれぞれの製造方法により絶縁樹脂の凹部構造を形成した。   The semiconductor package substrate used in the present invention is prepared by the above process and the effect is confirmed. In order to confirm the effect, the concave structure of the insulating resin was formed by the respective production methods of exposure and pressing.

半導体パッケージ基板に、ロールコーターにて絶縁樹脂（太陽インキ製造（株）製、ＰＳＲ−４０００）を接続端子上の乾燥膜厚が１５〜２０μｍとなるように塗布し、８０℃で乾燥させた。次いで、絶縁樹脂保護用テープをロールラミネーターによりラミネートし、絶縁樹脂を開口させる遮光部周辺にハーフトーンを有したガラスマスクを用いて露光、現像を実施することで、所望の凹部を形成した。光重合反応を収束させる為、露光後に絶縁樹脂保護用テープを剥離するまで、１時間エージングを行い、剥離後、現像を実施した。開口させるためのガラスマスクの遮光部はφ８０μｍのドットパターンにて評価を実施した。   An insulating resin (manufactured by Taiyo Ink Manufacturing Co., Ltd., PSR-4000) was applied to the semiconductor package substrate with a roll coater so that the dry film thickness on the connection terminal was 15 to 20 μm, and dried at 80 ° C. Then, a tape for insulating resin protection was laminated by a roll laminator, and exposure and development were performed using a glass mask having a halftone around the light shielding portion where the insulating resin was opened, thereby forming a desired recess. In order to converge the photopolymerization reaction, aging was performed for 1 hour until the insulating resin protecting tape was peeled off after exposure, and development was carried out after peeling. The light shielding part of the glass mask for opening was evaluated with a dot pattern of φ80 μm.

効果の確認方法としては、絶縁樹脂の硬化後に、断面を観察することにより、開口部の凹部深さを確認し、深さが０〜５μｍの範囲であることを確認した。   As a method for confirming the effect, the depth of the concave portion of the opening was confirmed by observing the cross section after curing of the insulating resin, and the depth was confirmed to be in the range of 0 to 5 μm.

実施例１の場合と同様にして、半導体パッケージ基板に絶縁樹脂層を形成し、絶縁樹脂保護用テープをロールラミネーターによりラミネートした。絶縁樹脂を開口させる遮光部を有したガラスマスクを用いて露光、現像を実施することで、開口部を形成した。   In the same manner as in Example 1, an insulating resin layer was formed on the semiconductor package substrate, and an insulating resin protective tape was laminated by a roll laminator. The opening was formed by performing exposure and development using a glass mask having a light-shielding portion for opening the insulating resin.

次いで、加圧・加熱プレスを行い、絶縁樹脂層の平坦化と硬化を同時に実施した。温度は１２０℃、３０分で処理した後、１７０℃まで昇温後６０分間保持し、時間経過後に自然冷却を実施した。圧力は０．５ＭＰａで実施し、温度が１００〜１５０℃の間加圧、１５０℃以上では圧力を開放し硬化した。   Next, pressurization / heating press was performed to simultaneously planarize and cure the insulating resin layer. After treating the temperature at 120 ° C. for 30 minutes, the temperature was raised to 170 ° C. and held for 60 minutes, and natural cooling was performed after the lapse of time. The pressure was 0.5 MPa, the temperature was 100-150 ° C., and the pressure was released at 150 ° C. or higher to cure.

効果の確認方法としては、絶縁樹脂の硬化後に、断面を観察することにより、開口部の平坦度を確認し、凸形状が０．５μｍ以下もしくは平坦であることを確認した。   As a method for confirming the effect, the flatness of the opening was confirmed by observing the cross section after the insulating resin was cured, and the convex shape was confirmed to be 0.5 μm or less or flat.

比較例Comparative example

半導体パッケージ基板において、本発明での製造方法を使用することなく、絶縁樹脂層を形成した基板を作製し、実施例１、２で作製した基板と絶縁樹脂表面の凹凸の高さおよび深さを測定した。   In the semiconductor package substrate, without using the manufacturing method of the present invention, a substrate on which an insulating resin layer was formed was produced, and the height and depth of the unevenness between the substrate produced in Examples 1 and 2 and the insulating resin surface were adjusted. It was measured.

Figure 2012074660
Figure 2012074660

実施例１、実施例２、及び比較例の結果を表１に示す。
表１から明らかなように、比較例では絶縁樹脂表面が凸形状で２．０μｍの段差を有しているのに対し、実施例１では絶縁樹脂表面に３μｍの凹形状が形成され、実施例２で得られた絶縁樹脂表面に０〜０．５μｍの凸形状が形成されている。それに対して、比較例では絶縁樹脂表面が凸形状で3３．０μｍの段差を有している。
つまり、実施例１、２の様に露光時もしくはプレス処理を施すことにより、半田接続端子上の絶縁樹脂表面を平坦ないしは凹形状に制御することが出来るため、従来、半田接続端子等の影響により絶縁樹脂表面が凸となり、実装時のアンダーフィルの充填性の低下を抑制することができ、実装時の接続性に有利に働くことが判る。 Table 1 shows the results of Example 1, Example 2, and Comparative Example.
As is clear from Table 1, the surface of the insulating resin is convex and has a step of 2.0 μm in the comparative example, whereas in Example 1, a concave shape of 3 μm is formed on the surface of the insulating resin. A convex shape of 0 to 0.5 μm is formed on the surface of the insulating resin obtained in 2. In contrast, in the comparative example, the surface of the insulating resin is convex and has a step of 33.0 μm.
In other words, the surface of the insulating resin on the solder connection terminal can be controlled to be flat or concave by performing exposure or pressing as in the first and second embodiments. Conventionally, due to the influence of the solder connection terminal, etc. It can be seen that the surface of the insulating resin becomes convex, so that a decrease in the filling property of the underfill at the time of mounting can be suppressed, and the connectivity at the time of mounting works advantageously.

１ａ、２ｄ、２ｄ′、９ｂ ・・・絶縁樹脂層
１ｂ、２ｃ、２ｃ′、４ｃ′、７ｆ、８ｂ、１０ｅ ・・・半田接続端子
１ｃ、１ｃ′、１０ｃ ・・・絶縁樹脂表面
２ａ ・・・内層回路
２ｂ、４ｄ ・・・ビアホール
１ｄ、２ｅ、６ｅ、８ｈ ・・・半田バンプ
１ｅ、２ｆ、９ｃ ・・・アンダーフィル
３ａ、４ａ ・・・コア層
３ｂ ・・・スルーホール
３ｃ、９ａ ・・・配線パターン
４ｂ ・・・層間絶縁樹脂
４ｃ ・・・配線パターン
４ｅ ・・・無電解銅メッキ
４ｆ ・・・感光性ドライフィルムレジスト
４ｇ ・・・パターンメッキ
４ｈ ・・・苛性ソーダ
６ａ、７ｅ、８ｃ、１０ｄ ・・・未硬化ソルダーレジスト
６ｂ、８ｄ ・・・絶縁樹脂保護用フィルム
６ｃ、８ｅ ・・・遮光パターン
６ｄ、７ｄ、８ｆ、１０ａ ・・・ソルダーレジスト開口部
６ｆ、７ｇ、８ｇ、１０ｆ ・・・現像液
７ａ ・・・ガラスマスク
７ｂ ・・・グレートーンもしくはハーフトーン部
７ｃ ・・・遮光部
８ａ ・・・金属板
８ａ′ ・・・金属板の凸部
８ｃ′ ・・・凹部
１０ｂ ・・・平板熱プレス
Ａ ・・・半導体パッケージ基板
Ｂ ・・・半導体チップ
Ｃ ・・・３次元配線基板 1a, 2d, 2d ', 9b ... Insulating resin layer 1b, 2c, 2c', 4c ', 7f, 8b, 10e ... Solder connection terminals 1c, 1c', 10c ... Insulating resin surface 2a Inner layer circuit 2b, 4d ... via holes 1d, 2e, 6e, 8h ... solder bumps 1e, 2f, 9c ... underfill 3a, 4a ... core layer 3b ... through holes 3c, 9a ..Wiring pattern 4b... Interlayer insulating resin 4c... Wiring pattern 4e... Electroless copper plating 4f... Photosensitive dry film resist 4g... Pattern plating 4h ... Caustic soda 6a, 7e, 8c 10d: Uncured solder resists 6b, 8d ... Insulating resin protecting films 6c, 8e ... Light shielding patterns 6d, 7d, 8f, 10a ... Solder resist openings f, 7g, 8g, 10f... Developer 7a... Glass mask 7b... Gray tone or halftone part 7c... Shading part 8a ... Metal plate 8a '. 8c '... depression 10b ... flat plate heat press A ... semiconductor package substrate B ... semiconductor chip C ... three-dimensional wiring board

Claims (6)

基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板において、
前記絶縁樹脂層の前記半田接続端子を被覆した部分の表面高さが前記半田接続端子以外を被覆した部分の高さより０〜５μｍ低い位置にある、
ことを特徴とする半導体パッケージ基板。 An insulating resin layer having an opening formed from the surface side that covers a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and exposes the plurality of solder connection terminals; and solder in the opening In a semiconductor package substrate having a plurality of solder bumps for mounting semiconductor chips formed by filling,
The surface height of the portion covering the solder connection terminal of the insulating resin layer is 0 to 5 μm lower than the height of the portion covering other than the solder connection terminal,
A semiconductor package substrate characterized by the above. 前記各開口部は、前記半田接続端子側から前記絶縁樹脂層の表面側に向かうにつれて開口径が徐々に大きく広がる形状に形成されていることを特徴とする請求項１記載の半導体パッケージ基板。   2. The semiconductor package substrate according to claim 1, wherein each of the openings is formed in a shape in which an opening diameter gradually increases from the solder connection terminal side toward the surface side of the insulating resin layer. 基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、
前記絶縁樹脂層の表面に対向して配置したマスク部材の遮光部を、前記絶縁樹脂層の前記開口部に対応する箇所に配置し、前記遮光部よりも遮光度が低い半遮光部を、前記絶縁樹脂層の前記開口部に対応する箇所の周縁であって、かつ、前記絶縁樹脂層の前記半田接続端子を被覆した部分に対応する箇所に配置し、
前記マスク部材を介して前記絶縁樹脂層の露光、現像を実施することにより形成した、
ことを特徴とする半導体パッケージ基板の製造方法。 An insulating resin layer having an opening formed from the surface side that covers a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and exposes the plurality of solder connection terminals; and solder in the opening A method of manufacturing a semiconductor package substrate having a plurality of solder bumps for mounting semiconductor chips formed by filling,
A light shielding portion of a mask member disposed to face the surface of the insulating resin layer is disposed at a location corresponding to the opening of the insulating resin layer, and a semi-light shielding portion having a light shielding degree lower than that of the light shielding portion, It is the periphery of the location corresponding to the opening of the insulating resin layer, and disposed at a location corresponding to the portion of the insulating resin layer that covers the solder connection terminal,
Formed by carrying out exposure and development of the insulating resin layer through the mask member,
A method of manufacturing a semiconductor package substrate. 基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、
前記絶縁樹脂層の表面を加熱プレスするプレス板に、突出高さが１〜４μｍの凸部を形成し、該凸部により、前記絶縁樹脂層の前記開口部に対応する箇所の周縁であって、かつ、前記絶縁樹脂層の前記半田接続端子を被覆した部分に対応する箇所を加熱プレスすると共に、前記プレス板の前記凸部以外の部分により、前記絶縁樹脂層の前記開口部に対応する箇所を加熱プレスすることにより形成した、
ことを特徴とする半導体パッケージ基板の製造方法。 An insulating resin layer having an opening formed from the surface side that covers a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and exposes the plurality of solder connection terminals; and solder in the opening A method of manufacturing a semiconductor package substrate having a plurality of solder bumps for mounting semiconductor chips formed by filling,
On the press plate that heat-presses the surface of the insulating resin layer, a protrusion having a protrusion height of 1 to 4 μm is formed, and the protrusion is a peripheral edge of the portion corresponding to the opening of the insulating resin layer. And a portion corresponding to the portion of the insulating resin layer corresponding to the portion of the insulating resin layer covered with the solder connection terminal, and a portion corresponding to the opening of the insulating resin layer by a portion other than the convex portion of the press plate Formed by hot pressing,
A method of manufacturing a semiconductor package substrate. 前記絶縁樹脂層の表面を熱処理しながら平坦化処理し、硬化させた後に、前記開口部を形成した、
ことを特徴とする請求項３又は４記載の半導体パッケージ基板の製造方法。 After the surface of the insulating resin layer was flattened while being heat-treated and cured, the opening was formed.
The method of manufacturing a semiconductor package substrate according to claim 3 or 4, 基板上に形成された導体配線および複数の半田接続端子からなる導体回路を被覆し前記複数の半田接続端子を露出させる開口部が表面側から形成された絶縁樹脂層と、前記開口部に半田を充填して形成した半導体チップ実装用の複数の半田バンプとを有する半導体パッケージ基板の製造方法であって、
前記絶縁樹脂層の表面を熱処理しながら平坦化処理し、硬化させた後に、前記開口部を形成した、
ことを特徴とする半導体パッケージ基板の製造方法。 An insulating resin layer having an opening formed from the surface side that covers a conductor circuit formed of a conductor wiring and a plurality of solder connection terminals formed on the substrate and exposes the plurality of solder connection terminals; and solder in the opening A method of manufacturing a semiconductor package substrate having a plurality of solder bumps for mounting semiconductor chips formed by filling,
After the surface of the insulating resin layer was flattened while being heat-treated and cured, the opening was formed.
A method of manufacturing a semiconductor package substrate.
JP2010220344A 2010-09-30 2010-09-30 Manufacturing method of semiconductor package substrate Expired - Fee Related JP5640613B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010220344A JP5640613B2 (en) 2010-09-30 2010-09-30 Manufacturing method of semiconductor package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010220344A JP5640613B2 (en) 2010-09-30 2010-09-30 Manufacturing method of semiconductor package substrate

Publications (2)

Publication Number Publication Date
JP2012074660A true JP2012074660A (en) 2012-04-12
JP5640613B2 JP5640613B2 (en) 2014-12-17

Family

ID=46170512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010220344A Expired - Fee Related JP5640613B2 (en) 2010-09-30 2010-09-30 Manufacturing method of semiconductor package substrate

Country Status (1)

Country Link
JP (1) JP5640613B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915354A (en) * 2013-01-03 2014-07-09 台湾积体电路制造股份有限公司 Improved solder mask shape for BOT laminate packages
TWI503944B (en) * 2013-04-18 2015-10-11 矽品精密工業股份有限公司 Semiconductor package and method of manufacture the same, shielding mask and package structure having the mask
US20220384383A1 (en) * 2021-06-01 2022-12-01 National Pingtung University Of Science And Technology Heat assisted flip chip bonding apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349427A (en) * 1999-06-07 2000-12-15 Ibiden Co Ltd Printed wiring board, printed wiring board for surface mounting, and surface-mount wiring board
JP2004128405A (en) * 2002-10-07 2004-04-22 Kyocera Corp Wiring board and its manufacturing method
JP2006201434A (en) * 2005-01-20 2006-08-03 Toppan Printing Co Ltd Photomask for exposure of solder resist and wiring substrate exposed using the same or method for producing the same
JP2006251386A (en) * 2005-03-10 2006-09-21 Fuji Photo Film Co Ltd Method for forming permanent pattern
JP2007164059A (en) * 2005-12-16 2007-06-28 Cmk Corp Exposure system for solder resist and method of manufacturing printed wiring board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000349427A (en) * 1999-06-07 2000-12-15 Ibiden Co Ltd Printed wiring board, printed wiring board for surface mounting, and surface-mount wiring board
JP2004128405A (en) * 2002-10-07 2004-04-22 Kyocera Corp Wiring board and its manufacturing method
JP2006201434A (en) * 2005-01-20 2006-08-03 Toppan Printing Co Ltd Photomask for exposure of solder resist and wiring substrate exposed using the same or method for producing the same
JP2006251386A (en) * 2005-03-10 2006-09-21 Fuji Photo Film Co Ltd Method for forming permanent pattern
JP2007164059A (en) * 2005-12-16 2007-06-28 Cmk Corp Exposure system for solder resist and method of manufacturing printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915354A (en) * 2013-01-03 2014-07-09 台湾积体电路制造股份有限公司 Improved solder mask shape for BOT laminate packages
TWI503944B (en) * 2013-04-18 2015-10-11 矽品精密工業股份有限公司 Semiconductor package and method of manufacture the same, shielding mask and package structure having the mask
US20220384383A1 (en) * 2021-06-01 2022-12-01 National Pingtung University Of Science And Technology Heat assisted flip chip bonding apparatus
US11682650B2 (en) * 2021-06-01 2023-06-20 National Pingtung University Of Science And Technology Heat assisted flip chip bonding apparatus

Also Published As

Publication number Publication date
JP5640613B2 (en) 2014-12-17

Similar Documents

Publication Publication Date Title
US8946906B2 (en) Multilayer wiring substrate and method of manufacturing the same
US8835773B2 (en) Wiring board and method of manufacturing the same
US20080315398A1 (en) Packaging substrate with embedded chip and buried heatsink
JP5461323B2 (en) Manufacturing method of semiconductor package substrate
JP2007324559A (en) Multilayer circuit board with fine pitch and fabricating method thereof
TWM512216U (en) Semiconductor substrate structure and semiconductor package structure
TW201448692A (en) Embedded high density interconnection printed circuit board and method for manufacturing same
JP2014107371A (en) Wiring board
TW202046840A (en) Circuit carrier board and manufacturing method thereof
TW201446084A (en) Printed circuit board and method for manufacturing same
JP2014039072A (en) Method for manufacturing wiring board
JP5640613B2 (en) Manufacturing method of semiconductor package substrate
US6808643B2 (en) Hybrid interconnect substrate and method of manufacture thereof
TWI531291B (en) Package board and method for manufactuing same
US10897823B2 (en) Circuit board, package structure and method of manufacturing the same
US20120103662A1 (en) Printed circuit board and manufacturing method thereof
KR20090038758A (en) Package substrate and the manufacturing method thereof
JP4725178B2 (en) Semiconductor device and manufacturing method thereof
CN113380720A (en) Circuit carrier plate structure and manufacturing method thereof
TW201536143A (en) Printed circuit board and method thereof
JP2002217248A (en) Transfer plate for pattern formation and method of manufacturing substrate for semiconductor device using it
KR20140025824A (en) Manufacturing method of electronic chip embedded circuit board
KR101004216B1 (en) Method for fabricating printed curcit board of chip embedded type joined with ultra-silm printed curcit board
JP2010287765A (en) Imprinting method, wiring pattern forming method, and multilayer electronic component
KR101081153B1 (en) Method for fabricating printed-circuit-board including embedded fine pattern

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130823

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140617

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140708

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140905

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140930

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141013

R150 Certificate of patent or registration of utility model

Ref document number: 5640613

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees