JP2011054652A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten wirings and to reduce in thickness a laminated semiconductor chip with a simple structure. <P>SOLUTION: In a semiconductor device 10, a first semiconductor chip 12 and a second semiconductor chip 13 are laminated. The first semiconductor chip 12 is formed in a quadrangle plate shape. The second semiconductor chip 13 is formed in a quadrangle plate shape and has conductive bumps 17 arranged in a region where four sides project outside compared to the first semiconductor chip 12 at prescribed intervals. In the first semiconductor chip 12, conductive bumps 14 with shorter wiring distance are arranged in vertical and lateral directions at prescribed intervals and are flip chip-bonded to an electrode of the substrate 11. The second semiconductor chip 13 is flip chip-bonded to the electrode of the substrate 11 by the conductive bumps 17 with longer wiring distance at an outer side of the first semiconductor chip 12. The respective conductive chips 14 and 17 are deposited by electrolytic plating and are formed in almost columnar shapes. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a stacked multichip module (MCM) in which a plurality of semiconductor chips are stacked and integrated with a sealing resin, and a method for manufacturing the same.

  Along with the downsizing of electronic equipment, there is an increasing demand for downsizing of semiconductor devices. In response to this, the semiconductor package has shifted from a conventional lead frame structure to a BGA (ball grid array) structure using protrusions such as solder bumps as external electrodes, thereby realizing a reduction in mounting area. Recently, a CSP (chip size package) in which the outer size of the semiconductor package is made equal to the size of the semiconductor chip has been developed, and the reduction in the area of the semiconductor device is approaching its limit.

  Therefore, in order to meet the demand for further miniaturization of semiconductor devices, a stack type MCM (multi-chip module) in which semiconductor chips are stacked in the height direction has been developed. The MCM is a module obtained by integrating a plurality of semiconductor chips, and a stack of semiconductor chips stacked in the height direction is called a stack type MCM. Stacked MCM is very effective for improving the mounting density of semiconductor devices.

Next, the stack MCM will be described with reference to FIG. The semiconductor device 1 shown in FIG. 6 is a stacked MCM in which two semiconductor chips 4A and 4B are stacked in the vertical direction, that is, the vertical direction. The lower semiconductor chip 4A is fixed to the substrate 2 with an adhesive, and is electrically connected to an electrode (not shown) of the substrate 2 by a wire 5A made of gold or the like. The upper semiconductor chip 4B is fixed on the lower semiconductor chip 4A by an adhesive resin or the like, and is electrically connected to an electrode (not shown) of the lower semiconductor chip 4A by a wire 5B made of gold or the like.
These semiconductor chips 4A and 4B are sealed with a sealing resin 6 together with the wires 5A and 5B. The semiconductor device 1 of the stack type multichip module MCM obtained in this way is connected to an electrode such as a mother board (not shown) by a substantially hemispherical solder bump 3 provided on the lower surface of the substrate 2.

Next, another type of semiconductor device will be described with reference to FIG. The semiconductor device 8 shown in FIG. 7 is a stacked MCM in which two semiconductor chips 4A and 4B are stacked in the height direction. In this semiconductor device 8, the lower semiconductor chip 4 </ b> A is flip-chip connected to the substrate 2 by solder bumps 9. The upper semiconductor chip 4B is fixed on the lower semiconductor chip 4A by an adhesive resin or the like, and is electrically connected to an electrode (not shown) of the substrate 2 by a wire 5B made of gold or the like.
These semiconductor chips 4A and 4B are sealed as a single package by a sealing resin 6 together with the wires 5B. The obtained stacked MCM semiconductor device 8 is connected to electrodes such as a mother board by solder bumps 3 provided on the substrate 2.

Note that a request for speeding up signal transmission is given as a requirement other than miniaturization of a semiconductor device. In high-speed signals, it is generally known that a shorter wiring length is more advantageous because the wiring inductance greatly affects signal transmission.
However, since conventional MCM type semiconductor devices 1 and 8 use wire bonding as shown in FIGS. 6 and 7, an increase in inductance due to wires 5A and 5B cannot be ignored in high-speed signal transmission. Further, since the wires 5A and 5B are always arranged in a loop shape, this is an obstacle to further thinning of the MCM semiconductor devices 1 and 8. Therefore, an MCM type semiconductor device that does not use wire bonding as shown in Patent Document 1 has been proposed.

The semiconductor device described in Patent Document 1 has a plurality of semiconductor chips, a semiconductor chip provided in the lowermost layer as a parent chip, and a plurality of semiconductor chips provided on the active surface thereof as child chips. It has a configuration in which chips are sequentially stacked. These small chips are each formed with through holes in the thickness direction, and these through holes are filled with a conductor. An internal connection electrode is formed on the active surface of each small chip.
Then, the conductor filled in the through hole is joined to the internal connection electrode via the electrode pad, so that the small chip is electrically connected to the other child chips adjacent below. .
With such a configuration, a highly integrated MCM type semiconductor device that does not use wires is obtained.

Japanese Patent No. 3893268

However, the semiconductor device described in Patent Document 1 includes a step of providing a through hole in a silicon wafer of a semiconductor chip and filling a conductor, a step of flip-chip mounting the semiconductor chip on a substrate, and a step of polishing the back surface. It is necessary and the manufacturing process is very complicated.
SUMMARY OF THE INVENTION In view of such circumstances, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the wiring of the semiconductor chip is shortened and the thickness is reduced with a simple configuration for stacked semiconductor chips.

The semiconductor device according to the present invention is a semiconductor device in which a plurality of semiconductor chips are stacked and integrated, and the plurality of stacked semiconductor chips are electrically connected by conductive bumps having different heights. Features.
According to the semiconductor device of the present invention, a plurality of semiconductor chips are stacked, and the plurality of stacked semiconductor chips having different heights are electrically connected to a substrate, another semiconductor chip, or the like by conductive bumps having different heights. By connecting, each wiring distance of the conductive bumps arranged between the substrate and other semiconductor chips and a plurality of stacked semiconductor chips is shortened. Therefore, compared with the conventional bonding wire, there is no increase in inductance, a high-speed signal transmission can be achieved, and a thin semiconductor device can be achieved. In addition, the structure is simple and the manufacture is facilitated even when compared with a semiconductor device in which adjacent semiconductor chips are connected to each other by a conductor filled with a through hole formed in the semiconductor chip.

In addition, the second semiconductor chip farther than the first semiconductor chip is electrically connected to the conductive bump in the region protruding outward from the first semiconductor chip with respect to the conductive bump connection object. Preferably it is.
When stacking a plurality of semiconductor chips, the first semiconductor chip on the near side can be connected to the conductive bump at an arbitrary position with respect to the conductive bump connection target, and the second semiconductor on the far side The chip can be connected to a connection object of the conductive bump by providing a conductive bump in a region protruding outside the first semiconductor chip. Thereby, a conductive bump can be connected to each of a plurality of stacked semiconductor chips without providing wire bonding, a through hole, and a conductor.
In addition, it is preferable that the connection object of a conductive bump is a board | substrate or another semiconductor chip.

Moreover, it is preferable that the conductive bump electrically connected to the semiconductor chip on the far side with respect to the conductive bump connection object is formed in a substantially columnar shape.
When the conductive bump is a solder bump manufactured by, for example, a solder printing method or a solder ball mounting method, the bump becomes a substantially hemispherical bump that increases in the lateral direction as the height increases. Although pinning cannot be achieved, the height can be increased without increasing the area in the width direction by forming at least the second conductive bump in a columnar shape, so the stacked height without interfering with multi-pinning Can be connected to different semiconductor chips.
Further, the conductive bump may be formed by laminating any material selected from copper, silver, tin, gold, and nickel, or any two or more materials.
Arbitrary materials, such as copper, silver, tin, gold | metal | money, nickel, can be employ | adopted as a conductive bump, and a conductive bump can be formed by laminating | stacking a different conductive bump material depending on the case.
In addition, the conductive bump may be formed by electrolytic plating. In this case, the height, cross-sectional area, material, shape, and the like can be arbitrarily selected and formed by electrolytic plating.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a power supply layer on a substrate by electroless plating in a method of manufacturing a semiconductor device in which a plurality of semiconductor chips are stacked and integrated, and a first resist on the power supply layer Forming a pattern, forming a first conductive bump on the first resist pattern by electrolytic plating, forming a second resist and patterning, and at least a part of the first resist Growing a second conductive bump by electroplating on the second resist pattern on the conductive bump, bonding the first semiconductor chip to the first conductive bump, and second conductive And a step of bonding the second semiconductor chip to the conductive bump, whereby the first semiconductor chip and the second semiconductor chip are laminated.
According to the method for manufacturing a semiconductor device according to the present invention, a conductive power feeding layer is formed on a substrate by electroless plating, and a pattern for forming conductive bumps is formed on the first and second resists thereon. When the height of the conductive bump is short, the conductive bump is deposited by electrolytic plating only with the first resist pattern. When the height is long, the conductive bump is deposited on the conductive bump deposited with the first resist. By depositing the conductive bumps by electrolytic plating with the second resist pattern, it is possible to form the conductive bumps having a length corresponding to the wiring distance of a plurality of stacked semiconductor chips. Thereby, the several semiconductor chip laminated | stacked on each conductive bump from which height differs can be joined and laminated | stacked, respectively.
Thereafter, the entire semiconductor device can be sealed with a sealing resin.

According to the semiconductor device of the present invention, the wiring distance of the stacked semiconductor chips is shortened by electrically connecting the stacked semiconductor chips by the conductive bumps having a distance corresponding to the stack height. Therefore, compared with the case where a bonding wire is used, there is no increase in inductance, and it is possible to cope with a higher speed and to realize a thinner semiconductor device. Furthermore, compared with the case where the semiconductor chip is filled with a conductor and adjacent semiconductor chips are connected to each other, the configuration is simple, the manufacturing is easy, and the cost can be reduced.
According to the method for manufacturing a semiconductor device according to the present invention, a semiconductor chip is formed by forming first and second conductive bumps having different heights on a power feeding layer of a substrate and having different heights depending on the first and second resists. By electrically connecting each according to the wiring distance, the wiring distance of the conductive bumps to the stacked semiconductor chips is shortened, so that there is no increase in inductance and it is possible to cope with high speed, and the semiconductor device can be thinned. . In addition, the structure is simple and the manufacturing is easy, and the manufacturing cost can be reduced.

It is a longitudinal cross-sectional view of the semiconductor device which laminated | stacked the semiconductor chip by embodiment of this invention. It is a plane perspective view which shows the laminated | stacked semiconductor chip and protrusion electrode in embodiment. (A)-(d) is sectional drawing which shows an example of a protruding electrode. It is a plane perspective view which shows the modification of the semiconductor device by embodiment. (A)-(l) is a figure which shows the manufacturing method of the semiconductor device by embodiment of this invention. It is a longitudinal cross-sectional view of the semiconductor device by a prior art. It is a longitudinal cross-sectional view which shows the other semiconductor device by a prior art.

Next, the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
The semiconductor device 10 according to the first embodiment shown in FIGS. 1 and 2 shows a plurality of stages, for example, a two-stage stack type multichip module (MCM). A semiconductor device 10 shown in FIG. 1 is provided by laminating a lower first semiconductor chip 12 and an upper second semiconductor chip 13 on a substrate 11 made of, for example, a printed circuit board. The lower first semiconductor chip 12 is provided with protruding electrodes 14 at a predetermined interval on the lower surface, and the protruding electrodes 14 are flip-chip connected to an electrode 11 a disposed on the substrate 11.
As shown in FIG. 2, the first semiconductor chip 12 is formed in, for example, a substantially square plate shape. In the example shown in FIG. 2, a plurality of protruding electrodes 14 are arranged at predetermined intervals in the vertical and horizontal directions on the surface facing the substrate 11. Has been. In a semiconductor chip having a large number of electrodes such as a CPU chip, the protruding electrodes 14 may be arranged on the entire surface of the chip like the first semiconductor chip 12.
Since the first semiconductor chip 12 has a short distance from the substrate 11, the protruding electrode 14 can be constituted by the solder electrode described above and can be flip-chip connected to the substrate.

In the plan view shown in FIG. 2, the second semiconductor chip 13 is formed in a substantially quadrangular plate shape that protrudes outward from the first semiconductor chip 12 on four sides, and a substantially rectangular frame that protrudes outward from the first semiconductor chip 12. A plurality of protruding electrodes 17 are arranged at predetermined intervals so as to surround the chip 12 outside the first semiconductor chip 12 in the shaped region 13a. The frame-shaped region 13 a provided in the second semiconductor chip 13 is flip-chip connected to the electrode 11 a of the substrate 11 by the protruding electrode 17.
In many semiconductor chips such as logic and microcomputer, the protruding electrodes 17 are arranged around the second semiconductor chip 13 like the semiconductor device 10 according to the present embodiment.
In the substrate 11, a plurality of solder bumps 18 are arranged on the surface opposite to the first and second semiconductor chips 12 and 13 for connection to a mother board or the like.

In FIG. 1 and FIG. 2, the protruding electrodes 14 and 17 that are conductive bumps are formed in a columnar shape such as a substantially cylindrical shape. In particular, the protruding electrode 17 longer than the protruding electrode 14 is formed in a two-stage substantially cylindrical shape in FIG. 1, but may be formed in a single substantially cylindrical shape having substantially the same outer diameter over the entire length.
Further, the two-stage semiconductor chips 12, 13 provided on the substrate 11 and the regions where these are flip-chip bonded to the electrodes 11 a of the substrate 11 by the protruding electrodes 14, 17 are sealed with a sealing resin 20.

The bump electrodes 14 and 17 can be formed into solder bump-shaped electrodes by a solder printing method or a solder ball mounting method that has been widely used for flip-chip bonding. If the height is increased as described above, the outer diameter increases, which may cause a problem that hinders the increase in the number of pins of the semiconductor chip and the narrow pitch of the pin arrangement, which is not preferable.
For example, solder formation by a printing method uses paste-like solder, so that it cannot be formed in a column shape elongated in the height direction. For example, in order to obtain a high dimension that can be connected to the second semiconductor chip 13, the substrate 11 It is necessary to increase the electrode area of the portion connected to. In addition, since the solder ball mounting method uses a substantially hemispherical solder, in order to obtain the height of the protruding electrodes 14 and 17, the electrode area of the surface connected to the substrate 11 is increased according to the height.
Therefore, when such a solder bump is used as the protruding electrode 17 for connecting to the second semiconductor chip 13 on the upper stage, the connection area to the substrate 11 is large, which is particularly disadvantageous.

Therefore, the protruding electrodes 14 and 17 are preferably formed of a metal material selected from copper, silver, tin, gold, nickel or the like instead of solder, or a combination thereof, in order to reduce the contact area, and preferably by electrolytic plating. Form in a columnar shape.
In the present embodiment, the protruding electrodes 14 and 17 are formed in a columnar shape by electroplating with a single metal material of any of copper, silver, tin, gold, and nickel. The protruding electrodes 14 and 17 may be formed by joining two or more kinds of metal materials by electrolytic plating.

As an example of such a protruding electrode, a modified example of the protruding electrode 17 (or 14) will be described with reference to FIGS.
The protruding electrode 17 shown in FIG. 3A is constituted by a single columnar electrode layer made of copper, and is connected to the electrode portion 11 a of the substrate 11 and the electrode portion 13 a of the solder bump of the second semiconductor chip 13. Is formed. This configuration is not preferable because copper may be dissolved in the tin component of solder (tin-lead), resulting in poor connection.
The protruding electrode 17 shown in FIG. 3 (b) is formed by connecting a nickel electrode layer 21b in a columnar shape to a copper electrode layer 21a and connecting it to a solder bump electrode portion 13a. In this case, nickel can barrier the dissolution of copper in tin, but the solder wetting spreads poorly.

The protruding electrode 17 shown in FIG. 3 (c) is formed by connecting a gold electrode layer 21b to a copper electrode layer 21a in a columnar shape, and this is connected to the solder bump electrode portion 13a. In this case, gold has good solder wettability, but since gold is dissolved in tin, copper is easily dissolved in tin. However, it is adopted depending on the application.
The protruding electrode 17 shown in FIG. 3 (d) is formed by connecting a nickel electrode layer 21b and a gold electrode layer 21c in a columnar shape to a copper electrode layer 21a. In this case, since the surface is gold, the solder wettability is good and the nickel layer becomes a barrier, so that copper does not dissolve in tin and is most preferable.
Although any of the protruding electrodes shown in FIGS. 3A to 3D described above can be employed, the conductive bump having the configuration shown in FIG. 3D is most preferable.

Next, FIG. 4 is a modification of the semiconductor device 10 according to the first embodiment. In the semiconductor device 10 according to this modification, the second semiconductor chip 22 disposed on the upper stage side with respect to the first semiconductor chip 12 on the lower stage protrudes outward from the first semiconductor chip 12 in two opposing regions. Are formed in a substantially rectangular shape. The protruding electrodes 17 are arranged at predetermined intervals on the protrusions 22 a and 22 a of the second semiconductor chip 22. The protruding electrodes 17 in a semiconductor chip such as a DRAM are often arranged in this manner.
The shape of the second semiconductor chip 22 and the arrangement of the protruding electrodes 17 are not limited to the shape and arrangement shown in FIGS. 2 and 4, and are arbitrary, and protrude outward from the first semiconductor chip 12. It is only necessary to have a region and be directly connected to the substrate 11 by the protruding electrode 17 in a region protruding out of the first semiconductor chip 12.
Further, as a modified example of the conductive bump, instead of the columnar protruding electrodes 14 and 17, a gold stud is provided and the conductive portion that changes to the protruding electrodes 14 and 17 by cutting off the front end side of the linear portion as a gold wire is provided. You may comprise as a bump.

In the semiconductor device 10 according to the present embodiment, the semiconductor chips 12, 13, or 22 to be stacked are configured in two stages, but it is also possible to stack semiconductor chips in three or more stages. In this case, the substantially cylindrical protruding electrodes 14, 17,... According to the present embodiment may be formed in connection with all the semiconductor chips 12, 13 (22),. When connecting the semiconductor chips installed in two or more stages to the substrate 11, the protruding electrodes 14, 17,... According to the present embodiment may be used for at least some of the semiconductor chips.
For example, when the semiconductor chip is configured by stacking three stages, the structure of the first embodiment or the modified example is adopted for the connection structure of the first and second semiconductor chips 12 and 13 (22), and the third stage. If the semiconductor package does not require high-speed signal transmission, it may be connected to the electrode 11a of the substrate 11 using a wire. In particular, when the third-stage semiconductor chip is smaller than the first-stage or second-stage semiconductor chips 12 and 13 (22) and there is no portion protruding outward, the third-stage semiconductor chip is connected to the substrate 11 with a wire or the like.

As described above, according to the semiconductor device 10 according to the present embodiment, the plurality of semiconductor chips 12 and 13 (22) are flip-chip bonded by the protruding electrodes 14 and 17 having a height corresponding to the stacking height. Since the wiring distance between the stacked semiconductor chips 12 and 13 and the substrate 11 is shortened, there is no increase in inductance as compared with the case where bonding wires are used, and it is possible to cope with higher speed. In addition, the semiconductor device 10 can be thinned.
Furthermore, compared with the case where the semiconductor chip is connected by providing a through hole in the semiconductor chip and filling the conductive bumps, the second semiconductor chip 13 on the upper stage side is outside the first semiconductor chip 12 on the lower stage side. Since it is connected to the substrate 11 by the substantially columnar projecting electrode 17, there is no need to form a through hole in the semiconductor chip and fill the conductive bump, and there is no need for a step of polishing the back surface after flip chip mounting, The structure is simple and easy to manufacture, and the manufacturing cost can be reduced.

Next, a method for manufacturing the semiconductor device 10 according to the embodiment of the present invention will be described with reference to FIGS. FIGS. 5A to 5L show an example of a manufacturing process of the stacked multichip module (MCM) according to the embodiment shown in FIGS.
FIG. 5A shows a state in which an electrode pad 11a made of copper is formed on a substrate 11 which is a printed circuit board. Next, in FIG. 2B, a power feeding layer 24 for forming the protruding electrode 14 by electrolytic plating was deposited on the surface of the substrate 11 by electroless plating. The power feeding layer 24 is formed as a thin copper layer by electroless copper plating.
In FIG. 2C, a resist 25 is formed to form the protruding electrode 14 for electrical connection to the first semiconductor chip 12, and a pattern for depositing the protruding electrode 14 is formed. As the resist 25, a photosensitive resist is used, and patterning is performed by exposure and development using a mask on which a pattern of a desired opening 25a is drawn.

In FIG. 4D, the protruding electrode 14 for electrically connecting the first semiconductor chip 12 to the pattern of the opening 25a formed of the resist 25 is grown by electrolytic plating. The resist 25 is peeled off after the plating is formed (see FIG. 5E).
Then, as shown in FIG. 5F, a resist 26 for depositing the protruding electrode 17 for electrically connecting the second semiconductor chip 13 is formed and patterned. As the resist 26, a photosensitive resist is used. Patterning is performed by exposure and development using a mask on which a pattern of the opening 26a formed only in the region of the protruding electrode 14 for forming the protruding electrode 17 as a desired pattern is drawn.
In this example, the opening 26a of the resist 26 is formed smaller than the first plating deposition opening 25a, but it may be the same size or larger.

Then, a columnar protruding electrode for the second semiconductor chip 13 is grown on the protruding electrode 14 by electrolytic plating in the opening 26a of the resist 26 to form a protruding electrode 17 having a height higher than the protruding electrode 14 ( (See (g) in the figure). Next, the resist 26 is peeled off (see FIG. 11H). Then, as shown in FIG. 4I, the power feeding layer 24 is removed by etching except for the protruding electrodes 14 and 17.
Further, in FIG. 6J, solder bumps 18 are formed on the surface of the printed board 11 opposite to the protruding electrodes 14 and 17. The solder bumps 18 are formed, for example, by mounting solder balls and reflowing. In FIG. 4 (k), electrode pads 28 and 29 provided on the first and second semiconductor chips 12 and 13 are provided with preliminary solders 30 and 30 and aligned with the protruding electrodes 14 and 17, respectively. . Then, as shown in FIG. 1L, the electrode pads 28 and 29 of the first and second semiconductor chips 12 and 13 and the protruding electrodes 14 and 17 are joined by reflow. Further, the first and second semiconductor chips 12 and 13 that are electrically connected via the protruding electrodes 14 and 17 on the substrate 11 are sealed with a sealing resin 20.
In this way, the semiconductor device 10 can be manufactured.

As described above, according to the manufacturing method of the semiconductor device 10 according to the present embodiment, since the electroless copper plating and the electrolytic copper plating are used for forming the protruding electrodes 14 and 17, the conventional printed circuit board manufacturing process, semiconductor chip mounting The stacked MCM semiconductor device 10 can be manufactured without introducing special new equipment into the process and the semiconductor package manufacturing process.
Further, the first and second semiconductor chips 12 and 13 are formed by stacking the protruding electrodes 14 and 17 having different heights by the first and second resists 25 and 26 on the power feeding layer 24 of the substrate 11. By connecting them according to the height, the wiring distance of the protruding electrodes 14 and 17 with respect to the stacked semiconductor chips 12 and 13 can be shortened, so that there is no increase in inductance, and it is possible to cope with high-speed signal transmission. It is simple and easy to manufacture, and the semiconductor device 10 can be thinned.

  In addition, since the protruding electrodes 14 and 17 are formed by columnar deposition by electroless plating and electrolytic plating, even if the distance from the substrate 11 is increased by stacking the plurality of semiconductor chips 12 and 13, the substrate 11 or The protruding electrodes 14 and 17 do not spread on the semiconductor chips 12 and 13 and the number of pins of the semiconductor chips 12 and 13 can be increased. Therefore, it is particularly useful for electronic devices that require thinning, high speed, and other pins.

In the present invention, the protruding electrodes 14 and 17 constitute a conductive bump.
In the semiconductor device 10 shown in FIG. 1, the first and second semiconductor chips 12 and 13 are stacked apart from each other. However, the first and second semiconductor chips 12 and 13 are bonded to each other through an insulating material such as an adhesive. Also good.
In the above-described embodiment, the protruding electrodes 14 and 17 of the stacked semiconductor chips 12 and 13 are configured to be flip-chip bonded to the substrate 11 such as a printed circuit board. As described above, the protruding electrodes 14 and 17 may be electrically connected to electrodes of another semiconductor chip by flip chip bonding or the like.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Board | substrate 12 1st semiconductor chip 13 2nd semiconductor chip 14, 17 Protruding electrode 18 Solder bump 20 Sealing resin 24 Feed layer 25, 26 Resist 28, 29 Electrode pad 30 Preliminary solder

Claims (6)

  A semiconductor device in which a plurality of semiconductor chips are stacked and integrated, wherein the stacked semiconductor chips are electrically connected by conductive bumps having different wiring distances.   The second semiconductor chip farther than the first semiconductor chip is electrically connected to the conductive bump in a region protruding outward from the first semiconductor chip with respect to the connection object of the conductive bump. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the conductive bump that is electrically connected to the semiconductor chip on at least a far side with respect to the connection target of the conductive bump is formed in a substantially columnar shape.   4. The conductive bump according to claim 1, wherein the conductive bump is formed by laminating any material selected from copper, silver, tin, gold, and nickel, or any two or more kinds of materials. Semiconductor device.   The semiconductor device according to claim 1, wherein the conductive bump is formed by electrolytic plating. In a manufacturing method of a semiconductor device formed by stacking and integrating a plurality of semiconductor chips,
Forming a power supply layer on the substrate by electroless plating;
Forming and patterning a first resist on the power feeding layer;
Growing a first conductive bump on the first resist pattern by electrolytic plating;
Forming and patterning the second resist; and growing at least a portion of the first conductive bumps by electroplating the second conductive bumps with a pattern of the second resist;
Bonding the first semiconductor chip to the first conductive bump and bonding the second semiconductor chip to the second conductive bump,
A method of manufacturing a semiconductor device, wherein the first semiconductor chip and the second semiconductor chip are stacked.

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