JP2010021416A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, capable of suppressing occurrence of a well proximity effect. <P>SOLUTION: The method for manufacturing a semiconductor device includes forming an anti-reflective coating BK on a main surface of a semiconductor substrate SUB. A resist pattern PR1 having an inclination widening toward a side of the semiconductor substrate SUB at a pattern end portion is formed on the anti-reflective coating BK. Ions are implanted into the main surface of the semiconductor substrate SUB using the resist pattern PR1 as a mask. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an ion implantation process using a resist pattern as a mask.

  Conventionally, in order to form elements such as transistors and diodes on a semiconductor substrate, it has been necessary to selectively implant impurity ions. A photolithography technique is used to form a resist pattern on a semiconductor substrate, and accelerated ions are implanted into the semiconductor wafer using the resist pattern as a mask. In the portion of the resist pattern where the resist remains, ions are trapped in the resist film and do not reach the substrate. On the other hand, in the portion of the resist pattern where no resist remains, the ions reach the inside of the substrate and become impurities, forming an n-type or p-type semiconductor region.

  The ions trapped in the resist collide with atoms constituting the resist, so that the energy is lost while the molecules are cut and polymerized, and then stop. Since the resist is an organic substance composed of a resin or a photosensitizer, it generally has an amorphous structure rather than a crystal. Therefore, ions implanted into the resist are scattered in all directions by colliding with atoms constituting the resist.

  The average distance until the ions stop (average free path) is approximately 1 μm, although it depends on the acceleration voltage, ion species, and resist composition. Therefore, in order to reliably trap ions in the resist, the resist film thickness needs to be 1 to 2 μm. Thus, inside the resist, ions move about 1 μm until they completely stop.

  The ions implanted into the resist in this manner are scattered in all directions in the resist and move in the mean free path. For this reason, in the case of ions that have entered the resist within a range within the mean free path from the side wall of the resist pattern, there are not a few ions that go out of the resist from the resist side wall before reaching the mean free path.

  Since the ions that have come out of the resist reach the semiconductor substrate, a region where ions are implanted more than necessary is formed in the semiconductor substrate, and the impurity distribution becomes uneven. That is, the performance of the element formed in the vicinity of the pn isolation boundary varies compared to the element characteristics at other positions. This effect is called the well proximity effect.

Such well proximity effects are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2007-36249 and 2007-305858.
JP 2007-36249 A JP 2007-305858 A

  Due to the well proximity effect, the performance of the element formed in the vicinity of the pn isolation boundary fluctuates compared to the element characteristics at other positions. From the viewpoint of designing an LSI (Large Scale Integrated Circuit), this appears as an inconvenience that variation in element performance increases.

  When designing an LSI, it is common to design in consideration of a certain degree of device characteristic variation. However, assuming that the variation is large, it is necessary to provide a sufficient margin, and as a result, the chip size is increased. At this time, there is a problem that the number of semiconductor integrated circuits that can be manufactured on one wafer is reduced and the chip unit price is increased.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of suppressing the occurrence of a well proximity effect.

The manufacturing method of the semiconductor device according to the present embodiment includes the following steps.
First, an antireflection film is formed on the main surface of the semiconductor substrate. On the antireflection film, a resist pattern having an inclination is formed so that the pattern spreads toward the semiconductor substrate side at the pattern end. Ions are implanted into the main surface of the semiconductor substrate using the resist pattern as a mask.

  According to the method for manufacturing a semiconductor device of the present embodiment, an antireflection film is formed on the main surface of the semiconductor substrate during ion implantation. For this reason, secondary ions scattered from the side wall of the resist pattern during ion implantation are captured by the antireflection film and hardly reach the main surface of the semiconductor substrate. Thereby, the implantation of secondary ions into the main surface of the semiconductor substrate is suppressed, and the occurrence of the well proximity effect can be suppressed.

  Further, the pattern end portion of the resist pattern has an inclination that spreads toward the semiconductor substrate side. For this reason, generation | occurrence | production of the secondary ion which goes to the main surface of a semiconductor substrate from a resist pattern can be suppressed. Thereby, the implantation of secondary ions into the main surface of the semiconductor substrate is suppressed, and the occurrence of the well proximity effect can be suppressed.

  Further, since the resist pattern is formed on the antireflection film, the end of the resist pattern can be inclined so as to spread toward the semiconductor substrate side.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a flowchart showing an ion implantation process in the method of manufacturing a semiconductor device in the first embodiment of the present invention. Referring to FIG. 1, in the ion implantation process, first, a semiconductor substrate for forming a semiconductor integrated circuit device is prepared. This semiconductor substrate is fixed on the stage (step S1). In this state, a photoresist is applied on the semiconductor substrate (step S2). The photoresist is selectively exposed (step S3), and after the exposure, the resist is developed to form a resist pattern having a fine pattern (step S4). Using this resist pattern as a mask, ions are selectively implanted into the main surface of the semiconductor substrate (step S5). Thereafter, the resist pattern is removed (step S6).

  By the ion implantation process described above, ions are selectively implanted into the main surface of the semiconductor substrate, whereby, for example, a well region or the like is formed on the main surface of the semiconductor substrate.

  In the method of manufacturing a semiconductor device in the embodiment of the present invention, a special improvement is applied to the photolithography method in the above ion implantation process. Thereby, secondary ions scattered from the resist pattern are suppressed from reaching the main surface of the semiconductor substrate, and a substantially uniform ion implantation profile is realized.

  In the present embodiment, the following means are adopted as means for suppressing ions scattered by the resist pattern from reaching the main surface of the semiconductor substrate.

  (1) After a photoresist is formed on a BARC (Bottom Anti-Reflective Coating) and the photoresist is developed, ions are implanted into the main surface of the semiconductor substrate through the BARC using the photoresist as a mask. After ion implantation, the BARC is peeled off as necessary.

  (2) After a resist pattern is formed on the main surface of the semiconductor substrate, the resist pattern is subjected to RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) treatment, and silicon (Si), germanium ( An organic material layer containing Ge) is formed. Ions are implanted into the main surface of the semiconductor substrate using the organic material layer and the resist pattern as a mask.

  (3) Ions are implanted into the main surface of the semiconductor substrate using a resist pattern having silicon, germanium and a dye as a mask.

  (4) The photoresist (or resist pattern) before the ion implantation process is entirely irradiated with an electron beam, and ions are implanted into the main surface of the semiconductor substrate using the negatively charged resist pattern as a mask.

  The well proximity effect can be quantified by measuring the impurity profile of ions implanted by the above means (1) to (4) with a transmission electron microscope.

  By injecting ions into the main surface of the semiconductor substrate by means of (1) to (4) above, the well proximity effect is reduced, so that a pn isolation boundary (for example, a p-type well and an n-type well in the semiconductor substrate). The fluctuation in the performance of the element formed near the boundary) can be reduced. From the viewpoint of designing an LSI (Large Scale Integrated circuit), there is an advantage that variation in element performance is reduced.

  When designing an LSI, it is common to design in consideration of a certain degree of device characteristic variation. The small variation means that the chip size can be reduced because it is not necessary to take a design margin more than necessary. That is, there is an advantage that the number of semiconductor integrated circuits that can be manufactured on one wafer increases and the chip unit price decreases.

  The means (1) to (4) described above can be employed alone or in any combination thereof in consideration of the degree of reduction of the well proximity effect.

(Embodiment 2)
This embodiment is based on the means (1) of the first embodiment.

  2 and 3A are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. FIG. 3B is a diagram showing the distribution of the p-type impurity concentration in the p-type well along the alternate long and short dash line IIIB-IIIB in FIG.

  Referring to FIG. 2, in the method of manufacturing a semiconductor device of the present embodiment, first, n-type region NR is formed on the main surface of p-type semiconductor substrate SUB. Trench TR is formed in the main surface of semiconductor substrate SUB, and filling layer BI is formed so as to fill trench TR. The trench TR and the filling layer BI constitute an STI (Shallow Trench Isolation).

  On the main surface of the semiconductor substrate SUB, an antireflection film BK to be BARC is formed. BARC is a coating-type antireflection film formed under a photoresist, and has the effect of eliminating halation from the underlying step by eliminating reflected light from the semiconductor substrate SUB. A photoresist PR1 is applied on the antireflection film BK. Thereafter, the photoresist PR1 is patterned by photolithography to form a resist pattern PR1.

  At this time, the resist pattern PR1 is formed so that the pattern end of the resist pattern PR1 is inclined so as to spread from the top toward the main surface of the semiconductor substrate SUB. The resist pattern PR1 having such an inclination can be formed by appropriately setting the thickness d of the antireflection film BK as will be described later.

  The inclination angle θ of the pattern end of the resist pattern PR1 is preferably 2 ° or more and 5 ° or less.

  Ions are implanted into the main surface of the semiconductor substrate SUB using the resist pattern PR1 as a mask. By this ion implantation, for example, a p-type well PW is formed on the main surface of the semiconductor substrate SUB. Thereafter, the resist pattern is removed by, for example, ashing, and the antireflection film BK is removed by, for example, etching.

  Referring to FIG. 3A, n-type well NW is formed on the main surface of semiconductor substrate SUB so as to be adjacent to p-type well PW by a method similar to the method for forming p-type well PW. Thereafter, an electronic device such as an n-channel MOS (Metal Oxide Semiconductor) transistor (hereinafter referred to as an nMOS transistor) NT is formed on the main surface of the semiconductor substrate SUB. In forming the nMOS transistor NT, first, a gate oxide film GI and a gate electrode GE are formed on the main surface of the semiconductor substrate SUB. By performing ion implantation or the like on the main surface of the semiconductor substrate SUB using the gate electrode or the like as a mask, a relatively low concentration n-type region LD is formed on the main surface of the semiconductor substrate SUB.

  Thereafter, sidewall insulating layer SW is formed on the main surface of semiconductor substrate SUB so as to cover the sidewall of gate electrode GE. By performing ion implantation or the like on the main surface of the semiconductor substrate SUB using the sidewall insulating layer SW, the gate electrode GE, and the like as a mask, a relatively high concentration n-type region HD is formed on the main surface of the semiconductor substrate SUB.

  A source / drain region SD having an LDD (Lightly Doped Drain) or MDD (Middle Doped Drain) structure is formed by the relatively low concentration n-type region LD and the relatively high concentration n-type region HD. Then, the nMOS transistor NT is formed by the pair of source / drain regions SD, the gate oxide film GI, and the gate electrode GE.

Also, a p ⁺ region PR is formed on the surface of the p-type well PW by ion implantation or the like. A refractory metal is formed in contact with the surfaces of p ⁺ region PR, source / drain region SD, and gate electrode GE, and heat treatment is performed. As a result, a refractory metal silicide layer SC is formed at the portion where each of the p ⁺ region PR, the source / drain region SD and the gate electrode GE is in contact with the refractory metal. Thereafter, unreacted refractory metal is removed.

Thus, the semiconductor device of this embodiment shown in FIG. 3A is manufactured.
Next, the operational effects of this embodiment will be described in comparison with the case where ions are implanted by the method shown in FIG.

  FIG. 4A is a diagram illustrating a state in which ion implantation is performed in a state where the antireflection film is not formed and the pattern end portion of the resist pattern is not inclined. FIG. 4B is a diagram showing the distribution of the p-type impurity concentration at positions along the alternate long and short dash line IVB-IVB in FIG.

  Referring to FIG. 4A, the antireflection film is not formed, and the pattern end of resist pattern PR is not inclined (that is, the pattern end is substantially perpendicular to the main surface of semiconductor substrate SUB). ), Secondary ions are excessively implanted into the main surface of the semiconductor substrate SUB from the side wall of the resist pattern PR during ion implantation.

  As a result, as shown in FIG. 4B, p-type impurity ions are excessively implanted in the vicinity of the pattern end (near the pn separation boundary), and the concentration distribution of the p-type impurity becomes nonuniform. For this reason, a so-called well proximity effect is produced in which the performance of the element formed in the vicinity of the pn isolation boundary fluctuates in comparison with the characteristics of the element formed in another position (for example, the central portion of the p-type well PW).

  On the other hand, according to the present embodiment, the antireflection film BK is formed on the main surface of the semiconductor substrate SUB during the ion implantation shown in FIG. For this reason, secondary ions scattered from the sidewall of the resist pattern PR1 during ion implantation are trapped in the antireflection film BK. That is, the secondary ions coming out of the resist pattern PR1 have already lost energy to some extent and are incident on the antireflection film BK obliquely, and can be trapped on the surface or inside of the antireflection film BK. This makes it difficult for secondary ions to reach the main surface of the semiconductor substrate SUB.

  Further, the pattern end portion of the resist pattern PR1 has an inclination that spreads from the top toward the main surface side of the semiconductor substrate SUB. For this reason, generation of secondary ions from the resist pattern PR1 toward the main surface of the semiconductor substrate SUB can be suppressed. Thereby, implantation of secondary ions into the main surface of the semiconductor substrate SUB is suppressed.

  As described above, according to the present embodiment, as shown in FIG. 3B, the non-uniformity of the p-type impurity concentration distribution at the end of the p-type well PW is improved as compared with FIG. As a result, the occurrence of the well proximity effect can be suppressed.

  Further, since the reflection light from the semiconductor substrate SUB can be suppressed by the antireflection film BK, the controllability of the dimension of the resist pattern PR1 is improved.

  In the present embodiment, it is preferable that the inclination angle θ of the pattern end portion of the resist pattern PR1 shown in FIG. 2 is 2 ° or more and 5 ° or less. This will be described below.

  The secondary ions are re-emitted around the normal direction of the sidewall of the resist pattern PR1. From this, it is necessary to consider the following two factors when determining the inclination angle θ.

  (A) From the viewpoint of expecting an improvement effect on the well proximity effect, the inclination angle θ at the pattern edge of the resist pattern PR1 should be larger.

  (B) If the inclination angle θ at the pattern edge of the resist pattern PR1 is too large, the chip area of the inclined portion of the inclination is wasted. Therefore, from the viewpoint of pursuing miniaturization of the semiconductor chip, it is better that the inclination angle θ is small.

  Since the above (a) and (b) are contradictory, in order to estimate the optimum value, the present inventor performed a Monte Carlo simulation of ion implantation.

This Monte Carlo simulation was performed using the structure shown in FIG. FIG. 5 shows a schematic cross-sectional view of the simulated structure. Referring to FIG. 5, the structure used for the simulation is a silicon substrate SUB, an antireflection film BK made of silicon oxide (SiO ₂ ) selectively formed on the surface of the silicon substrate SUB, and an antireflection film BK. And a resist pattern PR1 formed thereon.

With respect to this structure, a simulation was performed in the case of forming a p-type diffusion layer in the silicon substrate SUB by implanting boron ions (B ⁺ ) under the conditions of implantation energy: 200 keV and dose amount: 1 × 10 ¹³ / cm ^−2. It was. The results are shown in FIG. 6 and FIG.

  FIG. 6 shows the concentration distribution in the depth direction (Z direction) at each of the portion (center) along the alternate long and short dash line VIA-VIA and the portion (end) along the alternate long and short dashed line VIB-VIB in the structure of FIG. Yes. FIG. 7 shows the concentration distribution in the horizontal direction (X direction) of the portion along the alternate long and short dash line VIIA-VIIB in the structure of FIG.

  From the result of FIG. 6, when comparing the concentration distribution in the depth direction between the central portion and the end portion of the p-type diffusion layer, the pattern end portion is inclined even if the inclination angle is only 2 ° to 3 °. It can be seen that the influence of secondary ions is reduced. In particular, the influence of secondary ions is significantly reduced near the surface of the silicon substrate SUB at the end of the p-type diffusion layer.

  From the result of FIG. 7, it can be seen that the concentration of the end portion of the p-type diffusion layer is higher by one digit than the concentration of the central portion of the p-type diffusion layer due to the influence of the resist pattern PR1. It can also be seen that the inclination angle θ has a slight dependency at the end of the p-type diffusion layer.

  According to the results of these Monte Carlo simulations, the influence of secondary ions (that is, the well proximity effect) is reduced if the pattern end is inclined even if the inclination angle θ is only 2 ° to 3 °. If the inclination angle θ is too large (θ = 10 °), ions that pass through the resist pattern and are implanted into the main surface of the silicon substrate SUB cannot be ignored. Therefore, a preferable range of the inclination angle θ in the present embodiment is set to 2 ° to 5 °.

  Next, a method for providing the inclination angle θ to the resist pattern PR1 shown in FIG. 2 will be described.

  As a method of providing the inclination angle θ, there is a method of adopting an antireflection film BK to be BARC. However, in order to control the inclination angle θ to 2 ° to 5 °, the following method is required.

  First, in the normal BARC process, the film thickness d of the antireflection film BK is used such that the phase of the reflected light from the upper and lower surfaces of the antireflection film BK is inverted by 180 °. That is, by reversing the phase of the light reflected from the antireflection film BK by 180 ° with respect to the light incident on the antireflection film BK, the incident light and the reflected light cancel each other to prevent reflection.

  Here, for example, assuming that the resist patterns PR1, the antireflection film BK, and the semiconductor substrate SUB have respective refractive indexes Nresist, Nbarc, and Nsub, and the relationship of Nresist <Nbarc <Nsub is satisfied, then 4 × Nbarc × The relationship d = m × λ is established. Further, when the relationship Nbarc × Nbarc = Nresist × Nsub is established, the minimum reflectance can be set. This condition is a relationship often used in an antireflection process on a mask or wafer.

  However, in order to set the inclination angle θ of the resist pattern PR1 to 2 ° to 5 °, the reflected light is not completely reduced to 0, but some controlled reflected light is required. For example, a film thickness d of the antireflection film BK that sets the phase of the reflected light from the upper and lower surfaces of the antireflection film BK to 90 ° or 270 ° can be used.

  At this time, 4 × Nbarc × d = (m + 1/4) × λ and 4 × Nbarc × d = (m−1 / 4) × λ are established. When this condition is satisfied, reflected light from the antireflection film BK, which is the base of the resist pattern PR1, is moderately generated, and a resist pattern PR1 having an inclination angle θ of 2 ° to 5 ° is obtained. In the future, as the entire process becomes finer, the exposure wavelength, resist, BARC material, and the like will be changed. Needless to say, optimization work is required each time.

  By appropriately setting the film thickness d of the antireflection film as described above, it is possible to form the resist pattern PR1 having a pattern end portion having an inclination angle θ of 2 ° to 5 °.

(Embodiment 3)
This embodiment is based on the means (2) of the first embodiment.

  FIG. 8 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device in the third embodiment of the present invention. Referring to FIG. 8, in the present embodiment, n-type regions NR and STI are formed on the main surface of semiconductor substrate SUB through the same steps as in the second embodiment.

  Thereafter, a photoresist PR2 is applied on the main surface of the semiconductor substrate SUB. Thereafter, the photoresist PR2 is patterned by photolithography to form a resist pattern PR2. An organic material layer RE containing at least one of silicon and germanium is formed by, for example, RELACS processing so as to cover the periphery of the resist pattern PR2.

  Ions are implanted into the main surface of the semiconductor substrate SUB using the resist pattern PR1 and the organic material layer RE as a mask. By this ion implantation, for example, a p-type well PW is formed on the main surface of the semiconductor substrate SUB. Thereafter, the organic material layer RE and the resist pattern are removed.

  Referring to FIG. 3A, n-type well NW is formed on the main surface of semiconductor substrate SUB so as to be adjacent to p-type well PW by a method similar to the method for forming p-type well PW. Thereafter, through the same process as in the first embodiment, an electronic device such as an nMOS transistor NT is formed on the main surface of semiconductor substrate SUB. Thereby, the semiconductor device of the present embodiment shown in FIG. 3A is manufactured.

  Next, a method for forming the organic material layer RE shown in FIG. 8 by RELACS processing will be specifically described.

  9 to 12 are schematic cross-sectional views showing, in the order of steps, a method of forming the organic material layer RE by the RELACS process in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. Referring to FIG. 9, resist pattern PR2 is formed on the main surface of semiconductor substrate SUB on which STI is formed.

  Referring to FIG. 10, organic material PR3 is formed on the main surface of semiconductor substrate SUB so as to cover resist pattern PR2. This organic material PR3 is made of a material that contains at least one of silicon and germanium and cures by causing a thermal crosslinking reaction using an acid component in the resist pattern PR2 as a catalyst. The organic material PR3 is made of an aqueous base-soluble silicon-containing phenolic polymer containing, for example, at least one of silicon and germanium.

  When a silicon-containing resist is used for the organic material PR3, silicon-containing resists having various structures and compositions as disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-221687 are used. Further, from the viewpoint of shielding secondary ions, a configuration in which the silicon content of the base resin is high is preferable.

After the organic material layer RE is formed as described above, heat treatment is performed.
Referring to FIG. 11, by the heat treatment described above, organic material PR3 is cured by causing a thermal crosslinking reaction using an acid component in resist pattern PR2 as a catalyst in a portion in contact with resist pattern PR2. As a result, an organic material layer RE containing at least one of silicon and germanium is formed around the resist pattern PR2. Thereafter, the uncured portion of the organic material PR3 is removed by washing with water, for example.

  Referring to FIG. 12, the uncured portion of organic material PR3 is removed by the water washing removal described above, and the main surface of semiconductor substrate SUB is exposed. Thereby, the organic material layer RE covering the periphery of the resist pattern PR2 is formed by the RELACS process.

Next, the effect of this Embodiment is demonstrated.
According to the present embodiment, at the time of ion implantation, the organic material layer RE is formed around the resist pattern PR2, and the organic material layer RE contains at least one of silicon and germanium. For this reason, the ions implanted into the organic material layer RE during ion implantation collide with silicon or germanium in the organic material layer RE. Since silicon and germanium are heavier elements than carbon, ions that collide with silicon or germanium lose greater kinetic energy than when they collide with carbon, and therefore the mean free path of ions in the organic material layer RE is reduced. . Accordingly, ions are less likely to exit from the organic material layer RE, and secondary ion implantation into the main surface of the semiconductor substrate SUB is suppressed.

  As described above, in this embodiment as well, as shown in FIG. 3B, the non-uniformity of the p-type impurity concentration distribution at the end of the p-type well PW is shown in FIG. Better than. As a result, the occurrence of the well proximity effect can be suppressed.

(Embodiment 4)
This embodiment is based on the means (3) of the first embodiment.

  FIG. 13 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device in the fourth embodiment of the present invention. Referring to FIG. 13, in the present embodiment, n-type regions NR and STI are formed on the main surface of semiconductor substrate SUB through the same steps as in the second embodiment.

  Thereafter, a photoresist PR4 containing one or more selected from the group consisting of silicon, germanium and a dye is applied on the main surface of the semiconductor substrate SUB. Thereafter, the photoresist PR4 is patterned by photolithography to form a resist pattern PR4.

  Ions are implanted into the main surface of the semiconductor substrate SUB using the resist pattern PR4 as a mask. By this ion implantation, for example, a p-type well PW is formed on the main surface of the semiconductor substrate SUB. Thereafter, resist pattern PR4 is removed by, for example, ashing.

  Referring to FIG. 3A, n-type well NW is formed on the main surface of semiconductor substrate SUB so as to be adjacent to p-type well PW by a method similar to the method for forming p-type well PW. Thereafter, through the same process as in the first embodiment, an electronic device such as an nMOS transistor NT is formed on the main surface of semiconductor substrate SUB. Thereby, the semiconductor device of the present embodiment shown in FIG. 3A is manufactured.

  In the above, when a silicon-containing resist is used for the photoresist PR4, a resist using an aqueous base-soluble silicon-containing phenolic polymer as disclosed in JP 2000-221687A can be used.

  Silicon-containing resists used for the photoresist PR4 include silicon-containing resists having various structures and compositions as disclosed in Japanese Patent Application Laid-Open No. 2000-221687. Further, from the viewpoint of shielding secondary ions, a configuration in which the silicon content of the base resin is high is preferable.

  In the above, when a dye-containing resist is used for the photoresist PR4, an azo dye can be used as a dye to be included in the photoresist PR4. Azo dyes have various structures and compositions as disclosed in JP-A-2008-7732. From the viewpoint of shielding secondary ions, it is preferable that atoms with as large an atomic number as possible are included.

  According to the present embodiment, the resist pattern PR4 includes at least one of silicon, germanium, and a dye. For this reason, the ions implanted into the resist pattern PR4 at the time of ion implantation collide with silicon, germanium, or a dye in the resist pattern PR4. Since silicon, germanium, and pigment are heavier than carbon, ions that collide with silicon, germanium, and pigment lose greater kinetic energy than when they collide with carbon, so the mean free path of ions in resist pattern PR4 is reduced. . Therefore, ions are less likely to exit from the resist pattern PR4, and secondary ion implantation into the main surface of the semiconductor substrate SUB is suppressed.

  As described above, in this embodiment as well, as shown in FIG. 3B, the non-uniformity of the p-type impurity concentration distribution at the end of the p-type well PW is shown in FIG. Better than. As a result, the occurrence of the well proximity effect can be suppressed.

(Embodiment 5)
This embodiment is based on the means (4) of the first embodiment.

  FIG. 14 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device in the fifth embodiment of the present invention. Referring to FIG. 14, in the present embodiment, n-type regions NR and STI are formed on the main surface of semiconductor substrate SUB through the same steps as in the second embodiment.

  Thereafter, a negatively charged resist pattern PR5 is formed on the main surface of the semiconductor substrate SUB. The step of negatively charging the resist pattern PR5 includes, for example, a step of irradiating the photoresist with an electron shower.

  Ions are implanted into the main surface of the semiconductor substrate SUB using the negatively charged resist pattern PR5 as a mask. By this ion implantation, for example, a p-type well PW is formed on the main surface of the semiconductor substrate SUB. Thereafter, resist pattern PR4 is removed by, for example, ashing.

  Referring to FIG. 3A, n-type well NW is formed on the main surface of semiconductor substrate SUB so as to be adjacent to p-type well PW by a method similar to the method for forming p-type well PW. Thereafter, through the same process as in the first embodiment, an electronic device such as an nMOS transistor NT is formed on the main surface of semiconductor substrate SUB. Thereby, the semiconductor device of the present embodiment shown in FIG. 3A is manufactured.

  According to the present embodiment, the resist pattern PR5 is negatively charged by the electron shower irradiation. The ions implanted into the semiconductor substrate SUB during ion implantation are usually positive ions. Therefore, in the initial stage of ion implantation, ions are attracted to the resist pattern PR5 by Coulomb attraction, and ions implanted into the resist pattern PR5 become secondary ions and are not easily released from the resist pattern PR5. Therefore, ions are less likely to exit from the resist pattern PR5, and secondary ion implantation into the main surface of the semiconductor substrate SUB is suppressed.

  As described above, in this embodiment as well, as shown in FIG. 3B, the non-uniformity of the p-type impurity concentration distribution at the end of the p-type well PW is shown in FIG. Better than. As a result, the occurrence of the well proximity effect can be suppressed.

(Embodiment 6)
In this embodiment, the impurity proximity profile of ions as shown in FIG. 3B improved by the ion implantation method in Embodiments 1 to 5 is measured by a transmission electron microscope, so that the well proximity effect is obtained. Is quantified.

  Since the well proximity effect can be quantified using the transmission electron microscope as described above, the improvement effect according to the first to fifth embodiments can be monitored. As a result of this monitoring, if the improvement effect is insufficient, the conditions of the second to fifth embodiments can be changed, or a plurality of embodiments of the second to fifth embodiments can be used in combination. In addition, if the improvement effect is excessive, it can be adjusted by changing the conditions of Embodiments 2 to 5 so that the improvement effect is appropriate. As a result, the well proximity effect can be effectively reduced, and variations in transistor performance can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a method of manufacturing a semiconductor device having an ion implantation process using a resist pattern as a mask.

It is a flowchart which shows the ion implantation process in the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 which concerns on this invention. Schematic cross-sectional view (A) showing the first step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and the distribution of the p-type impurity concentration in the p-type well along the dashed-dotted line IIIB-IIIB in FIG. It is a figure (B) shown. FIG. 6A is a diagram showing a state in which ion implantation is performed in a state where an antireflection film is not formed and the pattern end portion of the resist pattern is not inclined, and p-type at a position along the alternate long and short dash line IVB-IVB. It is a figure (B) which shows distribution of impurity concentration. The schematic sectional drawing of the structure which performed the Monte Carlo simulation is shown. FIG. 6 shows concentration distributions in the depth direction in a portion (center) along the alternate long and short dash line VIA-VIA and a portion (end) along the alternate long and short dash line VIB-VIB in the structure of FIG. The density distribution of the horizontal direction of the part in alignment with the dashed-dotted line VIIA-VIIB in the structure of FIG. 5 is shown. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 3 of this invention. In the manufacturing method of the semiconductor device in Embodiment 3 of the present invention, it is a schematic sectional view of the 1st process of the method of forming organic material layer RE by RELACS processing. In the manufacturing method of the semiconductor device in Embodiment 3 of this invention, it is a schematic sectional drawing of the 2nd process of the method of forming organic-material layer RE by RELACS process. In the manufacturing method of the semiconductor device in Embodiment 3 of this invention, it is a schematic sectional drawing of the 3rd process of the method of forming organic-material layer RE by RELACS process. In the manufacturing method of the semiconductor device in Embodiment 3 of this invention, it is a schematic sectional drawing of the 4th process of the method of forming organic-material layer RE by RELACS process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 5 of this invention.

Explanation of symbols

  BI filling layer, BK antireflection film, GE gate electrode, GI gate oxide film, HD relatively high concentration region, LD relatively low concentration region, NR n-type region, NT nMOS transistor, PR, PR1, PR2, PR4 , PR5 resist pattern, PR3 organic material, PW p-type well, RE organic material layer, SC silicide layer, SD source / drain region, SUB semiconductor substrate, SW sidewall insulating layer, TR trench.

Claims (8)

Forming an antireflection film on the main surface of the semiconductor substrate;
Forming a resist pattern on the antireflection film having an inclination such that the pattern spreads toward the semiconductor substrate at a pattern end; and
And a step of implanting ions into the main surface of the semiconductor substrate using the resist pattern as a mask.   The step of forming the resist pattern includes the step of forming the resist pattern so that an end of the pattern spreads toward the semiconductor substrate at an inclination angle of 2 ° or more and 5 ° or less. Semiconductor device manufacturing method. Forming a resist pattern on the main surface of the semiconductor substrate;
Forming an organic material layer containing at least one of silicon and germanium around the resist pattern;
And a step of implanting ions into the main surface of the semiconductor substrate using the resist pattern and the organic material layer as a mask. The step of forming the organic material layer includes
Forming an organic material containing at least one of silicon and germanium and curing by causing a thermal crosslinking reaction using an acid component in the resist pattern as a catalyst; and covering the resist pattern;
Forming the organic material layer around the resist pattern by heat-curing the organic material at a portion in contact with the resist pattern by performing a heat treatment. Method. Forming a resist pattern including one or more selected from the group consisting of silicon, germanium and a dye on the main surface of the semiconductor substrate;
And a step of implanting ions into the main surface of the semiconductor substrate using the resist pattern as a mask. Forming a negatively charged resist pattern on the main surface of the semiconductor substrate;
And a step of implanting ions into the main surface of the semiconductor substrate using the resist pattern as a mask.   The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming a negatively charged resist pattern includes a step of irradiating the resist pattern with electrons.   The method of manufacturing a semiconductor device according to claim 1, wherein the ions are implanted into the main surface in order to form a well on the main surface of the semiconductor substrate.

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