JP2010087067A - Method of manufacturing soi substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify processes and to lower the cost even when a nitrogen-containing layer is provided between a silicon substrate and a base substrate, and to reduce laminating defects even when a substrate having waving such as a glass substrate is used as the base substrate. <P>SOLUTION: The method of manufacturing an SOI substrate includes the processes of: preparing a single-crystal semiconductor substrate and the base substrate; forming an oxide film on the single-crystal semiconductor substrate; forming an embrittled region in the single crystal semiconductor substrate through irradiation with ions; forming the nitrogen-containing layer on the oxide film or base substrate using a plasma CVD method; laminating the single-crystal semiconductor substrate and base substrate together with the oxide film and nitrogen-containing layer interposed; and separating the single-crystal semiconductor substrate at the embrittled region to form a single-crystal semiconductor layer on the base substrate with an insulating layer and the nitrogen-containing layer interposed, the nitrogen-containing layer being formed under conditions of a substrate temperature from a room temperature to &le;300&deg;C and a filming pressure of &ge;160 Pa. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a method for manufacturing a substrate provided with a semiconductor layer with an insulating film interposed therebetween, and particularly to a method for manufacturing an SOI (Silicon on Insulator) substrate. In addition, the present invention relates to a method for manufacturing a semiconductor device using a substrate provided with a semiconductor layer with an insulating film interposed therebetween.

In recent years, integrated circuits using an SOI (Silicon on Insulator) substrate in which a thin single crystal semiconductor layer exists on an insulating surface instead of a bulk silicon wafer have been developed. Since the parasitic capacitance between the drain of the transistor and the substrate is reduced by using the SOI substrate, the SOI substrate is attracting attention as improving the performance of the semiconductor integrated circuit.

As one of methods for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (see, for example, Patent Document 1). An outline of a method for manufacturing an SOI substrate by a hydrogen ion implantation separation method will be described below. First, a microbubble layer is formed at a predetermined depth from the surface by implanting hydrogen ions into a silicon wafer using an ion implantation method. Next, the silicon wafer implanted with hydrogen ions is bonded to another silicon wafer through the silicon oxide film. After that, by performing heat treatment, the microbubble layer becomes a cleavage plane, and a part of the silicon wafer into which hydrogen ions are implanted is separated into a thin film with the microbubble layer as a boundary, and is simply put on another bonded silicon wafer. A crystalline silicon film can be formed.

In addition, a method of forming a single crystal silicon layer on a base substrate made of glass using such a hydrogen ion implantation separation method has been proposed (for example, see Patent Document 2). In Patent Document 2, a silicon nitride film is provided on one surface of the single crystal silicon substrate or the support substrate in order to prevent impurities from the support substrate from diffusing to the single crystal silicon layer side, and formed on the silicon nitride film. A method is shown in which the bonded silicon oxide film is used as a bonding surface.

Since a glass substrate can be easily increased in area and cheaper than a silicon wafer, an SOI substrate having a large area and a low price can be manufactured by using the glass substrate as a base substrate. In the case where a substrate containing impurities such as a glass substrate is used as the base substrate, a silicon nitride film or a silicon nitride oxide film (hereinafter referred to as “silicon nitride film or the like”) is used to prevent diffusion of impurities contained in the base substrate. ) Is effective.
Japanese Patent Application Laid-Open No. 2000-124092 JP 2002-170942 A

However, a silicon nitride film or the like formed using a CVD method is difficult to make uniform in thickness compared to a film formed by heat treatment in a nitrogen atmosphere at a high temperature. In the case of application as, there is a possibility that poor bonding between the base substrate and the single crystal semiconductor substrate may occur. Further, a silicon nitride film or the like is less susceptible to hydrogen bonding at the bonding surface than a silicon oxide film, and for these reasons, generally, as disclosed in Patent Document 2, an oxide is formed on a silicon nitride film or the like. A silicon film is formed, and bonding is performed using the silicon oxide film as a bonding layer.

On the other hand, when a silicon nitride film or the like is provided on the single crystal silicon substrate side, a transistor formed using the single crystal silicon due to the influence of the interface state when the single crystal silicon and the silicon nitride film are formed in contact with each other. This may affect the characteristics of the element. Therefore, in consideration of element characteristics of a transistor or the like, it is necessary to provide an insulating film (for example, a silicon oxide film) between the single crystal silicon substrate and the silicon nitride film.

Thus, when a silicon nitride film or the like is provided between the single crystal silicon substrate and the base substrate, there is a problem that the number of processes increases. In manufacturing an SOI substrate, since the single crystal silicon substrate itself is expensive, it is important to reduce the cost by simplifying the process.

In addition, by using a large substrate such as a glass substrate as a base substrate, an SOI substrate having a large area and a low price can be manufactured. However, a glass substrate is easier to bend than a silicon wafer and has a waviness on the surface. In particular, it is difficult to perform mechanical polishing on a large-area glass substrate having a side exceeding 30 cm. Therefore, there is a demand for a bonding layer that suppresses poor bonding even when a glass substrate having undulations is used as the base substrate.

In view of the above problems, an object of the present invention is to simplify the process and achieve cost reduction even when a nitrogen-containing layer is provided between a silicon substrate and a base substrate. Another object is to reduce bonding defects even when a substrate with a wave, such as a glass substrate, is used as a base substrate.

In the present invention, a silicon substrate and a base substrate are bonded well using a nitrogen-containing layer as a bonding layer.

In one embodiment of the present invention, a single crystal semiconductor substrate and an insulating base substrate are prepared, an oxide film is formed over the single crystal semiconductor substrate, and the single crystal semiconductor substrate is irradiated with ions to be in the single crystal semiconductor substrate. Forming an embrittled region, forming a nitrogen-containing layer on the oxide film or the base substrate using a plasma CVD method, and bonding the single crystal semiconductor substrate and the base substrate through the oxide film and the nitrogen-containing layer, The step of separating the single crystal semiconductor substrate in the embrittlement region and forming the single crystal semiconductor layer over the base substrate through the insulating layer and the nitrogen-containing layer is performed. It is characterized by being performed at 300 ° C. or lower and a film forming pressure of 160 Pa or higher.

According to another aspect of the present invention, a single crystal semiconductor substrate and an insulating base substrate are prepared, an oxide film is formed over the single crystal semiconductor substrate, and the single crystal semiconductor substrate is irradiated with ions to form a single crystal semiconductor. An embrittled region is formed in the substrate, a nitrogen-containing layer is formed over the oxide film or the base substrate by a plasma CVD method, and the single crystal semiconductor substrate and the base substrate are bonded to each other through the oxide film and the nitrogen-containing layer. In addition, the step of separating the single crystal semiconductor substrate in the embrittlement region and forming the single crystal semiconductor layer over the base substrate through the insulating layer and the nitrogen-containing layer is performed. Is performed at a room temperature to 200 ° C. and a film forming pressure of 120 Pa or more.

In this specification, the average surface roughness (Ra) of the surface is obtained by extending the centerline average roughness defined in JIS B0601 to three dimensions so that it can be applied to the measurement surface. It can be expressed as “a value obtained by averaging the absolute values of deviations from the reference plane to the designated plane” and is defined by the following equation (1).

In Equation (1), S ₀ is four points represented by the measurement surface (coordinates (x ₁ , y ₁ ) (x ₁ , y ₂ ) (x ₂ , y ₁ ) (x ₂ , y ₂ )). Is a rectangular region surrounded by), and Z ₀ is the average height of the measurement surface.

Further, the root mean square surface roughness (Rms) can be expressed as “the square root of a value obtained by averaging the squares of deviations from the reference surface to the designated surface” and is defined by the following equation (2).

The maximum height difference (P-V) refers to the difference between the highest altitude Zmax and the lowest altitude Zmin on the measurement surface.

In the present specification, silicon oxynitride has a composition containing more oxygen than nitrogen, and preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering ( When measured using HFS (Hydrogen Forward Scattering), the concentration ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 to 10 for hydrogen. It is included in the atomic% range. Further, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a concentration range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor device.

In this specification, a display device includes a light-emitting device and a liquid crystal display device. The light emitting device includes a light emitting element, and the liquid crystal display device includes a liquid crystal element. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like.

According to the present invention, even when a nitrogen-containing layer is provided between a silicon substrate and a base substrate, the process can be simplified and cost reduction can be achieved.

According to the present invention, even when a substrate having a wave, such as a glass substrate, is used as the base substrate, bonding defects can be reduced.

Embodiments of the present invention will be described below with reference to the drawings. However, it will be readily understood by those skilled in the art that the present invention can be implemented in many different modes, and that forms and details can be changed without departing from the spirit and scope of the present invention. . Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing an SOI substrate having a nitrogen-containing layer between a single crystal semiconductor layer and a base substrate will be described with reference to drawings.

First, a single crystal semiconductor substrate 100 is prepared (see FIG. 1A-1).

As the single crystal semiconductor substrate 100, for example, a single crystal semiconductor substrate made of a Group 14 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate can be used. A compound semiconductor substrate such as gallium arsenide or indium phosphide can also be used. As a commercially available silicon substrate, a circular substrate having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), a diameter of 12 inches (300 mm), and a diameter of 16 inches (400 mm) is typical. is there. Note that the shape of the single crystal semiconductor substrate 100 is not limited to a circle, and the single crystal semiconductor substrate 100 can be processed into a rectangular shape or the like.

Next, an oxide film 102 is formed on the surface of the single crystal semiconductor substrate 100 (see FIG. 1A-2).

As the oxide film 102, for example, a single layer such as a silicon oxide film or a silicon oxynitride film, or a film in which these layers are stacked can be used. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like.

In this embodiment, the single crystal semiconductor substrate 100 is subjected to heat treatment to form an oxide film 102 (here, a SiOx film) (see FIG. 1A-2). The heat treatment is preferably performed by adding halogen in an oxidizing atmosphere.

For example, by performing heat treatment on the single crystal semiconductor substrate 100 in an oxidizing atmosphere to which chlorine (Cl) is added, the oxide film 102 subjected to chlorine oxidation can be formed. In this case, the oxide film 102 is a film containing chlorine atoms.

As an example of the heat treatment, a temperature of 900 ° C. to 1150 ° C. (typically, in an oxidizing atmosphere containing hydrogen chloride (HCl) at a ratio of 0.5 to 10% by volume (preferably 3% by volume) with respect to oxygen. Can be carried out at 1000 ° C.). The heat treatment time may be 0.1 to 6 hours, preferably 0.5 to 1 hour. The oxide film 102 to be formed has a thickness of 10 nm to 1000 nm (preferably 50 nm to 300 nm), for example, 100 nm.

In addition, by containing chlorine atoms in the oxide film 102, heavy metals (eg, Fe, Cr, Ni, Mo, etc.) that are exogenous impurities are collected and the single crystal semiconductor substrate 100 is prevented from being contaminated. There is an effect.

Further, by including halogen such as chlorine in the oxide film 102, impurities (for example, movable ions such as Na) that adversely affect the single crystal semiconductor substrate 100 can be gettered. In other words, by heat treatment performed after the oxide film 102 is formed, impurities contained in the single crystal semiconductor substrate 100 are deposited on the oxide film 102 and are captured by reacting with halogen (eg, chlorine). Accordingly, the impurity collected in the oxide film 102 can be fixed and contamination of the single crystal semiconductor substrate 100 can be prevented.

Further, the halogen atoms contained in the oxide film 102 are not limited to chlorine atoms. The oxide film 102 may contain fluorine atoms. In order to fluorinate the surface of the single crystal semiconductor substrate 100, the surface of the single crystal semiconductor substrate 100 is immersed in hydrofluoric acid and then thermally oxidized in an oxidizing atmosphere, or heat treatment is performed by adding NF ₃ to the oxidizing atmosphere. Can be done.

Next, by irradiating the single crystal semiconductor substrate 100 with ions having kinetic energy, an embrittled region 104 whose crystal structure is damaged is formed at a predetermined depth of the single crystal semiconductor substrate 100 (FIG. 1A-A). 3)). As shown in FIG. 1A-3, by irradiating the single crystal semiconductor substrate 100 with accelerated ions 103 through the oxide film 102, a region having a predetermined depth from the surface of the single crystal semiconductor substrate 100 is obtained. The ions 103 can be added to the fragile regions 104 to be formed. The ions 103 are ions that are excited by generating a plasma of the source gas by exciting the source gas and extracting ions contained in the plasma from the plasma by the action of an electric field.

The depth of the region where the embrittled region 104 is formed can be adjusted by the kinetic energy, mass and charge of the ions 103, the incident angle of the ions 103, and the like. Kinetic energy can be adjusted by acceleration voltage, dose, etc. An embrittled region 104 is formed in a region having a depth substantially equal to the average penetration depth of the ions 103. Therefore, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 100 is determined by the depth to which the ions 103 are added. In this embodiment, the depth at which the embrittlement region 104 is formed is adjusted so that the thickness of the single crystal semiconductor layer is greater than or equal to 10 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 200 nm.

The embrittlement region 104 can be formed by ion doping treatment. The ion doping process can be performed using an ion doping apparatus. A typical ion doping apparatus is a non-mass separation type apparatus that irradiates an object to be processed disposed in a chamber with all ion species generated by plasma excitation of a process gas. The non-mass separation type apparatus is because the object to be processed is irradiated with all ion species without mass separation of ion species in the plasma. On the other hand, the ion implantation apparatus is a mass separation type apparatus. An ion implantation apparatus is an apparatus that mass-separates ion species in plasma and irradiates a target object with ion species having a specific mass.

The main components of the ion doping apparatus are a chamber in which an object to be processed is arranged, an ion source for generating desired ions, and an acceleration mechanism for accelerating and irradiating ions. The ion source includes a gas supply device that supplies a source gas for generating a desired ion species, an electrode for generating a plasma by exciting the source gas, and the like. As an electrode for forming plasma, a filament-type electrode, an electrode for capacitively coupled high-frequency discharge, or the like is used. The acceleration mechanism includes an electrode such as an extraction electrode, an acceleration electrode, a deceleration electrode, and a ground electrode, and a power source for supplying power to these electrodes. The electrode constituting the acceleration mechanism is provided with a plurality of openings and slits, and ions generated by the ion source are accelerated through the openings and slits provided in the electrodes. Note that the configuration of the ion doping apparatus is not limited to that described above, and a mechanism according to need is provided.

In this embodiment, hydrogen is added to the single crystal semiconductor substrate 100 with an ion doping apparatus. A gas containing hydrogen is supplied as a plasma source gas. For example, H ₂ is supplied. Hydrogen gas is excited to generate plasma, and ions contained in the plasma are accelerated without mass separation, and the single crystal semiconductor substrate 100 is irradiated with the accelerated ions.

In the ion doping apparatus, the ratio of H ₃ ^{+ to} the total amount of ion species (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ) generated from hydrogen gas is 50% or more. More preferably, the ratio of H ₃ ⁺ is 80% or more. Since the ion doping apparatus does not perform mass separation, among a plurality of ion species generated in the plasma, H ₃ ^{+ is set} to 50% or more, preferably 80% or more. This is because by irradiating ions with the same mass, ions can be added while being concentrated at the same depth in the single crystal semiconductor substrate 100.

In order to form the embrittled region 104 in a shallow region, the acceleration voltage of the ions 103 needs to be lowered. However, by increasing the proportion of H ₃ ⁺ ions in the plasma, hydrogen ions can be efficiently converted into a single crystal. It can be added to the semiconductor substrate 100. Since H ₃ ⁺ ions have a mass three times that of H ⁺ ions, when one hydrogen atom is added at the same depth, the acceleration voltage of H ₃ ⁺ ions is three times the acceleration voltage of H ⁺ ions. It becomes possible to do. If the acceleration voltage of ions can be increased, the tact time of the ion irradiation process can be shortened, and productivity and throughput can be improved.

Since the ion doping apparatus is inexpensive and excellent in large area processing, irradiation with H ₃ ⁺ using such an ion doping apparatus improves the semiconductor characteristics, increases the area, reduces the cost, and improves the productivity. A remarkable effect such as can be obtained. In addition, when an ion doping apparatus is used, heavy metal may be introduced at the same time. However, by irradiating ions through the oxide film 102 containing chlorine atoms, contamination of the single crystal semiconductor substrate 100 with heavy metal is prevented. Can be prevented.

Note that the step of irradiating the single crystal semiconductor substrate 100 with the accelerated ions 103 can be performed with an ion implantation apparatus. The ion implantation apparatus is a mass separation type apparatus that mass-separates a plurality of ion species generated by plasma-exciting a source gas from a target object disposed in a chamber and irradiates specific ion species. Therefore, when an ion implantation apparatus is used, H ⁺ ions and H ₂ ⁺ ions generated by exciting hydrogen gas or PH ₃ are mass-separated to accelerate one of the H ⁺ ions or the H ₂ ⁺ ions. Then, the single crystal semiconductor substrate 100 is irradiated.

Next, a nitrogen-containing layer 106 (eg, an insulating film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film) is formed over the oxide film 102 (see FIG. 1A-4).

In this embodiment mode, the nitrogen-containing layer 105 is a layer (bonding layer) bonded to the base substrate. The nitrogen-containing layer 105 is a barrier layer for preventing impurities such as Na (sodium) contained in the base substrate from diffusing into the single crystal semiconductor layer when a single crystal semiconductor layer is provided on the base substrate later. Function as.

In the case where the nitrogen-containing layer 106 is used as a bonding layer, it is necessary to flatten the surface of the nitrogen-containing layer 106 in order to suppress a bonding failure between the single crystal semiconductor substrate 100 and the base substrate. Specifically, the average surface roughness (Ra) of the surface of the nitrogen-containing layer 106 is 0.5 nm or less, the root mean square roughness (Rms) is 0.60 nm or less, and more preferably the average surface roughness is 0.35 nm. Hereinafter, the root mean square roughness is 0.45 nm or less. The thickness of the nitrogen-containing layer 106 is preferably 10 nm to 200 nm, preferably 50 nm to 100 nm. This is because if the nitrogen-containing layer is formed with a large film stress, the film may be peeled off, while if it is formed too thin, the effect of suppressing the diffusion of impurities is reduced.

In addition, since hydrogen bonding greatly contributes to bonding with the base substrate, it is preferable to form the nitrogen-containing layer 106 so that a large amount of hydrogen is contained. By containing a large amount of hydrogen in the nitrogen-containing layer 106, it is possible to form a strong bond by hydrogen bonding with a base substrate such as glass.

In order to form such a nitrogen-containing layer 106, in this embodiment, a plasma CVD method is used to form the nitrogen-containing layer 106 at a substrate temperature of not less than room temperature and not more than 300 ° C. The film forming pressure is 160 Pa or higher. Alternatively, the nitrogen-containing layer 106 is formed at a substrate temperature during film formation of room temperature to 200 ° C. and a film formation pressure of 120 Pa or more.

By reducing the substrate temperature at the time of film formation, the surface roughness of the formed nitrogen-containing layer 106 can be reduced. This is because as the substrate temperature at the time of film formation increases, the etching reaction due to hydrogen radicals or the like on the deposition surface of the film becomes excessive, causing surface roughness. In addition, by reducing the substrate temperature during film formation, the dehydration reaction during film formation can be suppressed, and the amount of hydrogen contained in the nitrogen-containing layer 106 can be increased.

By increasing the pressure at the time of film formation, the roughness of the surface of the formed nitrogen-containing layer 106 can be reduced. As the pressure increases, collisions between hydrogen radicals and neutral molecules (atoms) frequently occur in the sheath formed between the substrate and the bulk plasma, and are caused by hydrogen radicals on the film deposition surface. This is because the etching reaction is suppressed. Further, the surface hydrogen abstraction reaction due to hydrogen radicals is suppressed, and the amount of hydrogen contained in the nitrogen-containing layer 106 can be increased.

Note that the room temperature refers to the room temperature of a clean room used for manufacturing a normal semiconductor device, and refers to 25 ° C. in this specification.

In this embodiment, film formation is performed using at least silane gas, ammonia gas, and hydrogen gas in a plasma CVD method. By using ammonia gas or hydrogen gas, the nitrogen-containing layer 106 containing a large amount of hydrogen in the film can be formed. In particular, a large amount of hydrogen can be contained in the nitrogen-containing layer 106 by forming a film by introducing hydrogen gas.

In the plasma CVD method, the nitrogen-containing layer 106 to be formed contains a large amount of hydrogen, whereby a film with low density (soft film quality) can be obtained. On the other hand, by performing heat treatment on the nitrogen-containing layer 106 containing a large amount of hydrogen, hydrogen in the film can be reduced and the denseness of the nitrogen-containing layer 106 can be increased (the film quality can be hardened). That is, the nitrogen-containing layer 106 formed in this embodiment contracts due to heat treatment.

Therefore, when the nitrogen-containing layer 106 is bonded to the base substrate in a state where the denseness is low, the nitrogen-containing layer 106 is not uneven even when the bonding surface on the base substrate side has unevenness. Therefore, it is possible to suppress poor bonding. Further, the densified nitrogen-containing layer 106 can be obtained by performing heat treatment at the same time as or after bonding.

When a large-area glass substrate is used as the base substrate, undulation of the surface of the glass substrate becomes a problem at the time of bonding, but by using the nitrogen-containing layer 106 with low density as a bonding layer, the glass surface Swelling can be relaxed and joined (see FIG. 3). As a result, even when a glass substrate with undulation is used as the base substrate, it is possible to suppress poor bonding.

In addition, it is preferable to perform heat treatment after performing pressure treatment when bonding to the base substrate. By performing the pressure treatment, the nitrogen-containing layer 106 can effectively absorb the unevenness present on the bonding surface on the base substrate side and suppress a bonding defect between the single crystal semiconductor substrate 100 and the base substrate. is there. The pressure treatment may be performed on the entire surface of the single crystal semiconductor substrate 100 or may be performed partially.

As shown in this embodiment mode, in the case where the nitrogen-containing layer 106 is formed after the embrittlement region 104 is formed, the single-crystal semiconductor is formed by reducing the substrate temperature when forming the nitrogen-containing layer 106 as much as possible. Degassing from the embrittled region 104 formed in the substrate 100 can be prevented.

Further, as shown in this embodiment mode, after the oxide film 102 is formed and before the nitrogen-containing layer 106 is formed, ions are added to the single crystal semiconductor substrate 100, so that the surface of the single crystal semiconductor substrate 100 is damaged. Formation of a layer can be suppressed. In addition, by forming the oxide film 102 having a uniform thickness on the single crystal semiconductor substrate 100 by using a thermal oxidation method, the uniformity in the depth direction of the embrittlement region 104 formed in the single crystal semiconductor substrate 100 is obtained. Can be improved. Furthermore, by adding ions before the formation of the nitrogen-containing layer 106, it is possible to prevent a damaged layer (surface roughness) associated with the addition of ions from occurring on the surface of the nitrogen-containing layer that becomes the bonding layer.

Next, the base substrate 120 is prepared (see FIG. 1B).

As the base substrate 120, for example, a substrate made of an insulator can be used. Specific examples include various glass substrates, quartz substrates, ceramic substrates, and sapphire substrates used in the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass. In addition, a single crystal semiconductor substrate (for example, a single crystal silicon substrate) or a polycrystalline semiconductor substrate (for example, a polycrystalline silicon substrate) may be used as the base substrate 120.

In this embodiment, a glass substrate is preferably used as the base substrate 120. When an inexpensive glass substrate that can be enlarged in area is used as the base substrate 120, the cost can be reduced. In particular, as the base substrate 120, for example, a mother glass substrate having a large area referred to as a sixth generation (1500 mm × 1850 mm), a seventh generation (1870 mm × 2200 mm), or an eighth generation (2200 mm × 2400 mm) is used. By manufacturing a SOI substrate by bonding a plurality of single crystal semiconductor substrates to a glass substrate, an increase in the area of the SOI substrate can be realized.

Next, the single crystal semiconductor substrate 100 and the base substrate 120 are attached to each other with the oxide film 102 and the nitrogen-containing layer 106 interposed therebetween (see FIG. 1C). Here, the single crystal semiconductor substrate 100 and the base substrate 120 are opposed to each other, and the surface of the nitrogen-containing layer 106 and the surface of the base substrate 120 are bonded to each other.

Further, after the single crystal semiconductor substrate 100 and the base substrate 120 are in close contact with each other through the oxide film 102 and the nitrogen-containing layer 106, 1 to 500 N / cm ² at one place of the single crystal semiconductor substrate 100 (or the base substrate 120), It is preferable to apply a pressure of about 1 to ²⁰ N / cm ² . In this case, the nitrogen-containing layer 106 and the base substrate 120 start to be bonded from the portion where the pressure is applied, and the bonding is spontaneously formed at the portion other than the portion where the pressure is applied and extends over the entire surface. This bonding is effected by van der Waals force or hydrogen bond, and can be performed at room temperature without heat treatment. Therefore, a substrate having a low heat resistant temperature such as a glass substrate is used for the base substrate 120. it can.

As described above, by using a film having a flat surface and low density as the nitrogen-containing layer 106, even when the nitrogen-containing layer is used as a bonding layer, bonding with the base substrate 120 is favorably performed. be able to.

Note that before the single crystal semiconductor substrate 100 and the base substrate 120 are bonded to each other, surface treatment of the nitrogen-containing layer 106 formed over the single crystal semiconductor substrate 100 and the base substrate 120 is preferably performed.

As the surface treatment, plasma treatment, ozone treatment, megasonic cleaning, two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen) or a combination of these methods can be performed. . In particular, after the plasma treatment is performed on at least one surface of the nitrogen-containing layer 106 and the base substrate 120, ozone treatment, megasonic cleaning, two-fluid cleaning, and the like are performed, so that the surfaces of the nitrogen-containing layer 106 and the base substrate 120 are removed. It is possible to remove dust such as organic matter and make the surface hydrophilic. As a result, the bonding strength between the nitrogen-containing layer 106 and the base substrate 120 can be improved.

In addition, after the nitrogen-containing layer 106 and the base substrate 120 are bonded, heat treatment for increasing the bonding strength is preferably performed. The temperature of this heat treatment is set to a temperature that does not cause cracks in the embrittled region 104, and for example, the heat treatment is performed in a temperature range of room temperature to less than 400 ° C. By this heat treatment, the nitrogen-containing layer 106 can be densified. Note that for the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used.

Further, a heat treatment for increasing the bonding strength and a pressure treatment may be performed. The pressure treatment is performed so that pressure is applied in a direction perpendicular to the bonding surface. By performing the pressure treatment, even when the surface of the base substrate 120 has unevenness, the unevenness is absorbed by the nitrogen-containing layer 106 having low density, and it is possible to effectively reduce the bonding failure. (See FIG. 3).

Next, heat treatment is performed at a temperature higher than the heat treatment, and the single crystal semiconductor substrate 100 is separated in the embrittled region 104, whereby the single crystal semiconductor layer 124 is formed over the base substrate 120 with the oxide film 102 and the nitrogen-containing layer 106 interposed therebetween. (See FIG. 1D).

By performing the heat treatment, the added element is precipitated in the minute holes formed in the embrittled region 104 due to the temperature rise, and the internal pressure rises. The increase in pressure causes a change in volume in a minute hole in the embrittled region 104 and a crack occurs in the embrittled region 104, so that the single crystal semiconductor substrate 100 is cleaved along the embrittled region 104. Since the oxide film 102 is bonded to the base substrate 120, a single crystal semiconductor layer 124 separated from the single crystal semiconductor substrate 100 is formed over the base substrate 120. In addition, the temperature of the heat treatment here is a temperature that does not exceed the strain point of the base substrate 120.

For this heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, the heating can be performed at a heating temperature of 550 ° C. or more and 730 ° C. or less and a treatment time of 0.5 minutes or more and 60 minutes or less.

Note that the heat treatment for increasing the bonding strength between the nitrogen-containing layer 106 and the base substrate 120 and the embrittlement region are performed by performing the heat treatment in FIG. 1D without performing the heat treatment for increasing the bonding strength described above. The separation heat treatment step in 104 may be performed simultaneously.

Through the above steps, an SOI substrate in which the single crystal semiconductor layer 124 is provided over the base substrate 120 with the oxide film 102 and the nitrogen-containing layer 106 interposed therebetween can be manufactured.

By using the manufacturing method described in this embodiment mode, the process can be simplified and cost reduction can be achieved even when a nitrogen-containing layer is provided between the silicon substrate and the base substrate. Further, even when a substrate having undulations such as glass is used as the base substrate, it is possible to suppress poor bonding. Further, even when a nitrogen-containing layer is used as a bonding layer, the bonding strength between the base substrate 120 and the single crystal semiconductor layer 124 can be improved.

Note that the method for manufacturing an SOI substrate described in this embodiment can be combined as appropriate with any of the manufacturing methods described in other embodiments in this specification.

(Embodiment 2)
In this embodiment, a method for manufacturing an SOI substrate, which is different from that in the above embodiment, will be described with reference to drawings. Specifically, a case where a nitrogen-containing layer serving as a bonding layer is provided on the base substrate side will be described.

First, the single crystal semiconductor substrate 100 is prepared (see FIG. 2A-1), and the oxide film 102 is formed over the single crystal semiconductor substrate 100 (see FIG. 2A-2). In this embodiment, the oxide film 102 serves as a bonding layer on the single crystal semiconductor substrate 100 side.

As the oxide film 102, for example, a single layer such as a silicon oxide film or a silicon oxynitride film, or a film in which these layers are stacked can be used. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like.

In this embodiment, the single crystal semiconductor substrate 100 is subjected to heat treatment to form an oxide film 102 (here, a SiOx film) (see FIG. 1A-2). The heat treatment is preferably performed by adding halogen in an oxidizing atmosphere.

For example, by performing heat treatment on the single crystal semiconductor substrate 100 in an oxidizing atmosphere to which chlorine (Cl) is added, the oxide film 102 subjected to chlorine oxidation can be formed. In this case, the oxide film 102 is a film containing chlorine atoms.

By containing chlorine atoms in the oxide film 102, the contained chlorine atoms form strain. As a result, the moisture absorption ratio of the oxide film 102 is improved, and the diffusion rate can be increased. That is, when moisture is present on the surface of the oxide film 102, moisture present on the surface can be quickly absorbed and diffused into the oxide film 102.

Next, by irradiating the single crystal semiconductor substrate 100 with ions having kinetic energy, an embrittled region 104 whose crystal structure is damaged is formed at a predetermined depth of the single crystal semiconductor substrate 100 (FIG. 2A-A). 3)). Note that details of a method for forming the embrittlement region 104 are omitted here because Embodiment Mode 1 can be referred to.

Next, the base substrate 120 is prepared (see FIG. 2B-1)), and the nitrogen-containing layer 126 is formed over the base substrate 120 (see FIG. 4B-2). In this embodiment mode, the nitrogen-containing layer 126 serves as a bonding layer on the base substrate 120 side. Note that the method for forming the nitrogen-containing layer 106 described in Embodiment Mode 1 can be applied to the nitrogen-containing layer 126.

Next, the single crystal semiconductor substrate 100 and the base substrate 120 are opposed to each other, and the surface of the oxide film 102 and the surface of the nitrogen-containing layer 126 are bonded (see FIG. 8C).

Further, after the single crystal semiconductor substrate 100 and the base substrate 120 are in close contact with each other through the oxide film 102 and the nitrogen-containing layer 106, 1 to 500 N / cm ² at one place of the single crystal semiconductor substrate 100 (or the base substrate 120), It is preferable to apply a pressure of about 1 to ²⁰ N / cm ² . In this case, the oxide film 102 and the nitrogen-containing layer 126 start to be joined from the portion to which the pressure is applied, and the junction is spontaneously formed at the portion other than the portion to which the pressure is applied and extends over the entire surface. This bonding is effected by van der Waals force or hydrogen bond, and can be performed at room temperature without heat treatment. Therefore, a substrate having a low heat resistant temperature such as a glass substrate is used for the base substrate 120. it can.

In addition, as shown in this embodiment, a damage layer (surface roughness) may be generated on the surface of the oxide film 102 by adding ions to the single crystal semiconductor substrate 100 after the oxide film 102 is formed. By using a film with a flat surface and low density as the nitrogen-containing layer 106, surface roughness of the oxide film 102 can be absorbed and bonding failure can be suppressed. Further, the densified nitrogen-containing layer 126 can be obtained by performing heat treatment at the same time as or after bonding.

Note that the surface treatment of the oxide film 102 formed over the single crystal semiconductor substrate 100 and the nitrogen-containing layer 126 formed over the base substrate 120 is performed before the single crystal semiconductor substrate 100 and the base substrate 120 are bonded to each other. It is preferable to carry out.

As the surface treatment, plasma treatment, ozone treatment, megasonic cleaning, two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen) or a combination of these methods can be performed. . In particular, after plasma treatment is performed on at least one surface of the oxide film 102 and the nitrogen-containing layer 126, ozone treatment, megasonic cleaning, two-fluid cleaning, and the like are performed, so that the surface of the oxide film 102 and the nitrogen-containing layer 126 is cleaned. It is possible to remove dust such as organic matter and make the surface hydrophilic. As a result, the bonding strength between the oxide film 102 and the nitrogen-containing layer 126 can be improved.

In addition, after the oxide film 102 and the nitrogen-containing layer 126 are bonded, it is preferable to perform heat treatment for increasing the bonding strength. The temperature of this heat treatment is set to a temperature that does not cause cracks in the embrittled region 104, and for example, the heat treatment is performed in a temperature range of room temperature to less than 400 ° C. The nitrogen-containing layer 126 can be densified by this heat treatment. Note that for the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used.

Generally, when heat treatment is performed at the same time as or after bonding the oxide film 102 and the nitrogen-containing layer 126, a dehydration reaction proceeds at the bonding interface, the bonding interfaces approach each other, and hydrogen bonds are strengthened or covalent bonds are formed. As a result, the bonding is strengthened. In order to promote the dehydration reaction, it is necessary to remove moisture generated at the bonding interface by the dehydration reaction by performing a heat treatment at a high temperature. In other words, when the heat treatment temperature after bonding is low, moisture generated at the bonding interface due to the dehydration reaction cannot be effectively removed, so that the dehydration reaction does not proceed and it is difficult to sufficiently improve the bonding strength.

On the other hand, when an oxide film containing chlorine atoms or the like is used as the oxide film 102, the oxide film 102 can absorb and diffuse moisture, and thus heat treatment after bonding is performed at a low temperature. However, it is possible to efficiently promote the dehydration reaction by absorbing and diffusing moisture generated at the bonding interface by the dehydration reaction into the oxide film 102. In this case, even when a substrate having low heat resistance such as glass is used as the base substrate 120, the bonding strength between the oxide film 102 and the nitrogen-containing layer 126 can be sufficiently improved. In addition, before the single crystal semiconductor substrate 100 and the base substrate 120 are bonded to each other, a bias voltage is applied to perform plasma treatment on the surface of the oxide film 102 to form micropores near the surface of the oxide film 102, thereby Can be effectively absorbed and diffused, and the bonding strength between the oxide film 102 and the nitrogen-containing layer 126 can be improved even at a low temperature.

Further, a heat treatment for increasing the bonding strength and a pressure treatment may be performed. The pressure treatment is performed so that pressure is applied in a direction perpendicular to the bonding surface. By performing the pressure treatment, even if the surface of the oxide film 102 is damaged, the damaged layer is absorbed by the nitrogen-containing layer 106 with low density, and the defective bonding can be effectively reduced. It becomes possible.

Next, heat treatment is performed at a temperature higher than that of the heat treatment, and the single crystal semiconductor substrate 100 is separated in the embrittled region 104, whereby the single crystal semiconductor layer 124 is formed over the base substrate 120 with the oxide film 102 and the nitrogen-containing layer 126 interposed therebetween. (See FIG. 2D).

For this heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, the heating can be performed at a heating temperature of 550 ° C. or more and 730 ° C. or less and a treatment time of 0.5 minutes or more and 60 minutes or less.

Note that the heat treatment for increasing the bonding strength between the oxide film 102 and the nitrogen-containing layer 126 and the embrittlement region are performed by performing the heat treatment in FIG. 2D without performing the heat treatment for increasing the bonding strength described above. The separation heat treatment step in 104 may be performed simultaneously.

Through the above steps, an SOI substrate in which the single crystal semiconductor layer 124 is provided over the base substrate 120 with the oxide film 102 and the nitrogen-containing layer 126 interposed therebetween can be manufactured.

By using the manufacturing method described in this embodiment mode, the process can be simplified and cost reduction can be achieved even when a nitrogen-containing layer is provided between the silicon substrate and the base substrate. Further, even when a substrate having undulations such as glass is used as the base substrate, it is possible to suppress poor bonding. Further, even when a nitrogen-containing layer is used as a bonding layer, the bonding strength between the base substrate 120 and the single crystal semiconductor layer 124 can be improved.

Note that the method for manufacturing an SOI substrate described in this embodiment can be combined as appropriate with any of the manufacturing methods described in other embodiments in this specification.

(Embodiment 3)
In this embodiment, a method for manufacturing a semiconductor device using the SOI substrate manufactured in the above embodiment will be described.

First, a method for manufacturing an n-channel thin film transistor and a p-channel thin film transistor is described with reference to FIGS. Various semiconductor devices can be formed by combining a plurality of thin film transistors (TFTs).

In this embodiment, the case where an SOI substrate manufactured using the process of FIG. 1 is used as an SOI substrate will be described. Needless to say, an SOI substrate manufactured by another method described in the above embodiment mode can also be used.

FIG. 4A is a cross-sectional view of an SOI substrate manufactured by the method described with reference to FIG.

First, the single crystal semiconductor layer 124 is element-isolated by etching to form semiconductor layers 251 and 252 as shown in FIG. The semiconductor layer 251 constitutes an n-channel TFT, and the semiconductor layer 252 constitutes a p-channel TFT.

As shown in FIG. 4C, an insulating film 254 is formed over the semiconductor layers 251 and 252. Next, the gate electrode 255 is formed over the semiconductor layer 251 with the insulating film 254 interposed therebetween, and the gate electrode 256 is formed over the semiconductor layer 252.

Note that before the single crystal semiconductor layer 124 is etched, an impurity element such as boron, aluminum, or gallium, or an impurity element such as phosphorus or arsenic is added to the single crystal semiconductor layer 124 in order to control the threshold voltage of the TFT. It is preferable to add to. For example, an impurity element is added to a region where an n-channel TFT is formed, and an impurity element is added to a region where a p-channel TFT is formed.

Next, as illustrated in FIG. 4D, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252. Specifically, first, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251. Therefore, the semiconductor layer 252 to be a p-channel TFT is masked with a resist, and an impurity element is added to the semiconductor layer 251. Phosphorus or arsenic may be added as the impurity element. By adding an impurity element by an ion doping method or an ion implantation method, the gate electrode 255 serves as a mask, and an n-type low-concentration impurity region 257 is formed in the semiconductor layer 251 in a self-aligning manner. A region of the semiconductor layer 251 that overlaps with the gate electrode 255 becomes a channel formation region 258.

Next, after removing the mask covering the semiconductor layer 252, the semiconductor layer 251 to be an n-channel TFT is covered with a resist mask. Next, an impurity element is added to the semiconductor layer 252 by an ion doping method or an ion implantation method. Boron can be added as the impurity element. In the impurity element addition step, the gate electrode 256 functions as a mask, and a p-type high-concentration impurity region 259 is formed in the semiconductor layer 252 in a self-aligned manner. The high concentration impurity region 259 functions as a source region or a drain region. A region overlapping with the gate electrode 256 of the semiconductor layer 252 becomes a channel formation region 260. Although the method of forming the p-type high concentration impurity region 259 after forming the n-type low concentration impurity region 257 has been described here, the p-type high concentration impurity region 259 can be formed first.

Next, after removing the resist covering the semiconductor layer 251, an insulating film having a single-layer structure or a stacked structure formed of a nitrogen compound such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like. By performing anisotropic etching of this insulating film in the vertical direction, sidewall insulating films 261 and 262 in contact with the side surfaces of the gate electrodes 255 and 256 are formed as shown in FIG. By this anisotropic etching, the insulating film 254 is also etched.

Next, as illustrated in FIG. 5B, the semiconductor layer 252 is covered with a resist 265. In order to form a high concentration impurity region functioning as a source region or a drain region in the semiconductor layer 251, an impurity element is added to the semiconductor layer 251 with a high dose by an ion implantation method or an ion doping method. Using the gate electrode 255 and the sidewall insulating film 261 as a mask, an n-type high concentration impurity region 267 is formed. Next, heat treatment for activating the impurity element is performed.

After the heat treatment for activation, an insulating film 268 containing hydrogen is formed as shown in FIG. After the insulating film 268 is formed, heat treatment is performed at a temperature of 350 ° C. to 450 ° C., and hydrogen contained in the insulating film 268 is diffused into the semiconductor layers 251 and 252. The insulating film 268 can be formed by depositing silicon nitride or silicon nitride oxide by a plasma CVD method with a process temperature of 350 ° C. or lower. By supplying hydrogen to the semiconductor layers 251 and 252, defects that become trapping centers in the semiconductor layers 251 and 252 and at the interface with the insulating film 254 can be effectively compensated.

Thereafter, an interlayer insulating film 269 is formed. The interlayer insulating film 269 is an insulating film made of an inorganic material such as a silicon oxide film or a BPSG (Boron Phosphorus Silicon Glass) film, or a single-layer film or a laminated structure selected from organic resin films such as polyimide and acrylic. It can be formed of a film. After a contact hole is formed in the interlayer insulating film 269, a wiring 270 is formed as shown in FIG. For example, the wiring 270 can be formed of a conductive film having a three-layer structure in which a low-resistance metal film such as an aluminum film or an aluminum alloy film is sandwiched between barrier metal films. The barrier metal film can be formed of a metal film such as molybdenum, chromium, or titanium.

Through the above steps, a semiconductor device having an n-channel TFT and a p-channel TFT can be manufactured. In the process of manufacturing the SOI substrate, the oxygen concentration of the semiconductor layer forming the channel formation region is reduced, so that a TFT with a small off-state current and a suppressed threshold voltage can be manufactured. The oxygen concentration of the semiconductor layer forming the channel formation region is preferably less than 1 × 10 ¹⁸ atoms / cm ³ , preferably less than 5 × 10 ¹⁷ atoms / cm ³ .

Although the method for manufacturing a TFT has been described with reference to FIGS. 4 and 5, a semiconductor device with high added value can be manufactured by forming various semiconductor elements such as a capacitor and a resistor in addition to the TFT. . Hereinafter, specific embodiments of the semiconductor device will be described with reference to the drawings.

First, a microprocessor will be described as an example of a semiconductor device. FIG. 6 is a block diagram illustrating a configuration example of the microprocessor 500.

The microprocessor 500 includes an arithmetic circuit 501 (also referred to as Arithmetic logic unit. ALU), an arithmetic circuit controller 502 (ALU Controller), an instruction analyzer 503 (Instruction Decoder), an interrupt controller 504 (Interrupt Controller), and a timing controller. 505 (Timing Controller), a register 506 (Register), a register controller 507 (Register Controller), a bus interface 508 (Bus I / F), a read-only memory 509, and a memory interface 510.

An instruction input to the microprocessor 500 via the bus interface 508 is input to the instruction analysis unit 503 and decoded, and then to the arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505. Entered. The arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instruction.

The arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 is a circuit that processes an interrupt request from an external input / output device or a peripheral circuit while the microprocessor 500 is executing a program. And processing an interrupt request. The register control unit 507 generates an address of the register 506 and reads and writes the register 506 in accordance with the state of the microprocessor 500. The timing control unit 505 generates a signal that controls the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1. As shown in FIG. 6, the internal clock signal CLK2 is input to another circuit.

Next, an example of a semiconductor device having a function of performing transmission / reception of data without contact and an arithmetic function will be described. FIG. 7 is a block diagram illustrating a configuration example of such a semiconductor device. The semiconductor device illustrated in FIG. 7 can be referred to as a computer that operates by transmitting and receiving signals to and from an external device by wireless communication (hereinafter referred to as “RFCPU”).

As illustrated in FIG. 7, the RFCPU 511 includes an analog circuit unit 512 and a digital circuit unit 513. The analog circuit portion 512 includes a resonance circuit 514 having a resonance capacity, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, and a modulation circuit 520. The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, an interface 524, a central processing unit 525, a random access memory 526, and a read only memory 527.

The outline of the operation of the RFCPU 511 is as follows. A signal received by the antenna 528 generates an induced electromotive force by the resonance circuit 514. The induced electromotive force is charged in the capacitor unit 529 through the rectifier circuit 515. Capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 529 does not need to be integrated on the substrate constituting the RFCPU 511, and can be incorporated into the RFCPU 511 as another component.

The reset circuit 517 generates a signal that resets and initializes the digital circuit portion 513. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. The demodulation circuit 519 is a circuit that demodulates the received signal, and the modulation circuit 520 is a circuit that modulates data to be transmitted.

For example, the demodulation circuit 519 is formed of a low-pass filter, and binarizes an amplitude modulation (ASK) reception signal based on the amplitude fluctuation. In addition, in order to transmit transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal, the modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514.

The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

A signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then decomposed into a control command and data by the RF interface 521. The control command is stored in the control register 522. The control command includes reading of data stored in the read-only memory 527, writing of data to the random access memory 526, an arithmetic instruction to the central processing unit 525, and the like.

The central processing unit 525 accesses the read-only memory 527, the random access memory 526, and the control register 522 via the interface 524. The interface 524 has a function of generating an access signal for any of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

As a calculation method of the central processing unit 525, a method in which an OS (operating system) is stored in the read-only memory 527 and a program is read and executed together with activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the system using both hardware and software, a system in which a part of arithmetic processing is performed by a dedicated arithmetic circuit and the remaining arithmetic operations are processed by the central processing unit 525 using a program can be applied.

Next, the display device will be described with reference to FIGS.

FIG. 8 is a diagram for explaining a liquid crystal display device. 8A is a plan view of a pixel of the liquid crystal display device, and FIG. 8B is a cross-sectional view of FIG. 8A taken along the line JK.

As shown in FIG. 8A, the pixel includes a single crystal semiconductor layer 320, a scan line 322 intersecting with the single crystal semiconductor layer 320, a signal line 323 intersecting with the scan line 322, a pixel electrode 324, and a pixel. An electrode 328 that electrically connects the electrode 324 and the single crystal semiconductor layer 320 is provided. The single crystal semiconductor layer 320 is a layer formed from a single crystal semiconductor layer provided over the base substrate 120 and constitutes a pixel TFT 325.

As the SOI substrate, the SOI substrate described in the above embodiment is used. As illustrated in FIG. 8B, the single crystal semiconductor layer 320 is stacked over the base substrate 120 with the oxide film 132 and the nitrogen-containing layer 121 interposed therebetween. As the base substrate 120, a glass substrate can be used. The single crystal semiconductor layer 320 of the TFT 325 is a film formed by element isolation of the single crystal semiconductor layer of the SOI substrate by etching. In the single crystal semiconductor layer 320, a channel formation region 340 and an n-type high concentration impurity region 341 to which an impurity element is added are formed. The gate electrode of the TFT 325 is included in the scanning line 322, and one of the source electrode and the drain electrode is included in the signal line 323.

A signal line 323, a pixel electrode 324, and an electrode 328 are provided over the interlayer insulating film 327. A columnar spacer 329 is formed on the interlayer insulating film 327. An alignment film 330 is formed to cover the signal line 323, the pixel electrode 324, the electrode 328, and the columnar spacer 329. The counter substrate 332 is provided with a counter electrode 333 and an alignment film 334 that covers the counter electrode. The columnar spacer 329 is formed to maintain a gap between the base substrate 120 and the counter substrate 332. A liquid crystal layer 335 is formed in a gap formed by the columnar spacers 329. At the connection portion between the signal line 323 and the electrode 328 and the high-concentration impurity region 341, a step is generated in the interlayer insulating film 327 due to the formation of the contact hole, so that the alignment of the liquid crystal in the liquid crystal layer 335 is easily disturbed at this connection portion. For this reason, columnar spacers 329 are formed at the step portions to prevent disorder of the alignment of the liquid crystal.

Next, an electroluminescent display device (hereinafter referred to as an EL display device) will be described with reference to FIG. FIG. 9A is a plan view of a pixel of the EL display device, and FIG. 9B is a cross-sectional view of FIG. 9A taken along the line JK.

As shown in FIG. 9A, the pixel includes a selection transistor 401 made of TFT, a display control transistor 402, a scanning line 405, a signal line 406, a current supply line 407, and a pixel electrode 408. Each pixel is provided with a light-emitting element having a structure in which a layer (EL layer) formed including an electroluminescent material is sandwiched between a pair of electrodes. One electrode of the light emitting element is a pixel electrode 408. In the semiconductor layer 403, a channel formation region, a source region, and a drain region of the selection transistor 401 are formed. In the semiconductor layer 404, a channel formation region, a source region, and a drain region of the display control transistor 402 are formed. The semiconductor layers 403 and 404 are layers formed from the single crystal semiconductor layer 124 provided over the base substrate.

In the selection transistor 401, the gate electrode is included in the scanning line 405, one of the source electrode and the drain electrode is included in the signal line 406, and the other is formed as the electrode 410. In the display control transistor 402, the gate electrode 412 is electrically connected to the electrode 411, one of the source electrode and the drain electrode is formed as an electrode 413 electrically connected to the pixel electrode 408, and the other is supplied with current. Included in line 407.

The display control transistor 402 is a p-channel TFT. As shown in FIG. 9B, a channel formation region 451 and a p-type high concentration impurity region 452 are formed in the semiconductor layer 404. Note that the SOI substrate manufactured in the embodiment is used as the SOI substrate.

An interlayer insulating film 427 is formed to cover the gate electrode 412 of the display control transistor 402. Over the interlayer insulating film 427, a signal line 406, a current supply line 407, electrodes 411, 413, and the like are formed. Further, a pixel electrode 408 that is electrically connected to the electrode 413 is formed over the interlayer insulating film 427. The peripheral portion of the pixel electrode 408 is surrounded by an insulating partition layer 428. An EL layer 429 is formed over the pixel electrode 408, and a counter electrode 430 is formed over the EL layer 429. A counter substrate 431 is provided as a reinforcing plate, and the counter substrate 431 is fixed to the base substrate 120 by a resin layer 432.

There are two methods for controlling the gradation of an EL display device: a current driving method in which the luminance of a light-emitting element is controlled by current, and a voltage driving method in which the luminance is controlled by voltage. When the difference in values is large, it is difficult to adopt, and for this purpose, a correction circuit for correcting variation in characteristics is required. When an EL display is manufactured by a manufacturing method including a manufacturing process of an SOI substrate, the selection transistor 401 and the display control transistor 402 have no variation in characteristics from pixel to pixel, so that a current driving method can be employed.

That is, various electrical devices can be manufactured by using an SOI substrate. Electrical equipment includes video cameras, digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game machines, personal digital assistants (mobile computers, mobile phones, portable game machines, electronic books, etc.) An image reproduction apparatus provided with a recording medium (specifically, an apparatus provided with a display device capable of reproducing audio data stored in a recording medium such as a DVD (digital versatile disc) and displaying the stored image data) An example of these is shown in FIG.

10A and 10B illustrate an example of a mobile phone to which the present invention is applied. FIG. 10A is a front view, FIG. 10B is a rear view, and FIG. 10C is when two housings are slid. It is a front view. The cellular phone 700 is composed of two housings 701 and 702. The cellular phone 700 is a so-called smartphone that has both functions of a cellular phone and a portable information terminal, has a built-in computer, and can perform various data processing in addition to voice calls.

A cellular phone 700 is composed of a housing 701 and a housing 702. The housing 701 includes a display portion 703, a speaker 704, a microphone 705, operation keys 706, a pointing device 707, a front camera lens 708, an external connection terminal jack 709, an earphone terminal 710, and the like. 711, an external memory slot 712, a rear camera 713, a light 714, and the like. The antenna is built in the housing 701.

In addition to the above structure, the cellular phone 700 may incorporate a non-contact IC chip, a small recording device, and the like.

The housings 701 and 702 (shown in FIG. 10A) which overlap with each other can be slid and developed as shown in FIG. 10C. In the display portion 703, a display panel or a display device to which the display device manufacturing method described in Embodiments 2 and 3 is applied can be incorporated. Since the display portion 703 and the front camera lens 708 are provided on the same surface, they can be used as a videophone. Further, by using the display portion 703 as a viewfinder, still images and moving images can be taken with the rear camera 713 and the light 714.

By using the speaker 704 and the microphone 705, the mobile phone 700 can be used as an audio recording device (recording device) or an audio reproducing device. In addition, operation keys 706 can be used to perform incoming / outgoing calls, simple information input operations such as e-mail, scroll operation of a screen displayed on the display unit, cursor movement operation for selecting information displayed on the display unit, and the like. Is possible.

In addition, it is convenient to use the keyboard 711 when there is a lot of information to be handled, such as creation of a document or use as a portable information terminal. Furthermore, by sliding the overlapping housings 701 and 702 (FIG. 10A), they can be developed as shown in FIG. When used as a portable information terminal, the mouse can be operated smoothly by using the keyboard 711 and the pointing device 707. The external connection terminal jack 709 can be connected to an AC adapter and various cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. In addition, a large amount of data can be stored and moved by inserting a recording medium into the external memory slot 712.

The rear surface of the housing 702 (FIG. 10B) is provided with a rear camera 713 and a light 714, and a still image and a moving image can be taken using the display portion 703 as a viewfinder.

Further, in addition to the above functional configuration, an infrared communication function, a USB port, a TV one-segment reception function, a non-contact IC chip, an earphone jack, or the like may be provided.

Various electronic devices described with reference to FIGS. 10A and 10B can be manufactured by applying the above-described manufacturing method of the transistor and the display device.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments in this specification.

In this example, the relationship between the surface roughness of a nitrogen-containing layer formed by plasma CVD and the substrate temperature during film formation will be described. Needless to say, the present invention is not limited to the following examples and is specified by the scope of the claims.

First, a silicon nitride oxide film having a thickness of about 200 nm was formed on a single crystal silicon substrate by plasma CVD. Here, different substrate temperatures (substrate temperatures at the time of film formation) were set, and a silicon nitride oxide film was formed for each substrate temperature. Next, the surface of the silicon nitride oxide film formed at different substrate temperatures was measured using an atomic force microscope (AFM). Thereafter, the single crystal silicon substrate and the glass substrate were bonded using the silicon nitride oxide film formed at each substrate temperature as a bonding layer, and the bonding state was observed.

In this example, in order to accurately measure the surface of the silicon nitride oxide film, the silicon nitride oxide film was formed directly on the single crystal silicon substrate.

Note that a silicon nitride oxide film is formed by a plasma CVD method under an atmosphere containing silane, nitrogen, and hydrogen under a pressure of 160 Pa (SiH ₄ : 14 sccm, N ₂ O: 20 sccm, NH ₃ : 150 sccm, H ₂ : 500 sccm), RF frequency 27.12 MHz, RF power 50 W, and electrode distance 20 mm. The substrate temperature was set based on the measurement result obtained by measuring the temperature separately using a reference glass substrate provided with a thermocouple. That is, the substrate temperature here can be regarded as the temperature of the substrate during film formation.

The measurement by AFM was performed in a dynamic force mode (DFM mode) with a measuring range of 1 μm × 1 μm using an apparatus manufactured by SII Nano Technology Co., Ltd. (SPI3800N / SPA-500).

The single crystal silicon substrate and the glass substrate bonded with the silicon nitride oxide film as the bonding layer are formed by stacking two substrates and then applying pressure by sandwiching the substrate end (one of the four corners) with fingers. This was done by gradually and spontaneously joining from the edge. In this example, bonding was performed using a substrate having an average surface roughness (Ra) of 0.3 nm or less as the glass substrate.

Table 1 shows the measurement results of AFM on the surface of the silicon nitride oxide film formed at each substrate temperature and the bonding state when the silicon nitride oxide film is bonded to the glass substrate as a bonding layer. FIG. 11 shows a plot of average surface roughness (Ra) on the surface of a silicon nitride oxide film formed at each substrate temperature.

As shown in Table 1 and FIG. 11, it was confirmed that the surface roughness of the silicon nitride oxide film formed in a state where the substrate temperature was low became small. When the substrate temperature during film formation was 300 ° C., the average surface roughness (Ra) was about 0.3 nm, and the bonding state was good. In addition, when the substrate temperature during film formation is 300 ° C. or lower (particularly between 100 ° C. and 250 ° C.), the change in average surface roughness of the surface of the silicon nitride oxide film accompanying the substrate temperature during film formation is small and bonding is also good Could be done.

From the above results, it was found that a silicon nitride oxide film having a flat surface can be formed by lowering the substrate temperature during film formation. It was confirmed that a silicon nitride oxide film having a flat surface can be formed by setting the substrate temperature at the time of film formation to 300 ° C. or lower. From this, it is considered that the substrate temperature during film formation is preferably from room temperature to 300 ° C.

In this example, the relationship between the content of hydrogen contained in a nitrogen-containing layer formed using a plasma CVD method and the substrate temperature during film formation will be described.

First, a silicon nitride oxide film was formed over a single crystal silicon substrate by a plasma CVD method. Here, a plurality of different substrate temperatures were set, and a silicon nitride oxide film was formed for each substrate temperature. Next, Fourier transform infrared spectroscopy (Fourier transform infrared) is performed on the hydrogen content (here, the Si—H bond amount and the N—H bond amount) contained in the silicon nitride oxide films formed at different substrate temperatures. Measurement was carried out using spectroscopy (FT-IR). In this example, FT-IR analysis was performed using an apparatus manufactured by Thermo Fisher Scientific (Magna 560). The silicon nitride oxide film was formed by plasma CVD under the same conditions as in Example 1.

FIG. 12A shows measurement results of the Si—H bond amount and the N—H bond amount included in the silicon nitride oxide film formed at each substrate temperature. FIG. 12B shows the ratio of the amount of Si—H bonds to the amount of N—H bonds contained in the silicon nitride oxide film.

FIG. 12 shows that the silicon nitride oxide film formed at a lower substrate temperature contained more Si—H bonds and N—H bonds in the film. In addition, it was confirmed that the Si—H bond ratio contained in the silicon nitride oxide film increased as compared to the N—H bond ratio as the substrate temperature during film formation decreased.

From the above results, it was confirmed that the content of hydrogen contained in the silicon nitride oxide film can be increased by lowering the substrate temperature during film formation.

In this example, the relationship between the film quality of a nitrogen-containing layer formed by plasma CVD and the substrate temperature during film formation will be described.

First, a silicon nitride oxide film was formed over a single crystal silicon substrate by a plasma CVD method. Here, a plurality of different substrate temperatures were set, and a silicon nitride oxide film was formed for each substrate temperature. Next, the etching rate and film hardness before and after heat treatment of the silicon nitride oxide film formed at different substrate temperatures were measured. Note that the silicon nitride oxide film was formed by plasma CVD under the same conditions as in Example 1. Further, the heat treatment was performed at 200 ° C. for 2 hours in a nitrogen atmosphere, and then further performed at 600 ° C. for 2 hours.

In this embodiment, the silicon nitride oxide film is etched using a high purity buffered hydrofluoric acid LAL500 (NH ₄ HF ₂ : 7.13%, NH ₄ F: 15.37% mixed aqueous solution) manufactured by Stella Chemifa Corporation. I went.

The hardness of the silicon nitride oxide film was evaluated using a nanoindentation method. The nanoindentation method was performed using an apparatus manufactured by MTS (NanoIndenter XP). Further, the silicon nitride oxide films formed at the respective substrate temperatures were measured at 15 points and evaluated by the average value.

First, FIG. 13 shows an etching rate before and after heat treatment of a silicon nitride oxide film formed at each substrate temperature. 13A shows an etching rate of the silicon nitride oxide film before the heat treatment, and FIG. 13B shows an etching rate of the silicon nitride oxide film after the heat treatment.

When the etching rate of the silicon nitride oxide film formed at each substrate temperature before the heat treatment was compared, the silicon nitride oxide film formed at a lower substrate temperature resulted in a higher etching rate (FIG. 13). (A)). In particular, it was observed that the etching rate gradually increased from a substrate temperature of 350 ° C. or lower during film formation, and the etching rate rapidly increased from a substrate temperature of 300 ° C. or lower during film formation.

In addition, when the etching rate of the silicon nitride oxide film formed at each substrate temperature after the heat treatment is compared, there is no difference in the etching rate of the silicon nitride oxide film regardless of the substrate temperature at the time of film formation. The result of being slow was obtained (FIG. 13 (B)).

From the result of FIG. 13, it is considered that the silicon nitride oxide film before the heat treatment has a higher etching rate as the substrate temperature at the time of film formation is lower, and the denseness of the film is lower as the substrate temperature at the time of film formation is lower. . On the other hand, it is considered that a densified silicon nitride oxide film can be obtained by performing heat treatment regardless of the substrate temperature at the time of film formation.

Next, FIG. 14 shows the hardness of the silicon nitride oxide film formed at each substrate temperature before and after the heat treatment. 14A shows the hardness of the silicon nitride oxide film before the heat treatment, and FIG. 14B shows the hardness of the silicon nitride oxide film after the heat treatment.

When the hardness of the silicon nitride oxide film formed at each substrate temperature before the heat treatment is compared, the hardness value of the silicon nitride oxide film decreases (the film quality becomes softer) as the substrate temperature at the time of film formation decreases. The result was obtained (FIG. 14A).

In addition, comparing the hardness of the silicon nitride oxide film deposited at each substrate temperature after heat treatment, the influence of the substrate temperature at the time of film formation is small, and it is constant by performing the heat treatment regardless of the substrate temperature at the time of film formation. It was found that a silicon nitride oxide film having a hardness of 10 nm was obtained (FIG. 14B).

From the results of FIG. 14, it can be said that the silicon nitride oxide film before the heat treatment becomes softer as the substrate temperature at the time of film formation is lowered. On the other hand, it can be said that by performing the heat treatment, a silicon nitride oxide film having a certain hardness can be obtained regardless of the substrate temperature at the time of film formation.

In this embodiment, the relationship between the roughness of the surface of the nitrogen-containing layer formed using the plasma CVD method and the pressure during film formation will be described.

First, a silicon nitride oxide film having a thickness of about 200 nm was formed on a single crystal silicon substrate by plasma CVD. Here, different pressures were set as the film formation pressure, and the silicon nitride oxide film was formed under each pressure. Next, the surface of the silicon nitride oxide film formed at different pressures was measured using an atomic force microscope (AFM).

In this example, in order to accurately measure the surface of the silicon nitride oxide film, the measurement was performed by directly forming the silicon nitride oxide film on the single crystal silicon substrate.

Note that the silicon nitride oxide film is formed by a plasma CVD method in an atmosphere containing silane, nitrogen, and hydrogen (SiH ₄ : 14 sccm, N ₂ O: 20 sccm, NH ₃ : 150 sccm, H ₂ : 500 sccm), RF The measurement was performed at a frequency of 27.12 MHz, an RF power of 50 W, and a distance between electrodes of 20 mm. The substrate temperature was tested at 200 ° C. and 300 ° C., respectively.

The measurement by AFM was performed in a dynamic force mode (DFM mode) with a measuring range of 1 μm × 1 μm using an apparatus manufactured by SII Nano Technology Co., Ltd. (SPI3800N / SPA-500).

Table 2 shows the measurement results of AFM on the surface of the silicon nitride oxide film deposited at each deposition pressure. FIG. 15 shows a plot of the average surface roughness (Ra) on the surface of the silicon nitride oxide film formed at each film forming pressure.

As shown in Table 2 and FIG. 15, it was found that a silicon nitride oxide film having a flat surface was formed by increasing the pressure during film formation regardless of the substrate temperature. When the substrate temperature is 300 ° C., the average surface roughness (Ra) of the surface of the silicon nitride oxide film is about 0.3 nm when the deposition pressure is 160 Pa, and a flat surface can be obtained. I understood. It was also found that when the film forming pressure was 160 Pa or more, the change in the average surface roughness of the surface of the silicon nitride oxide film accompanying the pressure during film formation was small.

When the substrate temperature is 200 ° C., it can be seen that the average surface roughness (Ra) of the surface of the silicon nitride oxide film is 0.3 nm or less and a flat surface can be obtained when the deposition pressure is 120 Pa. It was. It was also found that when the film forming pressure was 120 Pa or more, the change in the average surface roughness of the surface of the silicon nitride oxide film accompanying the pressure during film formation was small.

From the above results, it was found that a nitrogen-containing layer having a flat surface can be formed by increasing the pressure during film formation when forming the nitrogen-containing layer. In particular, when the substrate temperature during film formation was 300 ° C. or lower, it was confirmed that a silicon nitride oxide film having a flat surface can be formed by setting the film formation pressure to at least 160 Pa. It was also confirmed that when the substrate temperature during film formation was 200 ° C. or lower, a silicon nitride oxide film having a flat surface could be formed by setting the film formation pressure to 120 Pa or higher.

In this example, a barrier property against impurities of a nitrogen-containing layer formed using a plasma CVD method will be described.

First, a silicon nitride oxide film was formed over a glass substrate by a plasma CVD method. Here, a plurality of different substrate temperatures were set, and a silicon nitride oxide film was formed for each substrate temperature. Next, heat treatment was performed on the silicon nitride oxide films formed at different substrate temperatures, and then the concentration of sodium (Na) contained in the silicon nitride oxide film after the heat treatment was measured. Note that the silicon nitride oxide film was formed by plasma CVD under the same conditions as in Example 1. Further, the heat treatment was performed at 200 ° C. for 2 hours in a nitrogen atmosphere, and then further performed at 600 ° C. for 2 hours.

In this example, the concentration of sodium contained in the silicon nitride oxide film was measured using secondary ion mass spectrometry (SIMS).

FIG. 16 shows the measurement results of the concentration of sodium contained in the silicon nitride oxide film after film formation at each substrate temperature and heat treatment.

According to FIG. 16, the glass substrate contained 1 × 10 ¹⁸ atoms / cm ^{3 of} sodium, but the sodium concentration of the silicon nitride oxide film formed in contact with the glass substrate was that of the silicon nitride oxide film. Regardless of the substrate temperature at the time, it was below the measurement limit of SIMS analysis.

From the above results, it can be confirmed that the silicon nitride oxide film functions as a barrier layer for preventing sodium from diffusing from the glass substrate regardless of the substrate temperature at the time of film formation even when heat treatment is performed. It was.

4A and 4B illustrate an example of a method for manufacturing an SOI substrate of the present invention. 4A and 4B illustrate an example of a method for manufacturing an SOI substrate of the present invention. The schematic diagram which shows joining of the semiconductor substrate in which the nitrogen containing layer was formed, and a base substrate. 4A and 4B illustrate an example of a method for manufacturing an SOI substrate of the present invention. 4A and 4B illustrate an example of a method for manufacturing an SOI substrate of the present invention. FIG. 11 illustrates an example of a semiconductor device using an SOI substrate of the present invention. FIG. 11 illustrates an example of a semiconductor device using an SOI substrate of the present invention. FIG. 11 illustrates an example of a display device using an SOI substrate of the present invention. FIG. 11 illustrates an example of a display device using an SOI substrate of the present invention. The figure which shows an example of the usage pattern using the SOI substrate of this invention. The figure which shows the relationship between the substrate surface at the time of film-forming, and the average surface roughness of the surface of a silicon oxynitride film. The figure which shows the relationship between the board | substrate temperature at the time of film-forming, and the coupling | bonding amount of Si-H and NH of a silicon nitride oxide film. The schematic diagram which shows the relationship between the substrate temperature at the time of film-forming, and the etching rate of a silicon nitride oxide film. The figure which shows the relationship between the substrate temperature at the time of film-forming, and the hardness of a silicon nitride oxide film. The figure which shows the relationship between the pressure at the time of film-forming, and the average surface roughness of the surface of a silicon oxynitride film. The schematic diagram which shows the relationship between the board | substrate temperature at the time of film-forming, and the density | concentration of Na after heat processing.

Explanation of symbols

100 single crystal semiconductor substrate 102 oxide film 103 ion 104 embrittlement region 105 nitrogen containing layer 106 nitrogen containing layer 120 base substrate 121 nitrogen containing layer 124 single crystal semiconductor layer 126 nitrogen containing layer 132 oxide film 251 semiconductor layer 252 semiconductor layer 254 insulating film 255 Gate electrode 256 Gate electrode 257 Low concentration impurity region 258 Channel formation region 259 High concentration impurity region 260 Channel formation region 261 Side wall insulating film 265 Resist 267 High concentration impurity region 268 Insulating film 269 Interlayer insulating film 270 Wiring 320 Single crystal semiconductor layer 322 Scan line 323 Signal line 324 Pixel electrode 325 TFT
327 Interlayer insulating film 328 Electrode 329 Columnar spacer 330 Alignment film 332 Counter substrate 333 Counter electrode 334 Alignment film 335 Liquid crystal layer 340 Channel formation region 341 High-concentration impurity region 401 Selection transistor 402 Display control transistor 403 Semiconductor layer 404 Semiconductor layer 405 Scanning Line 406 Signal line 407 Current supply line 408 Pixel electrode 410 Electrode 411 Electrode 412 Gate electrode 413 Electrode 427 Interlayer insulating film 428 Partition layer 429 EL layer 430 Counter electrode 431 Counter substrate 432 Resin layer 451 Channel formation region 452 High concentration impurity region 500 Micro Processor 501 Arithmetic circuit 502 Arithmetic circuit control unit 503 Instruction analysis unit 504 Control unit 505 Timing control unit 506 Register 507 Register control unit 508 Bus interface 509 Dedicated memory 510 Memory Interface 511 RFCPU
512 Analog circuit section 513 Digital circuit section 514 Resonance circuit 515 Rectifier circuit 516 Constant voltage circuit 517 Reset circuit 518 Oscillation circuit 519 Demodulation circuit 520 Modulation circuit 521 RF interface 522 Control register 523 Clock controller 524 Interface 525 Central processing unit 526 Random access memory 527 Dedicated memory 528 Antenna 529 Capacitance unit 530 Power management circuit 700 Mobile phone 701 Case 702 Case 703 Display unit 704 Speaker 705 Microphone 706 Operation key 707 Pointing device 708 Surface camera lens 709 External connection terminal jack 710 Earphone terminal 711 Keyboard 712 External Memory slot 713 Rear camera 714 Light

Claims (5)

Prepare a single crystal semiconductor substrate and a base substrate made of an insulator,
Forming an oxide film on the single crystal semiconductor substrate;
Irradiating the single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate,
A nitrogen-containing layer is formed on the oxide film or the base substrate using a plasma CVD method,
Bonding the single crystal semiconductor substrate and the base substrate through the oxide film and the nitrogen-containing layer,
Separating the single crystal semiconductor substrate in the embrittlement region, and forming a single crystal semiconductor layer on the base substrate through the insulating layer and the nitrogen-containing layer,
The method for manufacturing an SOI substrate, wherein the nitrogen-containing layer is formed at a substrate temperature of room temperature to 300 ° C. and a film formation pressure of 160 Pa or more. Prepare a single crystal semiconductor substrate and a base substrate made of an insulator,
Forming an oxide film on the single crystal semiconductor substrate;
Irradiating the single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate,
A nitrogen-containing layer is formed on the oxide film or the base substrate using a plasma CVD method,
Bonding the single crystal semiconductor substrate and the base substrate through the oxide film and the nitrogen-containing layer,
Separating the single crystal semiconductor substrate in the embrittlement region, and forming a single crystal semiconductor layer on the base substrate through the insulating layer and the nitrogen-containing layer,
The method for manufacturing an SOI substrate is characterized in that the nitrogen-containing layer is formed at a substrate temperature of room temperature to 200 ° C. and a film formation pressure of 120 Pa or more. In claim 1 or claim 2,
A method for manufacturing an SOI substrate, wherein at least hydrogen gas, silane gas, and ammonia gas are used as a film forming gas for the nitrogen-containing layer. In any one of Claims 1 thru | or 3,
A method for manufacturing an SOI substrate, wherein the oxide film is formed by performing heat treatment on the semiconductor substrate in an oxidizing atmosphere containing hydrogen chloride. In any one of Claims 1 thru | or 4,
A method for manufacturing an SOI substrate, wherein a glass substrate is used as the base substrate.

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