JP2010147313A - Method of manufacturing soi substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a substrate (base substrate) provided with a semiconductor substrate with good yield, even when using the substrate easy to warp as the base substrate. <P>SOLUTION: The method of manufacturing the substrate provided with the semiconductor layer includes a process wherein the semiconductor layer provided on the substrate is irradiated with a laser beam to flatten the surface of the semiconductor layer. In the process of flattening the surface of the semiconductor layer, when the minimum irradiating energy density required for completely melting the semiconductor layer by irradiation of the laser beam is 100%, the irradiating energy density of the laser beam for irradiating the semiconductor layer is 72-98%, preferably 85-96%. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The invention disclosed in this specification relates to a method for manufacturing a substrate provided with a semiconductor layer. In addition, the present invention relates to a method for manufacturing a substrate provided with a semiconductor layer with an insulating layer interposed therebetween, and particularly relates to a method for manufacturing an SOI (Silicon on Insulator) substrate. Further, the present invention relates to a method for manufacturing a semiconductor device using these substrates. Further, the present invention relates to a method for manufacturing a display device using these substrates.

  In recent years, an integrated circuit using a substrate (typically, an SOI substrate) provided with a thin single crystal semiconductor layer on an insulating surface instead of a bulk silicon wafer has been actively developed. When an integrated circuit is formed using an SOI substrate, the parasitic capacitance between the drain of the transistor and the substrate is reduced, so that the performance of the semiconductor integrated circuit can be improved.

  As one method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (for example, see Patent Document 1). An outline of a method for manufacturing an SOI substrate by a hydrogen ion implantation separation method will be described below. First, a microbubble layer is formed at a predetermined depth from the surface by implanting hydrogen ions into a silicon wafer using an ion implantation method. Next, the silicon wafer implanted with hydrogen ions is bonded to another silicon wafer through the silicon oxide film. After that, by performing heat treatment, the microbubble layer becomes a cleavage plane, and a part of the silicon wafer into which hydrogen ions are implanted is separated into a thin film with the microbubble layer as a boundary, and is simply put on another bonded silicon wafer. A crystalline silicon film can be formed.

  On the surface (peeled surface) of the single crystal semiconductor layer after separation, a surface step and a defect layer exist. For this reason, it has been proposed to remove the surface step and the defective layer by mechanical polishing (see, for example, Patent Document 2).

Patent Document 2 describes that a glass substrate can be used as a base substrate on which a semiconductor layer for element formation is provided.
Japanese Patent Laid-Open No. 05-211128 JP 11-97379 A

  Since a glass substrate is easy to increase in area as compared with a silicon wafer and is inexpensive, using a glass substrate as a base substrate makes it possible to manufacture a large area and inexpensive SOI substrate. On the other hand, the glass substrate has a drawback that it is more flexible than a silicon wafer and has a undulation on the surface. For this reason, when a glass substrate is used as the base substrate, the planarization treatment of the peeled surface by mechanical polishing is not preferable from the viewpoint of processing accuracy, yield, and the like. In particular, it is difficult to perform mechanical polishing on a large-area glass substrate having a side exceeding 30 cm.

  As described above, when a flexible substrate such as a glass substrate is used as the base substrate, the problem that it is difficult to improve the unevenness of the surface of the single crystal semiconductor layer separated into a thin film shape becomes obvious.

  The invention disclosed in this specification has been made in view of the above problems, and even when a flexible substrate is used as a base substrate, a substrate (base substrate) provided with a semiconductor layer is manufactured with high yield. One of the purposes. Another object is to manufacture a high-performance semiconductor device with high yield.

  In order to solve the above problems, one embodiment of the invention disclosed in this specification uses the following configuration. That is, an exemplary embodiment of the present invention includes a step of planarizing a surface of a semiconductor layer by irradiating the semiconductor layer provided over the substrate with laser light in a method for manufacturing the substrate provided with the semiconductor layer. It is characterized by having. Then, in the step of flattening the surface of the semiconductor layer, when the minimum irradiation energy density necessary for completely melting the semiconductor layer by laser light irradiation is set to 100%, the irradiation of the laser light irradiated to the semiconductor layer The energy density is from 72% to 98%, preferably from 85% to 96%.

  An exemplary embodiment of the present invention includes a step of irradiating a single crystal semiconductor substrate with ions to form an embrittlement region in the single crystal semiconductor substrate, and the single crystal semiconductor substrate through an insulating layer. A step of bonding a base substrate, a step of separating the single crystal semiconductor substrate and the base substrate in the embrittled region, and forming a semiconductor layer over the base substrate via the insulating layer; and the semiconductor Irradiating the layer with laser light to planarize the surface of the semiconductor layer. Then, in the step of flattening the surface of the semiconductor layer, when the minimum irradiation energy density required for the semiconductor layer to be completely melted by irradiation with the laser beam is 100%, the semiconductor layer is irradiated The irradiation energy density of laser light is 72% to 98%.

  An exemplary embodiment of the present invention includes a step of irradiating a single crystal semiconductor substrate with ions to form an embrittlement region in the single crystal semiconductor substrate, and a step of forming an insulating layer over the base substrate. Bonding the single crystal semiconductor substrate and the base substrate through the insulating layer; separating the single crystal semiconductor substrate and the base substrate in the embrittled region; and isolating the insulating material on the base substrate. Forming a semiconductor layer through the layer; and irradiating the semiconductor layer with laser light to planarize a surface of the semiconductor layer. Then, in the step of flattening the surface of the semiconductor layer, when the minimum irradiation energy density required for the semiconductor layer to be completely melted by irradiation with the laser beam is 100%, the semiconductor layer is irradiated The irradiation energy density of laser light is 72% to 98%.

  An exemplary aspect of the present invention is characterized in that the insulating layer is formed using a plasma CVD apparatus that generates plasma by applying pulse-modulated power.

  An exemplary embodiment of the present invention includes a step of heating the semiconductor layer at a temperature of 640 ° C. or higher and lower than a strain point of the base substrate after the surface of the semiconductor layer is planarized. .

  According to an exemplary aspect of the present invention, the laser beam is a linear pulsed laser beam, and the linear pulsed laser beam is emitted when the semiconductor layer is irradiated with the linear pulsed laser beam. Irradiated a plurality of times. Preferably, the linear pulse laser beam is irradiated a plurality of times so that the overlap rate is 100%.

  One exemplary embodiment of the present invention is characterized in that a glass substrate is used as the base substrate.

  An exemplary embodiment of the present invention is characterized in that the semiconductor layer is made of a single crystal.

  In this specification, the term “single crystal” refers to a crystal in which the direction of the crystal axis is the same in any part of the sample when attention is paid to a crystal axis, and between the crystals. Refers to a crystal having no grain boundary. In the present specification, even if crystal defects and dangling bonds are included, a crystal in which the directions of crystal axes are aligned and no grain boundary exists as described above is a single crystal.

  In this specification, a “semiconductor device” refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor device.

  In this specification, the “display device” includes a light-emitting device and a liquid crystal display device. The light emitting device includes a light emitting element, and the liquid crystal display device includes a liquid crystal element. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like.

  In addition, in this specification, when “A and B are electrically connected” is described, when A and B are electrically connected (that is, between A and B) When connected with another element or another circuit) and when A and B are functionally connected (that is, functionally with another circuit between A and B) And the case where A and B are directly connected (that is, the case where A and B are connected without sandwiching another element or another circuit). .

  In this specification, ordinal numbers attached as “first”, “second”, and the like are used for convenience to describe various elements, members, regions, layers, and sections separately from others. It does not indicate a unique name as a matter for specifying the invention. Therefore, “first” can be appropriately replaced with “second”, “third”, or the like.

  According to the present invention, even when a flexible substrate is used as a base substrate, the single crystal semiconductor layer provided over the base substrate can be planarized. Further, even when a flexible substrate is used as the base substrate, a high-performance semiconductor element can be formed.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Note that in each of the embodiments described below, the same reference numeral is used in different drawings. In addition, in each of the embodiments and examples described below, the present invention can be implemented in appropriate combination with the other embodiments and examples described in this specification unless otherwise specified. is there.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing a substrate provided with a semiconductor layer will be described. Specifically, a method for manufacturing a substrate provided with a single crystal silicon layer with an insulating layer interposed therebetween (method for manufacturing an SOI substrate) will be described. However, the present invention is not limited to the configuration described in this embodiment.

  First, the single crystal semiconductor substrate 100 and the base substrate 120 are prepared (see FIGS. 1A and 1B).

  As the single crystal semiconductor substrate 100, a single crystal semiconductor substrate made of a Group 14 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate, or a compound semiconductor substrate such as gallium arsenide or indium phosphide is used. Can do. As a commercially available silicon substrate, a circular substrate having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), a diameter of 12 inches (300 mm), and a diameter of 16 inches (400 mm) is typical. Yes, any size silicon substrate can be used. Note that the shape of the single crystal semiconductor substrate 100 is not limited to a circle, and the single crystal semiconductor substrate 100 can be processed into a rectangular shape or the like. In this embodiment, the case where a single crystal silicon substrate is used as the single crystal semiconductor substrate 100 is described.

  As the base substrate 120, an insulating substrate is preferably used. Specific examples of the insulating substrate include various glass substrates used in the electronic industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass, quartz substrate, ceramic substrate, sapphire substrate, and plastic substrate. In addition, a single crystal semiconductor substrate (for example, a single crystal silicon substrate) or a polycrystalline semiconductor substrate (for example, a polycrystalline silicon substrate) can be used as the base substrate 120. However, in consideration of mass productivity and cost, It is preferable to use an inexpensive insulating substrate capable of increasing the area. In this embodiment, the case where a glass substrate which is one of insulating substrates is used as the base substrate 120 is described.

  Next, the insulating layer 102 is formed on the surface of the single crystal semiconductor substrate 100. Then, an embrittled region 104 having a damaged crystal structure is formed at a predetermined depth from the surface of the single crystal semiconductor substrate 100. Note that the embrittlement region 104 can be formed by irradiating the single crystal semiconductor substrate 100 with ions of hydrogen or the like having kinetic energy.

  The insulating layer 102 can be formed using a single layer or a stacked layer of insulating layers such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and a silicon nitride oxide film. The insulating layer 102 can be formed by a thermal oxidation method, a CVD method, a sputtering method, or the like.

  Note that in this specification, “silicon oxynitride” has a composition containing more oxygen than nitrogen, and is preferably Rutherford Backscattering Spectroscopy (RBS) and hydrogen front. When measured using a scattering method (HFS: Hydrogen Forward Scattering), the concentration ranges are 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 to 0.5 for hydrogen. The thing contained in the range of 1-10 atomic%. Further, in this specification, “silicon nitride oxide” has a composition containing more nitrogen than oxygen, and preferably has a concentration range when measured using RBS and HFS. The oxygen content is within a range of 5 to 30 atomic%, nitrogen is 20 to 55 atomic%, silicon is 25 to 35 atomic%, and hydrogen is 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

  Next, the single crystal semiconductor substrate 100 and the base substrate 120 are attached to each other with the insulating layer 102 interposed therebetween (see FIG. 1C).

  Next, heat treatment is performed to separate the single crystal semiconductor substrate 100 in the embrittled region 104, whereby the single crystal semiconductor layer 124 is provided over the base substrate 120 with the insulating layer 102 interposed therebetween (see FIG. 1D). By performing the heat treatment, the added element is precipitated in the minute holes formed in the embrittled region 104 due to the temperature rise, and the internal pressure rises. As the pressure rises, volume changes occur in minute holes in the embrittled region 104 and cracks occur in the embrittled region 104, so that the single crystal semiconductor substrate 100 is separated along the embrittled region 104. Since the insulating layer 102 is bonded to the base substrate 120, a single crystal semiconductor layer 124 separated from the single crystal semiconductor substrate 100 is formed over the base substrate 120. As a heating means for the heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, heating may be performed at a heating temperature of 550 ° C. or higher and 730 ° C. or lower and a processing time of 0.5 minutes or longer and within 60 minutes.

  Through the above steps, an SOI substrate including the single crystal semiconductor layer 124 over the base substrate 120 with the insulating layer 102 interposed therebetween can be manufactured as illustrated in FIG. Note that in this embodiment, the thickness of the single crystal semiconductor layer 124 may be greater than or equal to 100 nm and less than or equal to 300 nm, and preferably greater than or equal to 110 nm and less than or equal to 200 nm.

  Next, a step of planarizing the surface of the single crystal semiconductor layer 124 (hereinafter referred to as a “planarization step”) is performed. In one embodiment of the invention described in this embodiment, the surface of the single crystal semiconductor layer 124 is planarized by irradiating the surface of the single crystal semiconductor layer 124 formed over the base substrate 120 with the laser light 130. (See FIG. 1E).

  Note that irradiation with the laser light 130 may be performed only on a desired region in the single crystal semiconductor layer 124 that needs planarization. Accordingly, the entire surface of the single crystal semiconductor layer 124 may be planarized by irradiating the entire surface of the single crystal semiconductor layer 124 with laser light 130, or the laser beam 130 may be irradiated to a partial region of the single crystal semiconductor layer 124. Thus, part of the region of the single crystal semiconductor layer 124 may be planarized. Further, the irradiation with the laser beam 130 may be performed once for a desired region that needs to be planarized, or may be performed a plurality of times (for example, 5 to 20 times). However, when the laser beam 130 is irradiated a plurality of times on a desired region that needs to be flattened, it is preferable to irradiate the laser beam without scanning (that is, the overlap rate is 100%).

  Further, the shape of the beam spot of the laser beam 130 is not particularly limited, and may be any shape. For example, a rectangle (linear shape), a square, an ellipse, or a perfect circle may be used, but typically, a rectangle (linear shape) may be used.

  In general, unevenness is formed in the surface layer portion of the single crystal semiconductor layer 124 formed over the base substrate 120 after separation due to formation of the embrittled region 104, separation in the embrittled region 104, and the like, and flatness is impaired. It is. In this embodiment, as illustrated in FIG. 1E, the single crystal semiconductor layer 124 is irradiated with laser light 130 from the surface side of the single crystal semiconductor layer 124 having projections and depressions, whereby a surface layer portion of the single crystal semiconductor layer 124 is formed. Can be melted to improve the flatness. Note that the single crystal semiconductor layer 124 can be irradiated with laser light while the base substrate 120 provided with the single crystal semiconductor layer 124 is heated. The heating temperature may be a temperature below the strain point of the base substrate 120. For example, in the case of a glass substrate, heating may be performed in a temperature range of 300 ° C. to 700 ° C.

  In the planarization step, the energy density of the laser light 130 applied to the single crystal semiconductor layer 124 is set lower than the energy density when the crystal structure of the single crystal semiconductor layer 124 is changed by irradiation with the laser light 130. This is because when the energy density of the laser light 130 applied to the single crystal semiconductor layer 124 is too high, the single crystal semiconductor layer 124 is completely melted (completely melted) and the crystal structure is changed (microcrystallization). This is because irregularities occur on the surface of the semiconductor film. In this specification, “complete melting” means that the depth of the single crystal semiconductor layer 124 melted by irradiation with the laser light 130 is from the interface between the single crystal semiconductor layer 124 and the insulating layer 102 to the surface of the single crystal semiconductor layer 124. Is a phenomenon that is equal to the distance in the depth direction (the thickness of the single crystal semiconductor layer 124). In other words, the single crystal semiconductor layer 124 is melted over the entire layer to be in a liquid phase.

  That is, according to one embodiment of the invention described in this embodiment, the single crystal semiconductor layer 124 is not completely melted but the laser light 130 having an energy density that partially melts (partly melts) the single crystal. Irradiation from the surface side of the semiconductor layer 124 is performed to planarize the surface of the single crystal semiconductor layer 124. In this specification, “partial melting” means that the depth of the single crystal semiconductor layer 124 melted by irradiation with the laser light 130 is from the interface between the single crystal semiconductor layer 124 and the insulating layer 102 to the surface of the single crystal semiconductor layer 124. This is a phenomenon that becomes shallower than the distance in the depth direction (the thickness of the single crystal semiconductor layer 124). That is, the upper layer of the single crystal semiconductor layer 124 is melted to be in a liquid phase, while the lower layer is not melted and remains a solid single crystal semiconductor.

  When the single crystal semiconductor layer 124 is partially melted, the crystal growth of the melted portion by irradiation with the laser light 130 is performed based on the plane orientation of the unmelted single crystal semiconductor layer, and therefore, the single crystal semiconductor layer 124 is completely melted. In comparison, the surface of the single crystal semiconductor layer 124 can be planarized while suppressing change (microcrystallization) of the crystal structure.

  Note that the crystallinity of the single crystal semiconductor layer 124 can be evaluated by observation with an optical microscope, a Raman shift obtained from a Raman spectrum, a full width at half maximum, or the like. For example, the irradiation energy of the laser light 130 when the single crystal semiconductor layer 124 is completely melted and microcrystallized is obtained using the value of Raman shift (value A), and the single crystal semiconductor layer 124 is partially melted. The irradiation energy of the laser beam 130 is obtained using the Raman shift value (value B). Then, after irradiating the single crystal silicon layer with a plurality of laser beam irradiation energy conditions, the Raman shift under each condition is measured, and the point at which the value of the Raman shift changes from the value B to the value A It can be regarded as the energy density when the crystal structure of the semiconductor layer 124 changes. In other words, it can be said that the point at which the Raman shift value changes from the value B to the value A corresponds to the minimum energy density necessary for the single crystal semiconductor layer 124 to be completely melted.

  The laser oscillator applicable to this embodiment is a pulse oscillation type laser, and its oscillation wavelength is absorbed by the single crystal semiconductor layer 124 in consideration of the skin depth of the laser light and the like. Such a wavelength can be selected. For example, the wavelength of the ultraviolet light region (180 nm or more and 400 nm or less) may be selected. The repetition frequency is preferably 100 kHz or less and the pulse width is preferably 10 to 500 nsec. The laser medium can be any of solid, liquid, and gas. A typical pulsed laser is an excimer laser that oscillates laser light having a wavelength of 400 nm or less. As such an excimer laser, for example, an XeCl excimer laser having a repetition frequency of 10 Hz to 300 Hz, a pulse width of 25 nsec, and a wavelength of 308 nm can be used.

  In addition, the irradiation energy density of the laser light applied to the single crystal semiconductor layer 124 is determined by considering the wavelength of the laser light, the skin depth of the laser light, the thickness of the single crystal semiconductor layer 124, and the like. The irradiation energy density is such that it does not melt completely (that is, partially melts). In other words, the irradiation energy density of the laser light with which the single crystal semiconductor layer 124 is irradiated needs to be smaller than the minimum irradiation energy density necessary for the single crystal semiconductor layer 124 to be completely melted.

FIG. 3A shows the relationship between the irradiation energy density and the surface roughness of the single crystal semiconductor layer.
The object to be irradiated was a single crystal silicon (single crystal semiconductor layer 124) formed on a glass substrate (base substrate 120) with a silicon nitride oxide film and a silicon oxynitride film (insulating layer 102) interposed therebetween. The thickness of the single crystal semiconductor layer 124 was 140 nm. Various conditions of the irradiated laser light are as follows.

Laser type: XeCl excimer Laser wavelength: 308 nm
Oscillation method: Pulse oscillation repetition frequency: 30Hz
Pulse width: 25 ns Number of times of laser light irradiation on the single crystal semiconductor layer 124: once, five times, ten times

As shown in FIG. 3A, the degree of change in the surface roughness of the single crystal semiconductor layer 124 when the irradiation energy density is changed does not depend on the number of times of laser light irradiation and has almost the same tendency. I understand. Further, when the surface roughness of the single crystal semiconductor layer 124 is irradiated with laser light having an irradiation energy density equal to or higher than a predetermined value (in the vicinity of 750 mJ / cm ² in FIG. 3A), the planarization effect is obtained. It can be seen that is suddenly damaged. This is considered to be because the single crystal semiconductor layer 124 is completely melted. When the single crystal semiconductor layer 124 is completely melted, a large amount of seed crystals are generated at the interface between the single crystal semiconductor layer 124 and the insulating layer therebelow. When a large amount of seed crystals are generated in this way, the various crystals cannot be grown sufficiently, and a large amount of grain boundaries (ridges) are produced, resulting in a significant loss of flatness.

  The minimum irradiation energy density necessary for completely melting the single crystal semiconductor layer 124 by laser light irradiation is set to 100%, and the irradiation energy density on the horizontal axis in FIG. 3A is converted into a relative value (expressed in%). The result is shown in FIG.

  In one embodiment of the invention described in this embodiment, at least 100% is not exceeded when the minimum irradiation energy density necessary for the single crystal semiconductor layer 124 to be completely melted by laser light irradiation is 100%. The single crystal semiconductor layer 124 is prevented from being completely melted by irradiating the single crystal semiconductor layer 124 with laser light having an appropriate irradiation energy density. Preferably, 98% is the upper limit, and more preferably 96% is the upper limit. By determining the upper limit in this manner, the single crystal semiconductor layer 124 can be prevented from being completely melted by laser light irradiation, so that the surface of the single crystal semiconductor layer 124 can be sufficiently planarized.

On the other hand, as shown in FIG. 3B, the surface roughness of the single crystal semiconductor layer 124 is a laser beam having an irradiation energy density equal to or lower than a predetermined value (near 550 mJ / cm ² in FIG. 3A). It can be seen that even if irradiation is performed, the planarization is not sufficiently performed. This is considered to be because the irradiation energy necessary for planarization of the single crystal semiconductor layer 124 has not been reached.

  Thus, according to one embodiment of the invention described in this embodiment, when the minimum irradiation energy density necessary for the single crystal semiconductor layer 124 to be completely melted by laser light irradiation is 100%, 72% is the lower limit. And preferably 85% is the lower limit. By irradiation with laser light having an irradiation energy density of at least 72% or more, the surface of the single crystal semiconductor layer 124 can be sufficiently planarized.

  As described above, according to one embodiment of the present invention in this embodiment, laser irradiation to the single crystal semiconductor layer 124 is performed when the minimum irradiation energy density necessary for the single crystal semiconductor layer 124 to be completely melted is 100%. The energy density of light is set to 72% to 98%, preferably 85% to 96%. By defining the energy density condition of the laser light to be irradiated in this manner, the single crystal semiconductor layer 124 provided over the base substrate 120 can be sufficiently planarized with the insulating layer 102 interposed therebetween. Note that the effect of planarizing the surface of the single crystal semiconductor layer 124 by irradiation with laser light under such conditions can be obtained by appropriately selecting the wavelength, oscillation method, repetition frequency, and the like of the laser light within the above-described range. It is done.

  Note that the atmosphere for laser light irradiation is preferably such that the oxygen concentration in the chamber for laser light irradiation is reduced as much as possible so that oxygen is not taken into the single crystal semiconductor layer 124 in the planarization step. When oxygen in the atmosphere is taken into the single crystal semiconductor layer 124, an oxide film is formed on the surface of the single crystal semiconductor layer 124. When the region of the single crystal semiconductor layer 124 with the oxide film formed on the surface is irradiated again with laser light, the flatness of the surface of the single crystal semiconductor layer 124 is significantly impaired. For this reason, in the case where a structure in which laser light is irradiated to a predetermined region of the single crystal semiconductor layer 124 a plurality of times in the planarization step is employed, the oxygen concentration in the chamber is reduced as much as possible in order to perform sufficient planarization. It is particularly preferable to prevent oxygen from being taken into the crystalline semiconductor layer 124. As a specific method for reducing the oxygen concentration in the chamber, the atmosphere in the chamber may be a reducing atmosphere or an inert atmosphere (for example, a nitrogen atmosphere). Preferably, the oxygen concentration in the reducing atmosphere or the inert atmosphere is less than 100 ppm, more preferably less than 1 ppm.

  In addition, when oxygen in the atmosphere is taken into the single crystal semiconductor layer 124, characteristics of an element (eg, a transistor) including the single crystal semiconductor layer 124 may be adversely affected. In order to prevent such adverse effects, the atmosphere in the chamber irradiated with the laser light is a reducing atmosphere or an inert atmosphere, and the oxygen concentration in the reducing atmosphere or the inert atmosphere is less than 1 ppb, preferably less than 1 ppt. It is good to do.

  Further, it is preferable to perform heat treatment after the planarization step. By performing heat treatment, defects in the single crystal semiconductor layer 124 or defects at the interface between the single crystal semiconductor layer 124 and the insulating layer 102 can be repaired.

  In particular, the single crystal semiconductor layer 124 after being irradiated with the laser light 130 includes many defects in a region that has not been melted. However, by performing heat treatment at a high temperature, crystal defects in the single crystal semiconductor layer 124 and the like Can be repaired effectively. In this embodiment, the heating temperature of the single crystal semiconductor layer 124 is higher than the temperature of heat treatment in a later step, preferably 640 ° C. or higher (more preferably 700 ° C. or higher), and the single crystal semiconductor layer 124 The temperature at which 124 is not completely melted is lower than the strain point of the base substrate 120. For example, when a glass substrate is used as the base substrate, heat treatment at 640 ° C. to 750 ° C. is preferably performed.

  After the single crystal semiconductor layer 124 is irradiated with the laser light 130, heat treatment is performed on the single crystal semiconductor layer 124, so that crystal defects in the single crystal semiconductor layer 124 can be repaired. By forming a semiconductor element using the single crystal semiconductor layer 124 thus obtained, a high-performance semiconductor element can be obtained even when a flexible substrate is used as a base substrate.

  As a heating means for heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, or the like can be used.

  Alternatively, after the single crystal semiconductor layer 124 is irradiated with the laser light 130, the single crystal semiconductor layer 124 may be etched to reduce the thickness. Since the surface of the single crystal semiconductor layer 124 after etching depends on the surface state of the single crystal semiconductor layer 124 before etching, the surface of the single crystal semiconductor layer 124 is planarized by irradiation with laser light 130 before etching. Accordingly, the single crystal semiconductor layer 124 having flatness can be obtained even after thinning.

  For etching in the above-described thinning process, a dry etching method or a wet etching method can be used. When the dry etching method is used, a chloride gas such as boron chloride, silicon chloride, or carbon tetrachloride, a fluoride gas such as chlorine gas, sulfur fluoride, or nitrogen fluoride, or an oxygen gas may be used as an etching gas. When the wet etching method is used, a TMAH solution may be used as an etching solution.

  Note that in the case of adding a thinning process, the thickness of the single crystal semiconductor layer 124 after thinning can be determined as appropriate in accordance with characteristics of an element formed later from the single crystal semiconductor layer 124. For example, the thickness of the single crystal semiconductor layer 124 after thinning may be 5 nm to 200 nm, preferably 10 nm to 70 nm.

  In the case of reducing the thickness of the single crystal semiconductor layer 124, it is preferable to perform it after the planarization step and before the heat treatment. That is, by performing heat treatment after the thinning treatment, damage to the surface of the single crystal semiconductor layer 124 due to the etching of the thinning treatment can be repaired.

  By using the method described in this embodiment, the surface of the single crystal semiconductor layer provided over the base substrate can be sufficiently obtained even when a substrate such as glass with low heat resistance is used as the base substrate. It can be flattened.

(Embodiment 2)
In this embodiment, a method for bonding the single crystal semiconductor substrate 100 and the base substrate 120 in the manufacturing process of the SOI substrate illustrated in FIG. 1 will be described in detail with reference to the drawings. However, the present invention is not limited to the configuration described in this embodiment.

  First, the single crystal semiconductor substrate 100 is prepared (see FIG. 2A-1). The surface of the single crystal semiconductor substrate 100 may be cleaned appropriately in advance using sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), hydrochloric acid / hydrogen peroxide (HPM), dilute hydrofluoric acid (DHF), etc. To preferred. Further, cleaning may be performed by alternately discharging dilute hydrofluoric acid and ozone water.

  Next, an oxide film 132 is formed on the surface of the single crystal semiconductor substrate 100 (see FIG. 2A-2).

As an example of the oxide film 132, a single-layer film of a silicon oxide film or a silicon oxynitride film, or a film in which these layers are stacked can be used. The oxide film 132 may be formed by a thermal oxidation method, a CVD method, a sputtering method, or the like. In particular, when the oxide film 132 is formed using a CVD method, a silicon oxide film formed using an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ) is oxidized. Use in the membrane 132 is preferable from the viewpoint of productivity.

  In this embodiment, an oxide film 132 (here, a SiOx film) is formed by performing thermal oxidation treatment on the single crystal semiconductor substrate 100. The thermal oxidation treatment is preferably performed by adding halogen in an oxidizing atmosphere.

  For example, the single crystal semiconductor substrate 100 is subjected to thermal oxidation treatment in an oxidizing atmosphere to which chlorine (Cl) is added, so that the oxide film 132 subjected to chlorine oxidation is formed. In this case, the oxide film 132 is a film containing chlorine atoms.

  Chlorine atoms contained in the oxide film 132 form strain. As a result, the moisture absorption ratio of the oxide film 132 is improved and the diffusion rate is increased. That is, when moisture is present on the surface of the oxide film 132, moisture present on the surface can be quickly absorbed and diffused into the oxide film 132.

  As an example of the thermal oxidation treatment, a temperature of 900 ° C. to 1150 ° C. (typical) in an oxidizing atmosphere containing hydrogen chloride (HCl) at a ratio of 0.5 to 10% by volume (preferably 2% by volume) with respect to oxygen. Specifically, it can be performed at 1000 ° C.). The treatment time may be 0.1 to 6 hours, preferably 0.5 to 1 hour. The thickness of the oxide film formed by the thermal oxidation treatment may be 10 nm to 1000 nm (preferably 50 nm to 300 nm), for example, 100 nm.

In this embodiment, the concentration of chlorine atoms contained in the oxide film 132 is controlled to be 1 × 10 ¹⁷ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ . By including chlorine atoms in the oxide film 132, heavy metals (eg, Fe, Cr, Ni, Mo, etc.) that are extrinsic impurities can be collected and contamination of the single crystal semiconductor substrate 100 can be prevented.

  In addition, when the oxide film 132 includes halogen such as chlorine by HCl oxidation or the like, impurities (for example, movable ions such as Na) that adversely affect the single crystal semiconductor substrate can be gettered. In other words, by heat treatment performed after the oxide film 132 is formed, impurities contained in the single crystal semiconductor substrate are deposited on the oxide film 132 and are captured by reacting with halogen (eg, chlorine). Accordingly, the impurity collected in the oxide film 132 can be fixed and contamination of the single crystal semiconductor substrate 100 can be prevented. Further, the oxide film 132 can function as a film for fixing impurities such as Na contained in the glass when bonded to a glass substrate.

  In particular, inclusion of halogen such as chlorine in the film as the oxide film 132 by HCl oxidation or the like is effective in removing contamination of a semiconductor substrate that is used repeatedly or repeatedly when the semiconductor substrate is not sufficiently cleaned. It becomes.

Further, the halogen atoms contained in the oxide film 132 are not limited to chlorine atoms. For example, the oxide film 132 may contain fluorine atoms. In order to fluorinate the surface of the single crystal semiconductor substrate 100, the surface of the single crystal semiconductor substrate 100 is immersed in hydrofluoric acid and then subjected to thermal oxidation treatment in an oxidizing atmosphere, or NF ₃ is added to the oxidizing atmosphere. Thermal oxidation treatment may be performed.

  Next, by irradiating the single crystal semiconductor substrate 100 with ions having kinetic energy, an embrittled region 104 having a damaged crystal structure is formed at a predetermined depth of the single crystal semiconductor substrate 100 (FIG. 2A-A). 3)). As shown in FIG. 2A-3, a region having a predetermined depth from the surface of the single crystal semiconductor substrate 100 is obtained by irradiating the single crystal semiconductor substrate 100 with the accelerated ions 103 through the oxide film 132. The ions 103 can be added to the fragile regions 104 to be formed. The ions 103 are ions that are excited by generating a plasma of the source gas by exciting the source gas and extracting ions contained in the plasma from the plasma by the action of an electric field.

  The depth of the region where the embrittlement region 104 is formed can be adjusted by the kinetic energy, mass and charge of the ions 103, and the incident angle of the ions 103. Here, the kinetic energy can be adjusted by the acceleration voltage, the dose amount, and the like. Since the embrittlement region 104 is formed in a region having a depth substantially equal to the average penetration depth of the ions 103, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 100 at a depth to which the ions 103 are added. Is determined. In this embodiment, the depth at which the embrittlement region 104 is formed is adjusted so that the thickness of the single crystal semiconductor layer is 10 nm to 500 nm, preferably 50 nm to 200 nm.

  The embrittlement region 104 is preferably formed by an ion doping process using an ion doping apparatus, but can also be formed by an ion implantation process using an ion implantation apparatus. A typical ion doping apparatus is a non-mass separation type apparatus that irradiates an object to be processed disposed in a chamber with all ion species generated by plasma excitation of a process gas. The non-mass separation type apparatus is because the object to be processed is irradiated with all ion species without mass separation of ion species in the plasma. On the other hand, the ion implantation apparatus is a mass separation type apparatus. An ion implantation apparatus is an apparatus that mass-separates ion species in plasma and irradiates a target object with ion species having a specific mass.

  The main components of the ion doping apparatus are a chamber in which an object to be processed is arranged, an ion source for generating desired ions, and an acceleration mechanism for accelerating and irradiating ions. The ion source includes a gas supply device that supplies a source gas for generating a desired ion species, an electrode for generating a plasma by exciting the source gas, and the like. As an electrode for forming plasma, a filament-type electrode, an electrode for capacitively coupled high-frequency discharge, or the like is used. The acceleration mechanism includes electrodes such as an extraction electrode, an acceleration electrode, a deceleration electrode, and a ground electrode, and a power source for supplying power to these electrodes. The electrode constituting the acceleration mechanism is provided with a plurality of openings and slits, and ions generated by the ion source are accelerated through the openings and slits provided in the electrodes. Note that the configuration of the ion doping apparatus is not limited to that described above, and a mechanism according to need is provided.

In this embodiment, hydrogen is added to the single crystal semiconductor substrate 100 with an ion doping apparatus. At this time, a gas containing hydrogen (for example, H ₂ ) is supplied as a plasma source gas. Hydrogen gas is excited to generate plasma, ions contained in the plasma are accelerated without mass separation, and the single crystal semiconductor substrate 100 is irradiated with the accelerated ions.

Here, the single crystal semiconductor substrate 100 is irradiated with ions so that the ratio of H ₃ ⁺ to the total amount of ion species (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ) generated from hydrogen gas is 50% or more. To do. And preferably, the ratio of H ₃ ⁺ is 80% or more. Since the ion doping apparatus does not perform mass separation, one (H ₃ ⁺ ) of a plurality of ion species generated in plasma is preferably 50% or more, and more preferably 80% or more. By irradiation with ions having the same mass, ions can be added while being concentrated at the same depth in the single crystal semiconductor substrate 100.

In order to form the embrittled region 104 in a shallow region, the acceleration voltage of the ions 103 needs to be lowered. However, by increasing the proportion of H ₃ ⁺ ions in the plasma, hydrogen ions can be efficiently converted into a single crystal. It can be added to the semiconductor substrate 100. Since H ₃ ⁺ ions have a mass three times that of H ⁺ ions, when one hydrogen atom is added at the same depth, the acceleration voltage of H ₃ ⁺ ions is three times the acceleration voltage of H ⁺ ions. It becomes possible to do. If the acceleration voltage of ions can be increased, the tact time of the ion irradiation process can be shortened, and productivity and throughput can be improved.

Since the ion doping apparatus is inexpensive and excellent in large area processing, irradiation with H ₃ ⁺ using such an ion doping apparatus improves the semiconductor characteristics, increases the area, reduces the cost, and improves the productivity. A remarkable effect such as can be obtained. In addition, when an ion doping apparatus is used, heavy metal may be introduced into the single crystal semiconductor substrate 100 at the same time. However, by irradiating ions through the oxide film 132 containing chlorine atoms, a single crystal made of heavy metal is used. Contamination of the semiconductor substrate 100 can be prevented.

Note that as described above, the step of irradiating the single crystal semiconductor substrate 100 with the accelerated ions 103 can be performed with an ion implantation apparatus. The ion implantation apparatus is a mass separation type apparatus that mass-separates a plurality of ion species generated by plasma-exciting a source gas from a target object disposed in a chamber and irradiates specific ion species. Therefore, when an ion implantation apparatus is used, H ⁺ ions and H ₂ ⁺ ions generated by exciting hydrogen gas or PH ₃ are mass-separated to accelerate one of the H ⁺ ions or the H ₂ ⁺ ions. Then, the single crystal semiconductor substrate 100 is irradiated.

  Next, the base substrate 120 is prepared (see FIG. 2B-1). When using the base substrate 120, it is preferable to clean the surface of the base substrate 120 in advance. Specifically, the surface of the base substrate 120 is subjected to ultrasonic cleaning using hydrochloric acid / hydrogen peroxide (HPM), sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), dilute hydrofluoric acid (DHF), or the like. By performing such a cleaning process, the surface of the base substrate 120 can be planarized and the remaining abrasive particles can be removed.

  Next, an insulating layer 121 (eg, an insulating film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film) is formed over the surface of the base substrate 120 (see FIG. 2B-2).

  In this embodiment, the insulating layer 121 is a layer (a bonding layer) bonded to the oxide film 132 provided over the single crystal semiconductor substrate 100. In the case where a glass substrate is used as the base substrate, the insulating layer 121 has impurities such as Na (sodium) contained in the base substrate when a single crystal semiconductor layer having a single crystal structure is provided over the base substrate later. It functions as a barrier layer for preventing diffusion into the single crystal semiconductor layer.

  Further, since the insulating layer 121 serves as a bonding layer, it is preferable to smooth the surface of the insulating layer 121 in order to suppress bonding defects. Specifically, the average surface roughness (Ra) of the surface of the insulating layer 121 is 0.5 nm or less, the root mean square roughness (Rms) is 0.60 nm or less, and more preferably the average surface roughness is 0.35 nm or less. The insulating layer 121 is preferably formed so that the root mean square roughness is 0.45 nm or less. In order to smooth the surface of the insulating layer 121, it is preferable to form the insulating layer 121 using a plasma CVD apparatus that generates plasma by applying pulse-modulated power (high-frequency power), for example. However, the present invention is not limited to this, and other CVD methods or sputtering methods may be used. Note that the thickness of the insulating film is greater than or equal to 10 nm and less than or equal to 200 nm, preferably greater than or equal to 50 nm and less than or equal to 100 nm.

  Next, the surface of the single crystal semiconductor substrate 100 and the surface of the base substrate 120 are opposed to each other, and the surface of the oxide film 132 and the surface of the insulating layer 121 are bonded (see FIG. 2C).

In this embodiment mode, after the single crystal semiconductor substrate 100 and the base substrate 120 are closely attached to each other through the oxide film 132 and the insulating layer 121, 1 to 500 N / cm ² , preferably at one place of the single crystal semiconductor substrate 100. Applies a pressure of about 1 to ²⁰ N / cm ² . The oxide film 132 and the insulating layer 121 start to be joined from the portion to which pressure is applied, and the junction is spontaneously formed and reaches the entire surface. Since this bonding process is performed at room temperature without van der Waals force or hydrogen bonding and without heat treatment, a substrate having a low heat-resistant temperature such as a glass substrate can be used as the base substrate 120. .

  Note that before the single crystal semiconductor substrate 100 and the base substrate 120 are bonded to each other, surface treatment of the oxide film 132 formed over the single crystal semiconductor substrate 100 and the insulating layer 121 formed over the base substrate 120 is performed. It is preferable to carry out in advance.

  As the surface treatment, plasma treatment, ozone treatment, megasonic cleaning, two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen), or a combination of these methods as appropriate. Can do. In particular, after plasma treatment is performed on at least one surface of the oxide film 132 and the insulating layer 121, ozone treatment, megasonic cleaning, or two-fluid cleaning is performed, so that the organic matter on the surface of the oxide film 132 and the insulating layer 121 is removed. Dust can be removed and the surface can be hydrophilized. As a result, the bonding strength between the oxide film 132 and the insulating layer 121 can be further improved.

  Further, after the oxide film 132 and the insulating layer 121 are bonded, heat treatment for increasing the bonding strength is preferably performed. The temperature of this heat treatment is set to a temperature that does not cause cracks in the embrittled region 104. For example, heat treatment is performed in a temperature range of room temperature to less than 400 ° C. Alternatively, the oxide film 132 and the insulating layer 121 may be bonded while heating in this temperature range. As a heating means for the heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used.

  In general, when heat treatment is performed at the same time as or after bonding the oxide film 132 and the insulating layer 121, a dehydration reaction proceeds at the bonding interface, the bonding interfaces approach each other, and hydrogen bonds are strengthened or covalent bonds are formed. This strengthens the bonding. In order to promote the dehydration reaction, it is necessary to remove moisture generated at the bonding interface by the dehydration reaction by performing a heat treatment at a high temperature. In other words, when the heat treatment temperature after bonding is low, moisture generated at the bonding interface due to the dehydration reaction cannot be effectively removed, so that the dehydration reaction does not proceed and it is difficult to sufficiently improve the bonding strength.

  On the other hand, when an oxide film containing chlorine atoms or the like is used as the oxide film 132, the oxide film 132 can absorb and diffuse moisture, and thus heat treatment after bonding is performed at a low temperature. However, the moisture generated at the bonding interface by the dehydration reaction can be absorbed and diffused into the oxide film 132 to efficiently promote the dehydration reaction. In this case, even when a substrate having low heat resistance such as glass is used as the base substrate 120, the bonding strength between the oxide film 132 and the insulating layer 121 can be sufficiently improved. Further, by performing a plasma treatment by applying a bias voltage, micropores are formed in the vicinity of the surface of the oxide film 132 to effectively absorb and diffuse moisture, and the oxide film 132 and the insulating layer 121 can be diffused even at a low temperature. It is possible to improve the bonding strength.

  Next, heat treatment is performed and separation at the embrittled region 104 is performed, so that the single crystal semiconductor layer 124 is provided over the base substrate 120 with the oxide film 132 and the insulating layer 121 interposed therebetween (see FIG. 2D).

  By performing the heat treatment, the added element is precipitated in the minute holes formed in the embrittled region 104 due to the temperature rise, and the internal pressure rises. The increase in pressure causes a change in volume in a minute hole in the embrittled region 104 and a crack occurs in the embrittled region 104, so that the single crystal semiconductor substrate 100 is cleaved along the embrittled region 104. Since the oxide film 132 is bonded to the base substrate 120, the single crystal semiconductor layer 124 separated from the single crystal semiconductor substrate 100 is formed over the base substrate 120. Note that the heat treatment temperature here is set so as not to exceed the strain point of the base substrate 120.

  As a heating means for the heat treatment, a heating furnace such as a diffusion furnace or a resistance heating furnace, an RTA (rapid thermal annealing) apparatus, a microwave heating apparatus, or the like can be used. For example, when an RTA apparatus is used, the heating can be performed at a heating temperature of 550 ° C. or more and 730 ° C. or less and a treatment time of 0.5 minutes or more and 60 minutes or less.

  Note that the heat treatment for increasing the bonding strength between the base substrate 120 and the oxide film 132 is not performed, and only the heat treatment in FIG. 2D is performed, so that the bonding strength between the oxide film 132 and the insulating layer 121 can be increased. The increase heat treatment step and the separation heat treatment step in the embrittled region 104 may be performed simultaneously.

  Through the above steps, an SOI substrate in which the single crystal semiconductor layer 124 is provided over the base substrate 120 with the oxide film 132 and the insulating layer 121 interposed therebetween can be manufactured.

  By using the bonding method described in this embodiment, even when the insulating layer 121 is used as a bonding layer, the bonding strength between the base substrate 120 and the single crystal semiconductor layer 124 can be improved and reliability can be improved. Can be improved. Even when a glass substrate is used as the base substrate 120, diffusion of impurities into the single crystal semiconductor layer 124 formed over the base substrate 120 is suppressed, and the base substrate 120 and the single crystal semiconductor layer 124 are used. Can be formed.

  In addition, an insulating film containing nitrogen is formed on the base substrate side, and an oxide film having a halogen such as chlorine is formed on the semiconductor substrate side, thereby simplifying the manufacturing process and before bonding to the base substrate. An impurity element can be prevented from entering the semiconductor substrate. In addition, by forming an oxide film containing halogen such as chlorine as a bonding layer provided on the semiconductor substrate side, even when heat treatment after bonding is performed at a low temperature, the dehydration reaction is efficiently promoted and the bonding strength is improved. Can be made.

  Note that the separated single crystal semiconductor substrate 100 can be reused in the manufacturing process of an SOI substrate as described in Embodiment Mode 1.

  Note that although the case where the oxide film 132 is formed over the single crystal semiconductor substrate 100 and the insulating layer 121 is formed over the base substrate 120 is described in this embodiment mode, the present invention is not limited to this structure. Absent. For example, the oxide film 132 and the insulating layer 121 (for example, an insulating film containing nitrogen) are sequentially stacked over the single crystal semiconductor substrate 100, and the surface of the insulating layer 121 formed over the oxide film 132 and the base substrate are formed. You may make it join the surface with 120. FIG. In this case, the insulating layer 121 may be provided before the embrittlement region 104 is formed or after the embrittlement region 104 is formed. Further, an oxide film (for example, a silicon oxide film) may be further formed over the insulating layer 121 formed over the oxide film 132, and the surface of the oxide film and the surface of the base substrate 120 may be bonded to each other. .

  Further, in the case where mixing of impurities from the base substrate 120 to the single crystal semiconductor layer 124 does not cause a problem, the insulating layer 121 is not provided over the base substrate 120 and the single crystal semiconductor layer 124 is provided over the single crystal semiconductor substrate 100. The surface of the oxide film 132 and the surface of the base substrate 120 can be directly bonded. In this case, since the step of providing the insulating layer 121 can be omitted, cost reduction can be achieved by reducing the number of processes.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing a semiconductor device using an SOI substrate will be described. More specifically, an example of a method for manufacturing an n-channel TFT and a p-channel TFT as a semiconductor device will be described. However, the present invention is not limited to the configuration described in this embodiment.

  In this embodiment, the case where an SOI substrate manufactured using the process of FIG. 2 is used as an SOI substrate will be described. Needless to say, an SOI substrate manufactured by another method described in the above embodiment mode can also be used.

  FIG. 4A is a cross-sectional view of an SOI substrate manufactured by the method described with reference to FIG.

  First, the single crystal semiconductor layer 124 is element-isolated by etching to form semiconductor layers 251 and 252 as shown in FIG. The semiconductor layer 251 constitutes an n-channel TFT, and the semiconductor layer 252 constitutes a p-channel TFT.

  Next, as illustrated in FIG. 4C, an insulating film 254 is formed over the semiconductor layers 251 and 252. Next, the gate electrode 255 is formed over the semiconductor layer 251 with the insulating film 254 interposed therebetween, and the gate electrode 256 is formed over the semiconductor layer 252. Here, the insulating film 254 functions as a gate insulating film.

  Note that an impurity element imparting a p-type such as boron, aluminum, or gallium, or an n-type such as phosphorus or arsenic is used to control the threshold voltage of the TFT before the single crystal semiconductor layer 124 is etched. An impurity element to be added is preferably added to the single crystal semiconductor layer 124. For example, an impurity element imparting p-type conductivity is added to a region where an n-channel TFT is formed, and an impurity element imparting n-type conductivity is added to a region where a p-channel TFT is formed.

  Next, as illustrated in FIG. 4D, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252.

  Specifically, the semiconductor layer 252 to be a p-channel TFT is masked with a resist. Then, an impurity element imparting n-type conductivity is added to the semiconductor layer 251 by an ion doping method or an ion implantation method using the gate electrode 255 as a mask, so that an n-type low-concentration impurity region 257 is formed in a self-aligning manner. Note that a region of the semiconductor layer 251 that overlaps with the gate electrode 255 is a channel formation region 258.

  Next, after the mask covering the semiconductor layer 252 is removed, the semiconductor layer 251 to be an n-channel TFT is masked with a resist. Then, an impurity element imparting p-type conductivity is added to the semiconductor layer 252 by an ion doping method or an ion implantation method using the gate electrode 256 as a mask, so that a p-type high-concentration impurity region 259 is formed in a self-aligning manner. Here, the p-type high concentration impurity region 259 functions as a source region or a drain region. In the semiconductor layer 252, a region overlapping with the gate electrode 256 is a channel formation region 260.

  Although the method of forming the p-type high-concentration impurity region 259 after forming the n-type low-concentration impurity region 257 has been described here, after the p-type high-concentration impurity region 259 is formed first, An n-type low concentration impurity region 257 can also be formed.

  Next, after removing the resist covering the semiconductor layer 251, an insulating film having a single-layer structure or a stacked structure using a nitrogen compound such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like.

  Next, the insulating film is anisotropically etched in a direction perpendicular to the surface of the SOI substrate, so that the side wall insulating film in contact with the side surfaces of the gate electrodes 255 and 256 is formed as shown in FIG. 261 and 262 are formed. By this anisotropic etching, the insulating film 254 is also etched.

  Next, as illustrated in FIG. 5B, the semiconductor layer 252 is masked with a resist 265. Then, an impurity element imparting n-type conductivity is added to the semiconductor layer 251 by an ion doping method or an ion implantation method using the gate electrode 255 and the sidewall insulating film 261 as a mask, and the n-type high-concentration impurity region 267 is self-aligned. Form. Here, the n-type high concentration impurity region 267 functions as a source region or a drain region.

  Next, heat treatment is performed to activate the impurity elements. Through the above steps, a semiconductor device including an n-channel TFT and a p-channel TFT can be manufactured. However, it is preferable to add the following steps as necessary.

  After this heat treatment, an insulating film 268 containing hydrogen is formed as illustrated in FIG. After the insulating film 268 is formed, heat treatment is performed at a temperature of 350 ° C. to 450 ° C., and hydrogen contained in the insulating film 268 is diffused into the semiconductor layers 251 and 252. As an example of a method for forming the insulating film 268, silicon nitride or silicon nitride oxide can be deposited by a plasma CVD method with a process temperature of 350 ° C. or lower. By supplying hydrogen to the semiconductor layers 251 and 252, defects that become trapping centers in the semiconductor layer 251 and the semiconductor layer 252 and at the interface between the semiconductor layer 251 and the semiconductor layer 252 and the insulating film 254 are formed. It can compensate effectively.

  Next, an interlayer insulating film 269 is formed so as to cover the insulating film 268. As an example of a material forming the interlayer insulating film 269, an insulating film made of an inorganic material such as a silicon oxide film or a BPSG (Boron Phosphorus Silicon Glass) film, or an organic resin film such as polyimide or acrylic can be used. The interlayer insulating film 269 may have a single layer structure or a stacked structure film.

  Next, after forming a contact hole in the interlayer insulating film 269, a wiring 270 is formed. The wiring 270 is electrically connected to the source region or the drain region. As an example of a method for forming the wiring 270, the wiring 270 can be formed using a conductive film having a three-layer structure in which a low-resistance metal film such as an aluminum film or an aluminum alloy film is sandwiched between barrier metal films. As the barrier metal film, molybdenum, chromium, titanium, or the like can be used.

  Although this embodiment mode describes a method for manufacturing a TFT as an example of a semiconductor device, a high-value-added semiconductor device can be manufactured by integrally forming semiconductor elements such as a capacitor and a resistor in addition to a TFT. it can.

(Embodiment 4)
In this embodiment, a microprocessor is described as an example of a semiconductor device. FIG. 6 is a block diagram illustrating a configuration example of the microprocessor 500. However, the present invention is not limited to the configuration described in this embodiment.

  The microprocessor 500 includes an arithmetic circuit 501 (also referred to as Arithmetic logic unit. ALU), an arithmetic circuit controller 502 (ALU Controller), an instruction analyzer 503 (Instruction Decoder), an interrupt controller 504 (Interrupt Controller), and a timing controller. 505 (Timing Controller), a register 506 (Register), a register controller 507 (Register Controller), a bus interface 508 (Bus I / F), a read-only memory 509, and a memory interface 510.

  An instruction input to the microprocessor 500 via the bus interface 508 is input to the instruction analysis unit 503 and decoded, and then to the arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505. Entered. The arithmetic circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instruction.

  The arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 is a circuit that processes an interrupt request from an external input / output device or a peripheral circuit while the microprocessor 500 is executing a program. And processing an interrupt request. The register control unit 507 generates an address of the register 506 and reads and writes the register 506 in accordance with the state of the microprocessor 500. The timing control unit 505 generates a signal that controls the operation timing of the arithmetic circuit 501, the arithmetic circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing control unit 505 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1. As shown in FIG. 6, the internal clock signal CLK2 is input to another circuit.

  Next, an example of a semiconductor device having a function of performing transmission / reception of data without contact and an arithmetic function will be described. FIG. 7 is a block diagram illustrating a configuration example of such a semiconductor device. The semiconductor device illustrated in FIG. 7 can be referred to as a computer that operates by transmitting and receiving signals to and from an external device by wireless communication (hereinafter referred to as “RFCPU”).

  As illustrated in FIG. 7, the RFCPU 511 includes an analog circuit unit 512 and a digital circuit unit 513. The analog circuit portion 512 includes a resonance circuit 514 having a resonance capacity, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, and a modulation circuit 520. The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, an interface 524, a central processing unit 525, a random access memory 526, and a read only memory 527.

  The outline of the operation of the RFCPU 511 is as follows. A signal received by the antenna 528 generates an induced electromotive force by the resonance circuit 514. The induced electromotive force is charged in the capacitor unit 529 through the rectifier circuit 515. Capacitance portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 529 does not need to be integrated on the substrate constituting the RFCPU 511, and can be incorporated into the RFCPU 511 as another component.

  The reset circuit 517 generates a signal that resets and initializes the digital circuit portion 513. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. The demodulation circuit 519 is a circuit that demodulates the received signal, and the modulation circuit 520 is a circuit that modulates data to be transmitted.

  For example, the demodulation circuit 519 is formed of a low-pass filter, and binarizes an amplitude modulation (ASK) reception signal based on the amplitude fluctuation. In addition, in order to transmit transmission data by changing the amplitude of an amplitude modulation (ASK) transmission signal, the modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514.

  The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

  A signal input from the antenna 528 to the RFCPU 511 is demodulated by the demodulation circuit 519 and then decomposed into a control command, data, and the like by the RF interface 521. The control command is stored in the control register 522. The control command includes reading of data stored in the read-only memory 527, writing of data to the random access memory 526, calculation instructions to the central processing unit 525, and the like.

  The central processing unit 525 accesses the read-only memory 527, the random access memory 526, and the control register 522 via the interface 524. The interface 524 has a function of generating an access signal for any of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525.

  As a calculation method of the central processing unit 525, a method in which an OS (operating system) is stored in the read-only memory 527 and a program is read and executed together with activation can be employed. Further, it is also possible to adopt a method in which an arithmetic circuit is configured by a dedicated circuit and arithmetic processing is processed in hardware. In the system using both hardware and software, a system in which a part of arithmetic processing is performed by a dedicated arithmetic circuit and the remaining arithmetic operations are processed by the central processing unit 525 using a program can be applied.

(Embodiment 5)
In this embodiment, an example of a method for manufacturing a display device using an SOI substrate will be described. However, the present invention is not limited to the configuration described in this embodiment.

  FIG. 8 is a diagram for explaining a liquid crystal display device. 8A is a plan view of a pixel of the liquid crystal display device, and FIG. 8B is a cross-sectional view of FIG. 8A taken along the line JK.

  As shown in FIG. 8A, the pixel includes a single crystal semiconductor layer 320, a scan line 322 intersecting with the single crystal semiconductor layer 320, a signal line 323 intersecting with the scan line 322, a pixel electrode 324, and a pixel. An electrode 328 that electrically connects the electrode 324 and the single crystal semiconductor layer 320 is provided. The single crystal semiconductor layer 320 is a layer formed from a single crystal semiconductor layer provided over the base substrate 120 and constitutes a pixel TFT 325.

  As the SOI substrate, the SOI substrate described in the above embodiment is used. As shown in FIG. 8B, a single crystal semiconductor layer 320 is stacked over the base substrate 120 with the oxide film 132 and the insulating layer 121 interposed therebetween. As the base substrate 120, a glass substrate can be used. The single crystal semiconductor layer 320 of the TFT 325 is a film formed by element isolation of the single crystal semiconductor layer of the SOI substrate by etching. In the single crystal semiconductor layer 320, a channel formation region 340 and an n-type high concentration impurity region 341 to which an impurity element is added are formed. The gate electrode of the TFT 325 is included in the scanning line 322, and one of the source electrode and the drain electrode is included in the signal line 323.

  A signal line 323, a pixel electrode 324, and an electrode 328 are provided over the interlayer insulating film 327. A columnar spacer 329 is formed on the interlayer insulating film 327. An alignment film 330 is formed to cover the signal line 323, the pixel electrode 324, the electrode 328, and the columnar spacer 329. The counter substrate 332 is provided with a counter electrode 333 and an alignment film 334 that covers the counter electrode. The columnar spacer 329 is formed to maintain a gap between the base substrate 120 and the counter substrate 332. A liquid crystal layer 335 is formed in a gap formed by the columnar spacers 329. At the connection portion between the signal line 323 and the electrode 328 and the high-concentration impurity region 341, a step is generated in the interlayer insulating film 327 due to the formation of the contact hole, so that the alignment of the liquid crystal in the liquid crystal layer 335 is easily disturbed at this connection portion. For this reason, columnar spacers 329 are formed at the step portions to prevent disorder of the alignment of the liquid crystal.

  Next, an electroluminescent display device (hereinafter referred to as an EL display device) will be described with reference to FIG. FIG. 9A is a plan view of a pixel of the EL display device, and FIG. 9B is a cross-sectional view of FIG. 9A taken along the line JK.

  As shown in FIG. 9A, the pixel includes a selection transistor 401 made of TFT, a display control transistor 402, a scanning line 405, a signal line 406, a current supply line 407, and a pixel electrode 408. Each pixel is provided with a light-emitting element having a structure in which a layer (EL layer) formed including an electroluminescent material is sandwiched between a pair of electrodes. One electrode of the light emitting element is a pixel electrode 408. In the semiconductor layer 403, a channel formation region, a source region, and a drain region of the selection transistor 401 are formed. In the semiconductor layer 404, a channel formation region, a source region, and a drain region of the display control transistor 402 are formed. The semiconductor layers 403 and 404 are layers formed from the single crystal semiconductor layer 124 provided over the base substrate.

  In the selection transistor 401, the gate electrode is included in the scanning line 405, one of the source electrode and the drain electrode is included in the signal line 406, and the other is formed as the electrode 410. In the display control transistor 402, the gate electrode 412 is electrically connected to the electrode 411, one of the source electrode and the drain electrode is formed as an electrode 413 electrically connected to the pixel electrode 408, and the other is supplied with current. Included in line 407.

  The display control transistor 402 is a p-channel TFT. As shown in FIG. 9B, a channel formation region 451 and a p-type high concentration impurity region 452 are formed in the semiconductor layer 404. Note that the SOI substrate manufactured in the embodiment is used as the SOI substrate.

  An interlayer insulating film 427 is formed to cover the gate electrode 412 of the display control transistor 402. On the interlayer insulating film 427, a signal line 406, a current supply line 407, electrodes 411, 413, and the like are formed. Further, a pixel electrode 408 that is electrically connected to the electrode 413 is formed over the interlayer insulating film 427. The peripheral portion of the pixel electrode 408 is surrounded by an insulating partition layer 428. An EL layer 429 is formed over the pixel electrode 408, and a counter electrode 430 is formed over the EL layer 429. A counter substrate 431 is provided as a reinforcing plate, and the counter substrate 431 is fixed to the base substrate 120 by a resin layer 432.

  There are two methods for controlling the gradation of an EL display device: a current driving method in which the luminance of a light-emitting element is controlled by current, and a voltage driving method in which the luminance is controlled by voltage. When the difference in values is large, it is difficult to adopt, and for this purpose, a correction circuit for correcting variation in characteristics is required. When an EL display is manufactured by a manufacturing method including a manufacturing process of an SOI substrate, the selection transistor 401 and the display control transistor 402 have no variation in characteristics from pixel to pixel, so that a current driving method can be employed.

(Embodiment 6)
In this embodiment, a specific example of an electronic device mounted with an SOI substrate will be described. However, the present invention is not limited to the configuration described in this embodiment.

  Electronic devices include video cameras, digital cameras, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.) , An image reproducing apparatus provided with a recording medium (specifically, reproducing audio data stored in a recording medium such as a DVD (digital versatile disc), a Blu-ray Disc), and storing the stored image data For example). An example of them is shown in FIG.

  10A and 10B illustrate an example of a mobile phone to which the present invention is applied. FIG. 10A is a front view, FIG. 10B is a rear view, and FIG. 10C is when two housings are slid. It is a front view. The cellular phone 700 is composed of two housings 701 and 702. The cellular phone 700 is a so-called smartphone that has both functions of a cellular phone and a portable information terminal, has a built-in computer, and can perform various data processing in addition to voice calls.

  A cellular phone 700 is composed of a housing 701 and a housing 702. The housing 701 includes a display portion 703, a speaker 704, a microphone 705, operation keys 706, a pointing device 707, a front camera lens 708, an external connection terminal jack 709, an earphone terminal 710, and the like. 711, an external memory slot 712, a rear camera 713, a light 714, and the like. The antenna is built in the housing 701.

  In addition to the above configuration, the mobile phone 700 may appropriately include a non-contact IC chip, a small recording device, an infrared communication function, a USB port, a TV one-seg reception function, an earphone jack, and the like. .

  The housings 701 and 702 (shown in FIG. 10A) which overlap with each other can be slid and developed as shown in FIG. 10C. In the display portion 703, a display panel or a display device to which the method for manufacturing the display device described in Embodiments 2 and 3 is applied can be incorporated. Since the cellular phone 700 includes the display portion 703 and the front camera lens 708 on the same surface, the cellular phone 700 can be used as a video phone. Further, the rear surface of the housing 702 (FIG. 10B) is provided with a rear camera 713 and a light 714, and a still image and a moving image can be taken by using the display portion 703 as a viewfinder.

  In addition, it is preferable to add a function as a touch panel to the display portion 703 because the user of the mobile phone 700 can operate with intuition. Since the cellular phone 700 can be operated intuitively, the elderly and children can be easily handled, so that it can be used by a wide range of age groups. Note that a structure in which a function as a touch panel is added to the display portion is not limited to a mobile phone, and can be applied to any electronic device having a display portion. For example, the present invention can be applied to a display unit of an image playback device including the above-described electronic device, such as a video camera, a digital camera, a navigation system, an audio playback device, a computer, a game device, a portable information terminal, and a recording medium.

  Note that as an example of a method for adding a function as a touch panel to the display portion 703, an element such as a photosensor is provided in a region where the pixel of the liquid crystal display device or the EL display device described in Embodiment 9 is provided. The method of forming is mentioned.

  These electronic devices described with reference to FIGS. 10A to 10C can be manufactured using the above-described method for manufacturing the transistor and the display device as appropriate.

FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. The figure which shows the surface roughness of a single-crystal semiconductor layer. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 11 is a block diagram illustrating an example of a semiconductor device using an SOI substrate. 4A and 4B are a top view and a cross-sectional view illustrating an example of a display device using an SOI substrate. 4A and 4B are a top view and a cross-sectional view illustrating an example of a display device using an SOI substrate. FIG. 14 is an external view illustrating an example of an electronic device on which an SOI substrate is mounted.

Explanation of symbols

100 Single crystal semiconductor substrate 102 Insulating layer 103 Ion 104 Embrittlement region 120 Base substrate 121 Insulating layer 124 Single crystal semiconductor layer 130 Laser beam 132 Oxide film

Claims (8)

Irradiating the single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate;
Bonding the single crystal semiconductor substrate and the base substrate through an insulating layer;
Separating the single crystal semiconductor substrate and the base substrate in the embrittled region, and forming a semiconductor layer on the base substrate through the insulating layer;
Irradiating the semiconductor layer with laser light to planarize the surface of the semiconductor layer,
In the step of planarizing the surface of the semiconductor layer, when the minimum irradiation energy density required for the semiconductor layer to be completely melted by the irradiation of the laser beam is 100%, the laser beam that irradiates the semiconductor layer A method for manufacturing an SOI substrate, wherein the irradiation energy density is set to 72% to 98%. Irradiating the single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate;
Forming an insulating layer on the base substrate;
Bonding the single crystal semiconductor substrate and the base substrate through the insulating layer;
Separating the single crystal semiconductor substrate and the base substrate in the embrittled region, and forming a semiconductor layer on the base substrate through the insulating layer;
Irradiating the semiconductor layer with laser light to planarize the surface of the semiconductor layer,
In the step of planarizing the surface of the semiconductor layer, when the minimum irradiation energy density required for the semiconductor layer to be completely melted by the irradiation of the laser beam is 100%, the laser beam that irradiates the semiconductor layer A method for manufacturing an SOI substrate, wherein the irradiation energy density is set to 72% to 98%. In claim 2,
A method for manufacturing an SOI substrate, wherein the insulating layer is formed using a plasma CVD apparatus that generates plasma by applying pulse-modulated power. In any one of Claims 1 thru | or 3,
A method for manufacturing an SOI substrate, comprising: planarizing a surface of the semiconductor layer; and heating the semiconductor layer at a temperature of 640 ° C. to a strain point of the base substrate. In any one of Claims 1 thru | or 4,
The laser beam is a linear pulsed laser beam, and when the semiconductor layer is irradiated with the linear pulsed laser beam, the linear pulsed laser beam is irradiated a plurality of times. Manufacturing method. In claim 5,
A method for manufacturing an SOI substrate, wherein the irradiation with the linear pulse laser light is performed a plurality of times so that an overlap rate is 100%. In any one of Claims 1 thru | or 6,
A method for manufacturing an SOI substrate, wherein a glass substrate is used as the base substrate. In any one of Claims 1 thru | or 7,
The method for manufacturing an SOI substrate, wherein the semiconductor layer is made of a single crystal.

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