JP2009225642A - Power supply apparatus and semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To significantly reduce switching loss during light load and enhance accuracy in output voltage. <P>SOLUTION: When a coil current IL becomes lower than 0A and a reverse current occurs during light load, a reverse current detection circuit 7 outputs a reverse current detection signal RCP_DET. A PFM control circuit 2 generates a PFM pulse when receiving the reverse current detection signal RCP_DET. When a Hi level period of PFM pulse signal generated by the PFM control circuit 2 becomes longer than a Hi level period of PWM signal, a logic circuit 3 outputs a PFM pulse signal. A pulse skip circuit of a logic circuit 3 outputs a skip signal and stops PWM signal output in a period when the PWM signal is not at Hi level after an output voltage VOUT rises and a voltage level of an error signal EAO of an error amplifier 8 falls below a voltage level of a triangular wave SLOPE. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for improving the efficiency of a power supply device, and more particularly to a technique effective for reducing loss caused by switching loss in a DC-DC converter.

  Some electronic devices use, for example, a PWM (Pulse Width Modulation) type DC-DC converter as a stabilized DC power source.

  As this type of DC-DC converter, one using a hysteresis comparator in order to stabilize the output voltage is known (for example, see Patent Document 1).

In this case, the output voltage of the DC-DC converter is monitored, the output voltage and the reference voltage are compared by a hysteresis comparator, and when the monitored output voltage reaches the lower limit threshold value, the switching element that generates the output voltage When the output voltage reaches the upper limit threshold value, the switching of the switching element is stopped.
Japanese Patent Laid-Open No. 06-303766

  However, the present inventors have found that the output voltage control technique in the DC-DC converter as described above has the following problems.

  That is, the control of the output voltage using the hysteresis comparator depends on the voltage accuracy of the hysteresis of the hysteresis comparator, and there is a problem that it is difficult to reduce the ripple of the output voltage.

  In addition, a detection delay due to the hysteresis comparator also occurs, and there is a problem that it is difficult to control the output voltage with high accuracy.

  An object of the present invention is to provide a technique capable of greatly reducing the switching loss at light load and improving the accuracy of the output voltage.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a power supply device that converts a DC power supply voltage into an arbitrary DC voltage, and detects a driver unit that performs switching and a reverse current that flows from the output side of the power supply device to the driver unit side based on a drive signal. A reverse current detection unit that outputs as a detection signal, a first drive signal generation unit that monitors an output voltage output from the power supply device and generates a PWM signal to be supplied to the driver unit according to the monitor signal, Based on a detection signal detected by the reverse current detection unit, a second drive signal generation unit that generates a PFM signal to be supplied to the driver unit, a PWM signal generated by the first drive signal generation unit, or a second drive A signal control unit that selects any one of the PFM signals generated by the signal generation unit and outputs the selected PFM signal as a drive signal to the driver unit. The signal control unit outputs a PFM signal from the second drive signal generation unit. The PWM signal generated by the first drive signal generation unit is output as the drive signal during the period when the PFM signal is output from the second drive signal generation unit during the period when the PFM signal is output as the drive signal. When the PWM signal output from the first drive signal generation unit is stopped during the period in which the PFM signal is output, the output of the PFM signal is stopped.

  In the present invention, the signal control unit outputs the PWM signal generated by the first drive signal generation unit when the PFM signal is not output from the second drive signal generation unit, and the second drive signal generation unit outputs the PWM signal. When the PFM signal is output from the signal generation unit, the signal selection unit that outputs the PFM signal and the PWM signal output from the first drive signal generation unit are detected to be stopped, and a state detection signal is output. And an output control unit that stops the output of any drive signal of the PWM signal and the PFM signal during the period when the state detection unit outputs the state detection signal.

  Furthermore, according to the present invention, the power supply device includes a DC-DC converter.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention relates to a semiconductor integrated circuit device used in a power supply device that converts a DC power supply voltage into an arbitrary DC voltage, a driver unit that performs switching based on a drive signal, and a driver unit from the output side of the power supply device A reverse current detection unit that detects a reverse current flowing in the direction and outputs it as a detection signal; monitors an output voltage output from the power supply device; and generates a PWM signal to be supplied to the driver unit according to the monitor signal Drive signal generation unit, a second drive signal generation unit that generates a PFM signal to be supplied to the driver unit based on a detection signal detected by the reverse current detection unit, and a PWM generated by the first drive signal generation unit A signal control unit that selects either the signal or the PFM signal generated by the second drive signal generation unit and outputs the selected signal to the driver unit as a drive signal, and the signal control unit includes the second drive During the period when the PFM signal is not output from the signal generator, the PWM signal generated by the first drive signal generator is output as the drive signal, and during the period when the PFM signal is output from the second drive signal generator, The PFM signal is output as a drive signal. When the PWM signal output from the first drive signal generation unit is stopped during the period in which the PFM signal is output, the output of the PFM signal is stopped.

  In the present invention, the signal control unit outputs the PWM signal generated by the first drive signal generation unit when the PFM signal is not output from the second drive signal generation unit, and the second drive signal generation unit outputs the PWM signal. When the PFM signal is output from the signal generation unit, the signal selection unit that outputs the PFM signal and the PWM signal output from the first drive signal generation unit are detected to be stopped, and a state detection signal is output. And an output control unit that stops the output of any drive signal of the PWM signal and the PFM signal during the period when the state detection unit outputs the state detection signal.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The power conversion efficiency of the power supply device can be greatly improved.

  (2) Further, it is possible to generate a power supply voltage with low ripple and high voltage accuracy.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is an explanatory diagram illustrating a configuration example of a power supply device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram illustrating a configuration example of a logic circuit provided in the power supply device of FIG. 1, and FIG. 4 is a circuit diagram showing a configuration example of a PFM control circuit provided in one power supply apparatus, FIG. 4 is a timing chart of signals in each part of the power supply apparatus in FIG. 1, and FIG. 5 is a signal timing in the PFM control circuit in FIG. It is a chart.

  In the present embodiment, the power supply device 1 is composed of, for example, a DC-DC converter, and supplies a stable power supply to a semiconductor integrated circuit device or the like.

  As shown in FIG. 1, the power supply device 1 includes a PFM (Pulse Frequency Modulation) control circuit 2, a logic circuit 3, a driver 4, transistors 5 and 6, a backflow detection circuit 7, an error amplifier 8, a comparator 9, and a reference voltage circuit 10. , A triangular wave generator 11, a smoothing coil 12, a smoothing capacitor 13, and resistors 14 and 15.

  The PFM control circuit 2, logic circuit 3, driver 4, transistors 5 and 6, backflow detection circuit 7, error amplifier 8, comparator 9, reference voltage circuit 10, and triangular wave generator 11 are, for example, a semiconductor integrated circuit device. The smoothing coil 12, the smoothing capacitor 13, and the resistors 14 and 15 are circuits provided outside the semiconductor integrated circuit device.

  The PFM control circuit 2 serving as the second drive signal generation unit outputs a PFM pulse signal that controls the duty based on the backflow detection signal RCP_DET output from the backflow detection circuit 7 serving as the backflow current detection unit. The logic circuit 3 that is a signal control unit generates and outputs a PWM signal based on the comparison signal COMPOUT output from the backflow detection circuit 7 and the comparator 9, and the backflow detection circuit 7 detects the backflow current. In addition, a signal for forcibly turning off the transistors 5 and 6 constituting the driver section is output.

  The driver 4 drives the transistors 5 and 6 based on the PWM signal PWM_OUT output from the logic circuit 3. The transistors 5 and 6 are formed of a P-channel MOS (Metal Oxide Semiconductor) -FET (Field Effect Transistor).

  The power supply voltage VCC is connected to one connection portion of the transistor 5, and one connection portion of the transistor 5 is connected to the other connection portion of the transistor 5. A reference potential VSS is connected to the other connection portion of the transistor 6.

  The backflow detection circuit 7 detects a backflow current flowing from the output side of the power supply device 1 to the power supply voltage VCC or the reference potential VSS at a light load such as a standby state, and outputs a backflow detection signal RCP_DET. The backflow detection circuit 7 is composed of, for example, a comparator, and a connection portion between the transistor 5 and the transistor 6 is connected to a positive (+) side input terminal of the comparator.

  A feedback voltage VFB is connected to one input part of the error amplifier 8 constituting the first drive signal generation part, and the first drive signal generation part is connected to the other input part. The reference voltage VREF generated by the reference voltage circuit 10 is connected so as to be input.

  The error amplifier 8 amplifies an error between the feedback voltage VFB and the reference voltage VREF, and outputs it to the comparator 9 as an error signal EAO. The error signal EAO output from the error amplifier 8 is input to one input unit of the comparator 9 constituting the first drive signal generation unit, and the first input unit of the comparator 9 is connected to the first input unit. A triangular wave SLOPE generated by the triangular wave generator 11 constituting the drive signal generation unit is input.

  The comparator 9 compares the error signal EAO and the triangular wave SLOPE to generate a PWM signal having an arbitrary duty and outputs it as a comparison signal COMPOUT. One connection portion of the smoothing coil 12 is connected to a connection portion between the transistor 5 and the transistor 6, and the other connection portion of the smoothing coil 12 is connected to one connection portion of the smoothing capacitor 13, And one connection part of the resistor 14 is connected.

  One connection portion of the resistor 15 is connected to the other connection portion of the resistor 14. The reference potential VSS is connected to the other connection portion of the resistor 15 and the other connection portion of the smoothing capacitor 13.

  The voltage divided by the resistors 14 and 15 is input to the error amplifier 8 as a monitor voltage (feedback voltage VFB) of the output voltage VOUT of the power supply device 1.

  FIG. 2 is an explanatory diagram illustrating a configuration example of the logic circuit 3.

  The logic circuit 3 includes a latch 16, an OR circuit 17, an AND circuit 18, and a pulse skip circuit 19. A clock signal PWM_SET that is a clock signal generated based on a reference clock signal input to the logic circuit 3 is input to the control terminal of the latch 16.

  A comparison signal COMPOUT output from the comparator 9 is connected to an input portion of the latch 16 so as to be input. A PFM pulse signal output from the PFM control circuit 2 is connected to one input section of the OR circuit 17 that is a signal selection section, and the other connection section of the OR circuit 17 is connected to the other input section. Are connected to the output of the latch 16 and the input of the pulse skip circuit 19, respectively.

  One input part of an AND circuit 18 serving as an output control unit is connected to the output part of the OR circuit 17, and the other input part of the AND circuit 18 is connected to the output part of the pulse skip circuit 19. Is connected. The logical sum circuit 17 calculates the logical sum of the PWM signal output from the latch 16 and the PFM pulse signal, and performs switching with a pulse having a high duty.

  The pulse skip circuit 19 that is a state detection unit outputs a skip signal P_SKIP that is a state control signal based on the state of the PWM signal. When the PWM signal output from the latch 16 does not switch, the pulse skip circuit 19 outputs a Lo level skip signal P_SKIP and stops the output of the AND circuit 18. A signal output from the output unit of the AND circuit 18 is output to the driver 4 as a PWM signal PWM_OUT.

  FIG. 3 is a circuit diagram showing a configuration example of the PFM control circuit 2.

  The PFM control circuit 2 includes an inverter 20, constant current sources 21 and 22, transistors 23 and 24, a switch unit 25, a capacitor 26, and a comparator 27.

  The backflow detection signal RCP_DET output from the backflow detection circuit 7 is connected to the input portion of the inverter 20 so as to be input. The gates of the transistors 23 and 24 are connected to the output portion of the inverter 20.

  The transistor 23 is composed of a P-channel MOS, and the transistor 24 is composed of an N-channel MOS. The power supply voltage VCC is connected to one connection portion of the transistor 23 via the constant current source 21, and one connection portion of the transistor 24 is connected to the other connection portion of the transistor 23.

  A reference potential VSS is connected to the other connection portion of the transistor 24 via a constant current source 22, and an inverter is configured by these transistors 23 and 24.

  The connection portion between the transistor 23 and the transistor 24 is connected to the input portion of the switch portion 25. The output portion of the switch portion 25 is connected to the positive (+) side input terminal of the comparator 27 and one of the capacitors 26. Are connected to each other.

  A switch signal SW, which is a clock signal generated based on a reference clock signal input to the logic circuit 3, is connected to a control terminal of the switch unit 25.

  The negative (−) side input terminal of the comparator 27 is connected so that the triangular wave SLOPE generated by the triangular wave generator 11 is input. The reference potential VSS is connected to the other connection portion of the capacitor 26.

  Next, the operation in the power supply device 1 according to the present embodiment will be described.

  FIG. 4 is a timing chart of signals in each part of the power supply device 1. In FIG. 4, from the upper side to the lower side, the output voltage VOUT output from the power supply device 1, the output current Iout output from the power supply device 1, the coil current IL flowing through the smoothing coil 12, and the backflow detection circuit 7 output. Backflow detection signal RCP_DET, error signal EAO output from error amplifier 8, triangular wave SLOPE output from triangular wave generator 11, comparison signal COMPOUT output from comparator 9, clock signal PWM_SET input to the control terminal of latch 16, The PWM signal output from the latch 16, the skip signal P_SKIP output from the pulse skip circuit 19, the PFM pulse signal output from the PFM control circuit 2, and the signal timing of the PWM signal PWM_OUT output from the logic circuit 3 are shown respectively. Yes.

  First, during normal operation (at the time of heavy load), the power supply device 1 is operated by a PWM signal, and the signal rising timing of the PWM signal PWM_OUT output from the logic circuit 3 is input to the control terminal of the latch 16. The timing of the falling edge of the PWM signal PWM_OUT is determined by the rising edge of the comparison signal COMPOUT of the comparator 9.

  During the operation period of the PWM signal during the normal operation, the coil current IL does not flow back, so the backflow detection signal RCP_DET of the backflow detection circuit 7 is at the Lo level.

  Subsequently, when the load becomes a light load such as a standby time, the power supply device 1 shifts to a mode in which it operates by a PFM signal. After the transition from the heavy load to the light load, when the coil current IL is at a lower limit level than 0 A, that is, when a reverse current is generated, the reverse flow detection circuit 7 outputs a high-level reverse flow detection signal RCP_DET.

  When the Hi-level backflow detection signal RCP_DET is input, the PFM control circuit 2 generates a PFM pulse signal and outputs it to the logic circuit 3. When the Hi level period of the PFM pulse signal generated by the PFM control circuit 2 becomes longer than the Hi period of the PWM signal, the OR circuit 17 outputs the PFM pulse signal to the AND circuit 18, and the PWM circuit 18 outputs the PWM signal. A PFM pulse signal is output as the signal PWM_OUT.

  Further, when the load is light, the output voltage VOUT increases, and accordingly, the voltage level of the error signal EAO of the error amplifier 8 decreases, and the voltage level of the error signal EAO becomes lower than the voltage level of the triangular wave SLOPE. A period in which the PWM signal does not become Hi level occurs.

  When a period in which the PWM signal does not become Hi level occurs, the pulse skip circuit 19 outputs a Lo level skip signal P_SKIP. As a result, during the period in which the Lo level skip signal P_SKIP is output, the output of the PWM signal PWM_OUT is stopped and the PFM pulse signal is skipped.

  Next, the operation in the PFM control circuit 2 will be described using the timing chart of FIG.

  In FIG. 5, from the top to the bottom, the coil current IL flowing through the smoothing coil 12, the backflow detection signal RCP_DET output from the backflow detection circuit 7, the switch signal SW input to the control terminal of the switch unit 25, and the triangular wave generator The triangular wave SLOPE output from 11 and the signal timing of the PFM pulse signal output from the PFM control circuit 2 are shown.

  First, when the reverse current detection circuit 7 detects a reverse current and outputs a high level reverse current detection signal RCP_DET, the transistor 23 is turned on, and the capacitor 26 is charged during the period when the switch signal SW is high level.

  As a result, the reference voltage input to the positive (+) input terminal of the comparator 27 increases, and the duty of the PFM pulse signal output from the comparator 27 increases. Further, since the reverse current detection signal RCP_DET is at the Lo level during the period when the reverse current is not detected by the reverse current detection circuit 7, the transistor 24 is turned on, and the capacitor 26 is charged while the switch signal SW is at the Hi level. The electric charge is discharged, the reference voltage input to the positive (+) input terminal of the comparator 27 is lowered, and accordingly, the duty of the PFM pulse signal is reduced.

  Thereby, according to the present embodiment, the PFM pulse signal can be skipped at a light load, so that the switching loss of the transistors 5 and 6 can be reduced and the power conversion efficiency can be improved.

  Further, since the PFM pulse signal is skipped based on the error signal EAO of the error amplifier 8 with quick response, it is possible to generate a power supply voltage with low ripple and high voltage accuracy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Although the case where the present invention is applied to a step-down DC-DC converter has been described in the above embodiment, the present invention can generate a highly accurate power supply voltage even when applied to a step-up DC-DC converter. it can.

  The present invention is suitable for a power supply device such as a DC-DC converter that supplies a stabilized power supply to an electronic device.

It is explanatory drawing which shows the structural example of the power supply device by one embodiment of this invention. FIG. 2 is an explanatory diagram illustrating a configuration example of a logic circuit provided in the power supply device of FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a PFM control circuit provided in the power supply device of FIG. 1. 2 is a signal timing chart in each part of the power supply device of FIG. 1. 4 is a timing chart of signals in the PFM control circuit of FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply device 2 PFM control circuit 3 Logic circuit 4 Driver 5, 6 Transistor 7 Backflow detection circuit 8 Error amplifier 9 Comparator 10 Reference voltage circuit 11 Triangular wave generator 12 Smoothing coil 13 Smoothing capacitor 14, 15 Resistor 16 Latch 17 Logical sum Circuit 18 AND circuit 19 Pulse skip circuit 20 Inverters 21 and 22 Constant current sources 23 and 24 Transistor 25 Switch unit 26 Capacitor 27 Comparator

Claims (5)

A power supply device that converts a DC power supply voltage into an arbitrary DC voltage,
A driver unit that performs switching based on the drive signal;
A reverse current detection unit that detects a reverse current flowing from the output side of the power supply device to the driver unit side and outputs it as a detection signal;
A first drive signal generation unit that monitors an output voltage output from the power supply device and generates a PWM signal to be supplied to the driver unit in accordance with the monitor signal;
A second drive signal generation unit that generates a PFM signal to be supplied to the driver unit based on a detection signal detected by the reverse current detection unit;
A signal control unit that selects either the PWM signal generated by the first drive signal generation unit or the PFM signal generated by the second drive signal generation unit and outputs the selected signal to the driver unit as a drive signal; ,
The signal controller is
During a period when no PFM signal is output from the second drive signal generation unit, the PWM signal generated by the first drive signal generation unit is output as a drive signal, and the PFM signal is output from the second drive signal generation unit. Is output as a drive signal during the period when is output,
The power supply apparatus according to claim 1, wherein the output of the PFM signal is stopped when the PWM signal output from the first drive signal generation unit is stopped during the period in which the PFM signal is output. The power supply device according to claim 1, wherein
The signal controller is
When no PFM signal is output from the second drive signal generator, the PWM signal generated by the first drive signal generator is output, and the PFM signal is output from the second drive signal generator. A signal selector that outputs a PFM signal when
A state detection unit that detects that the PWM signal output from the first drive signal generation unit is in a stopped state and outputs a state detection signal;
A power supply apparatus comprising: an output control unit that stops output of any of the PWM signal and the PFM signal during a period in which the state detection unit outputs a state detection signal. The power supply device according to claim 1 or 2,
The power supply device
A power supply device that is a DC-DC converter. A semiconductor integrated circuit device used in a power supply device that converts a DC power supply voltage into an arbitrary DC voltage,
A driver unit that performs switching based on the drive signal;
A reverse current detection unit that detects a reverse current flowing from the output side of the power supply device to the driver unit side and outputs it as a detection signal;
A first drive signal generation unit that monitors an output voltage output from the power supply device and generates a PWM signal to be supplied to the driver unit in accordance with the monitor signal;
A second drive signal generation unit that generates a PFM signal to be supplied to the driver unit based on a detection signal detected by the reverse current detection unit;
A signal control unit that selects either the PWM signal generated by the first drive signal generation unit or the PFM signal generated by the second drive signal generation unit and outputs the selected signal to the driver unit as a drive signal; ,
The signal controller is
During a period when no PFM signal is output from the second drive signal generation unit, the PWM signal generated by the first drive signal generation unit is output as a drive signal, and the PFM signal is output from the second drive signal generation unit. Is output as a drive signal during the period when is output,
In the period during which the PFM signal is output, the output of the PFM signal is stopped when the PWM signal output from the first drive signal generator is stopped. The semiconductor integrated circuit device according to claim 4.
The signal controller is
When no PFM signal is output from the second drive signal generator, the PWM signal generated by the first drive signal generator is output, and the PFM signal is output from the second drive signal generator. A signal selector that outputs a PFM signal when
A state detection unit that detects that the PWM signal output from the first drive signal generation unit is in a stopped state and outputs a state detection signal;
A semiconductor integrated circuit device comprising: an output control unit that stops output of any drive signal of the PWM signal and the PFM signal during a period in which the state detection unit outputs a state detection signal.

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