JP2009170672A - Light source, light emitting device, and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light source etc., capable of suppressing variations in light quantity caused among a plurality of light emitting elements when the plurality of light emitting elements are connected in parallel. <P>SOLUTION: The light source according to the invention is constituted by electrically connecting the plurality of LED chips 10 in parallel. Each of the plurality of LED chips 10 has a substrate 11, a seed layer 12, an n-type semiconductor layer 14, a light emitting layer 15, and a p-type semiconductor layer 16. Further, the n-type semiconductor layer 14 includes a base layer 14a laminated directly on the seed layer 12. The seed layer 12 is a group III nitride compound semiconductor, has its film thickness set to 21 to 40 nm, and is deposited by a sputtering method. Further, the base layer 14a is a group III nitride compound semiconductor having ≤100 arcsec rocking curve half-value width on a (0002) plane and ≤250 arcsec rocking curve half-value width on a (10-10) plane. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a light source, a light emitting device, and a display device.

  In recent years, various light-emitting devices using light-emitting elements such as light-emitting diodes (LEDs) have been put into practical use. Such light emitting devices are widely used as lighting devices, backlights for liquid crystal panels, and the like. In addition, for example, in a liquid crystal television or the like, an increase in the amount of light of a light source in a backlight or the like is required as the screen size increases. In response to such a demand, it is conceivable to use a large-sized light emitting element or increase the number of light emitting elements as an aspect of increasing the light amount of a light source such as a backlight using the light emitting element.

  The amount of light emitted from the light emitting element increases as the size of the element increases. In general, a light emitting element of a large size has low light emission efficiency. That is, in the case of a large-sized light emitting element, the area of the electrode pad provided in the light emitting element must be increased in order to allow a current to flow uniformly through the light emitting element. At this time, since the electrode pad itself has a characteristic of absorbing light emitted from the light emitting element, the amount of light absorbed by the electrode pad increases as the area of the electrode pad increases.

  On the other hand, when the number of light-emitting elements is increased, for example, in order to obtain a light emission amount equivalent to that of a large-sized light-emitting element, it is necessary to provide a larger number of light-emitting elements than a large-sized light-emitting element. In this case, for example, the cost of mounting the light emitting element on the substrate to be mounted increases, leading to an increase in product cost.

  On the other hand, as a measure for reducing the number of light emitting elements mounted on a substrate to be mounted, it is conceivable to package a plurality of light emitting elements together. At this time, a method of electrically connecting a plurality of light emitting elements in one package or connecting them in series is conceivable. Here, when the series connection method is used, it is necessary to increase the driving voltage of one package as compared with the parallel connection method, and the driving voltage of a light emitting device including a plurality of packages is also high. turn into.

On the other hand, as a conventional technique described in the publication about a method of connecting a plurality of light emitting elements in parallel, a technique is disclosed in which a light source in which a plurality of light emitting elements are electrically connected in parallel is used in, for example, the above backlight device. (For example, refer to Patent Document 1).
Furthermore, a technique is also disclosed in which when a plurality of light emitting elements are connected in parallel to electricity, the light emitting elements are selected and used in advance so that the variation in forward voltage of the plurality of light emitting elements is within 0.1V. (For example, refer to Patent Document 2).

JP 2007-134722 A Japanese Patent Laid-Open No. 2006-222412

  By the way, when a plurality of light emitting elements having variations in electrical characteristics such as resistance value are electrically connected in parallel, the light emitting element having the smallest resistance value among these light emitting elements is compared with other light emitting elements. A lot of current will flow. Since the light amount of the light emitting element is generally proportional to the current, the light amount may vary between the plurality of light emitting elements due to the variation in the amount of current flowing between the plurality of light emitting elements connected in parallel. Furthermore, since the load is concentrated on the light emitting element having the smallest resistance value, there is a high possibility that the lifetime of the light emitting element will be remarkably shortened, and there is a concern that the reliability as a light source may be reduced.

  The present invention has been made to solve the technical problems as described above, and an object of the present invention is to provide a light amount generated between a plurality of light emitting elements in a light source in which a plurality of light emitting elements are connected in parallel. It is an object to provide a light source or the like that can suppress variations in the above.

  For this purpose, a light source to which the present invention is applied includes a plurality of light emitting elements and parallel connection means for electrically connecting the plurality of light emitting elements in parallel, and each light emitting element constituting the plurality of light emitting elements. Is composed of an element substrate, a first layer made of a group III nitride compound semiconductor and laminated directly on the element substrate, and laminated directly on the first layer, and the rocking curve half-width of the (0002) plane is And a second layer made of a group III nitride compound semiconductor having a rocking curve half-value width of 100 arcsec or less and a (10-10) plane of 250 arcsec or less.

  Here, the second layer is a group III nitride compound semiconductor having a rocking curve half width of (0002) plane of 60 arcsec or less and a rocking curve half width of (10-10) plane of 250 arcsec or less. Then, it is preferable from the point which can suppress further dispersion | variation in resistance value etc. of the some light emitting element connected in parallel electrically.

In such a light source, the parallel connection means may be a mounted body in which a plurality of light emitting elements are attached and a power supply path for supplying power to the plurality of light emitting elements is formed.
In such a light source, the first layer can be characterized by having a layer thickness of 21 nm or more and 40 nm or less. In this case, the first layer is formed by sputtering. Furthermore, the element substrate may be a sapphire substrate, the first layer may be AlN, and the second layer may be GaN.

  Furthermore, in such a light source, a plurality of other light emitting elements different from the plurality of light emitting elements, another parallel connection means for electrically connecting the other plurality of light emitting elements in parallel, a parallel connection means and another Connection means for electrically connecting the parallel connection means may further be provided.

When the present invention is regarded as a light-emitting device, a plurality of light-emitting elements each including a plurality of light-emitting elements and a first power supply path that electrically connects the plurality of light-emitting elements in parallel, Each of the light-emitting elements constituting the plurality of light-emitting elements includes: an element substrate; and a mounting substrate provided with a second power-feed path electrically connected to the first power-feed path provided in the light-emitting body. A first layer made of a group III nitride compound semiconductor and directly laminated on the element substrate, and laminated directly on the first layer, and a (0002) plane rocking curve half-width is 100 arcsec or less ( And a second layer made of a group III nitride compound semiconductor having a rocking curve half-width of 10-10) plane of 250 arcsec or less.
At this time, it is preferable that the plurality of light emitters be arranged at equal intervals on the mounting substrate in terms of suppressing light amount unevenness as the whole light emitting device.

  Further, when the present invention is regarded as a display device, the display device includes a display panel that displays an image, and a backlight that is provided on the back surface of the display panel and that irradiates light on the display panel. And a first power supply path provided in each of the light emitters, each of which has a plurality of light emitters attached thereto, and a first power supply path that electrically connects the plurality of light emitting elements in parallel. Each of the light-emitting elements constituting the plurality of light-emitting elements is composed of an element substrate and a group III nitride compound semiconductor. A first layer directly stacked on the first layer, and a first layer stacked directly on the first layer, the rocking curve half width of the (0002) plane is 100 arcsec or less, and the rocking curve half width of the (10-10) plane is 250 arcs. And a second layer made of a Group III nitride compound semiconductor is c or less.

  In such a display device, two or more light emitters constituting a plurality of light emitters are electrically connected to each other to form a plurality of light emitter groups, and each of the plurality of connection conductors constituting the plurality of connection conductors. And a plurality of power supplies for supplying power to the connection conductor.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the light source etc. which suppressed the dispersion | variation in the light quantity which arises between several light emitting elements when several light emitting elements are electrically connected in parallel.

The best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below in detail with reference to the accompanying drawings.
<Embodiment 1>
FIG. 1 is a diagram showing an overall configuration of a liquid crystal display device to which the present embodiment is applied. In FIG. 1, the vertical direction V and the horizontal direction H of the liquid crystal display device are indicated by arrows.

The liquid crystal display device includes a liquid crystal display module 50 and a backlight device (backlight) 40 provided on the back side (lower side in FIG. 1) of the liquid crystal display module 50.
The backlight device 40 that functions as a light emitting device includes a backlight frame 41 that houses a light source, and a light emitting unit 42 in which a plurality of light emitting diodes (referred to as LEDs in the following description) are arranged. Further, the backlight device 40 is made of a resin having a light-transmitting property with respect to visible light as a laminated body of optical films, and a diffusion plate 43 (scattering and diffusing light in order to make the entire surface uniform brightness) Plate or film) and prism sheets 44 and 45, which are diffraction grating films having a light condensing effect forward. Further, if necessary, a diffusion / reflection type luminance enhancement film 46 for improving the luminance is provided.

  On the other hand, the liquid crystal display module 50 is laminated on each glass substrate of the liquid crystal panel 51, which is configured by sandwiching liquid crystal between two glass substrates, and restricts vibration of light waves in a certain direction. Polarizing plates 52 and 53. Further, peripheral members such as a driving LSI (not shown) are also attached to the liquid crystal display device.

The liquid crystal panel 51 as one of the display panels includes various components not shown. For example, two glass substrates are provided with a display electrode (not shown), an active element such as a thin film transistor (TFT), a liquid crystal, a spacer, a sealant, an alignment film, a common electrode, a protective film, a color filter, and the like. .
Note that the structural unit of the backlight device 40 is arbitrarily selected. For example, a unit of only the backlight frame 41 having the light emitting unit 42 is referred to as a “backlight device (backlight)”, and there may be a distribution form that does not include the diffusion plate 43, the prism sheets 44 and 45, and the brightness enhancement film 46. .

FIG. 2 is a view for explaining the configuration of the backlight frame 41 and the light emitting unit 42 in the backlight device 40 as the light emitting device. The backlight device 40 is on the liquid crystal display module 50 side (upper surface side) shown in FIG. It is the figure seen from.
The backlight frame 41 forms a housing structure made of, for example, aluminum, magnesium, iron, or a metal alloy containing them. And the polyester film etc. which have the performance of white high reflection, for example are affixed inside the housing | casing structure, and it functions also as a reflector. The casing structure includes a back surface portion corresponding to the size of the liquid crystal display module 50 and side surface portions surrounding the four corners of the back surface portion. In addition, a heat sink structure including cooling fins for exhaust heat may be formed on the back surface portion and the side surface portion as necessary. In addition, a connector (not shown) for supplying power to a plurality of LED packages 20 (described later) constituting the light emitting unit 42 is provided on the back surface of the backlight frame 41.

  The light emitting unit 42 includes eight light emitting modules 30. The eight light emitting modules 30 are arranged in two rows in the vertical direction V and four rows in the horizontal direction H on the back surface of the backlight frame 41.

  FIG. 3 is a diagram for explaining the light emitting module 30. 3A is a top view of the light emitting module 30, and FIG. 3B is a side view of the light emitting module 30 as viewed from the direction of arrow A shown in FIG. 3A. FIG. 3B also shows a partial cross-sectional view of the LED package 20.

The light emitting module 30 includes a plurality (120 in this example) of LED packages 20 and a module substrate 31 as an attachment substrate.
The LED package 20 that functions as a light source and a light emitter includes a plurality of LED chips 10 (described later), and emits white light. The plurality of LED packages 20 are arranged on the module substrate 31 in 12 rows in the vertical direction V and 10 rows in the horizontal direction H as shown in FIG. Further, in the light emitting module 30 to which the present embodiment is applied, the plurality of LED packages 20 arranged on the module substrate 31 have substantially equal intervals between the LED packages 20 adjacent to each other in the vertical direction V (in this example, The distance between the LED packages 20 adjacent to each other in the horizontal direction H is also set to be substantially equal (in this example, about 1 inch). Therefore, 120 LED packages 20 are arranged in a substantially lattice pattern on the module substrate 31. The plurality of LED packages 20 need only be arranged at substantially equal intervals on the module substrate 31. For example, the three adjacent LED packages 20 may be arranged so as to form a substantially equilateral triangle. .

Further, in one light emitting module 30, the distance from the outermost LED package 20 to the end of the module substrate 31 is designed to be shorter than 1/2 inch. By setting in this way, as shown in FIG. 2, when the eight light emitting modules 30 are attached to the backlight frame 41, the intervals in the vertical direction V and the horizontal direction H between the adjacent LED packages 20 can be set. It is possible to arrange them equally (about 1 inch in this example).
Actually, in the light emitting unit 42 to which the present embodiment is applied, 960 (120 × 8) LED packages 20 have substantially equal intervals in the vertical direction V and the horizontal direction H between adjacent LED packages 20. Arranged on the backlight frame 41 in a substantially lattice pattern.

As described above, the module substrate 31 has a plurality of LED packages 20 attached thereto. As the base material of the module substrate 31, for example, a so-called glass epoxy in which a glass fiber is impregnated with an epoxy resin can be used. Further, as shown in FIG. 3B, an electrical wiring pattern 32 for supplying power to the LED package 20 is formed on the surface of the module substrate 31 on which the LED package 20 is attached (hereinafter referred to as an attachment surface). The The electrical wiring pattern 32 and the LED package 20 are electrically connected by solder or the like on the mounting surface of the module substrate 31.
A white resist is formed on the mounting surface of the module substrate 31 so as to reflect the light emitted from the LED package 20.

  As shown in FIGS. 3A and 3B, the module substrate 31 is provided with a screw hole 36 b for attaching the light emitting module 30 to the backlight frame 41. Then, the module substrate 31 is fixed to the backlight frame 41 at the screw hole 36b using screws 36a and the like.

In one light emitting module 30, a light emitting block 300 as a unit of light emission control is formed as shown by a broken line in FIG. The light emitting block 300 as the light emitting body group has a total of 12 LED packages 20 with 6 rows in the vertical direction V and 2 rows in the horizontal direction H. The light emitting module 30 is provided with a total of 10 blocks of the light emitting blocks 300 in two rows in the vertical direction V and five rows in the horizontal direction H.
In the present embodiment, the electrical wiring pattern 32 provided on the module substrate 31 functions as a second power supply path and a connection conductor.

FIG. 4 is a diagram for explaining the LED package 20. 4A is a top view (light emitting surface side) of the LED package 20, and FIG. 4B is a cross-sectional view taken along line IV-IV shown in FIG. 4A.
The LED package 20 emits white light having three primary colors of red (R), green (G), and blue (B). 4A, the LED package 20 includes three LED chips 10, a positive lead frame 291 and a negative lead frame 292, and a case 293 that functions as a mounting body.
Each LED chip 10 is a blue LED that emits blue light. In the present embodiment, the size of the LED chip 10 is 350 μm square, and the thickness thereof is 80 μm. In the LED package 20, the three LED chips 10 are electrically connected in parallel. The structure of the LED chip 10 will be described in detail later.

As shown in FIG. 4A, the positive lead frame 291 and the negative lead frame 292 are produced by punching a metal plate into an E shape. Then, as shown in FIG. 4B, the positional relationship between the positive lead frame 291 and the negative lead frame 292 is fixed by a case 293 made of white resin or the like.
The three LED chips 10 are each mechanically mounted on the positive lead frame 291 by solder or the like. Further, the positive electrodes (described later) of the three LED chips 10 are electrically connected to the positive lead frame 291 respectively, and the negative electrodes (described later) of the three LED chips 10 are electrically connected to the negative electrode lead frame 292 by bonding wires or the like. In this way, the three LED chips 10 in the LED package 20 are electrically connected in parallel.
In the present embodiment, the positive lead frame 291 and the negative lead frame 292 function as parallel connection means or one of the first power supply paths.

  In addition, lead frame terminals 291a and 292a are respectively provided on the side of the positive lead frame 291 and the negative lead frame 292 that are not electrically connected to the LED chip 10 (see FIG. 4B). . The lead frame terminals 291a and 292a are connected to the above-described electric wiring pattern 32 of the module substrate 31 using solder or the like, so that the electrical connection between the LED package 20 and the module substrate 31 and further mechanical A connection is made.

  Further, as shown in FIGS. 4A and 4B, a reflection wall 27 is provided around the three LED chips 10. The reflection wall 27 reflects the light emitted from the LED chip 10 and efficiently irradiates the light emitted from the LED chip 10 toward the diffusion plate 43 and the like (see FIG. 1). Further, a sealing resin 28 is provided inside the reflecting wall 27 so as to fill the three LED chips 10. In the present embodiment, the sealing resin 28 is added with a phosphor that emits red light upon receiving blue light and a phosphor that emits green light upon receiving blue light.

  FIG. 5 is a diagram for explaining another example of the shape of the lead frame of the LED package 20. The basic structure of the LED package 20 shown in FIGS. 5A to 5C is the same as that shown in FIG. 4, but the shapes of the positive lead frame 291 and the negative lead frame 292 are different. . In addition, about the thing similar to the LED package 20 demonstrated using FIG. 4, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.

  The example of the LED package 20 shown in FIG. 5A includes a positive lead frame 291 having a convex shape and a negative lead frame 292 having a concave shape. One LED chip 10 is attached to the protruding portion of the positive lead frame 291, and the other two LED chips 10 are attached to locations other than the protruding portion of the positive lead frame 291. As in the above example, the LED chip 10 and the lead frame are electrically connected, and the three LED chips 10 are connected in parallel.

  Next, in the example of the LED package 20 shown in FIG. 5B, the positive lead frame 291 and the negative lead frame 292 each have a rectangular shape. In addition, each lead frame is arranged substantially in parallel with a predetermined distance. The three LED chips 10 are attached to the positive lead frame 291 and the three LED chips 10 are connected in parallel as in the above example.

  Furthermore, the example of the LED package 20 shown in FIG. 5C includes a positive lead frame 291 having an L shape and a negative lead frame 292 having a square shape that fits inside the L shape. Is. The three LED chips 10 are attached at predetermined intervals along the L shape of the positive lead frame 291 having an L shape. As in the above example, in this example as well, the three LED chips 10 provided in the LED package 20 are connected in parallel.

FIG. 6 is a diagram for explaining electrical connection in the light emitting module 30.
Here, one light emitting module 30 will be described as a representative example, but the same applies to other light emitting modules 30 provided in the backlight device 40. In FIG. 6, a frame indicated by a broken line indicates the light emitting block 300, and a frame indicated by a one-dot chain line corresponds to a unit of one LED package 20.
First, in the LED package 20 indicated by a one-dot chain line in FIG. 6, three LED chips 10 are connected in parallel. As described above, the parallel connection of these three LED chips 10 is realized by the lead frames 291 and 292.

  And in the one light emission block 300 shown with a broken line in FIG. 6, the 12 LED packages 20 are connected in series. The twelve LED packages 20 are connected in series by an electric wiring pattern 32 provided on the module substrate 31. Further, as shown in FIG. 6, an individual power source P is provided for each light emitting block 300 (12 LED packages 20 connected in series). The twelve LED packages 20 are connected to the power source P through the electrical wiring pattern 32 and the like.

Next, the light emission operation of the backlight device 40 (see FIG. 1) will be described.
In each light emitting module 30 provided in the backlight device 40, a voltage is applied to twelve LED packages 20 connected in series for each light emitting block 300 by each power source P. A current flows through each of the twelve LED packages 20 in each light emitting block 300. At this time, in each LED package 20, a current flows through the three LED chips 10 connected in parallel to each other.

  As a result of current flowing through the three LED chips 10, the LED chip 10 emits blue light. At this time, part of the blue light emitted from the LED chip 10 is converted into red or green by the phosphor added to the sealing resin 28. As a result, white light including red (R), green (G), and blue (B) light is emitted from one LED package 20.

  Similarly, in the other light emitting blocks 300, and also in the other light emitting modules 30, white light including red (R), green (G), and blue (B) light is emitted from each LED package 20. It will be. Then, this light is mixed in the backlight frame 41 and irradiated to the diffusion plate 43. Further, after the color mixing is promoted by the diffusion plate 43 and the like, the light is irradiated toward the liquid crystal display module 50.

  Further, as described above, in the backlight device 40 to which the present embodiment is applied, since the power supply P is provided for each light emitting block 300, each light emitting block 300 is turned on by controlling each power supply P. , And can be controlled independently. Thus, when an image is displayed as a liquid crystal display device, it is possible to perform so-called area control such as turning off the light emitting block 300 located on the back side of the place where the display image becomes black.

  Further, by dispersing and providing three LED chips 10 in the LED package 20, for example, a temperature increase can be suppressed as compared with a case where one large-sized (for example, 550 μm square) chip is provided in the LED package 20. Is possible.

For example, in a light source of a device having a large light emitting area such as a backlight of a liquid crystal display device to which the present embodiment is applied, a large number of LED chips 10 are provided in order to obtain a predetermined light amount (such as luminance). There is a need. At this time, since the LED package 20 to which the present embodiment is applied includes the three LED chips 10 together, the mounting operation on the mounting target substrate or the like can be reduced to, for example, 1/3.
The three LED chips 10 provided in the LED package 20 are connected in parallel. Therefore, in the LED package 20, it is possible to suppress the drive voltage as compared with the case where the three LED chips 10 are connected in series. Accordingly, the driving voltage of the backlight device 40 and further the liquid crystal display device can be suppressed.

Next, the configuration of the LED chip 10 that is electrically connected in parallel in the LED package 20 described above will be described.
FIG. 7 is a cross-sectional view schematically showing the LED chip 10.
As shown in FIG. 7, the LED chip 10 includes a substrate 11 as an element substrate, a seed layer 12 as a first layer, and a semiconductor layer 100 made of a group III nitride compound semiconductor containing Ga as a group III element. I have. Then, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are stacked in this order on the seed layer 12, and the semiconductor layer 100 is configured by these layers.

<Board>
The substrate 11 in the LED chip 10 to which this embodiment is applied is made of sapphire. The material that can be used for the substrate 11 is not particularly limited as long as it is a substrate material on which a group III nitride compound semiconductor crystal is epitaxially grown.

<Seed layer>
The seed layer 12 is formed on the c-plane of the substrate 11 (sapphire substrate). In the present embodiment, the seed layer 12 is made of AlN. The material that can be used for the seed layer 12 may be a group III nitride compound semiconductor, and may contain Ga and In as group III elements, but among them, a composition containing Al is desirable. . Further, GaAlN may be used as the material of the seed layer 12, and in that case, the composition of Al is preferably 50% or more.

The seed layer 12 needs to cover at least 60% or more, preferably 80% or more of the surface of the substrate 11, and is preferably formed so as to cover 90% or more. The seed layer 12 is most preferably formed so as to cover 100% of the surface of the substrate 11, that is, the surface of the substrate 11 without a gap.
When the region where the seed layer 12 covers the surface of the substrate 11 becomes small, the substrate 11 is largely exposed. In such a case, the base layer 14a formed on the seed layer 12 and the base layer 14a formed directly on the substrate 11 have different lattice constants, resulting in a non-uniform crystal and hillocks and pits. There is a risk of it.
The seed layer 12 may be formed so as to cover the side surface in addition to the surface of the substrate 11, and may be formed so as to cover the back surface of the substrate 11.
In the present embodiment, the thickness of the seed layer 12 in the LED chip 10 is set to fall within a range of 21 nm to 40 nm.

<Semiconductor layer>
<N-type semiconductor layer>
The n-type semiconductor layer 14 includes a base layer 14a stacked on the seed layer 12, an n-type contact layer 14b stacked on the base layer 14a, and an n-type cladding layer 14c stacked on the n-type contact layer 14b. It consists of and.
<Underlayer>
The underlying layer 14a as the second layer is made of GaN. The material of the underlayer 14a may be the same as or different from that of the seed layer 12, but a group III nitride compound semiconductor containing Ga, that is, a GaN-based compound semiconductor is preferable, and an Al _X Ga _1-X N layer More preferably, it is composed of (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). Further, as a result of experiments by the present inventors, it was found that a group III nitride compound semiconductor containing Ga, that is, a GaN-based compound semiconductor is preferable as a material used for the underlayer 14a.

If necessary, the underlayer 14a may be doped with n-type impurities within the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , but undoped (<1 × 10 ¹⁷ / cm ^3). ) And undoped is preferable in terms of maintaining good crystallinity.
For example, when the substrate 11 has conductivity, electrodes can be formed above and below the LED chip 10 by doping the base layer 14a with a dopant to make it conductive. On the other hand, when an insulating material is used as the substrate 11, a chip structure in which the positive electrode and the negative electrode are provided on the same surface of the LED chip 10 is taken. It is more preferable that the crystallinity is improved.
Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.

  The film thickness of the underlayer 14a is set to 6 μm. In addition, although there is no special restriction | limiting about the thickness of the base layer 14a, Generally the range of 0.5 micrometer-20 micrometers is preferable. If it is less than 0.5 μm, dislocation looping may be insufficient, and if it exceeds 20 μm, there is no change in function, and the processing time is unnecessarily prolonged. Preferably, it is the range of 1 micrometer-15 micrometers.

<N-type contact layer>
The n-type contact layer 14b is 2 μm thick Si-doped GaN having an electron concentration of 1 × 10 ¹⁹ / cm ³ .
Note that the n-type contact layer 14b is not limited to this, but the n-type contact layer 14b is an Al _X Ga _1-X N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦) in the same manner as the base layer 14a. 0.5, more preferably 0 ≦ x ≦ 0.1).

Further, the n-type contact layer 14b is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ^19. When it is contained at a concentration of / cm ³ , it is preferable in terms of maintaining good ohmic contact with the negative electrode, suppressing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge.

  In addition, it is preferable that the group III nitride compound semiconductor which comprises the base layer 14a and the n-type contact layer 14b is the same composition, These total film thicknesses are 0.5 micrometer-20 micrometers, Preferably they are 1 micrometer-15 micrometers, More preferably Is preferably set in the range of 1 μm to 10 μm. When the film thickness is within this range, the crystallinity of the semiconductor is maintained well.

<N-type cladding layer>
It is preferable to provide an n-type cladding layer 14c between the n-type contact layer 14b and the light emitting layer 15. By providing the n-type cladding layer 14c, effects such as electron supply to the active layer and relaxation of the lattice constant difference can be provided.
In the present embodiment, the n-type cladding layer 14c is In _0.1 Ga _0.9 N having a thickness of 20 nm and an electron concentration of 1 × 10 ¹⁸ / cm ³ .
The n-type clad layer 14a is not limited to this, and can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. When the n-type cladding layer 14c is made of GaInN, it is desirable to make it lower than the In concentration of GaInN in the well layer.

The n-type doping concentration of the n-type cladding layer 14c is preferably in the range of 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably in the range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the light emitting element.
The n-type contact layer can also serve as an underlayer and / or an n-type cladding layer, and the underlayer can also serve as an n-type contact layer and / or an n-type cladding layer. .

<Light emitting layer>
The light emitting layer 15 is a layer that is stacked on the n-type semiconductor layer 14 and a p-type semiconductor layer 16 is stacked thereon. The light emitting layer 15 can take a multiple quantum well structure, a single well structure, a bulk structure, or the like. In the present embodiment, as shown in FIG. 7, the light emitting layer 15 includes a barrier layer 15a made of a group III nitride compound semiconductor and a well layer 15b made of a group III nitride compound semiconductor containing indium alternately and repeatedly. The barrier layers 15a are arranged on the n-type semiconductor layer 14 side and the p-type semiconductor layer 16 side. In the example shown in FIG. 7, the light emitting layer 15 includes six barrier layers 15 a and five well layers 15 b that are alternately and repeatedly stacked, and the barrier layer 15 a is disposed on the uppermost layer and the lowermost layer of the light emitting layer 15. The multi-quantum well configuration is such that a well layer 15b is disposed between the barrier layers 15a.

In the present embodiment, the barrier layer 15a is GaN having a thickness of 16 nm. As the barrier layer 15a, for _example, it is possible to use _{Al c Ga 1-c N (} 0 ≦ c <0.3) III nitride compound semiconductor such as.
The well layer 15b is In _0.2 Ga _0.8 N having a layer thickness of 3 nm. The well layer 15b, as a group III nitride compound semiconductor containing indium, for _example, can be used _{Ga 1-s In s N (} 0 <s <0.4) gallium nitride indium such.

<P-type semiconductor layer>
The p-type semiconductor layer 16 includes a p-type cladding layer 16a and a p-type contact layer 16b. The p-type contact layer may also serve as the p-type cladding layer.

<P-type cladding layer>
The p-type cladding layer 16a is made of Al _0.02 Ga _0.98 N doped with Mg, and its film thickness is 5 nm. Examples of the p-type cladding layer 16a include those of Al _d Ga _1-d N (0 <d ≦ 0.4, preferably 0.1 ≦ d ≦ 0.3). When the p-type cladding layer 16a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer 15.

The p-type doping concentration of the p-type cladding layer 16a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.

<P-type contact layer>
The p-type contact layer 16b is Al _0.02 Ga _0.98 N doped with Mg, and the film thickness is 0.2 μm. The p-type contact layer 16b includes at least Al _e Ga _1-e N (0 ≦ e <0.5, preferably 0 ≦ e ≦ 0.2, more preferably 0 ≦ e ≦ 0.1). This is a Group III nitride compound semiconductor layer. When the Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the translucent positive electrode 17 (described later).

Further, when the p-type contact layer 16b contains a p-type dopant at a concentration in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , good ohmic contact can be maintained, cracking can be prevented, and good It is preferable at the point of crystalline maintenance, More preferably, it is the range of 5 * 10 < ¹⁹ > -5 * 10 < ²⁰ > / cm < ³ >. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.

In addition, the semiconductor layer 100 which comprises the LED chip 10 of this invention is not limited to the thing of embodiment mentioned above.
For example, as the material of the semiconductor layer 100, addition to the foregoing, for example, and by a general formula _{Al x Ga y In z N 1} -A M A (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1 X + Y + Z = 1. Group III nitride compound semiconductor represented by the symbol M represents a group V element different from nitrogen (N) and 0 ≦ A <1 is known. However, these well-known group III nitride compound semiconductors can be used without any limitation.

  In addition, a group III nitride compound semiconductor containing Ga as a group III element can contain other group III elements in addition to Al, Ga, and In. If necessary, Ge, Si, Mg, Ca, Zn , Be, P, As and B can also be contained. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

<Translucent positive electrode>
The translucent positive electrode 17 is an electrode having translucency formed on the p-type semiconductor layer 16.
The material of the transparent positive electrode 17 is not particularly _{limited, ITO (In 2 O 3 -SnO} 2),
A material such as AZO (ZnO—Al ₂ O ₃ ), IZO (In ₂ O ₃ —ZnO), or GZO (ZnO—Ga ₂ O ₂ ) can be used. Further, as the translucent positive electrode 17, any structure including a conventionally known structure can be used without any limitation.
The translucent positive electrode 17 may be formed so as to cover the entire surface on the p-type semiconductor layer 16, or may be formed in a lattice shape or a tree shape with a gap.

<Positive electrode bonding pad>
The positive electrode bonding pad 18 is a substantially circular electrode formed on the translucent positive electrode 17.
As the material of the positive electrode bonding pad 18, various structures using Au, Al, Ni, Cu and the like are well known, and those known materials and structures can be used without any limitation. However, it is necessary to form a bond with GaN, ITO, IZO, etc., and it is necessary to form a bond with a stable metal oxide such as Cr, Ti, etc., and then make a structure that enables wire bonding by placing Au etc. is there.
The thickness of the positive electrode bonding pad 18 is preferably in the range of 100 to 1000 nm. Further, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 18 is more preferably 300 nm or more. Furthermore, it is preferable to set it as 500 nm or less from a viewpoint of manufacturing cost.

<Negative electrode>
The negative electrode 19 is in contact with the n-type contact layer 14 b of the n-type semiconductor layer 14 constituting the semiconductor layer 100. Therefore, as shown in FIG. 7, the negative electrode 19 has an exposed region 14d formed by removing a part of the p-type semiconductor layer 16, the light emitting layer 15, and the n-type semiconductor layer 14 to expose the n-type contact layer 14b. It is formed in a substantially circular shape on the top.
As materials for the negative electrode 19, negative electrodes having various compositions and structures are well known, and these known negative electrodes can be used without any limitation.

Then, the manufacturing method of LED chip 10 is demonstrated.
To manufacture the LED chip 10 shown in FIG. 7, first, a laminated semiconductor wafer in which the semiconductor layer 100 is formed on the substrate 11 is manufactured. In order to produce a laminated semiconductor wafer, first, a substrate 11 is prepared. It is desirable to use the substrate 11 after pretreatment. For example, when the substrate 11 made of sapphire is used, a wet method such as a well-known RCA cleaning method can be used to keep the surface hydrogen-terminated. This stabilizes the film forming process.

Further, the substrate 11 may be disposed in the chamber of the sputtering apparatus, and the pretreatment may be performed by a method such as sputtering before forming the seed layer 12. Specifically, a pretreatment for cleaning the surface can be performed in the chamber by exposing the substrate 11 to Ar or N ₂ plasma. By causing plasma such as Ar gas or N ₂ gas to act on the surface of the substrate 11, organic substances and oxides attached to the surface of the substrate 11 can be removed. In this case, if a voltage is applied between the substrate 11 and the chamber without applying power to the target, the plasma particles efficiently act on the substrate 11.

After pre-processing the substrate 11, a seed layer 12 is formed on the substrate 11 by sputtering.
The orientation of the n-type semiconductor layer 14 formed on the seed layer 12 is greatly influenced by the state of the seed layer 12. In the past, the MOCVD method has been desirable for obtaining the seed layer 12 having high crystallinity. However, the MOCVD method is a method in which decomposed metals are stacked on the substrate 11. First, nuclei are formed, then crystals grow around the nuclei, and are gradually formed, so that they are as thin as the seed layer 12. In the case of forming a film, the uniformity may be insufficient.
On the other hand, the sputtering method is preferable because it enables high-density film formation, so that a uniform film can be formed even when a thin film is formed. Therefore, by forming the seed layer 12 by the sputtering method, the seed layer 12 can be formed so as to cover the surface of the substrate 11 without a gap, and the in-plane uniform seed layer 12 can be formed. An n-type semiconductor layer 14 having a high crystal orientation can be grown on the uniform seed layer 12.
In the present embodiment, among the sputtering methods, an RF (high frequency) sputtering method is employed in which the target surface is hardly charged up and the deposition rate is stable.

The substrate temperature at the time of forming the seed layer 12 by the sputtering method was set to 300 to 800 ° C. Further, Al is used as a sputtering target. Moreover, about the pressure in a furnace, and the nitrogen partial pressure, the pressure in a furnace was 0.3 Pa or more. This is because at a pressure lower than this, the amount of nitrogen present is small and the sputtered metal adheres without becoming nitride. The upper limit of the pressure is not particularly defined as long as plasma can stably exist.
Further, the ratio of the nitrogen flow rate to the flow rate of nitrogen and argon was set so that nitrogen was 20% or more and 90% or less. This is because the sputtered metal adheres as it is at a flow rate ratio below this, while the amount of argon is small and the sputter rate decreases at a flow rate ratio above this. Note that, as a particularly desirable condition, the ratio of nitrogen flow rate may be 30% or more and 90% or less.

As the nitrogen raw material, a generally known compound can be used without any problem, but in particular, when nitrogen is used as the raw material, an apparatus is simple and it is difficult to obtain a high reaction rate. However, N ₂ is used in the present embodiment. Even with N ₂ , a usable film forming speed can be obtained, and it is the most suitable nitrogen source in view of the balance with the apparatus cost.

  In this embodiment, a c-plane sapphire substrate is introduced into a sputtering apparatus, the substrate is heated to 500 ° C. in a chamber, and nitrogen gas is introduced at a flow rate of 40 sccm. Thereafter, the pressure in the chamber was maintained at 2.0 Pa, a high frequency bias of 100 W was applied to the substrate side, and the substrate surface was cleaned by exposure to nitrogen plasma for 15 seconds.

  Subsequently, the distance between the target and the substrate is adjusted to 60 mm, argon and nitrogen gas are introduced, the substrate temperature is heated to 500 ° C., and then high-frequency power with a predetermined output is applied to the target side, and the pressure in the furnace is adjusted. The film formation of the AlN layer was started on the c-plane of the sapphire substrate under the conditions of 10 sccm of argon gas and 30 sccm of nitrogen gas (the ratio of nitrogen to the total gas was 75%). Then, after depositing AlN for a predetermined time, the plasma was stopped and the substrate temperature was lowered.

The substrate 11 on which the seed layer 12 taken out from the sputtering apparatus was formed was introduced into an MOCVD furnace, and an n-type semiconductor layer 14 (GaN layer) was formed by the method described below.
First, the substrate was placed on a carbon susceptor for heating disposed in the MOCVD furnace, and after flowing nitrogen gas through the MOCVD furnace, the heater was operated to raise the substrate temperature to 1150 ° C. The amount of ammonia was adjusted so that the group V element / group III element ratio was 6000. Subsequently, hydrogen containing trimethylgallium (TMG) vapor was supplied into the MOCVD furnace, and deposition of a GaN layer on the substrate was started. After the undoped GaN layer having a thickness of 6 μm was grown for about 1 hour, the supply of the raw material to the MOCVD furnace was terminated and the growth was stopped. Thereafter, power supply to the heater was stopped, and the temperature of the substrate was lowered to room temperature. The taken-out substrate exhibited a colorless and transparent mirror shape.

  Thereafter, on the substrate 11 on which the seed layer 12 is formed, as shown in FIG. 7, an n-type semiconductor layer 14 including a base layer 14a, an n-type contact layer 14b, and an n-type cladding layer 14c, a barrier layer 15a, and a well layer The light emitting layer 15 made of 15b, the p-type cladding layer 16a of the p-type semiconductor layer 16 and the p-type contact layer 16b are formed by MOCVD (metal organic chemical vapor deposition) capable of forming a layer with good crystallinity. A film was formed.

The carrier gas in the MOCVD method is hydrogen (H ₂ ) or nitrogen (N ₂ ), trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a group III material, and trimethyl aluminum (TMA) as an Al source. Alternatively, triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, and ammonia, hydrazine or the like as the N source which is a group V raw material are used.

In addition, as the n-type impurity of the dopant element, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a Si raw material, germane gas (GeH ₄ ) is used as a Ge raw material, and tetramethyl germanium ((CH ₃ ) ₄ Ge ) And tetraethylgermanium ((C ₂ H ₅ ) ₄ Ge) can be used.

For the p-type impurity of the dopant element, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) can be used as the Mg raw material.

On the p-type contact layer 16b of the semiconductor layer 100 shown in FIG. 7 obtained in this manner, a light-transmitting positive electrode 17 and a positive electrode bonding pad 18 are sequentially formed by using a photolithography method.
Next, the exposed region 14d on the n-type contact layer 14b is formed by dry etching the semiconductor layer 100 on which the translucent positive electrode 17 and the positive electrode bonding pad 18 are formed.
Then, the LED chip 10 shown in FIG. 7 is obtained by forming the negative electrode 19 on the exposed region 14d by using a photolithography method.

  The manufacturing method of the LED chip 10 of the present invention is not limited to the above-described example. For example, the semiconductor layer 100 is formed by sputtering, MOCVD (metal organic chemical vapor deposition), or HVPE. Any method capable of growing a semiconductor layer, such as (halide vapor phase epitaxy) or MBE (molecular beam epitaxy) may be used in combination.

Next, the relationship between the film thickness of the seed layer 12 and the crystallinity of the foundation layer 14a will be described.
FIG. 8 is a diagram showing the relationship between the film thickness of the seed layer 12 and the rocking curve half width of the underlayer 14a for a plurality of LED chip samples. The rocking curve half width is one of the indices for evaluating the degree of crystal orientation of the underlayer 14a and the like.

  Here, in the semiconductor layer 100, the n-type contact layer 14b is formed on the base layer 14a, the n-type cladding layer 14c is formed on the n-type contact layer 14b, the light emitting layer 15 is formed on the n-type cladding layer 14c, and the p-type semiconductor layer 16 is formed. Are stacked in order. Accordingly, if the crystal orientation of the base layer 14a is good, the crystallinity of the semiconductor layer 100 is good. If the crystal orientation of the base layer 14a is not good, the crystallinity of the semiconductor layer 100 is bad.

The crystal structure of the underlayer 14a (AlN) is a close-packed structure, and the (10-10) plane corresponds to a plane perpendicular to the crystal substrate surface of the underlayer 14a. The crystal of the underlayer 14a has a structure in which hexagonal columns grow vertically on the substrate surface. For example, if the hexagonal columns, which are crystals of the underlayer 14a, are arranged in the same direction in the plane, there is no gap, but if they are slightly different, a gap is generated between the hexagonal column and the hexagonal column. . This gap indicates the degree of crystal orientation and is considered to correspond to threading dislocations. Therefore, in the underlayer 14a, it is necessary that not only the (0002) plane parallel to the substrate surface but also the crystal orientation of the (10-10) plane perpendicular to the substrate surface satisfy a predetermined condition.
Further, since the underlayer 14 a is laminated on the seed layer 12, it is considered that the crystal orientation of the underlayer 14 a is greatly affected by the crystal state of the seed layer 12.

Therefore, the present inventors prepared various types of samples having different thicknesses of the seed layer 12 formed on the substrate 11 and further formed the underlayer 14a thereon, and the underlayer 14a of each sample was prepared. An experiment was conducted in which the crystal plane was measured by the rocking curve method.
Specifically, Sample A1, Sample A2, Sample A3, and Sample A4 were produced as satisfying the film thickness condition (21 nm to 40 nm) of the seed layer 12 to which this embodiment is applied. On the other hand, Sample B1 and Sample B2 that do not satisfy the film thickness condition of the seed layer 12 to which the present embodiment is applied were also produced. The deposition conditions and film thickness of the seed layer 12 for these samples are shown below. These samples are all manufactured according to the manufacturing method described above except that the film formation conditions (or film thickness) of the seed layer 12 are different.

With respect to the above six types of samples, the half width of the X-ray rocking curve was measured for the (0002) plane and the (10-10) plane of the base layer 14a.
In the measurement of the X-ray rocking curve method, CuKα ray was used as the X-ray source, and incident light having a divergence angle of 0.01 ° was used and measured using a Spectraly PANaltical X'pert Pro MRD apparatus.

  In consideration of errors due to the way the substrate is attached to the apparatus and the orientation direction with respect to the substrate differ depending on the sample to be measured, the rocking curve measurement of the (0002) plane finds a peak corresponding to the (0002) plane, The correction is performed by optimizing 2θ and ω, and then adjusting the Psi to measure the rocking curve in the direction in which the peak intensity is maximized.

  Moreover, the rocking curve measurement of the (10-10) plane was performed using X-rays transmitted through the surface under the condition that X-rays were totally reflected. Specifically, when X-rays that diverge in the vertical direction are incident on the sample to be measured placed horizontally, a part of the X-rays are totally reflected, and the X-rays were used. The detector was fixed at a 2θ position corresponding to the (10-10) plane, and φ scan was performed. Then, a six-fold symmetric peak was measured, and after fixing the optical system at the peak position showing the maximum intensity, 2θ and ω were optimized, and rocking curve measurement was performed.

  As shown in FIG. 8, the half width of the X-ray rocking curve of the (0002) plane of the underlayer 14a is as large as about 180 arcsec in the sample B1 in which the seed layer 12 has a film thickness of 20 nm or less. On the other hand, Sample A1, Sample A2, Sample A3, and Sample A4 included in the range where the film thickness of the seed layer 12 is 21 nm or more and 40 nm or less has a small value of about 50 arcsec or less. Further, in the sample B2 in which the film thickness of the seed layer 12 is 41 nm or more, it is about 50 arcsec or less.

  On the other hand, as shown in FIG. 8, the full width at half maximum of the X-ray rocking curve of the (10-10) plane of the base layer 14a is as large as about 270 arcsec in the sample B1 in which the seed layer 12 has a film thickness of 20 nm or less. On the other hand, Sample A1, Sample A2, Sample A3, and Sample A4 in which the film thickness of the seed layer 12 is included in the range of 21 nm to 40 nm is stable in the range of 200 to 225 arcsec. And in the sample B2 in which the film thickness of the seed layer 12 is 41 nm or more, it is about 260 arcsec and tends to be large in the region where the film thickness exceeds 41 nm.

  Considering the above results, in the region where the thickness of the seed layer 12 is less than 21 nm, the crystallinity of the seed layer 12 is poor, and the (0002) plane and (10-10) of the underlying layer 14a formed thereon It is considered that the plane orientation was not sufficient and the X-ray rocking curve half-width was increased. On the other hand, when the seed layer 12 is thicker than 21 nm, the seed layer 12 is crystallized and the crystal planes are aligned, thereby improving the orientation of the (0002) plane and the (10-10) plane of the underlayer 14a. The X-ray rocking curve half-width is considered to have been reduced. However, since the crystallinity of the (10-10) plane is obtained from the substrate 11, when the film thickness of the seed layer 12 exceeds 40 nm, the underlayer 14 a formed thereon becomes information from the substrate 11. It is considered that the X-ray rocking curve half-value width was increased due to the poor degree of orientation.

FIG. 9 is a diagram for explaining the forward current-forward voltage characteristics (hereinafter referred to as I _F -V _F characteristics) between the LED chip 10 to which the present exemplary embodiment is applied and the comparative LED chip 90. It is.
Here, three LED chips 10 (10-1, 10-2, 10-3) cut out from the laminated semiconductor wafer manufactured based on the film thickness condition of the seed layer 12 similar to the above sample A3, and the above Prepare three LED chips 90 (90-1, 90-2, 90-3) for comparison cut out from the laminated semiconductor wafer manufactured based on the film thickness condition of the seed layer 12 similar to the sample B1 of It was measured each _I F -V _F characteristics.

First, the LED chip 90 for comparison, as shown in FIG. 9 (b), variations occur in the _I F -V _F characteristic between the LED chips 90-1, 90-2 and 90-3 for comparison It was. That is, it has been found that the resistance value varies greatly among the plurality of comparative LED chips 90. This means that when the same voltage is applied to the plurality of LED chips 90 for comparison, the variation in the current flowing through each LED chip 90 is large.

Further, since the light emission amount of the LED chip is proportional to the current, thus if a plurality of LED chips 90 for comparison I _F -V _F characteristic varies greatly were connected in parallel, each of these LED chips 90 The amount of emitted light varies greatly.

On the other hand, as shown in FIG. 9A, the I _F -V _F characteristics of the LED chips 10-1, 10-2, and 10-3 were almost the same. Therefore, as described above, the variation in resistance value among these LED chips 10 is small, and the variation in current flowing when the same voltage is applied is also small. Therefore, even when a plurality of LED chips 10 are connected in parallel, it is possible to suppress variation in the amount of light of each LED chip 10.
Further, since the resistance values of the plurality of LED chips 10 are uniform, it is possible to suppress the load from being concentrated on any one of the LED chips 10, and the reliability (durability) as the LED package 20 including the plurality of LED chips 10. ) Can be increased.

As described above, by optimizing the deposition conditions of the seed layer 12 formed on the substrate 11, the crystallinity of the semiconductor layer 100 stacked thereon is improved. Therefore, it is possible to obtain a homogeneous LED chip 10 from a laminated semiconductor wafer having good crystallinity, and further, variation in electrical characteristics such as resistance values among the obtained LED chips 10 is reduced.
Further, as described in the previous stage, even when a plurality of LED chips 10 are attached to the LED package 20, the variation in the light amount of each LED chip 10 provided in one LED package 20 is naturally reduced. Also in the relationship with the LED package 20, the variation in the amount of light can be reduced. Furthermore, by providing the backlight device 40 with a plurality of LED packages 20 with small variations in the amount of light in this way, it is possible to suppress the occurrence of unevenness in the amount of light in the backlight device 40.

The LED package 20 described above uses a lead frame, but is not necessarily limited to an embodiment using a lead frame.
FIG. 10 is a diagram for explaining the LED package 290. FIG. 10A is a top view (light emitting surface side) of the LED package 290, and FIG. 10B is an XX cross section shown in FIG. In addition, about the thing similar to the LED package 20 mentioned above, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.

  As shown in FIG. 10A, the LED package 290 includes three LED chips 10 and a package substrate 22 on which the three LED chips 10 are mounted. As the package substrate 22, for example, a glass epoxy substrate or the like can be used as a material. As shown in FIG. 10B, the package substrate 22 faces the module substrate 31 when the LED chip 10 is mounted (hereinafter referred to as a mounting surface) and the above-described LED package 20 is mounted. And a surface (hereinafter referred to as a non-mounting surface).

  As shown in FIG. 10B, power supply bumps 25 and heat dissipation bumps 26 are provided on the mounting surface of the package substrate 22 that functions as a mounting body, corresponding to each LED chip 10. On the other hand, on the non-mounting surface of the package substrate 22, there are an electric wiring pattern 23 that becomes a path for supplying power to the LED chip 10 and a heat radiation pattern 24 that becomes a discharge path of heat generated by light emission of the LED chip 10. Is formed. The three LED chips 10 are electrically connected in parallel by the electric wiring pattern 23.

  The power supply bumps 25 provided on the mounting surface side of the package substrate 22 and the electric wiring pattern 23 provided on the non-mounting surface side are electrically connected through a through hole provided through the package substrate 22. Connected. Similarly, the heat dissipation bumps 26 provided on the mounting surface side of the package substrate 22 and the heat dissipation pattern 24 provided on the non-mounting surface side are heated by a through hole or the like provided through the package substrate 22. Connected.

  When each LED chip 10 is attached to the package substrate 22, the heat dissipation bump 26 and the LED chip 10 are thermally connected by soldering, and the electrodes provided on the LED chip 10 and the above-described power supply bump 25. Are electrically connected by wire bonding or the like.

  Then, the LED package 290 having the above configuration is electrically attached to the module substrate 31 in the same manner as the LED package 20 described above (see FIG. 3). At that time, by forming a wiring pattern for heat dissipation on the module substrate 31, heat generated from the LED package 290 can be more effectively released. Thus, the LED package 290 is preferable in that a heat dissipation path is formed in each of the three LED chips 10.

  As described above, the example in which the plurality of LED chips 10 are electrically connected in parallel in the LED package 20 or the LED package 290 has been described. However, it is not always necessary to electrically connect the plurality of LED chips 10 in parallel in units of packages such as the LED package 20. For example, the plurality of LED chips 10 are configured to be directly mounted on the module substrate 31, and, for example, three of the plurality of LED chips 10 are electrically connected in parallel by the electric wiring pattern 32 provided on the module substrate 31. It can also be configured to be connected. In this case, the module substrate 31 functions as a parallel connection unit and a connection unit.

  Further, by changing the composition of In in the well layer 15b in the LED chip 10, it is possible to emit ultraviolet light. In that case, for example, by adding a phosphor that emits red light upon receiving ultraviolet light to the sealing resin 28, a phosphor that emits green light, and a phosphor that emits blue light, The emitting LED package 20 can be obtained.

  In the above description, the example in which the number of LED chips 10 provided in the LED package 20 is three has been described. However, the present invention is not limited to this. The number of LED chips 10 provided in the LED package 20 may be any number as long as it is plural.

It is a figure which shows the whole structure of the liquid crystal display device with which this Embodiment is applied. It is a figure for demonstrating the structure of a backlight frame and a light emission unit. It is a figure for demonstrating a light emitting module. It is a figure for demonstrating an LED package. It is a figure for demonstrating the other example about the shape of a lead frame. It is a figure for demonstrating the electrical connection in a light emitting module. It is sectional drawing which showed the LED chip typically. It is the figure which showed the relationship between the film thickness of a seed layer, and the rocking curve half value width of a base layer about the sample of a some LED chip. It is a figure for demonstrating the forward current-forward voltage characteristic with the LED chip to which this Embodiment is applied, and the LED chip for a comparison. It is a figure for demonstrating the other example about an LED package.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... LED chip, 11 ... Board | substrate, 12 ... Seed layer, 14a ... Underlayer, 14b ... N-type contact layer, 14c ... N-type clad layer, 14d ... Exposed region, 15a ... Barrier layer, 15b ... Well layer, 16 ... p-type semiconductor layer, 16a ... p-type cladding layer, 16b ... p-type contact layer, 100 ... semiconductor layer, 20 ... LED package, 30 ... light emitting module, 31 ... module substrate, 300 ... light emitting block, 40 ... backlight device 42 ... light emitting unit, 50 ... liquid crystal display module

Claims (11)

A plurality of light emitting elements;
A parallel connection means for electrically connecting the plurality of light emitting elements in parallel;
Each light emitting element constituting the plurality of light emitting elements,
An element substrate;
A first layer made of a group III nitride compound semiconductor and directly stacked on the element substrate;
The III-nitride compound semiconductor is directly laminated on the first layer, and has a (0002) plane rocking curve half-width of 100 arcsec or less and a (10-10) plane rocking curve half-width of 250 arcsec or less. And a second layer. The second layer is
2. The light source according to claim 1, wherein the light source is a group III nitride compound semiconductor having a rocking curve half width of (0002) plane of 60 arcsec or less and a rocking curve half width of (10-10) plane of 250 arcsec or less.   2. The light source according to claim 1, wherein the parallel connection means is a mounting body on which the plurality of light emitting elements are attached and a power supply path for supplying power to the plurality of light emitting elements is formed.   The light source according to claim 1, wherein the first layer has a layer thickness of 21 nm to 40 nm.   The light source according to claim 4, wherein the first layer is formed by a sputtering method.   2. The light source according to claim 1, wherein the element substrate is a sapphire substrate, the first layer is AlN, and the second layer is GaN. A plurality of other light emitting elements different from the plurality of light emitting elements;
Other parallel connection means for electrically connecting the other plurality of light emitting elements in parallel;
The light source according to claim 1, further comprising connection means for electrically connecting the parallel connection means and the other parallel connection means. A light-emitting body comprising a plurality of light-emitting elements and a first power supply path that electrically connects the plurality of light-emitting elements in parallel;
A plurality of the light emitters, and a mounting substrate provided with a second power feed path that is electrically connected to the first power feed path provided in each of the light emitters,
Each light emitting element constituting the plurality of light emitting elements,
An element substrate;
A first layer made of a group III nitride compound semiconductor and directly stacked on the element substrate;
A III-nitride compound semiconductor that is directly stacked on the first layer and has a (0002) plane rocking curve half-width of 100 arcsec or less and a (10-10) plane rocking curve half-width of 250 arcsec or less. And a second layer.   The light emitting device according to claim 8, wherein the plurality of light emitters are arranged at equal intervals on the mounting substrate. A display device that includes a display panel that displays an image, and a backlight that is provided on the back surface of the display panel and emits light to the display panel,
The backlight is
A light-emitting body comprising a plurality of light-emitting elements and a first power supply path that electrically connects the plurality of light-emitting elements in parallel;
A plurality of the light emitters, and a mounting substrate provided with a second power feed path that is electrically connected to the first power feed path provided in each of the light emitters,
Each light emitting element constituting the plurality of light emitting elements,
An element substrate;
A first layer made of a group III nitride compound semiconductor and directly stacked on the element substrate;
A III-nitride compound semiconductor that is directly stacked on the first layer and has a (0002) plane rocking curve half-width of 100 arcsec or less and a (10-10) plane rocking curve half-width of 250 arcsec or less. And a second layer. A plurality of connecting conductors that electrically connect two or more light emitters constituting the plurality of light emitters to form a plurality of light emitter groups;
The display device according to claim 10, further comprising: a plurality of power supplies that supply power to each of the connection conductors constituting the plurality of connection conductors.

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