JP2009158721A - Method of manufacturing chip resistor, and chip resistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a chip resistor that improves the anticorrosion property of a front surface electrode, increases the area of an external electrode layer on the side of the front surface, and employs the external electrode layer that is not peeled easily. <P>SOLUTION: A resistor body layer is formed between the front surface electrodes 2 that counter each other, and the layer is covered with a protective layer 5 made of resin material. In the process of forming the protective layer outside the product region, the same layer is formed as a spacing control layer 8. When sputtering is performed after piling a plurality of produced rectangular chip components (as shown in (M) and (N) in Fig.7), the spacing control layer 8 controls the spacing between upper and lower rectangular chip components and prevents the state of inclined lamination. A metal thin film is formed extending from the edge surface of the substrate to part of the protective film. Then, the external electrode layer is plated on the metal thin film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a chip resistor used as an electronic circuit component, and more particularly to a method of manufacturing a micro-sized chip resistor and a chip resistor manufactured by the manufacturing method.

  There are various sizes of resistors, such as a relatively large 3.2 mm × 1.6 mm called “3216” and a small 0.4 mm × 0.2 mm nominal called “0402”. Resistor sizes tend to become smaller.

  FIG. 11 is a cross-sectional view for explaining an example of a conventional chip resistor. In the figure, 11 is an insulating substrate, 12 is a top electrode, 13 is a bottom electrode, 14 is a resistor layer, 15 is a protective layer, 15a is a first protective layer, 15b is a second protective layer, 16 is an end face electrode film, 17 Is an external electrode layer, 17a is a nickel plating layer, and 17b is a solder plating layer.

  As the insulating substrate 11, an insulating substrate such as alumina is used, a pair of upper surface electrodes 12 are formed on the left and right ends of the upper surface, and a pair of lower electrodes 13 are formed on the left and right ends of the lower surface of the insulating substrate 11. Has been. A resistor layer 14 is formed so as to overlap a part of the pair of upper surface electrodes 12. A protective layer 15 is formed on the surface of the resistor layer 14, and in this example, the protective layer 15 is formed by a first protective layer 15a using a glass paste and a second protective layer 15b using an epoxy resin. Has been. The end surface electrode film 16 is formed on the end surface of the insulating substrate 11 so as to short-circuit the end surface of the upper surface electrode 12 and the end surface of the lower surface electrode 13 by sputtering. In this example, the external electrode layer 17 is formed of a nickel plating layer 17a and a solder plating layer 17b.

  In addition to this conventional chip resistor, a general chip resistor is usually manufactured using a multi-piece insulating substrate. The multi-piece insulating substrate is divided into individual resistor regions by dividing grooves, and the dividing grooves are primary divided grooves (also referred to as vertical grooves) in a direction perpendicular to the longitudinal direction of the resistor layer 14. ) And secondary divided grooves (also referred to as transverse grooves) parallel to the longitudinal direction of the resistor layer 14.

  In the manufacturing method using a multi-piece insulating substrate, the top electrode 12 is screen-printed with a thick film glaze paste so as to straddle the lateral groove on the surface, and baked to form the top electrode 12. The bottom electrode 13 is formed in the same manner. Thereafter, the resistor paste 14 is formed by screen printing and baking the resistor paste. The first protective layer 15a is formed on the surface of the resistor layer 14 by screen printing using a glass paste and baking. Here, trimming using laser light is performed to correct the resistance value. Next, the second protective layer 15b is formed so as to be polymerized to a part of the upper surface electrode 12 and the first protective layer 15a.

  After being divided along the primary dividing groove, sputtering is performed so as to cover the end surfaces of the insulating substrate 11 and the end surfaces of the upper surface electrode 12 and the lower surface electrode 13 in the strip-shaped chip component primarily divided into strips. An end face electrode film 16 is formed. Next, after secondary division along the secondary division grooves to form individual pieces, the nickel plating layer 17a and the solder plating layer 17b are plated in this order to manufacture a chip resistor.

  Regarding the formation of the end face electrode film 16, a method using thin film forming means such as sputtering by stacking strip-shaped chip parts divided along the primary dividing groove is employed. As described, a thin film is formed only on the end face.

  Further, in the chip resistor described in Patent Document 3, as shown in FIG. 12, the auxiliary layer 15c is formed at both ends of the second protective layer 15b, and the structure has excellent mounting stability. Yes. The chip resistor shown in FIG. 12 is the same as the chip resistor described in FIG. 11 except that the auxiliary layer 15c is added, and the same reference numerals as those in FIG. The end face electrode film 16 is also formed by forming a thin film only on the end face as described in Patent Document 1 and Patent Document 2.

  Thus, the end face electrode film in the conventional chip resistor is usually formed only on the end face. In Patent Document 1, paragraph [0009] states that “the end face electrode made of a metal thin film extends to the upper surface of the protective layer 31. As a preventive measure, there is a method in which a resist is formed in advance on an unnecessary portion so that a metal thin film is not formed on the surface other than the end surface electrode forming surface and lifted off after the end surface electrode is formed. In Patent Document 2, paragraph [0014] describes that “the film thickness of the end face electrode thin film is made uniform and the electrode material is prevented from wrapping around the protective layer”.

  In the above-described chip resistor, as shown in FIGS. 11 and 12, a slight gap is likely to occur between the edge of the protective layer 15 and the edge of the external electrode layer 17, and the sulfide gas can easily enter depending on the use environment. There's a problem. When hydrogen sulfide or the like reacts with silver contained in the upper surface electrode 12, silver sulfide is formed. However, since silver sulfide is an insulator, it causes a fluctuation in resistance value. In a very small chip resistor, the width of the upper surface electrode 12 is also very small, so that it has been recognized that the influence of the resistance value variation of the upper surface electrode 12 becomes large.

  Further, the second protective layer 15b and the auxiliary layer 15c made of a resin material are easy to sag at the time of printing and heating for curing, and the amount of spread due to sag is not constant, so the upper electrode is not covered with the protective layer. The dimension on the upper surface side of the external electrode layer 17 described with reference to FIGS. 11 and 12 varies depending on the influence (becomes larger or smaller and does not become constant). In any case, in a chip resistor having a nominal size of 1.0 mm × 0.5 mm or less called “1005”, the area of the external electrode layer 17 on the upper surface side is small.

  Patent Document 4 and Patent Document 5 describe a chip resistor in which an external electrode layer is formed so as to extend to a part of the upper surface of the protective layer, taking into account the size and linearity of the upper surface side of the external electrode layer. . This chip resistor is formed so that the end face electrode layer also extends to a part of the upper surface of the protective layer. In the step of forming the end face electrode layer, the end face electrode layer is not formed on the upper face and the lower face of the protective layer. The region is masked to form a sputtered film, and then the masking is removed and electrode plating is applied to the surface of the sputtered film.

  FIG. 13 is a cross-sectional view for explaining an example of a chip resistor in which an external electrode layer is formed so as to extend to a part of the upper surface of the protective layer. In the figure, the same parts as those in FIG.

  The end face electrode film 16 is formed on both end faces of the insulating substrate 11 and end faces of the upper face electrode 12 and the lower face electrode 13 by sputtering, and further, on the upper face side, from the both ends of the upper face electrode 12, respectively, It is formed so as to extend to a part of the surface of the protective layer 15 beyond the boundary position with the protective layer 15. On the lower surface side, the lower surface side is formed so as to cover the lower surface electrode 13 from both ends of the lower surface electrode 3.

  FIG. 15 is a cross-sectional view in order of steps for explaining an example of the manufacturing method of the chip resistor explained in FIG. In the figure, the same parts as those in FIG. Reference numeral 18 denotes a masking layer.

  FIG. 15A shows an insulating substrate. The insulating substrate 1 is made of an insulator made of alumina or the like, and a multi-piece insulating substrate is usually used in order to facilitate mass production. The multi-piece insulating substrate is divided into individual resistor regions by dividing grooves. The dividing groove is also referred to as a primary dividing groove (also referred to as a longitudinal groove) in a direction orthogonal to the longitudinal direction of the resistor layer 14 and a secondary dividing groove (also referred to as a transverse groove) parallel to the longitudinal direction of the resistor layer 14. ) And more.

  FIG. 15B shows a process of forming the upper surface electrode and the lower surface electrode. A thick film glaze paste containing conductive particles such as Ag or Ag—Pd is screen-printed on the surface of the insulating substrate 11 and baked to form the upper surface electrode 12. Subsequently, the lower surface electrode 13 is similarly formed on the lower surface (back surface) of the insulating substrate.

FIG. 15C shows a resistance layer forming step. A resistor paste such as RuO ₂ is screen-printed and fired to form the resistor layer 14.

  FIG. 15D shows the first protective layer forming step. The first protective layer 15a is formed on the surface of the resistor layer 4 by screen printing using a glass paste such as a lead borosilicate glass system and baking.

  Although the illustration of the resistance value correcting step is omitted, in order to correct the resistance value to a desired value, trimming is performed using laser light while measuring the resistance value. Trimming marks are partially formed, and the resistance value is adjusted to a desired value.

  FIG. 15E shows a second protective layer forming step. A second protective layer 15b is formed by forming a layer by applying or screen printing a synthetic resin such as an epoxy resin so as to be polymerized to a part of the upper surface electrode 12 and the first protective layer 15a, and then heat-curing. Is done. The second protective layer 15 b is formed so as to cover the resistor layer 14, but in the lateral direction, the second protective layer 15 b is formed so as to protrude from the resistor layer 14 and cover a part of the upper surface electrode 2. Further, the vertical pattern of the second protective layer 15b is formed so as to have a so-called solid shape continuously in the primary dividing groove direction from the secondary dividing groove to the adjacent resistor region. The

  FIG. 15F shows a masking layer forming step. The masking layer 18 regulates the formation area of the thin film by screen-printing a masking agent on areas where the thin film described later is not formed on the upper and lower surfaces. As the masking agent, for example, cellulose resin is used. A masking layer 18 is also formed on the lower electrode 13 side.

  Next is the primary division step. A strip-shaped chip component is formed that is cracked along the primary dividing groove and the individual pieces are arranged in a strip shape in the vertical direction.

  FIG. 15G shows an end face electrode film forming step. The end face electrode film 6 is formed by attaching a metal thin film such as Ni—Cr to the front and back surfaces of the strip-shaped chip component divided into strips by a thin film forming means by sputtering.

  FIG. 15H is a masking layer removal step. When a cellulose resin is used as a masking agent, the strip-shaped chip component is washed with water to remove the masking layer. When other masking agents or resist agents are used, the masking layer is removed suitably using a solvent. By removing the masking layer, the thin film on the masking layer is also removed, and the end face electrode film 16 is formed so as to extend from the end face of the strip-shaped chip component to a part of the upper face of the second protective layer 15b.

  The strip-shaped chip component on which the end face electrode film 16 is formed is divided into individual pieces in a secondary dividing step of dividing along the secondary dividing grooves.

  FIG. 15I shows an external electrode layer forming step. An external electrode layer 17 is formed on the surface of the end face electrode film 16. In this example, a nickel plating layer 17a and a solder plating layer 17b are sequentially applied to the external electrode layer by electrolytic plating.

  In the chip resistor, the external electrode layer is formed so as to extend to a part of the upper surface of the protective layer, even in a chip resistor in which an auxiliary layer is formed on both ends of the protective layer as described in FIG. Has been done. As seen in Patent Document 6, even in a chip resistor in which an auxiliary layer is formed on both ends of a protective layer, the sputtering film in the step of forming the external electrode layer is performed using a masking layer.

  FIG. 14 is a cross-sectional view for explaining an example of a chip resistor having an auxiliary layer on the protective layer. An auxiliary layer 15c is formed at both ends of the second protective layer 15b to provide a structure with excellent mounting stability. The chip resistor shown in FIG. 14 is the same as the chip resistor described in FIG. 13 except that the auxiliary layer 15c is added, and the same reference numerals as those in FIG. 13 are given to the respective parts.

  The chip resistor described with reference to FIGS. 11 and 12 has dust on the surface of the protective layer and the protective layer at the edge of the second protective layer 15b (FIG. 11) or the auxiliary layer 15c (FIG. 12) overlapping the upper electrode 12. The plating may also extend to the surface of the protective layer due to the metal component of the upper surface electrode 12 floating on the surface. There is also a problem that such a plating elongation portion is not fixed, and the plating peels off starting from this portion. The upper surface electrode 12 contains a glass component, and the bonding of the plating is weak at the portion where the glass component is exposed on the electrode surface. For this reason, in reflow at the time of mounting, the entire plating of the external electrode layer 17 by plating covering the upper surface electrode 12 may be peeled off by being pulled by solder or the like. In particular, in a chip resistor having a nominal size of 1.0 mm × 0.5 mm or less called “1005”, such a problem is likely to occur because the electrode size is small. This tendency is particularly great in a chip resistor having a nominal size of 0.6 mm × 0.3 mm or less called “0603”.

  On the other hand, the chip resistor described with reference to FIGS. 13 and 14 can improve the corrosion resistance of the upper surface electrode because the boundary between the external electrode layer and the protective layer 15 is covered with the upper surface electrode layer including the sputtered film. There is also an advantage that the area of the external electrode layer on the upper surface side can be increased.

  However, in the chip resistor described with reference to FIGS. 13 and 14, masking is performed on the upper surface and the lower surface of the protective layer where the end face electrode layer is not formed, and a sputtered film is formed. Forming an external electrode layer by electrode plating on the surface of the film solves the problems of the dimensions and linearity of the upper surface side of the external electrode layer. The step of removing the masking film after the step is indispensable.

If a sputtered film can be formed without using a masking film, an advantage that the manufacturing process is simplified can be brought about. However, when sputtering is performed without using a masking film, as shown in FIG. 16, when the strip-shaped chip components 19 are stacked, they may not be inclined and become parallel. This causes a problem that the sputtering wraparound is insufficient and a sputtered film is not formed up to the end of the protective layer.
Japanese Patent No. 3473205 Japanese Patent No. 3825576 JP 2005-286016 A JP-A-1-189102 JP 2004-128218 A JP 2005-191404 A

  The present invention provides a chip capable of forming a metal thin film by a thin film forming means so as to extend from an end face of an insulating substrate to a part of the protective layer beyond the boundary position between the upper surface electrode and the protective layer without using a masking film. It is an object of the present invention to provide a method of manufacturing a resistor and a chip resistor manufactured by the manufacturing method.

  The present invention provides an upper electrode layer forming step in the individual resistor regions of a multi-piece insulating substrate having a product region composed of a plurality of individual resistor regions and an outer product region around the product region, After the upper electrode layer, the resistor layer, and the protective layer of the resin material were formed by the resistor layer forming step and the protective layer forming step, respectively, a strip-shaped chip component was manufactured by first dividing it into strips. A plurality of the strip-shaped chip parts are stacked, and an electrode film is formed so as to extend to a part of the protective layer beyond the boundary position between the upper surface electrode and the protective layer by a thin film forming means from the end face side obtained by primary division. In the chip resistor manufacturing method, the strip-shaped chip component is simultaneously formed in at least one layer forming step of the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step. The same layer is formed so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component also in the product outside region of the multi-cavity insulating substrate that is the product outside region in the strip. is there.

  The present invention also features a chip resistor manufactured by the above-described chip resistor manufacturing method.

  According to the chip resistor manufacturing method of the present invention, in the at least one layer forming step of the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step, The same layer is formed in a region outside the product of the multi-piece insulating substrate to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component. A layer that is formed outside this product area and that can regulate the space between the upper and lower strip-shaped chip components in a state where the strip-shaped chip components are stacked is referred to as a “space regulation layer”. When the interval regulating layer formed in the same step as at least one layer forming step among the step, the resistor layer forming step, and the protective layer forming step is overlapped with the strip-shaped chip parts after the primary division, Since the interval between the strip-shaped chip parts can be regulated, the problem as described in FIG. 16 does not occur, and the metal thin film is formed from the upper surface electrode to a part of the protective layer using the thin film forming means without using the masking layer. It is possible to form so as to extend up to. Therefore, mass production is possible, the manufacturing method is simplified, and the chip resistor can be manufactured. Therefore, a different process for forming the interval regulating layer is not required. In addition, the chip resistor manufactured by the manufacturing method of the present invention is inexpensive, and the edge of the protective layer is covered with the metal thin film by extending the end face electrode film which is a metal thin film. Since the external electrode layer is laminated, the upper surface electrode is not attacked by the atmospheric gas, and the corrosion resistance of the upper surface electrode can be improved. Further, since the external electrode layer extends to a part of the protective layer, the area of the external electrode layer on the upper surface side can be increased and the external electrode layer is plated on the metal thin film formed by the thin film forming means. There is an effect that peeling of the external electrode layer can be prevented.

  FIG. 1 is a cross-sectional view for explaining a first embodiment of the chip resistor of the present invention. In the figure, 1 is an insulating substrate, 2 is an upper electrode, 3 is a lower electrode, 4 is a resistor layer, 5 is a protective layer, 5a is a first protective layer, 5b is a second protective layer, 6 is an end face electrode film, 7 Is an external electrode layer, 7a is a nickel plating layer, and 7b is a solder plating layer.

  A pair of upper surface electrodes 2 are formed on the left and right ends of the upper surface of the insulating substrate 1 using alumina or the like, and a pair of lower surface electrodes 3 are formed on the left and right ends of the lower surface of the insulating substrate 1. The bottom electrode 3 is not necessarily required. A resistor layer 4 is formed between the upper surface electrodes so as to overlap a part of the pair of upper surface electrodes 2. A protective layer 5 is formed on the surface of the resistor layer 4. The protective layer 5 is formed so as to cover a part of the upper surface electrode 2 from the surface of the resistor layer. In this embodiment, the protective layer 5 is formed of a first protective layer 5a using glass and a second protective layer 5b using a resin such as an epoxy resin.

  The end face electrode film 6 is a thin film electrode layer formed by restricting the formation region by thin film forming means such as sputtering, and is formed on both end faces of the insulating substrate 1 and on the end faces of the upper surface electrode 2 and the lower surface electrode 3. Further, on the upper surface side, the upper electrode 2 is formed so as to extend from both ends of the upper electrode 2 to a part of the protective layer 5 beyond the edge of the protective layer 5, that is, the boundary position between the upper electrode 2 and the protective layer 5. ing. It is desirable that the inner end of the end face electrode film 6 be in a range not exceeding the position of the inner end of the upper surface electrode 2. This is because if the extension of the end face electrode film 6 to the upper surface exceeds the position above the upper surface electrode 2, a problem arises that the capacitance component increases and the high frequency characteristics deteriorate. In other words, the length of the end surface electrode film on the upper surface (the length in the lateral groove direction from the end surface) is larger than the length from the end surface to the edge of the protective layer 5, and the length of the upper surface electrode 2 (in the lateral groove direction from the end surface) Is a range smaller than the length of. Further, the lower surface side is formed so as to cover at least a part of the lower surface electrode 3 from both ends of the lower surface electrode 3. It may be formed so as to cover all of the lower surface electrode 3.

  On the end face electrode film 6, the external electrode layer 7 is formed by plating in the order of the nickel plating layer 7a and the solder plating layer 7b. The solder plating layer 7b is not limited to Sn—Pb solder material, and Sn—Ag plating or Sn plating can be used. In this specification, including these, the adhesiveness to the solder is good. This layer is called a solder plating layer.

  3 is a cross-sectional view in order of steps for explaining an example of the manufacturing method of the chip resistor described in FIG. 1, and FIGS. 4 to 8 are the manufacturing of the chip resistor of the present invention using a multi-piece substrate. It is for demonstrating the Example of a method. In the figure, the same parts as those in FIG. 1a is a primary dividing groove, 1b is a secondary dividing groove, 1A is a product area, 1B is an outside product area, 4a is a trimming mark, 8 is a spacing restriction layer, 8a is a first spacing regulation layer, and 8b is a second spacing regulation. A layer, 8c is a third interval regulating layer, and 9 is a target. 3 shows a cross-sectional view of only one chip resistor, the multi-piece insulating substrate 1 in an appropriate process is shown in FIGS. 4 to 5, the layers and films formed in the process are hatched. In order to make the order of the processes easy to see, the hatching is illustrated by hatching in which the inclination directions are alternately reversed in the sequential processes.

  3A and 4A show an insulating substrate. The insulating substrate 1 is made of an insulator made of alumina or the like, and a multi-piece insulating substrate is usually used in order to facilitate mass production. As shown in FIG. 4A, the insulating substrate 1 is generally a multi-piece insulating substrate so that a large number of chip resistors can be manufactured. The multi-piece insulating substrate is divided into individual resistor regions by dividing grooves, and the dividing grooves are primary dividing grooves (vertical grooves) in a direction perpendicular to the longitudinal direction of the resistor layer 4. And secondary dividing grooves (also referred to as transverse grooves) parallel to the longitudinal direction of the resistor layer 4 (FIG. 3). In addition, in the case of a multi-piece insulating substrate, a product is not manufactured in the entire region up to the end of the substrate, and a predetermined region in the peripheral portion is set as a non-product region 1B in which a product is not manufactured. A portion excluding the peripheral portion is defined as a product region 1A. In product area 1A, it can be said that it is divided into individual resistor areas by dividing grooves. 4A shows the upper surface side, the same dividing groove is formed on the lower surface side, and in this embodiment, the dividing groove is formed on both the upper surface side and the lower surface side. The insulated substrate 1 was used. An insulating substrate in which no dividing groove is formed may be used on the lower surface side. However, the insulating substrate with the dividing grooves formed on both sides is easy to divide. In particular, in the small-sized chip resistor of “1005” or less, the insulating substrate with the dividing grooves formed on both sides. Should be used.

  FIG. 3B shows a process of forming the upper surface electrode and the lower surface electrode. A thick film glaze paste containing conductive particles such as Ag or Ag—Pd is screen-printed on the surface of the insulating substrate 1 and baked to form the upper surface electrode 2. In the multi-cavity substrate, FIG. 4B shows a lower electrode forming process, and FIG. 4C shows an upper electrode forming process. In this embodiment, the lower surface electrode is formed first, and then the upper surface electrode is formed. However, the order may be reversed.

  As shown in FIG. 4 (B), the lower surface electrode 3 is continuously formed in the resistor region that straddles the primary division groove 1a and is adjacent in the primary division groove direction, and is also continuous in the region outside the product. Formed. However, the adjacent resistor regions may be formed so as to be electrically separated, and also separated into the region outside the product, and in the step of forming the bottom electrode layer, the same layer as the bottom electrode layer is formed at the same time. Also good.

  As shown in FIG. 4C, the upper electrode 2 is formed so as to straddle the primary dividing groove 1a and to electrically isolate the resistor regions adjacent to each other in the primary dividing groove direction. The same layer is formed at the same time in the same process as the first interval regulating layer 8a in the region outside the product, separately from the upper surface electrode 2. Since an external electrode layer is formed on the upper surface electrode 2 as described later, the upper surface electrode 2 corresponds to an internal electrode.

3C and 4D show a resistance layer forming process. A resistor paste such as RuO ₂ is screen-printed and fired to form the resistor layer 4. A layer of resistive paste is printed and baked in the same process also on the first interval regulating layer formed in the outside product region, and formed as the second interval regulating layer 8b.

  3D and 4E show the first protective layer forming step. The first protective layer 5a is formed on the surface of the resistor layer 4 by screen printing using a glass paste such as lead borosilicate glass and baking. The first protective layer 5a is used as a protective layer for the laser light used in the resistance value correcting step, but the formation of the first protective layer 5a may be omitted. In this embodiment, the first protective layer 5a is not formed on the second interval regulating layer formed in the region outside the product, but it may be formed in the same process.

  FIG. 5F shows a resistance value correcting step. In order to correct the resistance value of the resistor layer 4 to a desired value, trimming is performed using laser light while measuring the resistance value. Trimming marks 4a are partially formed, and the resistance value is adjusted to a desired value.

  3E and 5G show the second protective layer forming step. By applying or screen printing a synthetic resin, for example, an epoxy resin so as to be polymerized into a part of the upper surface electrode 2 and the first protective layer 5a (or the resistor layer 3 when the first protective layer 5a is omitted). The second protective layer 5b is formed by layer formation and heat curing. The second protective layer 5b made of synthetic resin is advantageous in that it does not give a thermal history compared to glass. The second protective layer 5 b is formed so as to cover the resistor layer 4, but in the lateral direction, the second protective layer 5 b is formed so as to protrude from the resistor layer 4 and cover a part of the upper surface electrode 2. Further, the pattern in the secondary dividing groove direction of the second protective layer 5b is formed so as to have a so-called solid shape continuously in the vertical direction from the secondary dividing groove to the adjacent resistor region. Alternatively, each of the resistor layers may be formed so as to cover a part of the resistor layer 4 and the upper surface electrode 2 so as not to reach the lateral groove. Also in the second protective layer forming step, as shown in FIG. 5G, the same layer is formed on the second interval restricting layer as the third interval restricting layer 8c in the same process in the region outside the product.

  FIGS. 5 (H) and 6 (I) are plan views showing an outline before the primary division process of the multi-piece substrate, and the chip resistances in the manufacturing process shown in FIG. 3 (E) arranged vertically and horizontally. The number of units is shown in a small number for the sake of clarity of the figure, and is actually much larger than 8 × 11 as shown in the figure. Depending on the size of the insulating substrate and the size of the chip resistor, The number of chip resistors manufactured from a single multi-chip substrate is determined.

  FIG. 5H shows the upper surface side of the substrate. In the product region, the second protective layer 5b is formed in a row, and the upper surface electrode 2 can be seen therebetween. Space regulation layers 8 in which first to third space regulation layers are laminated are formed on the left and right sides (both ends in the primary division groove direction) of the outside product region.

  FIG. 6I shows the lower surface side of the substrate. The lower surface electrodes 3 are formed in a row from the product region to the left and right sides of the non-product region (both ends in the primary dividing groove direction).

  6J, FIG. 6K, and FIG. 7L are primary division processes. A strip-shaped chip component is formed that is cracked along the primary dividing groove and the individual pieces are arranged in a strip shape in the vertical direction (primary dividing groove direction). FIG. 6J shows a strip-shaped chip component viewed from above, and the second protective layer 5b is formed in one row, and the upper surface electrode 2 is visible above and below. A space regulating layer 8 is formed in the left and right product outer regions. FIG. 6K is a side view of the strip-shaped chip component, in which the second protective layer 5b and the space regulating layer 8 are illustrated on the left and right sides thereof. The top electrode and the bottom electrode are not shown. FIG. 7L is a perspective view of the strip-shaped chip component. An interval regulating layer 8 is formed on both ends of the upper surface of the insulating substrate 1, and the upper electrode 2 and the protective layer 5 are formed therebetween. As can be seen from FIG. 6 (J), the lower surface electrode 3 extends integrally to the left and right product outer regions, but may be formed separately for each individual resistor region. . The bottom electrode need not be formed in the left and right product outer regions.However, as in this embodiment, the left and right product outer regions are also provided with the bottom electrode in order to have the function of the space regulating layer. May be.

  7 (M) and 7 (N) are diagrams for explaining a state in which the strip-shaped chip parts are stacked, and FIG. 7 (M) is an enlarged front view of the vicinity of the end in the stacked state. (N) is a perspective view of a stacked state. In these drawings, a part of the number in the middle in the actual stacked state is shown. 7 (M) and 7 (N), the lower surface electrode 3 is illustrated as being formed separately for each resistor region, unlike FIG. 4 (B). Even when the lower surface electrodes 3 are formed separately, the same layer may be formed simultaneously in the region outside the product to form the interval regulating layer 8k. However, it is not necessary to form the space regulation layer 8k in consideration of the layer configuration of the space regulation layer described above.

  In the state where the strip-shaped chip parts are stacked, a pressing force is applied using a weight or a spring. As seen in FIG. 7M, there is a gap between the upper electrode 2 and the lower electrode 3, and a sputtered film can be formed up to a part of the protective layer 5 through this gap. In this stacked state, as shown in FIG. 7 (M), the distance between the strip-shaped chip parts is the distance formed over the entire width in the short side direction in the region outside the product on the upper surface of the strip-shaped chip parts. Since it is regulated by the regulation layer 8, the inclined state as described with reference to FIG. 16 does not occur, and sputtering is performed almost uniformly on both end sides of the protective layer 5 in the longitudinal direction (secondary dividing groove direction) of the resistor layer. A metal thin film can be formed.

  3F and 8 show the end face electrode film forming step. The end face electrode film 6 is formed by performing sputtering from the target 9 from the end face side of the primarily divided chip parts stacked. The incident angle of sputtering is preferably substantially perpendicular to the primary divided end face of the strip-shaped chip component. By this sputtering, a metal thin film such as Ni—Cr is attached to the front and back surfaces of the strip-shaped chip component, and the end face electrode film 6 is formed. Since the metal thin film is not formed in the portion where the second protective layer 5b is in close contact with the strip-shaped chip component thereon, the end face electrode film 6 is connected to the top face electrode 2 from the end face of the insulating substrate 1 on the upper face side. It is formed to extend to a part of the second protective layer 5b beyond the boundary position with the second protective layer 5b, and is formed to at least a part of the lower surface electrode 2 on the lower surface side.

  The strip-shaped chip component on which the end face electrode film 6 is formed is divided into individual pieces in a secondary dividing step of dividing along the secondary dividing grooves. The primary division process and the secondary division process are not limited to cracking. A method of dividing by using a dicing blade may be employed. In this method, an insulating substrate in which primary divided grooves and secondary divided grooves are not necessarily formed may be used.

  FIG. 3G shows an external electrode layer forming step. When the end face electrode film 6 is formed on the surface of the end face electrode film 6 and part of the lower face electrode 3, an external electrode layer is formed on the surface of the lower face electrode 3 that is not covered by the end face electrode film 6. In this embodiment, the external electrode layer is formed by sequentially electrolytically plating a nickel plating layer 7a and a solder plating layer 7b.

  In the above-described steps, the order of the upper surface electrode forming step and the resistor layer forming step may be reversed. That is, the resistor layer may be formed after the upper surface electrode is formed, the resistor layer may be formed first, and then the upper surface electrode may be formed. In other words, the resistor layer may be overlaid on the upper surface electrode, or the upper surface electrode may be overlaid on the resistor layer. Therefore, in the chip resistor of the present invention, the structure in which the resistor layer is formed on the upper surface electrode so as to overlap a part thereof, and the upper surface electrode is provided on the resistor layer so as to overlap the part thereof. It includes both formed structures.

  In the chip resistor manufacturing method according to the above-described embodiment, the end face electrode film and the bottom electrode 3 are formed on the lower surface side of the insulating substrate by forming the bottom electrode 3 by screen printing and baking the thick film glaze paste. Although the external electrode layer is formed, the external electrode layer is formed on the back surface of the insulating substrate 1 without forming the bottom electrode 3 after the end surface electrode film is directly formed on the back surface of the insulating substrate 1 by the above-described end surface electrode film formation step. Alternatively, no electrode may be formed on the lower surface of the insulating substrate 1.

  The thickness of the interval restriction layer will be described. In the chip resistor described with reference to FIG. 1, the height of the surface of the protective layer 5 from the upper surface of the insulating substrate 1 can be calculated by arithmetically summing the height of each layer and each film in the manufacturing process described above. It is the total thickness of the resistor layer 4, the first protective layer 5a, and the second protective layer 5b. The thicknesses of the interval restricting layers are the first interval restricting layer 8a (upper surface electrode 2) and the second interval restricting layer 8b. Since the total thickness of the (resistor layer 4) and the third interval regulating layer 8c (second protective layer 5b), the height of the interval regulating layer 8 is higher than the height of the second protective layer 5b. It can be said that the thickness is reduced by the thickness of the layer 5a. However, in actuality, the thickness is not always arithmetically added due to the overlap between the upper surface electrode 2 and the resistor layer 4 or in the manufacturing process such as printing / curing. As will be described later, in consideration of compression due to the elasticity of the protective layer of the resin material, the height of the space regulating layer 8 before stacking is preferably made lower than the height of the second protective layer 5b. From this design of height, the layer configuration of the spacing regulating layer produced in the same process may be selected, and not necessarily all of the upper surface electrode 2, the resistor layer 4, and the second protective layer 5b. In addition, the layer configuration of the interval regulating layer manufactured in the same process may be selected from the layers and films formed in the product region including the first protective layer 5a. In this selection, when only one layer is selected, it is better to select the thickest layer. Therefore, when selecting one of the upper electrode layer, the resistor layer, and the protective layer of the resin material as the spacing regulating layer, when selecting only one layer, the thickest layer, in one example, protecting the resin material A layer is selected. Therefore, in this example, it is preferable to select at least the second protective layer 5b (resin layer).

  In the state where the strip-shaped chip parts are stacked, a pressing force is applied using a weight or a spring. By this pressing force, the protective layer of the resin material formed in a slightly chevron shape due to the sagging is slightly compressed and the central portion becomes flat. Therefore, in order to prevent the metal thin film formed by sputtering formed so as to extend to a part of the protective layer from excessively extending, the thickness of the gap regulating layer is considered in consideration of the pressing force and the amount of compressive deformation of the protective layer. It is preferable to determine the thickness (layer configuration of the interval regulating layer). The upper surface of the space regulation layer formed on the upper surface of the lower strip-shaped chip component does not completely adhere to the lower surface of the strip-shaped chip component located on the upper surface of the lower strip-shaped chip component because the thickness of the space regulation layer is somewhat thin. In the pressed stacked state, even if the strip-shaped chip component is inclined, the inclination is not so large as to generate the portion 20 where the end portions contact with each other as described in FIG. Since the described problem can be avoided, only one layer or two layers may be selected from the upper electrode layer, the resistor layer, and the protective layer of the resin material. However, in the pressed stacking state, the spacing regulation layer is such that the upper surface of the spacing regulation layer formed on the upper surface of the lower strip-shaped chip component is completely in close contact with the lower surface of the strip-shaped chip component positioned thereon. It is better to select the layer structure.

  The shape of the interval regulating layer will be described with reference to FIG. FIG. 9 is a diagram for explaining three typical patterns. A part of the non-product area of the multi-chip substrate is illustrated on the left side, and one of the non-product areas of the strip-shaped chip parts is illustrated on the right side. The parts are illustrated. In the figure, 1 is an insulating substrate, 1a is a primary dividing groove, and 8 is an interval regulating layer.

  FIG. 9A shows a pattern in which the space regulating layer 8 is continuously formed between the primary dividing grooves 1a in the region outside the product of the multi-piece substrate. This pattern is the pattern of the interval regulating layer in FIGS. 4C, 4D, and 5G. In the strip-shaped chip component, the interval regulating layer 8 is formed over the entire width in the short side direction.

  FIG. 9B shows a pattern in which an interval regulating layer 8 having a length shorter than the distance between the primary division grooves 1a is formed across the primary division grooves 1a in the area outside the product of the multi-piece substrate. is there. For example, it is the same length as the length of the lower surface electrode 3 and the upper surface electrode 2 in FIG. 4 (B) and FIG. 4 (C). In the strip-shaped chip component, the space regulating layers 8 are formed at both ends in the short side direction.

  FIG. 9C shows a pattern in which the space regulating layer 8 is formed in the vicinity of the primary division groove 1a so as not to straddle the primary division groove 1a in the non-product region of the multi-piece substrate. is there. In the strip-shaped chip component, the interval regulating layer 8 is formed in the vicinity of both end portions in the short side direction. In this pattern, the two space regulation layers 8 formed in the vicinity of both end portions of one strip-shaped chip component may be connected.

  In any pattern, the interval regulating layer 8 includes at least the vicinity of both ends in the short side direction of the strip-shaped chip component in the region outside the product of the multi-piece insulating substrate that is the region outside the product in the strip-shaped chip component. It is necessary from the viewpoint of solving the problem described with reference to FIG. In addition, each layer in the case of forming the interval regulating layer by a plurality of layers may be formed in the same pattern, but if it is formed so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component. Therefore, the plurality of layers may be formed in different patterns.

  FIG. 2 is a cross-sectional view for explaining a second embodiment of the chip resistor of the present invention. In the figure, the same parts as those in FIG. 5c is an auxiliary layer. The chip resistor of this embodiment is the same as the chip resistor described in the first embodiment except that the auxiliary layer 5c is added, and each part is described with the same reference numerals as in FIG. Is omitted.

  In this embodiment, since the vicinity of the central portion of the surface of the protective layer 5 in the first embodiment is rounded so that the chip resistor is mounted on a printed circuit board or the like, the chip resistor is mounted by a suction nozzle. When the chip resistor is mounted on a predetermined land on the printed circuit board by pressing with a vacuum nozzle, the pressing force concentrates on the top of the rounded protective layer 16 on the chip resistor surface side, This is a countermeasure taken in view of the fact that the resistor may be cracked. The problem of this cracking is that the problem of cracking increases as the thickness of the insulating substrate decreases with the miniaturization of the chip resistor.

  In the second embodiment, two rows of apexes are formed by the auxiliary layer 5 c at both ends of the protective layer 5. The auxiliary layer 5c is formed in parallel with the primary dividing groove (end surface of the insulating substrate). As a result, the top of the two rows of auxiliary layers 5c formed higher than the top of the rounded chevron can be stably adsorbed to the suction nozzle. Further, when mounting on a predetermined land of the printed circuit board, the pressing force of the suction nozzle can be applied to the back electrode located below the auxiliary layer 5c, and the problem of cracking can be prevented.

  In this embodiment, the end electrode layer 6 on the upper surface extends from the end surfaces of both ends of the insulating substrate 1 to the edge of the protective layer 5, that is, beyond the boundary position between the upper electrode 2 and the protective layer 5, and the top of the protective layer. In the example, it is formed so as to extend to the vicinity of the top of the auxiliary layer 5c.

  The chip resistor manufacturing method described with reference to FIG. 2 only needs to add a step of forming the auxiliary layer 5c to the manufacturing method described with reference to FIGS. That is, the second protective layer is formed by coating and screen printing a synthetic resin, for example, an epoxy resin in the second protective layer forming step in FIGS. 3 (E) and 5 (G), followed by heat curing. After 5b is formed, the auxiliary layer 5c is formed by the same method on both ends of the second protective layer 5b by the auxiliary layer forming step shown in FIG. The order of the second protective layer forming step and the auxiliary layer forming step may be reversed to form the auxiliary layer first, and then form the second protective layer. Also in this auxiliary layer forming step, the space regulating layer 8d is formed. However, as described above, the spacing regulating layer 5d may not be formed in the auxiliary layer forming step in consideration of the layer configuration of the spacing regulating layer.

  In addition, although sputtering was used as a thin film formation means in the end face electrode film, it is not limited to this. Thin film forming means such as ion plating or vapor deposition may be used.

It is sectional drawing for demonstrating the 1st Example of the chip resistor of this invention. It is sectional drawing for demonstrating the 2nd Example of the chip resistor of this invention. FIG. 4 is a cross-sectional view in order of steps for explaining an example of the manufacturing method of the chip resistor explained in FIG. 1. It is sectional drawing for demonstrating the 2nd Example of the chip resistor of this invention. It is explanatory drawing of one Example of the manufacturing method of the chip resistor of this invention. It is explanatory drawing of one Example of the manufacturing method of the chip resistor of this invention. It is explanatory drawing of one Example of the manufacturing method of the chip resistor of this invention. It is explanatory drawing of one Example of the manufacturing method of the chip resistor of this invention. It is explanatory drawing of the pattern of a space | interval control layer. It is explanatory drawing of the other Example of the manufacturing method of the chip resistor of this invention. It is sectional drawing for demonstrating an example of the conventional chip resistor. It is sectional drawing for demonstrating another example of the conventional chip resistor. FIG. 12 is a cross-sectional view in order of steps for explaining an example of the manufacturing method of the chip resistor explained in FIG. 11. It is sectional drawing for demonstrating another example of the conventional chip resistor. It is sectional drawing for demonstrating another example of the conventional chip resistor. It is explanatory drawing of the problem in the formation method of the metal thin film by sputtering.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 1a ... Vertical groove, 1b ... Horizontal groove, 2 ... Upper surface electrode, 3 ... Lower surface electrode, 4 ... Resistor layer, 5 ... Protective layer, 5a ... 1st protective layer, 5b ... 2nd protective layer, 5c ... auxiliary layer, 6 ... end face electrode film, 7 ... external electrode layer, 7a ... nickel plating layer, 7b ... solder plating layer, 8 ... masking layer.

Claims (11)

A top electrode layer forming step and a resistor layer forming are performed on the individual resistor regions of a multi-piece insulating substrate having a product region composed of a plurality of individual resistor regions and an outer product region at the periphery of the product region. After forming the upper surface electrode layer, the resistor layer, and the protective layer of the resin material by the step and the protective layer forming step, respectively, the strip-shaped chip component is manufactured by first dividing it into strips, and the plurality of the strips thus manufactured A step of forming an electrode film so as to extend to a part of the protective layer over the boundary position between the upper surface electrode and the protective layer by thin film forming means from the end face side of the primary division by overlapping the chip-shaped chip parts In the manufacturing method of the chip resistor,
The multi-cavity insulating substrate that simultaneously serves as an out-of-product region in the strip-shaped chip component in at least one layer forming step of the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step A method of manufacturing a chip resistor, wherein the same layer is formed in the outside region of the product so as to include at least both end portions in the short side direction of the strip-shaped chip component.   The one layer forming step is a layer forming step of forming a layer having the thickest layer formed in the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step. A method for manufacturing a chip resistor according to claim 1. A top electrode layer forming step and a resistor layer forming are performed on the individual resistor regions of a multi-piece insulating substrate having a product region composed of a plurality of individual resistor regions and an outer product region at the periphery of the product region. After forming the upper surface electrode layer, the resistor layer, and the protective layer of the resin material by the step and the protective layer forming step, respectively, the strip-shaped chip component is manufactured by first dividing it into strips, and the plurality of the strips thus manufactured A step of forming an electrode film so as to extend to a part of the protective layer over the boundary position between the upper surface electrode and the protective layer by thin film forming means from the end face side of the primary division by overlapping the chip-shaped chip parts In the manufacturing method of the chip resistor,
In the layer forming step of any two of the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step, the plurality of multi-chips that respectively become regions outside the product in the strip-shaped chip component, respectively. A method of manufacturing a chip resistor, wherein the same layer is formed also in a region outside the product of the insulating substrate so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component. A top electrode layer forming step and a resistor layer forming are performed on the individual resistor regions of a multi-piece insulating substrate having a product region composed of a plurality of individual resistor regions and an outer product region at the periphery of the product region. After forming the upper surface electrode layer, the resistor layer, and the protective layer of the resin material by the step and the protective layer forming step, respectively, the strip-shaped chip component is manufactured by first dividing it into strips, and the plurality of the strips thus manufactured A step of forming an electrode film so as to extend to a part of the protective layer over the boundary position between the upper surface electrode and the protective layer by thin film forming means from the end face side of the primary division by overlapping the chip-shaped chip parts In the manufacturing method of the chip resistor,
The product of the multi-cavity insulating substrate that simultaneously becomes an out-of-product region in the strip-shaped chip component in all the layer forming steps of the upper surface electrode layer forming step, the resistor layer forming step, and the protective layer forming step. A method for manufacturing a chip resistor, wherein the same layer is formed in the outer region so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component.   The method further includes a glass protective layer forming step of forming a protective layer of a glass material under the protective layer, and in the glass protective layer forming step, the multi-cavity insulation serving as a region outside the product in the strip-shaped chip component The method for manufacturing a chip resistor according to claim 1, wherein the same layer is not formed in a region outside the product of the substrate.   The method further includes a glass protective layer forming step of forming a protective layer of a glass material under the protective layer, and in the glass protective layer forming step, the multiple pieces that become the product outside region in the strip-shaped chip component are simultaneously obtained. 5. The same layer as claimed in claim 1, wherein the same layer is also formed in an outside product region of the insulating substrate so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component. Method of manufacturing a chip resistor.   After forming the protective layer of the resin material in the protective layer forming step, the method further includes an auxiliary layer forming step of forming an auxiliary layer of the resin material on both ends of the protective layer. In the auxiliary layer forming step, the strip The chip resistor according to any one of claims 1 to 6, wherein the same layer is not formed in an area outside the product of the multi-piece insulating substrate which is an area outside the product in a chip-shaped chip component. Production method.   After forming the protective layer of the resin material in the protective layer forming step, it further includes an auxiliary layer forming step of forming an auxiliary layer of the resin material on both ends of the protective layer, and also in the auxiliary layer forming step, Forming the same layer so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component also in the non-product region of the multi-cavity insulating substrate that is the region outside the product of the strip-shaped chip component The method for manufacturing a chip resistor according to claim 1, wherein the chip resistor is a semiconductor chip.   Before or after the upper surface electrode forming step, there is a lower surface electrode forming step, and in the lower surface electrode forming step, the multi-cavity insulating substrate that is the product outer region in the strip-shaped chip component has a product outer region. 9. The method of manufacturing a chip resistor according to claim 1, wherein the same layer is not formed.   Before or after the upper surface electrode forming step, there is a lower surface electrode forming step, and at the same time in the lower surface electrode forming step, the product out-of-product region of the multi-piece insulating substrate that becomes an out-of-product region in the strip-shaped chip component 9. The method of manufacturing a chip resistor according to claim 1, wherein the same layer is formed so as to include at least the vicinity of both ends in the short side direction of the strip-shaped chip component. .   A chip resistor manufactured by the method for manufacturing a chip resistor according to claim 1.

Images