WO2014109224A1

WO2014109224A1 - Chip resistor

Info

Publication number: WO2014109224A1
Application number: PCT/JP2013/084491
Authority: WO
Inventors: 臣祐千原; 泰赤羽
Original assignee: コーア株式会社
Priority date: 2013-01-11
Filing date: 2013-12-24
Publication date: 2014-07-17
Also published as: JP2014135427A

Abstract

Provided is a chip resistor capable of preventing damage due to heat shock over all of a solder join part containing a back-surface electrode and an end-face electrode. The chip resistor (1) is provided with: surface electrodes (4) provided to the surface of a ceramic substrate (2); a resistor body (5) connecting the pair of surface electrodes (4); a back-surface electrode (3) provided to the back surface of the ceramic substrate (2); an insulating protective layer (an undercoat layer (7) and an overcoat layer (8)) for coating the resistor body (5); a pair of end-face electrodes (6) bridging between the surface electrodes (4) and the back-surface electrode (3), the end-face electrodes (6) provided to both end faces of the ceramic substrate (2); a barrier layer (9) coating the end-face electrodes (6), the surface electrodes (4), and the back-surface electrode (3); and a solder plating (10) layer coating the barrier layer (9), the end-face electrodes (6) being formed of a spatter film containing chrome and the barrier layer (9) material, and the barrier layer (9) being formed of a plating layer comprising nickel or copper having a thickness of 8-30 µm.

Description

Chip resistor

The present invention relates to a surface mount type chip resistor which is mounted on a circuit board by soldering.

FIG. 5 is a cross-sectional view schematically showing a conventional general chip resistor. The chip resistor 21 shown in the figure is made of a rectangular parallelepiped ceramic substrate 22, a pair of surface electrodes 23 made of sintered silver or the like provided at both ends in the longitudinal direction of the upper surface of the ceramic substrate 22, and ruthenium oxide or the like. A resistor 24 provided between the pair of surface electrodes 23, an insulating protective layer 25 covering the resistor 24, and provided at both ends in the longitudinal direction of the lower surface of the ceramic substrate 22 made of sintered silver or the like. A pair of back surface electrodes 26 and a pair of end surface electrodes 27 provided on both end surfaces in the longitudinal direction of the ceramic substrate 22 to bridge the front surface electrode 23 and the back surface electrode 26. A plating layer 28 is attached to the front surface electrode 23, the end surface electrode 27, and the back surface electrode 26 that are continuous in a shape.

In the chip resistor 21, the ceramic substrate 22 is obtained by dividing a large substrate along a vertical and horizontal dividing groove, and a large number of ceramic substrates 22 are obtained. The back electrode 26, the protective layer 25, and the like are collectively formed. The resistance value of the chip resistor 21 is adjusted by forming a trimming groove (not shown) in the resistor 24. The protective layer 25 generally has a two-layer structure, and an undercoat layer formed before adjusting the resistance value for trimming the resistor 24 and an overcoat layer formed after adjusting the resistance value are laminated. ing. The end surface electrode 27 is formed on a split surface of a strip-shaped substrate obtained by first dividing a large substrate on which a large number of protective layers 25 are formed. After the end surface electrode 27 is formed, the strip-shaped substrate is separated into pieces ( The chip layer is divided into two parts, and the plated layer 28 is deposited on each chip. This plating layer 28 includes an innermost nickel (Ni) plating layer in close contact with the base electrode layer, and an outermost solder (Sn / Pb) plating layer or tin (Sn) plating layer exposed on the outer surface. It has a laminated structure of more than one layer.

By the way, this type of chip resistor 21 is surface-mounted by mounting a back electrode 26 on a land provided on a circuit board and soldering, but the thermal environment changes to the chip resistor 21 after mounting. Is repeated (hereinafter referred to as heat shock), the solder joints are easily damaged by thermal stress and cracks are likely to occur. When a crack due to heat shock occurs in the solder joint, the solder joint is a place where the back electrode 26 of the chip resistor 21 and the land of the circuit board are electrically and mechanically connected. It may lead to poor conduction.

Therefore, conventionally, a chip resistor has been proposed in which the back electrode has a two-layer structure of an inner layer made of baked silver and an outer layer made of a conductive resin so that thermal stress acting on the solder joint can be reduced (for example, , See Patent Document 1). In such a conventional chip resistor, since the outer layer of the back electrode that contacts the solder joint on the land of the circuit board is made of a conductive resin, it acts on the solder joint compared to the case where the back electrode is made only of sintered silver. The effect of relaxing the thermal stress is expected.

JP 2008-84905 A

However, in the conventional chip resistor described in Patent Document 1, although consideration is given to relieve the thermal stress acting on the solder joint between the land of the circuit board and the back electrode, the solder joint of the end face electrode portion is considered. No measures are taken for thermal stress acting on the parts, so when mounted on a circuit board such as an in-vehicle electronic device that has a long life requirement for heat shock, the solder joints of the end face electrode parts are affected by heat shock. Cracks are likely to occur. In addition, when the melting point of the solder paste used with the recent lead-free process becomes high, mounting on the circuit board becomes a reflow condition at a high temperature, so that the resin component of the back electrode deteriorates during reflow, There is a risk that the back electrode peels off at the portion. Furthermore, since the back electrode has a two-layer structure of baked silver and conductive resin, there is a problem that the manufacturing process becomes complicated and the manufacturing cost increases.

The present invention has been made in view of such a state of the art, and an object thereof is to provide a chip resistor that can prevent damage due to heat shock of the entire solder joint including the back electrode and the end electrode. It is in.

In order to achieve the above object, a chip resistor of the present invention includes a pair of surface electrodes provided at both longitudinal ends of the surface of the ceramic substrate, and the ceramic substrate connected to the pair of surface electrodes. A resistor provided on the front surface, a pair of back electrodes provided on both ends in the longitudinal direction of the back surface of the ceramic substrate, an insulating protective layer covering the resistor, and provided on both end surfaces of the ceramic substrate A pair of end surface electrodes that bridge the front surface electrode and the back surface electrode, a barrier layer that covers the end surface electrode, the front surface electrode, and the back surface electrode, and a solder plating layer that covers the barrier layer; The end face electrode is formed of a sputtered film containing chromium and the material of the barrier layer, and the barrier layer is a plating made of nickel or copper having a thickness of 8 μm to 30 μm. It was configured to be formed of layers.

In the chip resistor configured as described above, since the end face electrode, the front surface electrode, and the back surface electrode are covered with a barrier layer formed with a thick plating thickness (8 μm to 30 μm), the barrier layer is subjected to thermal stress (heat shock). On the other hand, it becomes a cushion material, and fatigue and cracks due to the thermal stress of the entire solder joint including the back electrode and the end electrode can be prevented. In addition, since the end face electrode is formed of a sputtered film containing chromium and a barrier layer material (nickel or copper) having good adhesion to the ceramic substrate, the boundary portion between the barrier layer and the end face electrode is strengthened. Also, it can cope with internal stress generated when the barrier layer is formed thick.

In the chip resistor of the present invention, the end face electrode, the front surface electrode, and the back surface electrode are covered with a thick (8 to 30 μm) barrier layer, so that the barrier layer becomes a cushioning material against thermal stress (heat shock). Fatigue and cracks due to the thermal stress of the entire solder joint including the back electrode and the end electrode can be prevented. In addition, since the end face electrode is formed of a sputtered film containing chromium and a barrier layer material (nickel or copper) having good adhesion to the ceramic substrate, the boundary portion between the barrier layer and the end face electrode is strengthened. Further, fatigue and cracks due to internal stress generated when the barrier layer is formed thick can be prevented. In addition, this chip resistor does not require a complicated manufacturing process of the back electrode, and therefore it is easy to avoid an increase in cost. Therefore, a chip resistor that is resistant to heat shock and has a long service life can be provided at low cost.

It is sectional drawing which shows typically the chip resistor which concerns on the example of embodiment of this invention. It is sectional drawing of the principal part which shows the mounting state of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is sectional drawing which shows the conventional common chip resistor typically.

Hereinafter, embodiments of the invention will be described with reference to the drawings. As shown in FIG. 1, a chip resistor 1 according to an embodiment of the present invention is provided at both ends in the longitudinal direction of a rectangular parallelepiped ceramic substrate 2 and the back surface (lower surface in FIG. 1) of the ceramic substrate 2. A pair of backside electrodes 3, a pair of front surface electrodes 4 provided at both ends in the longitudinal direction of the surface of the ceramic substrate 2 (upper surface in FIG. 1), and both ends of the pair of surface electrodes 4 are overlapped with the ceramic substrate 2. A resistor 5 provided on the surface of the ceramic substrate 2, a pair of end face electrodes 6 provided on both end faces in the longitudinal direction of the ceramic substrate 2 to bridge the back electrode 3 and the surface electrode 4, and the resistor 5. Two-layer protective layer (undercoat layer 7 and overcoat layer 8), barrier layer 9 applied to the front electrode 4, the end face electrode 6 and the back electrode 3, and solder plating applied to the barrier layer 9 Layer 10 and It is.

The ceramic substrate 2 is an insulating substrate containing alumina as a main component, and the ceramic substrate 2 is obtained by dividing a large-size substrate, which will be described later, along a vertical and horizontal dividing groove. The back electrode 3 is obtained by screen-printing Ag paste and drying and firing, and the front electrode 4 is also obtained by screen-printing Ag paste and drying and firing. The resistor 5 is obtained by screen-printing a resistor paste such as ruthenium oxide, drying and firing, and the resistance value of the chip resistor 1 is adjusted by forming a trimming groove (not shown) in the resistor 5. Has been. The end face electrode 6 is formed on the end face of the ceramic substrate 2 by sputtering, and is made of a sputtered film containing chromium (Cr) having good adhesion to the ceramic substrate 2 and a material of a barrier layer 9 described later. The barrier layer 9 is a plating layer made of nickel (Ni) or copper (Cu), and the solder plating layer 10 is a plating layer made of tin (Sn) -lead (Pb), lead-free Sn, or the like. When manufacturing the chip resistor 1, a large number of front surface electrodes 4, resistors 5, back surface electrodes 3, undercoat layers 7, overcoat layers 8, and the like are collectively formed on a large substrate.

As shown in FIG. 2, the chip resistor 1 is mounted on a land 31 provided on a circuit board 30 with the back electrode 3 facing downward, and is the outermost solder plating layer 10 covering the barrier layer 9. Are mounted by solder 32. Since the barrier layer 9 is formed to have a thickness of 8 μm to 30 μm so as to cover the end face electrode 6, the front surface electrode 4, and the back surface electrode 3, the barrier layer 9 becomes a cushioning material against thermal stress (heat shock), Fatigue and cracks due to the thermal stress of the entire solder joint including the end face electrode 6 and the back face electrode 3 can be prevented. Moreover, since the end face electrode 6 covered with the barrier layer 9 is formed of a sputtered film containing chromium having good adhesion to the ceramic substrate 2 and the material of the barrier layer 9 (nickel or copper), the barrier layer 9 and the end face electrode 6 are strengthened, and fatigue and cracks due to internal stress generated when the barrier layer 9 is formed thick can be prevented.

Next, the manufacturing process of the chip resistor 1 configured as described above will be described with reference to FIGS. The first to tenth steps will be described with reference to FIG. 3, and the eleventh to fifteenth steps will be described with reference to FIG.

First, as shown in FIG. 3 (a), as shown in FIG. 3A, an unbaked back electrode 3 is formed by screen-printing and drying Ag paste on the back surface of a large substrate 40 on which a large number of ceramic substrates 2 are taken. After the formation, as a second step, the unfired surface electrode 4 is formed by screen-printing and drying an Ag / Pd paste on the surface of the large substrate 40. The large-sized substrate 40 is provided with a primary division groove and a secondary division groove (both not shown) in advance in a lattice shape, and each square divided by both division grooves is equivalent to one piece. This is the chip area.

Next, after firing the unfired back electrode 3 and the front electrode 4 at a high temperature of about 850 ° C. as a third step, a resistor paste such as ruthenium oxide is screened on the surface of the large substrate 40 as a fourth step. By printing and drying, an unfired resistor 5 is formed in each chip region as shown in FIG. At that time, both ends in the longitudinal direction of the resistor 5 are overlapped with the surface electrodes 4 provided at both ends in the longitudinal direction of each chip region. In the next fifth step, the resistor 5 is fired at a high temperature of about 850 ° C. Note that the firing of the third step described above may be omitted, and the back electrode 3, the front electrode 4 and the resistor 5 may be fired simultaneously in this fifth step. In this case, the firing step is reduced to reduce the cost. It becomes possible.

Next, as a sixth step, after a glass paste is screen-printed in a region covering the resistor 5, the glass paste is baked at a high temperature of about 600 ° C. in the seventh step, as shown in FIG. Then, an undercoat layer 7 corresponding to the primary protective coat covering the resistor 5 is formed. Next, as an eighth step, the undercoat layer 7 and the resistor 5 are irradiated with laser to form a trimming groove (not shown), thereby adjusting to a desired resistance value.

Next, as a ninth step, after screen printing a glass paste or an epoxy resin paste so as to cover the undercoat layer 7, this is baked in the tenth step (for example, the glass paste is fired at about 600 ° C., The resin paste is heated and cured at about 200 ° C.) to form an overcoat layer 8 corresponding to a secondary protective coat covering the resistor 5 and the undercoat layer 7. This overcoat layer 8 is for protecting the resistor 5 from the external environment. By forming the undercoat layer 7 and the overcoat layer 8 in this way, a protective layer having a two-layer structure covering the resistor 5 is obtained.

The process up to this point is a batch process for the large-sized substrate 40 for taking a large number of pieces, but in the next eleventh step, the primary break processing is performed in which the large-sized substrate 40 is divided into strips along the primary dividing grooves by a break. I do. Thereby, the strip-shaped substrate 41 provided with a plurality of chip regions is obtained.

Then, in the next twelfth step, by sputtering Cr / Ni on the divided surface of the strip-shaped substrate 41, as shown in FIG. 4A, an end face electrode that bridges the back electrode 3 and the front electrode 4 6 is formed. This end face electrode 6 contains chromium (Cr) having good adhesion to the ceramic substrate 2 (large format substrate 40 or strip substrate 41) and nickel (Ni) which is a material of the barrier layer 9 formed in the next step. The thickness of the sputtered film is set to 500 mm or more in order to prevent erosion of the solder.

Thereafter, as a thirteenth step, secondary break processing is performed in which the strip-shaped substrate 41 is divided along the secondary division grooves by a break. Thereby, an individual piece (chip alone) having the same size as the chip resistor 1 is obtained.

Next, as a fourteenth step, by applying electrolytic plating to the individual ceramic substrate 2 of each chip, as shown in FIG. A continuous barrier layer 9 is formed. The barrier layer 9 is a nickel plating layer covering the front electrode 4, the end face electrode 6 and the back electrode 3, and the film thickness is set to 8 μm to 30 μm so as to be a cushioning material against heat shock. Here, if the thickness of the barrier layer 9 is thinner than 8 μm, the cushioning effect becomes insufficient and it becomes difficult to prevent cracks. Conversely, if the thickness of the barrier layer 9 exceeds 30 μm, the barrier layer 9 Since the generated internal stress becomes excessively large, the thickness of the barrier layer 9 is preferably set to 8 μm to 30 μm.

Next, as a fifteenth step, a solder plating layer 10 is formed by electrolytic plating so as to cover the barrier layer 9, thereby forming a two-layered plating layer (barrier layer 9 as shown in FIG. 4C). And the chip resistor 1 having the solder plating layer 10) are completed.

As described above, the chip resistor 1 according to this embodiment is connected to the pair of surface electrodes 4 provided at both ends in the longitudinal direction of the surface of the ceramic substrate 2 and the pair of surface electrodes 4. A resistor 5 provided on the surface of the ceramic substrate 2, a pair of back electrodes 3 provided at both longitudinal ends of the back surface of the ceramic substrate 2, and an insulating protective layer (undercoat layer) covering the resistor 5 7 and the overcoat layer 8), a pair of end face electrodes 6 provided on both end faces of the ceramic substrate 2 to bridge the front face electrode 4 and the back face electrode 3, and the end face electrode 6, the front face electrode 4 and the back face A barrier layer 9 covering the electrode 3 and a solder plating layer 10 covering the barrier layer 9 are provided. The end face electrode 6 is formed of a sputtered film containing chromium and the material of the barrier layer 9, and the barrier Since the layer 9 is formed of a plating layer made of nickel or copper having a thickness of 8 μm to 30 μm, the barrier layer 9 serves as a cushioning material against thermal stress (heat shock), and solder bonding including the back electrode 3 and the end surface electrode 6 Fatigue and cracks resulting from the thermal stress of the entire part can be prevented. In addition, since the end face electrode 6 covered with the barrier layer 9 is formed of a sputtered film containing chromium having good adhesion to the ceramic substrate 2 and the material of the barrier layer 9 (nickel or copper), the barrier layer 9 And the end face electrode 6 are strengthened, and fatigue and cracks due to internal stress generated when the barrier layer 9 is formed thick can be prevented.

In the embodiment described above, the barrier layer 9 is formed of a nickel plating layer and the end face electrode 6 is formed of a sputtered film containing chromium and nickel. However, the barrier layer 9 is made of a nickel plating layer. Instead, a copper (Cu) plating layer can also be used. In this case, the end face electrode containing chromium and copper is formed by sputtering Cr / Cu on the dividing surface of the strip-shaped substrate 41 in the twelfth step described above. 6 may be formed. Further, the end face electrode 6 may contain titanium (Ti) or the like other than that as long as it contains at least chromium and the material of the barrier layer 9 (nickel or copper). When the nickel plating layer is used, the end face electrode 6 can be formed of a Cr—Ni—Cu sputtered film or a Cr—Ni—Ti sputtered film.

1 Chip Resistor 2 Ceramic Base 3 Back Electrode 4 Front Electrode 5 Resistor 6 End Electrode 7 Undercoat Layer (Protective Layer)
8 Overcoat layer (protective layer)
9 Barrier layer 10 Solder plating layer 30 Circuit board 31 Land 32 Solder 40 Large format board 41 Strip board

Claims

A pair of surface electrodes provided at both longitudinal ends of the surface of the ceramic substrate, a resistor provided on the surface of the ceramic substrate so as to be connected to the pair of surface electrodes, and a longitudinal direction of the back surface of the ceramic substrate A pair of back electrodes provided at both ends, an insulating protective layer covering the resistor, and a pair provided on both ends of the ceramic substrate to bridge the surface electrode and the back electrode An end face electrode, a barrier layer covering the end face electrode, the surface electrode and the back electrode, and a solder plating layer covering the barrier layer,
The end face electrode is formed of a sputtered film containing chromium and the material of the barrier layer, and the barrier layer is formed of a plated layer made of nickel or copper having a thickness of 8 μm to 30 μm. Resistor.