JP2008235723A - Wafer body structure and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer body structure in which post-processing such as packaging can be performed upon a part of a semiconductor substrate with an integrated circuit formed therein, using a manufacturing facility designed for semiconductor substrates whose size is smaller than that of the semiconductor substrate, and a manufacturing method thereof. <P>SOLUTION: A wafer body structure includes a carrier wafer 10, a wafer chip 21 that is bonded on one side of the carrier wafer 10 and smaller than the carrier wafer, and a filling layer 30 filling the space around the wafer chip 21 on the carrier wafer 10. The wafer chip 21 is a part of a semiconductor substrate larger than the carrier wafer 10 and is positioned inside an edge of the carrier wafer 10 as a whole. A planar shape of the filling layer 30 is approximately identical to an outer form of the carrier wafer 10 and the thickness of the filling layer 30 is approximately equal to that of the wafer chip 21. The carrier wafer 10 and the filling layer 30 have a coefficient of thermal expansion equal to that of the wafer chip 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wafer structure and a method for manufacturing the same, and more specifically, formed on a wafer-like carrier substrate by bonding a part of a semiconductor substrate larger than the carrier substrate, for example, as a whole. The present invention relates to a wafer structure that can be handled in the same manner as a wafer-like semiconductor substrate having substantially the same size, and a manufacturing method thereof.

  In recent years, integrated circuit devices have been further miniaturized and highly functionalized, but the cost of manufacturing equipment has been increasing rapidly. Therefore, in order to reduce the manufacturing cost, in order to obtain more integrated circuit devices (integrated circuit chips) from a single semiconductor wafer (hereinafter also simply referred to as a wafer), the scale of the wafer is increased along with the miniaturization of the process. Is progressing. This is because, since it is necessary to go through hundreds of steps to manufacture an integrated circuit device, the larger the wafer diameter, the more integrated circuit devices that can be processed at a time, which is advantageous in terms of manufacturing cost. It is. Recently, a wafer having a diameter of 12 inches (about 30 cm) has been widely used.

As a related technology of the present invention, there is an embedded wafer level chip size package (EWLP) technology. In EWLP, a plurality of WLPs (LSI chips) are die-bonded at predetermined positions on a flat base plate, and then the resin is embedded to the very top of the WLP by utilizing the thickness of the embedded WLP. Therefore, the wiring can be formed by the build-up method. When embedding (sealing) with resin is completed, an insulating layer and a through hole are formed in the resin and then copper plating is performed to form a circuit layer electrically connected to the aluminum electrode of the WLP (LSI chip). . Then, external connection terminals such as solder balls are formed on the surface of the resin, and then dicing is performed to separate each WLP. As a result, a chip size package is obtained in which WLP is embedded in the resin and external connection terminals are formed on the surface thereof (see Non-Patent Document 1).
(Electronic Materials July 2005 issue "Mounting Technology Guidebook 2005" published by Industrial Research Council, pp 183 to 187)

  By the way, for example, when post-processing such as packaging is performed on each of the integrated circuits formed in a wafer having a diameter of 12 inches while maintaining the wafer, for example, a process of forming a wafer level chip size package In the case of carrying out the above, it is not always necessary to carry out the wafer as it is in consideration of only the execution of the subsequent processing. For example, the wafer may be cut into ¼, and post-treatment may be performed using the obtained wafer piece (¼ cut piece). By doing so, for example, it becomes possible to perform subsequent processing in an existing previous generation manufacturing facility designed for a wafer having a diameter of 8 inches (about 20 cm), so that only the existing manufacturing facility can be effectively used. In addition, the manufacturing cost of the integrated circuit device is reduced, which is convenient.

  However, since the integrated circuit device manufacturing facility is designed to perform each process in the form of a substantially circular wafer, a quarter wafer piece cannot be passed through the manufacturing facility as it is. In addition, it is not preferable that the wafer is cut by a dicing method using a conventional general dicing saw because a cutting margin of the dicing saw is generated between integrated circuit regions (chip regions) in the wafer. .

  Accordingly, an object of the present invention is to provide a semiconductor substrate (for example, a semiconductor having a diameter of 8 inches) smaller than the semiconductor substrate with respect to a part of a semiconductor substrate (for example, a semiconductor wafer having a diameter of 12 inches) having an integrated circuit formed therein. It is an object of the present invention to provide a wafer structure capable of performing post-processing such as packaging using a manufacturing facility designed for (wafer).

  Another object of the present invention is to provide a method for manufacturing a wafer structure, which can manufacture the above-described wafer structure at a low cost with a simple method.

  Other objects of the present invention which are not specified here will become apparent from the following description and the accompanying drawings.

(1) In a first aspect of the present invention, a wafer structure is provided. This wafer structure is
A wafer-like carrier substrate;
A first semiconductor substrate having a planar shape smaller than the carrier substrate, bonded to one plane of the carrier substrate;
A filler layer that embeds a space around the first semiconductor substrate on the carrier substrate;
The first semiconductor substrate is a part of a second semiconductor substrate having a larger planar shape than the carrier substrate;
The first semiconductor substrate is entirely disposed inside the periphery of the carrier substrate,
The planar shape of the filler layer is substantially the same as the outer shape of the carrier substrate, and the thickness of the filler layer is substantially the same as the thickness of the first semiconductor substrate. The surface of the substrate is exposed from the filler layer,
The carrier substrate and the filler layer have a thermal expansion coefficient equivalent to that of the first semiconductor substrate.

  (2) In the wafer structure according to the first aspect of the present invention, as described above, one plane of the wafer-like carrier substrate is a part of the second semiconductor substrate having a larger planar shape than the carrier substrate. A first semiconductor substrate having a planar shape smaller than that of the carrier substrate is bonded. The first semiconductor substrate is entirely disposed inside the periphery of the carrier substrate, that is, the entire first semiconductor substrate is on the carrier substrate and there is no portion protruding from the carrier substrate. .

  In addition, a space around the first semiconductor substrate on the carrier substrate is filled with the filler layer. The planar shape of the filler layer is formed substantially the same as the outer shape of the carrier substrate, and the thickness of the filler layer is substantially the same as the thickness of the first semiconductor substrate, The surface of the first semiconductor substrate is exposed from the filler layer.

  Therefore, the outer shape of the wafer structure according to the first aspect of the present invention is equivalent to a single semiconductor wafer having substantially the same planar shape as the carrier substrate. The same handling as a single wafer is possible.

  Moreover, since the carrier substrate and the filler layer have the same thermal expansion coefficient as that of the first semiconductor substrate, the carrier substrate, the filler layer, and the first semiconductor substrate have a thermal expansion coefficient. Due to the difference, the phenomenon of peeling at the joint surfaces does not occur. Therefore, it is possible to perform a desired process such as packaging on the first semiconductor substrate from the surface of the first semiconductor substrate exposed from the filler layer.

  Therefore, the wafer structure according to the first aspect of the present invention is a semiconductor substrate having a size smaller than that of a part of a semiconductor substrate (for example, a semiconductor wafer having a diameter of 12 inches) having an integrated circuit formed therein. Post-processing such as packaging can be performed using a manufacturing facility designed for a semiconductor wafer (for example, a semiconductor wafer having a diameter of 8 inches).

  (3) In a preferred example of the wafer structure according to the first aspect of the present invention, the first semiconductor substrate is a cut piece of the second semiconductor substrate in which an integrated circuit is formed.

  In another preferred example of the wafer structure according to the first aspect of the present invention, the same single-crystal or polycrystalline semiconductor substrate as the first semiconductor substrate is used as the carrier substrate.

  In this example, the same semiconductor layer as the first semiconductor substrate is preferably used as the filler layer, or a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used.

  In another preferred example of the wafer structure according to the first aspect of the present invention, the first semiconductor substrate is made of single crystal silicon, and the carrier substrate is made of single crystal silicon or polycrystalline silicon.

  In this example, a silicon layer is preferably used as the filler layer, or a glass layer having a thermal expansion coefficient equivalent to that of silicon is used.

  In still another preferred example of the wafer structure according to the first aspect of the present invention, the first semiconductor substrate is formed of a compound semiconductor, and the carrier substrate is the same monocrystalline or polycrystalline compound semiconductor as the first semiconductor substrate. It is formed from a substrate.

  In this example, preferably, a layer of the same compound semiconductor as the first semiconductor substrate is used as the filler layer, or a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used.

  In still another preferred example of the wafer structure according to the first aspect of the present invention, the carrier substrate has a workability equivalent to that of the first semiconductor substrate. In this example, there is an advantage that the process for the first semiconductor substrate can be performed from the back side of the carrier substrate through the carrier substrate. The “workability” in this example refers to the processing conditions set for the first semiconductor substrate when desired processing (for example, etching, thin film formation, etc.) is performed on the first semiconductor substrate. This means that the same processing is performed on the carrier substrate.

  In this example, it is preferable that the integrated circuit inside the first semiconductor substrate is disposed on the side opposite to the carrier substrate. By doing so, it is possible to form an electrode or the like that penetrates the carrier substrate and reaches the integrated circuit from the back surface side of the first semiconductor substrate.

(4) In the 2nd viewpoint of this invention, the manufacturing method of a wafer structure is provided. The manufacturing method of this wafer structure is as follows:
Bonding a first semiconductor substrate having a planar shape smaller than the carrier substrate to one plane of a wafer-like carrier substrate so that the entire semiconductor substrate is disposed inside the periphery of the carrier substrate;
By embedding a filler in a space around the first semiconductor substrate on the carrier substrate, the planar shape is substantially the same as the outer shape of the carrier substrate, and the thickness is equal to the thickness of the first semiconductor substrate. Forming a filler layer that is substantially identical,
The filler layer is formed such that a surface of the first semiconductor substrate is exposed from the filler layer;
The carrier substrate and the filler layer have a thermal expansion coefficient equivalent to that of the first semiconductor substrate.

  (5) In the method for manufacturing a wafer structure according to the second aspect of the present invention, the wafer structure is manufactured through the steps as described above. Therefore, the wafer structure according to the first aspect of the present invention is manufactured. Obviously you can.

  In addition, the step of bonding the first semiconductor substrate onto the carrier substrate can be easily performed by using a known anodic bonding method without using an adhesive or a pressure-sensitive adhesive. The step of forming the filler layer by embedding a filler in a space existing around the first semiconductor substrate on the carrier substrate is performed by, for example, filling and solidifying a known semiconductor fine powder using an appropriate mold. This can be easily implemented. In order to expose the surface of the first semiconductor substrate from the filler layer, the filler layer may be polished using, for example, a CMP (Chemical Mechanical Polishing) method.

  Therefore, according to the method for manufacturing a wafer structure according to the second aspect of the present invention, the wafer structure can be manufactured by a simple method and at low cost.

  (6) In a preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, the first semiconductor substrate is a cut piece of the second semiconductor substrate in which an integrated circuit is formed.

  In another preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, the step of bonding the first semiconductor substrate onto the carrier substrate is performed using an anodic bonding method. This is because the first semiconductor substrate can be firmly bonded onto the carrier substrate without using an adhesive or an adhesive.

  In still another preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, the step of forming the filler layer includes forming the carrier substrate having the first semiconductor substrate fixed on one surface thereof as a mold. And a step of filling and solidifying the filler powder in a molding space formed around the first semiconductor substrate on the carrier substrate inside the mold. This is because the filler layer can be formed easily and in a short time.

  In this example, if necessary, a step of polishing or etching the filler layer covering the surface of the first semiconductor substrate is performed in order to expose the surface of the first semiconductor substrate from the filler layer. . In the case of polishing, this step is preferably performed by a known CMP method. In the case of etching, this step is preferably performed by a known dry etching method.

  In this example, any powder such as semiconductor powder or glass powder may be used as the filler powder as long as the coefficient of thermal expansion is the same as that of the first semiconductor substrate. However, it is preferable to use the same semiconductor powder as the first semiconductor substrate.

  However, the step of forming the filler layer may be performed by depositing a thin film of the filler, if there is no cost problem, or by filling a SOG (Spin-On-Glass) material. You may implement by heat-hardening.

  In still another preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, a single crystal silicon substrate is used as the first semiconductor substrate, and a single crystal or polycrystalline silicon substrate is used as the carrier substrate. Is done.

  In this example, a silicon layer is preferably used as the filler layer, or a glass layer having a thermal expansion coefficient equivalent to that of silicon is used.

  In still another preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, a compound semiconductor substrate is used as the first semiconductor substrate, and the same single crystal or multiple as the first semiconductor substrate is used as the carrier substrate. A crystalline compound semiconductor substrate is used.

  In this example, preferably, a layer of the same compound semiconductor as the first semiconductor substrate is used as the filler layer, or a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used.

  In still another preferred example of the method for manufacturing a wafer structure according to the second aspect of the present invention, the first semiconductor substrate has a planar shape larger than that of the first semiconductor substrate using a stealth dicing technique. It is formed by cutting the substrate. In this example, there is an advantage that the second semiconductor substrate can be cut with almost no kerfloss (cutting allowance) and without generating chipping or cracks at the cut portion.

  (7) In the wafer structure according to the first aspect of the present invention and the method for producing a wafer structure according to the second aspect of the present invention, it goes without saying that any semiconductor substrate can be used as the first semiconductor substrate. However, a single crystal silicon substrate or a compound semiconductor substrate such as GaAs, which is generally used for integrated circuits, is preferable.

  The carrier substrate has the same coefficient of thermal expansion as that of the first semiconductor substrate, and even if used in combination with the first semiconductor substrate, the operation of the integrated circuit in the first semiconductor substrate is hindered. Any material can be used as long as it does not occur, but a single crystal or polycrystalline silicon substrate and a single crystal or polycrystalline compound semiconductor substrate are preferable. An insulating film may be formed on the surface of the carrier substrate.

Any filler can be used as long as it has the same coefficient of thermal expansion as that of the first semiconductor substrate. The same semiconductor powder as the first semiconductor substrate (for example, silicon powder) can be preferably used, but glass powder having the same coefficient of thermal expansion as the first semiconductor substrate (for example, borosilicate (B ₂ O ₃ .SiO _4)). System) glass) or the like.

  The carrier substrate and the filler are required to have the same coefficient of thermal expansion as that of the first semiconductor substrate. Here, “equivalent” is not only the same, but is almost the same. When the desired processing such as packaging is performed on the first semiconductor substrate, the first semiconductor substrate, the carrier substrate, and the first semiconductor substrate are caused by a difference in thermal expansion coefficient. This means that the phenomenon of peeling at the joint surface does not occur.

  As long as an integrated circuit is formed therein, the thickness of the first semiconductor substrate is not limited, but for example, a range of 0.1 μm to 750 μm is preferable.

  The thickness of the carrier substrate may be any thickness as long as it can be flowed to a desired manufacturing facility in a state where the wafer substrate is bonded to the first semiconductor substrate. For example, a range of 500 μm to 1000 μm is preferable. It is.

  (8) The technique disclosed in Non-Patent Document 1 is a technique in which a plurality of WLPs (LSI chips) are die-bonded on a base plate and a resin is embedded to the very upper surface of these WLPs. Clearly different.

  In the wafer structure according to the first aspect of the present invention, a part of a semiconductor substrate (for example, a semiconductor wafer having a diameter of 12 inches) in which an integrated circuit is formed has a smaller semiconductor substrate (for example, a semiconductor substrate having a smaller size). It is possible to perform post-processing such as packaging using a manufacturing facility designed for a semiconductor wafer having a diameter of 8 inches.

  In the method for manufacturing a wafer structure according to the second aspect of the present invention, there is an effect that the wafer structure according to the first aspect of the present invention can be manufactured by a simple method and at low cost. .

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

(Configuration of the first embodiment)
FIG. 1 shows a wafer structure 1 according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of the wafer structure 1, FIG. 1 (b) is a front view thereof, and FIG. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 2 is a plan view showing an example of a processing semiconductor wafer 20 used for the wafer structure 1.

  As shown in FIG. 1, this wafer structure 1 includes a carrier wafer 10 having a diameter of 8 inches, and a wafer piece (first surface) 21e having one main surface (back surface) 21e bonded to the surface of the carrier wafer (carrier substrate) 10. Semiconductor substrate) 21 and a filler layer 30 filled in a substantially annular space around the wafer piece 21. The carrier wafer 10 and the filler layer 30 are formed of a material having a thermal expansion coefficient equivalent to that of the wafer piece 21. The carrier wafer 10 and the wafer piece 21 are directly bonded by a known anodic bonding method, and no adhesive or pressure-sensitive adhesive is present between the bonded surfaces.

  As shown in FIG. 2, the wafer piece 21 is one piece obtained by cutting a processing semiconductor wafer (second semiconductor substrate) 20 having a diameter of 12 inches almost equally into four pieces, and has a diameter of 8 inches. It has a smaller planar shape than the carrier wafer 10. Therefore, the entire wafer piece 21 is on the carrier wafer 10 and does not protrude from the periphery of the carrier wafer 10. The entire back surface 21 e of the wafer piece 21 is in contact with the surface of the carrier wafer 10. The other main surface (front surface) 21 a of the wafer piece 21 is exposed from the filler layer 30. Here, the “surface” of the wafer piece 21 refers to a plane on the side of the wafer piece 21 where the integrated circuit region C is formed.

  The surface 30 a of the filler layer 30 is in the same plane as the surface 21 a of the wafer piece 21. In other words, the surface 30 a of the filler layer 30 is flush with the surface 21 a of the wafer piece 21. The surface 21 a of the wafer piece 21 is exposed from the surface 30 a of the filler layer 30. Therefore, it is possible to process the wafer piece 21 directly from above (surface side). Further, it is possible to process the wafer piece 21 from below (back side) via the carrier wafer 10.

  Inside the wafer piece 21, a plurality of integrated circuit regions C are formed on the surface side thereof (see FIG. 9). These integrated circuit regions C are regularly arranged inside the wafer piece 21. A set of integrated circuits (not shown) is built in each integrated circuit region C.

  The filler layer 30 is a layer formed by filling a substantially annular space around the wafer piece 21 on the carrier wafer 10 with a predetermined filler. The planar shape (contour) of the filler layer 30 is the same as that of the carrier wafer 10. The thickness of the filler layer 30 is the same as the thickness of the wafer piece 21. Therefore, the filler layer 30 and the wafer piece 21 form a single layer on the carrier wafer 10 having the same planar shape as the carrier wafer 10. It is also possible that the wafer piece 21 is embedded inside the filler layer 30 on the carrier wafer 10.

  As described above, the wafer structure 1 has a two-layer structure including the carrier wafer 10 and the layer formed of the filler layer 30 and the wafer piece 21 formed on the carrier wafer 10. It can be considered an inch wafer. Therefore, it can be introduced into equipment for wafers having a diameter of 8 inches, and mechanical operations such as conveyance and gripping can be performed as they are, and packaging is performed for each integrated circuit region C of the wafer piece 21. It is possible to perform necessary processing (processing).

  The wafer piece 21 is fixed to the carrier wafer 10 by known plasma anodic bonding. Accordingly, as shown in FIGS. 1B and 1C, there is no adhesive or adhesive between the wafer piece 21 and the carrier wafer 10, and the back surface 21 e of the wafer piece 21 and the surface of the carrier wafer 10. Are in direct contact with each other.

  As shown in FIG. 1A, the arrangement of the wafer piece 21 on the carrier wafer 10 is such that one of the two straight portions 21b perpendicular to each other with the corner portion 21c of the wafer piece 21 sandwiched between the carrier wafer 10 and It is set to be parallel to the orientation flat 11. This is because the crystal orientation of the wafer piece 21 can be easily discriminated by using the orientation flat 11 of the carrier wafer 10 as a clue.

  As shown in FIG. 2, the wafer piece 21 is formed by cutting a processing semiconductor wafer 20 having a diameter of 12 inches into a cutting line 26 orthogonal to the orientation flat 25 and parallel to the orientation flat 25 (in other words, orthogonal to the cutting line 26. The plane shape is a fan shape with a central angle of 90 °. By cutting along the cutting lines 26 and 27, the semiconductor wafer 20 for processing is divided into four, resulting in quarter wafer pieces 21, 22, 23, and 24. Accordingly, the two cut sides of the wafer piece 21, that is, the straight line portion 21b are orthogonal to each other, and the corner portion 21c at the intersection of the straight line portion 21b is a right angle. This also applies to the wafer piece 22 that has a mirror image relationship with the wafer piece 21. The other two wafer pieces 23 and 24 have a planar shape that approximates a sector shape with a central angle of 90 °, but the portions corresponding to the orientation flats 25 are missing, so that the wafer pieces 21 and 22 is different.

  These wafer pieces 21, 22, 23, and 24 are all obtained by equally dividing the processing semiconductor wafer 20 having a diameter of 12 inches into quarters, so that each side is 6 inches (about 15 cm) or less. It has a smaller planar shape than a semiconductor wafer having a diameter of 8 inches (about 20 cm). Therefore, when the wafer piece 21 is bonded onto the carrier wafer 10, the entire wafer piece 21 is positioned on the carrier wafer 10, and the wafer piece 21 does not protrude outward from the outer peripheral edge of the carrier wafer 10.

  Here, a single crystal silicon wafer is used as the processing semiconductor wafer 20. Accordingly, the wafer piece 21 bonded onto the carrier wafer 10 is made of single crystal silicon. The carrier wafer 10 is made of polycrystalline silicon, that is, a polycrystalline silicon wafer. The filler layer 30 is obtained by filling a fine powder of polycrystalline silicon and curing it into a layer. Accordingly, the carrier wafer 10 and the filler layer 30 are both made of polycrystalline silicon, and the same material as the wafer piece 21 made of single crystal silicon. Therefore, these three have the same thermal expansion coefficient, and their workability with respect to etching, thin film deposition, and the like is almost the same.

The filler layer 30 is not silicon powder, but glass powder having a thermal expansion coefficient equivalent to silicon (for example, borosilicate glass powder), or silicon powder and low thermal expansion polyimide resin (thermal expansion coefficient is 3.0 to 4.5 × 10 ⁻⁷ cm / cm / ° C.) or the like.

  The thickness of the processing semiconductor wafer 20 and the carrier wafer 10 is not limited, but the thickness of the processing semiconductor wafer 20 is, for example, 100 μm, and the thickness of the carrier wafer 10 is, for example, 200 μm. Alternatively, the thickness of the processing semiconductor wafer 20 may be 50 μm, the thickness of the carrier wafer 10 may be 600 to 720 μm, for example, the thickness of the processing semiconductor wafer 20 may be 10 μm, and the thickness of the carrier wafer 10 may be, for example, It is good also as 450 micrometers.

  As described above in detail, in the wafer structure 1 according to the first embodiment of the present invention, the wafer-like carrier substrate, that is, the surface (one plane) of the carrier wafer 10 has a planar shape larger than that of the carrier wafer 10. A wafer piece 21 (first semiconductor substrate), which is a cut piece of the semiconductor wafer 20 for use (second semiconductor substrate) and has a planar shape smaller than that of the carrier wafer 10, is joined. The whole wafer piece 21 is arranged inside the periphery of the carrier wafer 10, that is, the whole wafer piece 21 is on the carrier wafer 10, and there is no portion protruding from the carrier wafer 10.

  Further, the space around the wafer piece 21 on the carrier wafer 10 is filled with the filler layer 30. The planar shape of the filler layer 30 is formed substantially the same as the outer shape of the carrier wafer 10, and the thickness of the filler layer 30 is substantially the same as the thickness of the wafer piece 21. The surface 21 a of 21 is exposed from the filler layer 30.

  Therefore, the outer shape of the wafer structure 1 is equivalent to a single semiconductor wafer having a plane shape substantially the same as that of the carrier wafer 10, and handling equivalent to that of a single wafer in mechanical operations such as conveyance and gripping. Is possible.

  Moreover, since the carrier wafer 10 and the filler layer 30 are made of the same silicon as the wafer piece 21, they have not only the same thermal expansion coefficient but also the same workability. For this reason, the phenomenon that the carrier wafer 10, the filler layer 30, and the wafer piece 21 are separated from each other due to the difference in thermal expansion coefficient does not occur, and the wafer exposed from the filler layer 30. The desired processing such as packaging can be performed on the wafer piece 21 without hindrance not only from the front side of the piece 21 but also from the back side of the wafer piece 21 via the carrier wafer 10.

  Therefore, the wafer structure 1 has a semiconductor substrate (for example, a semiconductor having a diameter of 8 inches) smaller than the semiconductor substrate with respect to a part of a semiconductor substrate (for example, a semiconductor wafer having a diameter of 12 inches) having an integrated circuit formed therein. It is possible to perform post-processing such as packaging without any trouble using a manufacturing facility designed for a wafer.

  The wafer structure 1 is used to cut a wafer piece 21, which is a cut piece of a 12-inch diameter silicon wafer 20 having a large number of integrated circuit regions C formed therein, and has a diameter of 8 inches smaller than the wafer piece 21. FIG. 9 shows an example of forming a chip size package for each integrated circuit region C using a manufacturing facility designed for a silicon wafer.

  FIG. 9 shows a situation in which the embedded electrode 70 is formed from the back surface 21 e side of the wafer piece 21 for each of the integrated circuit regions C inside the wafer piece 21.

  First, after forming a mask by photolithography, the carrier wafer 10 is selectively removed from the back side of the wafer structure 1 manufactured as described above by dry etching using the mask. A through hole 71 is formed in the carrier wafer 10. Next, the wafer piece 21 is selectively removed from the back surface side of the wafer structure 1 by a dry etching method using the same mask, and a through hole 72 is formed in the wafer piece 21. The through hole 72 communicates with the through hole 71 and reaches a conductive region or a wiring film (not shown) in the integrated circuit region C.

Next, an insulating film 73 such as silicon dioxide (SiO ₂ ) is formed on the inner wall surfaces of the through holes 71 and 72 by, for example, a CVD (Chemical Vapor Deposition) method to cover the entire inner wall surface. At this time, since the insulating film 73 is also formed on the conductive area of the corresponding integrated circuit area C or the exposed surface of the wiring film at the tip of the through hole 72, it is removed by the dry etching method.

  Next, after depositing tungsten (W) from the back surface of the carrier wafer 10 by, for example, the CVD method, the W film on the back surface of the carrier wafer 10 is selectively removed by the CMP method, so that the inside of the through holes 71 and 72 is obtained. The conductor 74 is formed by leaving the W film. The conductor 74 is in contact with the conductive region of the corresponding integrated circuit region C or the exposed surface of the wiring film. Polycrystalline silicon or the like may be used instead of W.

  As described above, the embedded electrode 70 penetrating the carrier wafer 10 and the wafer piece 21 and electrically connected to the corresponding integrated circuit region C is formed. Thereafter, if the external electrode electrically connected to the buried electrode 70 is formed by a known method, the packaging process is completed. Finally, if the carrier wafer 10 and the wafer piece 21 are diced together along the dicing lines 28 and 29 of the wafer piece 21, a plurality of chip-like integrated circuit devices for each integrated circuit region C are obtained simultaneously. These integrated circuit devices have a CSP (Chip-Size Package) because the package is almost the same size as the chip.

  The process after the formation of the embedded electrode 70 is well known and will not be described in detail. For example, (1) an insulating film is formed on the back surface of the carrier wafer 10, and (2) the insulating film of (1) (3) (2) The conductor is embedded in the through hole, and (4) (3) the solder ball as the external electrode is formed at the end of the conductor in order. Just do it.

(Production method of the first embodiment)
Next, a method for manufacturing the wafer structure 1 having the above-described configuration will be described with reference to FIGS.

  First, as shown in FIG. 2, a processing semiconductor wafer 20 made of single crystal silicon having a diameter of 12 inches is prepared. The semiconductor wafer 20 has a large number of integrated circuit regions C formed therein and has not yet been packaged. Each of the integrated circuit regions C is subjected to predetermined packaging as described below, and then divided into individual pieces for each integrated circuit region C by dicing to obtain a chip-like integrated circuit device. It is done.

  An example of the arrangement of the integrated circuit region C of the processing semiconductor wafer 20 is shown in FIG. As shown in FIG. 7, a large number of integrated circuit regions C are formed in a region on the surface side of the processing semiconductor wafer 20, and an integrated circuit is formed in each of the integrated circuit regions C. The integrated circuit regions C are regularly arranged in the up and down direction and the left and right direction in FIG. 7 (direction parallel to the surface of the processing semiconductor wafer 20), and between the adjacent integrated circuit regions C, dicing lines 28 are respectively provided. Is formed. At the time of dicing, the dicing saw is moved along the dicing line 28. Therefore, the gap between adjacent chip regions C is considered in consideration of the width of a portion (cutting allowance) cut and removed by the cutter. Street) T is formed. Therefore, the integrated circuit regions C are arranged apart from each other by the gap (street) T.

  Next, as shown in FIG. 2, the semiconductor wafer 20 for processing is evenly cut along cutting lines 26 and 27 orthogonal to each other to obtain ¼ wafer pieces 21, 22, 23 and 24. This cutting uses a “stealth dicing” technique and does not use a dicing saw. A technique called “stealth dicing” is a technique in which a laser beam having a wavelength that passes through a silicon wafer is condensed to form a locally altered portion at and near the condensing portion of the silicon wafer. Is a technology that separates from the inside. The division is performed by growing a crack on the surface of the silicon wafer by applying an external stress such as a tape expand. This is because when stealth dicing is used, an altered portion is simply formed inside the silicon wafer along the scanning line of the laser beam, and the silicon wafer is not divided and maintains the wafer state.

  The principle of “stealth dicing” is as follows. First, laser light having a wavelength that is transparent to a semiconductor wafer is condensed by an objective lens optical system so as to be focused on the inside of the semiconductor wafer. A laser beam that has very high light condensing performance, can be focused to the diffraction limit level, and is capable of high-repetition and short-pulse oscillation. A density state is formed. Further, when the laser beam that has shown transmission characteristics with respect to the semiconductor wafer exceeds a certain peak power density in the focusing process, the semiconductor wafer locally exhibits very high absorption characteristics due to the nonlinear absorption effect. Therefore, if the nonlinear absorption effect is generated only near the focal point inside the semiconductor wafer by optimizing the optical system and laser characteristics, laser processing can be performed locally and selectively only inside the semiconductor wafer. it can. At the same time, if the relative position of the laser beam and the semiconductor wafer is changed according to the dicing pattern, dicing can be realized without damaging the front and back surfaces of the semiconductor wafer. In this way, stealth dicing cleaves a semiconductor wafer from the inside (see Hamamatsu Photonics' technical document “Stealth Dicing Technology and its Applications” published in March 2005).

  According to stealth dicing, it can be divided with little kerf loss. Therefore, as shown in FIG. 7, when the cutting lines 26 and 27 of the processing semiconductor wafer 20 are arranged at the center of the gap (street) T between the chip regions C, the processing semiconductor wafer 20 is cut without cutting allowance. It is divided almost as it is along the lines 26 and 27, and becomes four wafer pieces 21, 22, 23, and 24. For this reason, chipping and cracks do not occur at the cutting location, and the two sides of each of the four wafer pieces 21, 22, 23, and 24 along the cutting lines 26 and 27 are kept linear, and the cutting line The corners of each of the wafer pieces 21, 22, 23, 24 in the vicinity of the intersection of 26 and 27 are also kept at a right angle. Therefore, as described above, if the wafer piece 21 is positioned so as to be aligned with the orientation flat 25 of the carrier wafer 10 by using, for example, one of the two sides (straight line portion 21b) of the wafer piece 21. The crystal orientation of the wafer piece 21 can be determined using the orientation flat 25. This also applies to the other wafer pieces 22, 23, 24.

  Of the four wafer pieces 21, 22, 23 and 24 thus obtained, the wafer piece 21 is selected, and after placing and positioning on the surface of the carrier wafer 10 as shown in FIG. Bonding is performed by the “plasma anodic bonding” method. Do not use adhesives or adhesives. At this time, the orientation (posture) of the wafer piece 21 with respect to the carrier wafer 10 is set so that one of the two cut sides 21 a of the wafer piece 21 is parallel to the orientation flat 11 of the carrier wafer 10. The state at this time is as shown in FIG.

  “Anodic bonding” is generally known as a method of bonding by bonding glass and silicon, metal, etc., and applying heat and voltage. The principle is that at the same time as heating, a voltage is applied with the glass side as the cathode and the silicon side as the anode, so that the positive ions in the glass are forcibly diffused to the cathode side, and electrostatic attraction is generated between the glass and silicon. It is generated to promote adhesion, and glass and silicon are chemically reacted to join. Anodic bonding is also used for bonding silicon and silicon, silicon and metal, silicon and ceramics, and is also applied to bonding of semiconductors other than silicon and bonding of glass and glass.

Further, during anodic bonding, for example, oxygen (O ₂ ) plasma is generated in the chamber of the anodic bonding apparatus to perform ashing (O ₂ plasma ashing). Thereby, since the joint surface of both is activated, joint strength improves. Such a process is called “plasma anodic bonding”.

  The application of the voltage at the time of anodic bonding is performed, for example, so that the wafer piece 21 serves as an anode and the carrier wafer 10 serves as a cathode. The conditions at that time are, for example, temperature = 160 ° C., applied voltage = 100 V, applied pressure = 1000 N, and application time of voltage and pressure = 5 to 60 minutes.

  A method of bonding the wafer piece 21 to the surface of the carrier wafer 10 without using an adhesive or an adhesive is not limited to the anodic bonding method. Any method other than the anodic bonding method can be used as long as the wafer piece 21 can be bonded to the surface of the carrier wafer 10 without using an adhesive or an adhesive.

  Next, the carrier wafer 10 having the wafer piece 21 bonded to the surface is accommodated in the forming die 40 shown in FIG. The mold 40 has an internal space into which the carrier wafer 10 can be fitted, and the internal space has a planar shape reflecting the orientation flat 11 of the carrier wafer 10. Therefore, when the carrier wafer 10 is accommodated in this internal space with the wafer piece 21 facing upward, the back surface of the carrier wafer 10 is held in contact with the bottom of the mold 40 and the outer peripheral edge of the carrier wafer 10 is molded. A molding space 41 is formed above the carrier wafer 10 in close contact with the inner surface of the mold 40.

  Therefore, a predetermined filler powder 31 is filled in the molding space 41. The molding space 41 has a planar shape such that the filler layer 30 shown in FIG. 1 can be obtained, but the upper end 42 of the molding die 40 is located higher than the surface 21a of the wafer piece 21, so that the molding space When the filler powder 31 is filled in 41, the filler powder 31 covers the entire surface 21 a of the wafer piece 21. Therefore, not only the carrier wafer 10 but also the wafer piece 21 is buried in the filler powder 31 and cannot be seen from the outside of the mold 40.

  When the molding die 40 is heated to a predetermined temperature and the filler powder 31 is sintered and cured, the filler powder 31 is integrated with the carrier wafer 10 and the wafer piece 21. Therefore, when the combined body of the carrier wafer 10, the wafer piece 21, and the cured filler powder 31 is taken out of the mold 40, the combined body is in a state as shown in FIG.

  Next, after attaching the support substrate 50 to the back surface of the carrier wafer 10 using an appropriate adhesive or adhesive, the surface 31a of the filler powder 31 cured by using the polishing tool 60 by the CMP method is used as a wafer piece. Polishing is performed until the surface 21a of 21 is exposed. As a result, the filler layer 30 filling the space around the wafer piece 21 on the carrier wafer 10 is obtained. The state at this time is as shown in FIG. 6, and the surface 30a of the filler layer 30 and the surface 21a of the wafer piece 21 are located in the same plane. The planar shape of the filler layer 30 is the same as the planar shape of the molding space 41, that is, the planar shape of the carrier wafer 10.

  When the filler powder 31 is filled and cured in the molding space 41, the surface 21a of the wafer piece 21 is exposed from the filler powder 31 by precisely controlling the thickness of the filler powder 31. If possible, it is natural that the step of polishing the surface 31a of the filler powder 31 with the polishing tool 60 is unnecessary.

  Through the steps as described above, the wafer structure 1 according to the first embodiment of the present invention shown in FIG. 1 is manufactured.

  As the filler powder 31 filled in the molding space 41 of the mold 40 in the process of FIG. 4, since the wafer piece 21 and the carrier substrate 10 are both made of silicon, silicon powder is used accordingly. . As the silicon powder, it is preferable to use silicon fine powder of nanometer (nm) order. For example, it is preferable to use fine silicon powder having an average particle size in the range of 10 nm to 500 nm. Although nano-order silicon fine powder tends to agglomerate and harden as it is, aggregation can be suppressed by covering the periphery of the silicon fine powder with an appropriate coating agent. When the fine silicon powder coated on the periphery in this manner is dispersed in an appropriate solvent, a fluid containing the fine silicon powder (nanosilicon fluid) is obtained. This nanosilicon fluid fills the molding space 41.

  When the forming die 40 is heated to, for example, 200 ° C. after filling the nanosilicon fluid into the forming space 41, the coating agent and the solvent evaporate and the silicon fine powder comes into contact with each other, and the filler powder 31 is substantially uniform. Cured into a silicon film. Thereafter, the combined body of the carrier wafer 10, the wafer piece 21 and the hardened silicon fine powder may be taken out from the mold 40.

  As the filler powder 31, a silicon powder larger than the nm order may be used. In this case, since there is no fear of aggregation as described above, the silicon powder itself may be filled up to the same level as the upper end 42 of the mold 40 as shown in FIG. Thereafter, if the silicon powder is heated and cured, it is cured almost uniformly and becomes a polycrystalline or amorphous silicon film. The subsequent steps are the same as described above.

  As the silicon fine powder, a known one may be used. For example, Jinan Ginfeng Product Co., Ltd. (a Chinese company, see http://japan.alibaba.com/manufacture/5075386) provides silicon powder. Although the use is different from that of the present invention, Japanese Patent Application Laid-Open No. 2006-070089 discloses nanosilicon powder that emits fluorescence and a method for producing the same.

  As described above in detail, in the method for manufacturing the wafer structure 1 according to the first embodiment of the present invention, the process of obtaining the wafer piece 21 by using the processing semiconductor wafer 20 uses a known stealth dicing technique. Can be realized easily. The step of bonding the wafer piece 21 onto the carrier wafer 10 can be easily performed by a known anodic bonding method without using an adhesive or a pressure-sensitive adhesive. In addition, the step of forming the filler layer 30 by embedding the filler powder 31 in the space around the wafer piece 21 on the carrier wafer 10 is performed by filling a known semiconductor powder with an appropriate mold 40. It can be easily carried out by curing. In order to expose the surface 21a of the wafer piece 21 from the filler layer 30, the surface 31a of the filler powder 31 may be polished using a CMP method. Therefore, according to this manufacturing method, the wafer structure 1 according to the first embodiment of the present invention can be manufactured by a simple method and at low cost.

(Configuration of Second Embodiment)
FIG. 8 shows a wafer structure 1A according to the second embodiment of the present invention. FIG. 8 (a) is a plan view of the wafer structure 1A, FIG. 8 (b) is a front view thereof, and FIG. ) Is a cross-sectional view taken along the line AA in FIG.

  In the wafer structure 1A according to the second embodiment, the carrier wafer 10a includes the same semiconductor part 10 ′ as the carrier wafer 10 used in the wafer structure 1 according to the first embodiment, and one of the semiconductor parts 10 ′. The structure is the same as that of the wafer structure 1 of the first embodiment except that the insulating film 12 is formed on the main surface. Therefore, the same elements in FIG. 8 are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

As the insulating film 12, since the semiconductor portion 10 ′ is made of silicon, SiO ₂ which is an oxide thereof is preferable, but other insulating films (for example, Si ₃ N ₄ or SiN—SiO) can also be used. This is because even when the insulating film 12 is present, the thermal expansion coefficient and workability are maintained substantially equal to those of the semiconductor portion 10 ′.

  Thus, it is not necessary for the carrier wafer to be entirely made of a semiconductor such as silicon, and a part thereof may include an insulating film.

  It goes without saying that the same effects as those of the wafer structure 1 of the first embodiment can be obtained also in the wafer structure 1A of the second embodiment. Moreover, since the manufacturing method of the wafer structure 1A of the second embodiment is the same as that of the wafer structure 1 of the first embodiment, the description thereof is omitted.

(Configuration of Third Embodiment)
FIG. 10 is a view similar to FIG. 9, showing a wafer structure 1B according to the third embodiment of the present invention.

  The wafer structure 1B according to the third embodiment is the same as the wafer structure 1 according to the first embodiment, except that the wafer piece 21 is bonded to the carrier wafer 10 with the direction of the wafer piece 21 turned upside down. It is the same as the wafer structure 1 of the form. Therefore, in FIG. 8, the same elements as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the case where a chip size package for each integrated circuit region C is formed on the wafer piece 21 using the wafer structure 1B using a manufacturing facility designed for a silicon wafer having a smaller diameter of 8 inches, the following is performed. The following steps are performed.

  First, after forming a mask by photolithography, the carrier wafer 10 is selectively removed from the back side of the wafer structure 1 manufactured as described above by dry etching using the mask. A through hole 71 a is formed in the carrier wafer 10.

Next, an insulating film 73a such as SiO ₂ is formed on the inner wall surface of the through hole 71a by, for example, a CVD method to cover the entire inner wall surface.

  Next, after depositing W from the back surface of the carrier wafer 10 by, for example, the CVD method, the W film on the back surface of the carrier wafer 10 is selectively removed by the CMP method, so that the W film is left inside the through hole 71a. Thus, the conductor 73a is obtained. The conductor 73a is in contact with the conductive region on the surface side of the corresponding integrated circuit region C or the exposed surface of the wiring film.

  As described above, the embedded electrode 70a that penetrates the carrier wafer 10 and the wafer piece 21 and is electrically connected to the corresponding integrated circuit region C is formed. Thereafter, if the external electrode electrically connected to the embedded electrode 70a is formed by a known method, the packaging process is completed. Finally, if the carrier wafer 10 and the wafer piece 21 are diced together along the dicing lines 28 and 29 of the wafer piece 21, a chip-like integrated circuit device is obtained for each integrated circuit region C.

(Other embodiments)
The first to third embodiments described above show examples embodying the present invention. Therefore, the present invention is not limited to these embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

  For example, in the embodiment described above, a ¼ cut piece of a carrier substrate (carrier wafer) is used as the first semiconductor substrate (wafer piece), but the present invention is not limited to this. The first semiconductor substrate (wafer piece) may be a part of the second semiconductor substrate having a larger planar shape than the carrier substrate, and may be a ½ cut piece of the second semiconductor substrate. Further, it may be one of cut pieces obtained by cutting the wafer-like second semiconductor substrate with two or more cutting lines parallel to the orientation flat, or cutting with two or more cutting lines orthogonal to the orientation flat. One piece may be sufficient, and the cutting line 27 parallel to the orientation flat, the cutting line 26 orthogonal to the orientation flat, and one of the cutting pieces cut | disconnected by one or more other cutting lines may be sufficient. As described above, the cutting mode can be arbitrarily selected as necessary.

  Further, in the above-described embodiment, the second semiconductor substrate having a diameter of 12 inches (about 30 cm) is cut and subjected to subsequent processing in an existing manufacturing facility designed for a wafer having a diameter of 8 inches (about 20 cm). However, the present invention is not limited to this. The first semiconductor substrate (wafer piece) can be arbitrarily changed as necessary as long as it is a part of the second semiconductor substrate having a larger planar shape than the carrier substrate (carrier wafer). For example, a second semiconductor substrate having a diameter of 8 inches may be cut and subjected to subsequent processing in an existing manufacturing facility designed for a wafer having a diameter of 6 inches (about 15 cm).

  In the above-described embodiment, a single crystal silicon wafer is used as the processing semiconductor wafer, but a compound semiconductor wafer such as GaAs may be used. In this case, the first semiconductor substrate (wafer piece) bonded on the carrier substrate (carrier wafer) is made of the same compound semiconductor. The carrier substrate (carrier wafer) is the same compound semiconductor wafer (single crystal or polycrystalline) as the first semiconductor substrate (wafer piece), and the filler layer is filled with the same compound semiconductor powder to form a layer. It is preferable to use a hardened material. The filler layer may be formed of glass powder having a thermal expansion coefficient equivalent to that of the compound semiconductor.

  The process of packaging the wafer structure and the method of performing those processes can be arbitrarily changed.

(A) is a top view of the wafer structure concerning a 1st embodiment of the present invention, (b) is the front view, and (c) is a sectional view which met an AA line of (a). It is a top view which shows an example of the semiconductor wafer for a process used for the wafer structure of FIG. (A) is a top view which shows the manufacturing method of the wafer structure which concerns on 1st Embodiment of this invention for every process, (b) is sectional drawing along the BB line of (a). (A) is a top view which shows the manufacturing method of the wafer structure which concerns on 1st Embodiment of this invention for every process, (b) is sectional drawing along CC line of (a), and is a continuation of FIG. It is. (A) is a top view which shows the manufacturing method of the wafer structure which concerns on 1st Embodiment of this invention for every process, (b) is sectional drawing along the DD line of (a), and is a continuation of FIG. It is. (A) is a top view which shows the manufacturing method of the wafer structure which concerns on 1st Embodiment of this invention for every process, (b) is sectional drawing along the EE line of (a), and is a continuation of FIG. It is. It is explanatory drawing which shows an example of arrangement | positioning of an integrated circuit area | region in the semiconductor wafer for a process used as the wafer piece for the wafer structure which concerns on 1st Embodiment of this invention. (A) is a top view of the wafer structure concerning a 2nd embodiment of the present invention, (b) is the front view, and (c) is a sectional view which met an AA line of (a). Using the wafer structure according to the first embodiment of the present invention, a wafer piece having a large number of integrated circuit regions formed therein is used for each integration using a manufacturing facility designed for a smaller silicon wafer. FIG. 2 is a partial enlarged cross-sectional view taken along the line AA in FIG. 1A, illustrating an example of forming a chip size package for a circuit region. FIG. 10 is a partially enlarged cross-sectional view similar to FIG. 9 showing a wafer structure according to a third embodiment of the present invention.

Explanation of symbols

1, 1A, 1B Wafer structure 10, 10a Carrier wafer 10 'Semiconductor portion of carrier wafer 11 Orientation flat of carrier wafer 12 Insulating film 20 Semiconductor wafer for processing 21, 21, 23, 24 Wafer piece 21a Wafer piece surface 21b Wafer Straight portion of piece 21c Corner portion of wafer piece 21d Curved portion of wafer piece 21e Back side of wafer piece 25 Orientation flat of wafer piece 26, 27 Cutting line 28, 29 Dicing line 30 Filler layer 30a Filler layer surface 31 Filler Powder 31a Filler material powder surface 40 Mold 41 Mold space 42 Mold upper end 50 Support substrate 60 Polishing tool 70, 70a Embedded electrode 71, 71a Through hole 72 Through hole 73, 73a Insulating film 74, 74a Conductor C Integrated circuit area T Gap between chip areas (street)

Claims (25)

A wafer-like carrier substrate;
A first semiconductor substrate bonded to one main plane of the carrier substrate and having a planar shape smaller than the carrier substrate;
A filler layer that embeds a space around the first semiconductor substrate on the carrier substrate;
The first semiconductor substrate is a part of a second semiconductor substrate having a larger planar shape than the carrier substrate;
The first semiconductor substrate is entirely disposed inside the periphery of the carrier substrate,
The planar shape of the filler layer is substantially the same as the outer shape of the carrier substrate, and the thickness of the filler layer is substantially the same as the thickness of the first semiconductor substrate. The surface of the substrate is exposed from the filler layer,
The carrier substrate and the filler layer have a thermal expansion coefficient equivalent to that of the first semiconductor substrate.   The wafer structure according to claim 1, wherein the first semiconductor substrate is a cut piece of the second semiconductor substrate in which an integrated circuit is formed.   The wafer structure according to claim 1, wherein the carrier substrate is the same single crystal or polycrystalline semiconductor substrate as the first semiconductor substrate.   The wafer structure according to claim 2, wherein the same semiconductor layer as the first semiconductor substrate is used as the filler layer.   The wafer structure according to claim 2 or 3, wherein a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used as the filler layer.   The wafer structure according to claim 1, wherein the first semiconductor substrate is made of single crystal silicon, and the carrier substrate is made of single crystal silicon or polycrystalline silicon.   The wafer structure according to claim 6, wherein a silicon layer is used as the filler layer.   The wafer structure according to claim 6, wherein a glass layer having a thermal expansion coefficient equivalent to that of silicon is used as the filler layer.   2. The wafer structure according to claim 1, wherein the first semiconductor substrate is formed of a compound semiconductor, and the carrier substrate is formed of the same single crystal or polycrystalline compound semiconductor substrate as the first semiconductor substrate.   The wafer structure according to claim 9, wherein a layer of the same compound semiconductor as the first semiconductor substrate is used as the filler layer.   The wafer structure according to claim 9, wherein a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used as the filler layer.   The wafer structure according to claim 1, wherein the carrier substrate has a workability equivalent to that of the first semiconductor substrate. Bonding a first semiconductor substrate having a planar shape smaller than the carrier substrate to one main plane of the wafer-like carrier substrate so that the entirety of the first semiconductor substrate is disposed inside the periphery of the carrier substrate;
By embedding a filler in a space around the first semiconductor substrate on the carrier substrate, the planar shape is substantially the same as the outer shape of the carrier substrate, and the thickness is equal to the thickness of the first semiconductor substrate. Forming a filler layer that is substantially identical,
The filler layer is formed such that a surface of the first semiconductor substrate is exposed from the filler layer;
The method of manufacturing a wafer structure, wherein the carrier substrate and the filler layer have a thermal expansion coefficient equivalent to that of the first semiconductor substrate.   The method of manufacturing a wafer structure according to claim 13, wherein a cut piece of the second semiconductor substrate having an integrated circuit formed therein is used as the first semiconductor substrate.   The method for manufacturing a wafer structure according to claim 13 or 14, wherein the step of bonding the first semiconductor substrate onto the carrier substrate is performed using an anodic bonding method. Forming the filler layer comprises:
Disposing the carrier substrate having the first semiconductor substrate fixed to one surface inside a mold; and
The method further comprises a step of filling and solidifying the filler powder in a molding space formed around the first semiconductor substrate on the carrier substrate inside the molding die. 2. A method for producing a wafer structure according to item 1.   The wafer according to claim 16, further comprising a step of polishing or etching the filler layer covering the surface of the first semiconductor substrate to expose the surface of the first semiconductor substrate from the filler layer. Manufacturing method of structure.   18. The method of manufacturing a wafer structure according to claim 16, wherein the same powder as the first semiconductor substrate is used as the filler powder.   19. The method of manufacturing a wafer structure according to claim 13, wherein a single crystal silicon substrate is used as the first semiconductor substrate, and a single crystal or polycrystalline silicon substrate is used as the carrier substrate.   The method for manufacturing a wafer structure according to claim 19, wherein a silicon layer is used as the filler layer.   The method for manufacturing a wafer structure according to claim 19, wherein a glass layer having a thermal expansion coefficient equivalent to that of silicon is used as the filler layer.   19. The compound semiconductor substrate according to claim 13, wherein a compound semiconductor substrate is used as the first semiconductor substrate, and a single-crystal or polycrystalline compound semiconductor substrate that is the same as the first semiconductor substrate is used as the carrier substrate. Manufacturing method of wafer structure.   23. The method of manufacturing a wafer structure according to claim 22, wherein a layer of the same compound semiconductor as the first semiconductor substrate is used as the filler layer.   23. The method for manufacturing a wafer structure according to claim 22, wherein a glass layer having a thermal expansion coefficient equivalent to that of the first semiconductor substrate is used as the filler layer. The said 1st semiconductor substrate is formed by cut | disconnecting the 2nd semiconductor substrate which has a planar shape larger than the said 1st semiconductor substrate using a stealth dicing technique. Manufacturing method of wafer structure.

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