CN102163559B - Manufacturing method of stack device and device chip process method - Google Patents
Manufacturing method of stack device and device chip process method Download PDFInfo
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- CN102163559B CN102163559B CN2010102466864A CN201010246686A CN102163559B CN 102163559 B CN102163559 B CN 102163559B CN 2010102466864 A CN2010102466864 A CN 2010102466864A CN 201010246686 A CN201010246686 A CN 201010246686A CN 102163559 B CN102163559 B CN 102163559B
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- 238000000034 method Methods 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000000576 coating method Methods 0.000 claims description 119
- 239000011248 coating agent Substances 0.000 claims description 116
- 238000011068 loading method Methods 0.000 claims description 96
- 239000000463 material Substances 0.000 claims description 43
- 238000000465 moulding Methods 0.000 claims description 33
- 239000002904 solvent Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000003672 processing method Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000003797 solvolysis reaction Methods 0.000 claims description 2
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 claims 1
- 239000012790 adhesive layer Substances 0.000 abstract 7
- 235000012431 wafers Nutrition 0.000 description 115
- 238000004140 cleaning Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000000354 decomposition reaction Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000000227 grinding Methods 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- SECXISVLQFMRJM-UHFFFAOYSA-N N-methyl-pyrrolidinone Natural products CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002118 epoxides Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- -1 pottery Chemical compound 0.000 description 2
- LLHKCFNBLRBOGN-UHFFFAOYSA-N propylene glycol methyl ether acetate Chemical compound COCC(C)OC(C)=O LLHKCFNBLRBOGN-UHFFFAOYSA-N 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000003522 acrylic cement Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- RBFDCQDDCJFGIK-UHFFFAOYSA-N arsenic germanium Chemical compound [Ge].[As] RBFDCQDDCJFGIK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015271 coagulation Effects 0.000 description 1
- 238000005345 coagulation Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000011034 rock crystal Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002195 soluble material Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01L2924/01—Chemical elements
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- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/19041—Component type being a capacitor
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Abstract
A method of bonding and detaching a temporary carrier used for handling a wafer during the fabrication of semiconductor devices includes bonding a wafer onto a carrier through a first adhesive layer and a second adhesive layer, in which the edge zone of the wafer and the carrier is covered by the first adhesive layer while the edge zone is not covered by the second adhesive layer. A wafer edge clean process is then performed to remove the first adhesive layer adjacent the edge of the wafer and expose the edge zone of the carrier, followed by removing the second adhesive layer from the carrier. After detaching the carrier from the wafer, the first adhesive layer remaining on the wafer is removed. It becomes more easily to detach the carrier from the thinned device wafer without causing damages.
Description
Technical field
The present invention relates to a kind of making of semiconductor device, process during particularly a kind of semiconductor device is made (handle) thinning the employed interim loading plate of wafer joint with unload (detaching) method.
Background technology
Since the continual improvement of integrated level (integration density) of each electronic unit (that is, transistor, diode, resistance, electric capacity etc.), the Fast Growth development that semiconductor is already continued.Main, the improvement of integrated level comes from minimum feature size (minimum feature size) and constantly dwindles and allow that more parts are integrated in the existing chip area.Therefore when createing three dimensional integrated circuits (three-dimensional integrated circuit, 3DIC) and solving device quantity and increase, be present in the limiting factor of intraconnections length and quantity between the device.Nude film to the stacking joint of wafer (die to wafer) for forming a kind of mode of 3DIC, wherein one or more than one nude film be engaged on the wafer, and the size of nude film can be less than the chip on the wafer (chip).For the thickness that reduces semiconductor packages, increase the speed of chip, and high density components makes, thereby is devoted to reduce the thickness of semiconductor wafer.Therefore, important 3D technical matters one of them be how to process the wafer thinning.The typical process that is used for provisional joint is included in and applies a sticker on bearing wafer and/or the device wafer, device wafer is engaged with loading plate, loading plate is processed and then removed to device wafer.
Reduced down in thickness is carrying out so-called brilliant back-grinding back on the surface of containing circuit pattern (pattern-formed circuity) in the semiconductor wafer, usually attach a support plate by a sticky material on the semiconductor wafer, to assist the processing of wafer.Because the die strength of thinning is not enough and be easier to deform, for example crooked (bending) and/or warpage (warping), therefore utilizing cutting technique to make before wafer is divided into other chip package, wafer surface is carried out sealing (for example, thermosetting epoxy resin) with moulding material (molding compound) first.Waffer edge can expose the sticky material of a part in the tradition moulding process, makes Waffer edge impaired easily during carrying out subsequent technique (for example time etching or dry ecthing), and fragmentation (chipped) for example occurs after unloading loading plate.When particularly using the sticky material of thermosetting (thermosetting), the high temperature dorsal part technique that device wafer carries out makes adhesion strength cause the infringement of low dielectric constant material layer greater than the low dielectric constant material layer in the device wafer during loading plate unloads separating process.Similarly, during carrying out dorsal part technique, the reduced viscosity of sticky material makes sticky material flow into the glass loading plate and causes other problem.
Summary of the invention
The object of the invention is to overcome defective of the prior art.
In one embodiment of the invention, a kind of manufacture method of stack device comprises: a wafer is provided, and it has a first surface and a second surface relative with it, has wherein applied one first adhesion coating on the first surface; A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing loading plate; Via the first adhesion coating and the second adhesion coating the first surface of wafer is engaged to loading plate, wherein the marginal zone of loading plate is covered by the first adhesion coating; From the second surface chip thinning, to form the wafer of a thinning; A plurality of nude films are engaged on the wafer of thinning; Removal is adjacent to the first adhesion coating of the Waffer edge of thinning, and this two adhesion coating that exposes the marginal zone of loading plate and be adjacent to the marginal zone of loading plate; Apply a luminous energy or heat energy, to decompose the second adhesion coating; Unload loading plate from wafer; And remove the first adhesion coating on the first surface remain in wafer.
In another embodiment of the present invention, a kind of manufacture method of stack device comprises: a wafer is provided, and it has a first surface and a second surface relative with it, has wherein applied one first adhesion coating on the first surface; A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing loading plate; Via the first adhesion coating and the second adhesion coating the first surface of wafer is engaged to loading plate, wherein the marginal zone of loading plate is covered by the first adhesion coating; From the second surface chip thinning, to form the wafer of a thinning; A plurality of nude films are engaged on the wafer of thinning, to form stacking to wafer of a nude film; At stacking formation one moulding material of nude film to wafer; Edge at contiguous moulding material forms a passage, and wherein passage passes the edge of moulding material, wafer and the first adhesion coating of a part; Remove in the edge of moulding material, wafer and the first adhesion coating part around passage, and the second adhesion coating that exposes the marginal zone of loading plate and be adjacent to this marginal zone of loading plate; Remove the second adhesion coating; Unload this loading plate from wafer; And remove the first adhesion coating on the first surface remain in wafer.
In further embodiment of this invention, a kind of processing method of device wafer, comprise: a device wafer is provided, it comprises the semiconductor substrate with a front surface and a back of the body surface, and wherein a through hole electrode that is filled with electric conducting material is formed in the semiconductor base and from front surface and extends into semiconductor base to a degree of depth toward back of the body surface; Front surface at semiconductor base forms one first adhesion coating, with the edge of cladding system wafer; A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing loading plate; Via the first adhesion coating and the second adhesion coating device wafer is engaged to loading plate, wherein the marginal zone of loading plate is covered by the first adhesion coating; From the back of the body surface of semiconductor base thinning apparatus wafer, to expose an end points of through hole electrode; Back of the body surface at semiconductor base forms a metallization structure, to be electrically connected to the end points that exposes of through hole electrode; One nude film is engaged on the device wafer, to be electrically connected metallization structure; Remove the first adhesion coating of apparatus adjacent Waffer edge, to expose this marginal zone of loading plate; Remove the second adhesion coating; Unload loading plate from wafer; And remove the first adhesion coating.
The present invention can follow-up carry out thinning and dorsal part technique during processing unit wafer easily, easier under the situation of not damaging the device wafer from thinning unload loading plate.
Description of drawings
Fig. 1 illustrates according to the rectilinear nude film of the embodiment manufacturing flow chart to die stack, and it comprises the joint of interim loading plate and unloads.
Fig. 2 A to Fig. 2 K illustrates according to the method for Fig. 1 and makes nude film to the generalized section of an embodiment of the stages of die stack.
Fig. 3 A to Fig. 3 C illustrates the generalized section according to an embodiment of the joint of interim loading plate and the method that the method that unloads is processed the device wafer with through hole electrode.
Fig. 4 illustrates according to the rectilinear nude film of the embodiment manufacturing flow chart to die stack, and it comprises the joint of interim loading plate and unloads.
Fig. 5 A to Fig. 5 G illustrates according to the method for Fig. 4 and makes nude film to the generalized section of an embodiment of the stages of die stack.
Wherein, description of reference numerals is as follows:
100,500~method;
102,104,106,108,112,114,116,118,120,122,124,126,510,512,514,516,518~step;
200~device wafer;
200 "~device wafer of thinning;
200a~the first side;
200b, 200b "~the second side;
200e~edge;
202~the first adhesion coatings;
204~metallization structure;
210~semiconductor base;
210 "~substrate of thinning;
210a~front surface;
210b, 210 "~back of the body surface;
220~through hole electrode;
220a~end points;
240~interconnect structure;
250~dorsal part separator;
260~connection pad;
280~conductive structure;
300~loading plate;
300e~marginal zone;
302~the second adhesion coatings;
400~nude film;
402~nude film is stacking to wafer;
402a~moulding is stacking;
404~moulding material;
405~passage;
406~light source;
408~nude film is stacking to nude film.
Embodiment
In the following description, many specific detail parts have been proposed, with abundant understanding the present invention.Yet, any under in the technical field those of ordinary skill will understand that the present invention can carry out under these specific detail situations not having.In some examples, known configurations and technique are not described in detail in detail, to avoid making the present invention produce unnecessary obscuring.
The mentioned meaning about " embodiment " refers to be contained among at least one embodiment of the present invention relevant for mentioned specific feature (feature), structure or characteristic in the present embodiment in this specification.Therefore, " in one embodiment " term indication that each place occurs in this specification be not expressed as completely identical embodiment.Moreover specific feature, structure or characteristic can be done combination with one or more embodiment in any appropriate manner.Be understandable that following accompanying drawing does not illustrate according to ratio, and the usefulness that only furnishes an explanation.
Please refer to Fig. 1, it illustrates rectilinear nude film according to an embodiment to the stacking manufacturing flow chart of nude film (die to die), and it comprises the joint of interim loading plate (temporary caiier) and unloads.Please refer to Fig. 2 A to Fig. 2 K, it illustrates according to the method for Fig. 1 and makes nude film to an embodiment of the stages of die stack.
The initial step 102 of method 100 is to apply one first adhesion coating at a device wafer, and then carry out step 104, applies one second adhesion coating at a loading plate.Fig. 2 A illustrates the generalized section at a device wafer 200 coatings one first adhesion coating 202 of an embodiment, in order to be attached at the loading plate 300 that applies the second adhesion coating 302.Have a plurality of semiconductor chips in the device wafer 200, wherein each chip comprises a substrate, is formed with known electronic installation on it.Substrate can be made of semi-conducting material, silicon, arsenic germanium, Thassos (rock crystal) wafer, sapphire, glass, quartz, pottery, thermosets etc.Usually cover one layer or more dielectric layer and conductive layer in the substrate.Conductive layer provides connection and the wiring (routing) of below electronic installation.Device wafer 200 has the first side 200a and with respect to the second side 200b of the first side 200a.On the first side 200a, be formed with integrated circuit, comprise active (active) and passive (passive) device, for example transistor, resistance, electric capacity etc. are in order to connect connection pad and/or other interconnect structures.
The first adhesion coating 202 places the first side 200a top, so that device wafer 200 is attached loading plate 300.In one embodiment, the edge 200e of the first side 200a of the first adhesion coating 202 cladding system wafers 200.The first adhesion coating 202 can be an individual layer, multilayer cohesive structure or composite bed and is applied to spin coating (spin on) or lamination coating (lamination) technique, wherein at least one adhesion coating comprises wet-chemical removal type sticky material, for example thermoplasticity (thermal plastic) material, solvent-soluble shaped material.Also can use the sticky material of other types, for example pressure sensibility sticky material, photo-curable sticky material, epoxides or its combination etc.Sticky material can place on the surface of half aqueous or colloid, and it can be out of shape under pressurized immediately.The first adhesion coating 202 can carry out easily physical property or chemistry and divest.
Loading plate 300 be by removing or soluble material is consisted of, for example, and silicon, glass, quartz, pottery, silica, aluminium oxide, macromolecule, plastic cement, acrylic (acrylic-based) material, any other transparent material or its combination.Loading plate 300 is smooth, can be attached at device wafer 200.The thickness of loading plate 300 at 550 microns (μ m) to 850 microns scopes.The diameter of loading plate 300 is greater than the diameter of device wafer 200, however the exactly so size that depends on device wafer 200 of the size of loading plate 300.During processing or processing, the physical property of loading plate 300 generator wafers 200 supports, and loading plate 300 is transparent, to allow penetrating of light, and for example laser or ultraviolet light (UV).
The second adhesion coating 302 places loading plate 300 tops, so that device wafer 200 is attached loading plate 300.In one embodiment, except the marginal zone 300e of loading plate 300, the second adhesion coating 302 covers the major part of loading plate 300.The second adhesion coating 302 can be an individual layer or composite bed and is applied to spin coating or lamination coating technique.In one embodiment, the second adhesion coating 302 is made of light decomposability sticky material, for example laser-sensitive material, UV sensitive material or pyrolytic material, it can be decomposed when being exposed to luminous energy or heat energy (for example, infrared light (IR), laser, UV etc.) and lose viscosity.In another embodiment, the second adhesion coating 302 is made of the solvolysis sticky material, thermoplastic for example, it can decompose with solvent, for example the photoresist related solvents (as, propylene glycol monomethyl ether ester (propylene glycol methyl ether acetate, PGMEA) or N-N-methyl 2-pyrrolidone N-(N-methyl pyrrolidinone, NMP)).
Carry out the step 106 of method 100, device wafer is engaged with loading plate.Fig. 2 B illustrates and device wafer 200 is inverted and via adhesion coating 202 and 302 and be engaged to generalized section on the loading plate 300, can follow-up carry out thinning and dorsal part technique during processing unit wafer 200 easily.The first adhesion coating 302 covers the marginal zone 300e of the second adhesion coating 302 and loading plate 300.
Carry out the step 108 of method 100, the dorsal part of device wafer is carried out thinning.Fig. 2 C illustrates the generalized section that device wafer 200 carries out wafer thinning technique.After conforming to loading plate 300, the non-structure (structure-free) of device wafer 200 is distinguished (the second side 200b) be machined to required final thickness.For instance, can be undertaken forming by the mode of grinding (grinding), etching and/or grinding and polishing have the set thickness chip thinning 200 of (depending on the semiconductor packages application target) ".In one embodiment, device wafer 200 is thinned to about 5 microns to 50 microns thickness.In another embodiment, device wafer 200 is thinned to about 25 microns to 250 microns thickness.
Carry out the step 110 of method 100, at the dorsal part formation metallization structure of device wafer.Fig. 2 D is illustrated in the device wafer 200 of thinning " the second side 200b " the upper generalized section that forms metallization structure 204.The metallization structure 204 of dorsal part comprises that interconnect structure (for example, (re-distribution line reroutes, RDL)), external contact structure (for example, the solder projection of individual other semiconductor chip (solder bump) or contain copper bump) and/or as other structure of power line, inductance, electric capacity or any passive component.Metallization structure 204 can be made of the formed copper of method, aluminium, copper alloy or other electric conducting materials such as plating, electroless-plating, sputter (sputtering), chemical vapour deposition (CVD)s (chemical vapor deposition).
Carry out the step 112 of method 100, with chip join to the dorsal part of device wafer.Fig. 2 E illustrates the device wafer 200 that a plurality of nude films 400 are engaged and are electrically connected to thinning " the second side 200b " on metallization structure 400 and form nude film to stacking 402 generalized section of wafer.Joint method comprises general employed method, and for example oxide layer engages etc. copper joint, adhesion joint and solder projection silicon layer bond, copper oxide layer joint, oxide layer.Nude film 400 can comprise memory chip, radio frequency (radio frequency, RF) chip, logic chip or other chips.Each nude film 400 has first surface and second surface, and integrated circuit is formed on the first surface.In one embodiment, the first surface of nude film 400 is engaged to the device wafer 200 of thinning ".In one embodiment, the second surface 14b of nude film 400 is engaged to the device wafer 200 of thinning ".
Carry out the step 114 of method 100, nude film is carried out moulding (molding) to wafer stacking.Fig. 2 F illustrates the generalized section of nude film being carried out moulding process to stacking 402 of wafer and forming the stacking 402a of a moulding.One moulding material 404 be coated on nude film to wafer stacking 402 on, and insert space between the adjacent nude film 400.Moulding process is at the device wafer 200 of thinning " Edge preserving one uncovering area.Moulding material 404 can be made of curing materials, for example macromolecular material, resin material, polyimides (polyimide), silica, epoxides, benzocyclobutene (benzocyclobutene, BCB), SilkTM (Tao Shi chemical company (Dow Chemical)) or its combination.Moulding process comprises ejection formation, compression forming, steel plate printing, rotary coating or the following moulding process that develops.After coating molding material 404, be cured or baking procedure, with coagulation forming material 404.
Carry out the step 116 of method 100, the stacking 402a of self-forming unloads loading plate 300.Fig. 2 G to Fig. 2 I illustrates the stages generalized section that loading plate unloads separating process.Begin to carry out the step 118 of step 116, remove the device wafer 200 that is positioned at thinning by a clean method " the first adhesion coating 202 of edge 200e; with the marginal zone 300e that exposes loading plate 300 and the second adhesion coating 302 that is adjacent to marginal zone 300e, shown in Fig. 2 G.Clean method can be chemical hydro-peening (jetting) technique or wet type trough washery (wet bench) technique.Carry out the step 120 of step 116, remove the second adhesion coating 302.In one embodiment, remove the second adhesion coating 302 by light source 406 decomposition, shown in Fig. 2 H.Light source 406 leads to loading plate 300 and passes loading plate 300, and the second adhesion coating 302 is decomposed after absorbing light energy.Light source 406 can comprise infrared light (IR), laser, irradiation light etc.In other embodiments, can remove the second adhesion coating 302, for example NH4OH by solvent decomposition method.
Usually after finishing wafer level test, carry out the step 122 of step 116, separate loading plate 300 and the stacking 402a of moulding, shown in Fig. 2 I.Because the second adhesion coating 302 removes by decomposition or solvent, therefore easier under the situation of not damaging from the device wafer 200 of thinning " unload loading plate 300.Unload separating process and can be any suitable (de-bonding) technique of peeling off, make the device wafer 200 of thinning " in semiconductor structure possess its integrality.For instance, utilize solvent, UV irradiation or (pulled off) mode that pulls to unload separating process, to remove loading plate 300 from the first adhesion coating 202.
Carry out the step 124 of method 100, remove and stay the device wafer 200 of thinning " upper the first adhesion coating 202.Fig. 2 J illustrates the device wafer 200 to thinning " the first side 200a carry out wafer cleaning procedure to remove the generalized section of the first adhesion coating 202.In one embodiment, wafer cleaning procedure is wet process, with chemical stripping the first adhesion coating 302.In other are implemented, can be by thermal decomposition, peel off, plasma cleaning, granula cleaning (pellet cleaning) etc. remove the first adhesion coating 202, thereby exposed in other semiconductor chip in order to be engaged to electrical joint and to be formed at the device wafer 200 of thinning " the external contact of the first side 200a.
Carry out the step 126 of method 100, along Cutting Road the stacking 402a of moulding is cut into other nude film to stacking 408 of nude film with conventional process.Fig. 2 K illustrates a plurality of nude films to stacking 408 generalized section of nude film.After carrying out cutting technique, stacking wafer can be assembled on the IC-card by anisotropic conductive film (anisotropically conductive connection film).
One or more nude film of device wafer 200 can have in one or more substrate via electrode (through substrate via, TSV) is formed at.Fig. 3 A to Fig. 3 C illustrates an embodiment who has the device wafer of through hole electrode according to the method manufacturing of Fig. 1 and Fig. 2 A to Fig. 2 K, wherein omits explaining of same or similar part.
The have a plurality of silicon through hole electrodes device wafer 200 of (through silicon via, TSV) is engaged to loading plate 300 by adhesion coating 202 and 302 generalized section is shown according to the step 102 of method 100 to 106, Fig. 3 A.
The generalized section of the stacking 402a of moulding that comprises a plurality of silicon through hole electrodes (TSV) is shown to 112, Fig. 3 B according to the step 108 of method 100.After carrying out dorsal part thinning technique, an end points 220a of through hole electrode 220 exposes and/or protrudes from the substrate 210 of thinning " back of the body surface 210b ", shown in Fig. 2 B.Form dorsal part separator 250, to cover the wafer 210 of thinning " dorsal part.Conductive structure 280, for example solder projection or copper bump are formed at above the end points 220a of through hole electrode 220, to be engaged to nude film 400.Conductive structure 280 also comprises rerouting office layer (RDL) and connection pad, and it can form before making solder projection or copper bump.
The generalized section that the stacking 402a of loading plate 300 self-supporting types unloads is shown according to the step 114 of method 100 to 124, Fig. 3 C.Again moulding material 404 is coated on after stacking 402 tops of nude film to wafer, remove the device wafer 200 that is positioned at thinning by a clean method " first adhesion coating 202 at edge, with the marginal zone 300e that exposes loading plate 300 and the second adhesion coating 302 (not shown in Fig. 3 C) of neighboring edge district 300e.Then utilize light source 406 to decompose and remove the second adhesion coating 302, shown in Fig. 2 H.In addition, can remove the second adhesion coating 302 by solvent decomposition method.Next, the stacking 402a of self-forming unloads loading plate 300 and without causing damage.Then carry out following steps, remove the device wafer 200 remain in thinning by wafer cleaning procedure " on the first adhesion coating 202, for example with wet process, chemistry divests the first adhesion coating 202.
The feature of many embodiment more than has been described, although the use of the interim loading plate that discloses relates to the making of TSV device wafer, yet be understandable that the method that disclose in this place may be implemented in the application type that other need use provisional loading plate, for example imageing sensor, MEMS (micro electro mechanical system) (microelectromechanical systems, MEMS) or other 3DIC use.
Please refer to Fig. 4, it illustrates according to the rectilinear nude film of the embodiment manufacturing flow chart to die stack, and it comprises the joint of interim loading plate and unloads.Please refer to Fig. 5 A to Fig. 5 G, it illustrates according to the method for Fig. 4 and makes nude film to the generalized section of an embodiment of the stages of die stack, wherein omits same or similar explaining in Fig. 1 to Fig. 3.
Then, method 500 carry out step 510, from nude film stacking 402 of wafer is unloaded loading plate 300.Fig. 5 A to Fig. 5 G illustrates the stages generalized section that loading plate unloads separating process.Begin to carry out the step 512 of step 510, the device wafer 200 of little cutting (trimming) thinning " the edge, with form around and the passage 405 at the stacking 402a of contiguous moulding edge, shown in Fig. 5 B.By patterning method, laser cutting instrument for example, the device wafer 200 that passage 405 is cut wear moulding material 404 and thinning ", and extend the first adhesion coating 202 of putting a part and do not contact loading plate 300 and/or the second adhesion coating 302.In addition, also can form passage 405 with etch process.The diameter of passage 405 is less than 5 millimeters (mm).
Carry out the step 514 of step 510, remove the device wafer 200 that is positioned at thinning by a clean method " the first adhesion coating 202 of edge 200e; with the marginal zone 300e that exposes loading plate 300 and the second adhesion coating 302 that is adjacent to marginal zone 300e, shown in Fig. 5 C.Clean method can be chemical spray cleaning process or wet type trough washery technique, in order to remove the part around passage 405, comprised the moulding material 404 at the stacking 402a of contiguous moulding edge, the device wafer 200 of thinning " and the first adhesion coating 202; thereby expose the second adhesion coating 302 of the marginal zone 300e of contiguous loading plate 300, equally also exposed the marginal zone 300e of loading plate 300.
Carry out the step 516 of step 510, remove the second adhesion coating 302.In one embodiment, remove the second adhesion coating 302 by light source 406 decomposition, shown in Fig. 5 D.Light source 406 leads to loading plate 300 and passes loading plate 300, and the second adhesion coating 302 is decomposed after absorbing light energy.Light source 406 can comprise infrared light (IR), laser, irradiation light etc.In other embodiments, can remove the second adhesion coating 302 by solvent decomposition method.
Usually after finishing wafer level test, carry out the step 518 of step 510, stacking 402 to wafer of loading plate 300 and nude film separately is shown in Fig. 5 E.Because the second adhesion coating 302 removes by decomposition or solvent, therefore easier under the situation of not damaging from the device wafer 200 of thinning " unload loading plate 300.Unload separating process and can be any suitable stripping technology, make the device wafer 200 of thinning " in semiconductor structure possess its integrality.For instance, utilize solvent, UV irradiation or the mode that pulls to unload separating process, to remove loading plate 300 from the first adhesion coating 202.
Carry out the step 124 of method 500, remove and stay the device wafer 200 of thinning " upper the first adhesion coating 202.Fig. 5 F illustrates the device wafer 200 to thinning " the first side 200a carry out wafer cleaning procedure to remove the generalized section of the first adhesion coating 202.In one embodiment, wafer cleaning procedure is wet process, with chemical stripping the first adhesion coating 302.Therefore, exposed in other semiconductor chip in order to be engaged to electrical joint and to be formed at the device wafer 200 of thinning " the external contact of the first side 200a.Carry out the step 126 of method 500, along Cutting Road the stacking 402a of moulding is cut into other nude film to stacking 408 of nude film with conventional process.Fig. 5 G illustrates a plurality of nude films to stacking 408 generalized section of nude film.After carrying out cutting technique, stacking wafer can be assembled on the IC-card by anisotropic conductive film.
In the above detailed description, the present invention contrasts its specific embodiment and explains.Yet, be clear that very much without departing from the spirit and scope of the present invention, when making various changes, structure, technique and change, as claimed in claim.Therefore, specification and accompanying drawing are for the example explanation rather than in order to limit the present invention.Be understandable that the present invention can use other different combinations and environment, and do in can be the herein expressed inventive concept scope to change and change.
Claims (10)
1. the manufacture method of a stack device comprises:
One wafer is provided, and it has a first surface and a second surface relative with it, has wherein applied one first adhesion coating on this first surface;
A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing this loading plate;
Via this first adhesion coating and this second adhesion coating this first surface of this wafer is engaged to this loading plate, wherein this marginal zone of this loading plate is covered by this first adhesion coating;
From this this wafer of second surface thinning, to form the wafer of a thinning;
A plurality of nude films are engaged on the wafer of this thinning;
Removal is adjacent to this first adhesion coating of the Waffer edge of this thinning, and this second adhesion coating that exposes this marginal zone of this loading plate and be adjacent to this marginal zone of this loading plate;
Apply a luminous energy or heat energy, to decompose this second adhesion coating;
Unload this loading plate from this wafer; And
Removal remains in this first adhesion coating on this first surface of this wafer.
2. the manufacture method of stack device as claimed in claim 1, wherein this luminous energy comprises infrared light, laser or ultraviolet light.
3. the manufacture method of stack device as claimed in claim 1, wherein this first adhesion coating is made of wet-chemical removal type sticky material.
4. the manufacture method of stack device as claimed in claim 1, wherein this second adhesion coating is made of light breakdown type or thermal decomposition type or solvolysis type sticky material.
5. the manufacture method of a stack device comprises:
One wafer is provided, and it has a first surface and a second surface relative with it, has wherein applied one first adhesion coating on this first surface;
A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing this loading plate;
Via this first adhesion coating and this second adhesion coating this first surface of this wafer is engaged to this loading plate, wherein this marginal zone of this loading plate is covered by this first adhesion coating;
From this this wafer of second surface thinning, to form the wafer of a thinning;
A plurality of nude films are engaged on the wafer of this thinning, to form stacking to wafer of a nude film;
At stacking formation one moulding material of this nude film to wafer;
Edge at contiguous this moulding material forms a passage, and wherein this passage passes the edge of this moulding material, this wafer and this first adhesion coating of a part;
Remove in the edge of this moulding material, this wafer and this first adhesion coating part around this passage, and this second adhesion coating that exposes this marginal zone of this loading plate and be adjacent to this marginal zone of this loading plate;
Remove this second adhesion coating;
Unload this loading plate from this wafer; And
Removal remains in this first adhesion coating on this first surface of this wafer.
6. the manufacture method of stack device as claimed in claim 5, wherein the diameter of this passage is less than 5 millimeters.
7. the manufacture method of stack device as claimed in claim 5, the step of wherein removing this second adhesion coating comprise and apply a luminous energy or heat energy or solvent to decompose this second adhesion coating.
8. the manufacture method of stack device as claimed in claim 5, wherein this first adhesion coating is made of wet-chemical removal type sticky material.
9. the processing method of a device wafer comprises:
One device wafer is provided, and it comprises the semiconductor substrate with a front surface and a back of the body surface, and wherein a through hole electrode that is filled with electric conducting material is formed in this semiconductor base and from this front surface and extends into this semiconductor base to one degree of depth toward this back of the body surface;
This front surface at this semiconductor base forms one first adhesion coating, to cover the edge of this device wafer;
A loading plate that has applied one second adhesion coating is provided, and a marginal zone of exposing this loading plate;
Via this first adhesion coating and this second adhesion coating this device wafer is engaged to this loading plate, wherein this marginal zone of this loading plate is covered by this first adhesion coating;
Carry on the back this device wafer of surperficial thinning from this of this semiconductor base, to expose an end points of this through hole electrode;
This back of the body surface at this semiconductor base forms a conductive structure, to be electrically connected to this end points that exposes of this through hole electrode;
One nude film is engaged on this device wafer, to be electrically connected this conductive structure;
Remove this first adhesion coating at contiguous this device wafer edge, to expose this marginal zone of this loading plate;
Remove this second adhesion coating;
Unload this loading plate from this wafer; And
Remove this first adhesion coating.
10. the processing method of device wafer as claimed in claim 9 is wherein removed the step of this second adhesion coating for applying a luminous energy or heat energy to decompose this second adhesion coating.
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US12/707,752 US7883991B1 (en) | 2010-02-18 | 2010-02-18 | Temporary carrier bonding and detaching processes |
US12/707,752 | 2010-02-18 |
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PL1961744T3 (en) | 2005-11-18 | 2013-09-30 | Ono Pharmaceutical Co | Basic group-containing compound and use thereof |
JP5257068B2 (en) * | 2006-05-16 | 2013-08-07 | 小野薬品工業株式会社 | Compound containing acidic group which may be protected and use thereof |
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-
2010
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US7883991B1 (en) | 2011-02-08 |
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TWI446419B (en) | 2014-07-21 |
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