JP2008227157A - Semiconductor device and manufacturing method thereof, active matrix substrate, electro-optic device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces deterioration in the electrical characteristics of a semiconductor layer due to the floating effect of a substrate and which exhibits superior electrical characteristics, as well as to provide a manufacturing method for such a semiconductor device, an active matrix substrate, an electro-optic device, and an electronic apparatus. <P>SOLUTION: On the semiconductor device, a gate electrode 26 is formed on a substrate body 10A, and a monocrystal semiconductor layer 1 is formed on the gate electrode 26 via insulating layers 2, 11, while a non-monocrystal semiconductor layer 4 is formed which covers at least a channel region 1c on the monocrystal semiconductor layer 1 at the surface on the opposite side of the surface where the gate electrode 26 is formed on the monocrystal semiconductor layer 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, an active matrix substrate, an electro-optical device, and an electronic apparatus.

Conventionally, an SOI (Silicon On Insulator) technique for forming a silicon film on an insulating substrate and forming a semiconductor layer on the silicon film is known. As this SOI technology, a method is disclosed in which hydrogen ions are implanted on a single crystal silicon substrate, bonded to a support substrate, and then a silicon thin film is separated from a hydrogen implanted region of the single crystal silicon substrate by heat treatment. (For example, refer to Patent Document 1). In addition, a single crystal silicon thin film is epitaxially grown on a silicon substrate having a porous surface, bonded to the support substrate, the silicon substrate is removed, and the porous silicon layer is etched, thereby epitaxially growing the single crystal silicon film on the support substrate. A technique for forming a crystalline silicon thin film is disclosed (for example, see Patent Document 2). An SOI substrate formed by the above bonding method is different from a normal bulk semiconductor substrate, and a transparent substrate such as quartz or glass can be used as a support base. Accordingly, a high-performance semiconductor device can be formed in an electro-optical device that requires light transmission, such as a transmissive liquid crystal device.
US Pat. No. 5,374,564 JP-A-4-346418

  However, in the MIS (Metal Insulator Semiconductor) type semiconductor device using the conventional SOI substrate, since the lower part of the channel formation region is completely separated by the base insulating film, the channel formation region is held at a predetermined potential. There is a problem that cannot be done. As a result, a so-called substrate floating effect is generated, and the channel formation region is in an electrically floating state. For this reason, when a high voltage is applied to the drain electrode, surplus carriers are generated by impact ionization due to collision between carriers accelerated by a high electric field in the vicinity of the drain region and the crystal lattice, and accumulate in the lower portion of the channel. When surplus carriers accumulate in the lower part of the channel, the channel potential rises, and there is a problem that the source / channel / drain NPN structure (in the case of the N channel type) operates as an apparent bipolar semiconductor device (parasitic bipolar effect). . As a result, an abnormal current is generated, and the electrical characteristics of the semiconductor device are deteriorated, for example, the breakdown voltage between the source and the drain of the semiconductor device is deteriorated.

  Accordingly, the present invention provides a semiconductor device that exhibits excellent electrical characteristics by suppressing deterioration of the electrical characteristics of the semiconductor layer caused by the substrate floating effect, a manufacturing method thereof, an active matrix substrate, an electro-optical device, and an electronic apparatus. To do.

In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device including a thin film transistor having a single crystal semiconductor layer on an insulating substrate, wherein a gate electrode is formed on the insulating substrate, and the gate electrode The single crystal semiconductor layer is formed over the insulating layer, and a surface of the single crystal semiconductor layer opposite to the surface on which the gate electrode is formed covers at least the channel region of the single crystal semiconductor layer. A crystalline semiconductor layer is formed.
With this structure, when a high voltage is applied to the drain of the thin film transistor, carriers are accelerated by a high electric field in the vicinity of the drain region of the single crystal semiconductor layer, and the crystal lattice collides with the carriers. Surplus carriers are generated by the impact ionization phenomenon caused by the collision. The generated surplus carriers move to the non-single-crystal semiconductor layer that covers the channel region of the single-crystal semiconductor layer. Surplus carriers that have moved to the non-single-crystal semiconductor layer are captured by crystal defects included in the non-single-crystal semiconductor layer, and the crystal defects serve as recombination centers for the surplus carriers. Thus, excess carriers are prevented from accumulating in the channel region of the single crystal semiconductor layer, and an increase in channel potential is prevented.
Therefore, even when the channel region of the thin film transistor is in an electrically floating state, the increase in channel potential is prevented by the non-single-crystal semiconductor layer, the parasitic bipolar phenomenon in the semiconductor device is prevented, and the electrical characteristics are improved. A semiconductor device exhibiting excellent electrical characteristics can be obtained.

In the semiconductor device of the present invention, the non-single-crystal semiconductor layer is formed on the channel region of the single-crystal semiconductor layer, and is connected to the source region and the drain region of the single-crystal semiconductor layer, respectively. An electrode is provided on a surface of the single crystal semiconductor layer opposite to the surface on which the gate electrode is formed, and the source electrode and the drain electrode are provided separately from the non-single crystal semiconductor layer. Features.
With such a structure, the single crystal semiconductor layer can function as an active layer of the thin film transistor. In addition, excess carriers can be prevented from being accumulated in the channel region by the non-single-crystal semiconductor layer, and a parasitic bipolar phenomenon can be prevented. Further, since the non-single-crystal semiconductor layer is provided apart from the source electrode and the drain electrode, the non-single-crystal semiconductor layer can be grounded by being connected to, for example, a ground potential wiring. Thereby, an increase in channel potential can be prevented more effectively.

Alternatively, in the semiconductor device of the present invention, the non-single-crystal semiconductor layer includes the channel region of the single-crystal semiconductor layer and the source region and drain region of the single-crystal semiconductor layer so as to cover the single-crystal semiconductor layer. A source electrode and a drain electrode provided on the opposite side of the gate electrode of the single crystal semiconductor layer are electrically connected to the source region and the drain region through the non-single crystal semiconductor layer, respectively. It is characterized by being.
With this configuration, it is possible to prevent excess carriers from being accumulated in the channel region by the non-single-crystal semiconductor layer, and to prevent a parasitic bipolar phenomenon. Further, as described above, the manufacturing process of the thin film transistor can be simplified and the productivity of the semiconductor device can be improved as compared with the case where the non-single-crystal semiconductor layer is provided apart from the source electrode and the drain electrode.

In the semiconductor device of the present invention, the non-single-crystal semiconductor material constituting the non-single-crystal semiconductor layer is amorphous silicon or polycrystalline silicon.
With such a structure, the non-single-crystal semiconductor layer is formed in a state including crystal defects. Accordingly, surplus carriers can be captured by crystal defects included in the non-single-crystal semiconductor layer, and accumulation of surplus carriers in the channel region of the single-crystal semiconductor layer is prevented, thereby preventing an increase in channel potential. it can.

  Further, in the method for manufacturing a semiconductor device of the present invention, an insulating layer is formed on one surface side of a single crystal semiconductor substrate, and ions are implanted into the single crystal semiconductor substrate from the insulating layer side to form ions at a predetermined depth. Forming an implantation layer; forming a gate electrode on an insulating substrate; covering the gate electrode; forming a first insulating layer; and forming the ion implantation layer on the first insulating layer side of the insulating substrate. After bonding the insulating layer side of the single crystal semiconductor substrate formed with, the single crystal semiconductor substrate is separated at an ion implantation layer portion, and the insulating layer and the first insulating layer are formed on the insulating substrate. A step of forming a single crystal semiconductor layer, a step of patterning the single crystal semiconductor layer formed on the insulating substrate, a second insulating layer covering the patterned single crystal semiconductor layer, The single insulating layer Forming a non-single-crystal semiconductor layer covering the channel region at least in the opening, and forming the opening reaching the channel region of the crystalline semiconductor layer; and on the second insulating layer including the non-single-crystal semiconductor layer Forming a third insulating layer, forming contact holes reaching the source region and the drain region of the single crystal semiconductor layer in the third insulating layer and the second insulating layer, and contacting the drain region and the source region with the contact And a step of forming a source electrode and a drain electrode through holes.

By manufacturing in this way, a single crystal semiconductor layer having a predetermined thickness can be formed over the insulating substrate via the first insulating layer and the insulating layer. In addition, a non-single-crystal semiconductor layer can be formed on the opposite side of the single-crystal semiconductor layer from the gate electrode so as to cover the channel region of the single-crystal semiconductor layer. Further, by adjusting the positional relationship between the opening provided in the second insulating layer and the contact hole provided in the third insulating layer and the second insulating layer, the amorphous semiconductor layer is separated from the source electrode and the drain electrode. Can be provided.
Therefore, even when the channel region of the thin film transistor is in an electrically floating state, the increase in channel potential is prevented by the non-single-crystal semiconductor layer, the parasitic bipolar phenomenon in the semiconductor device is prevented, the electrical characteristics are improved, and excellent A semiconductor device exhibiting excellent electrical characteristics can be manufactured. Further, since the non-crystalline semiconductor layer and the source and drain electrodes can be provided apart from each other, the non-single-crystal semiconductor layer can be grounded by being connected to a wiring having a ground potential, for example, and the channel potential can be increased. Can be manufactured more effectively.

  Alternatively, in the method for manufacturing a semiconductor device of the present invention, an insulating layer is formed on one surface side of a single crystal semiconductor substrate, and ion implantation is performed from the insulating layer side into the single crystal semiconductor substrate to form an ion implantation layer. A step of forming a gate electrode on an insulating substrate, forming a first insulating layer covering the gate electrode, and forming the ion implantation layer on the first insulating layer side of the insulating substrate. After bonding the insulating layer side of the single crystal semiconductor substrate, the single crystal semiconductor substrate is separated at an ion implantation layer portion, and the single crystal semiconductor is disposed on the insulating substrate via the insulating layer and the first insulating layer. Forming a layer; forming a non-single-crystal semiconductor layer on the single-crystal semiconductor layer including a channel region, a source region, and a drain region of the single-crystal semiconductor layer; and Non-single crystal Patterning a conductor layer collectively, forming a second insulating layer covering the patterned single crystal semiconductor layer and the non-single crystal semiconductor layer, and forming the source of the non-single crystal semiconductor layer in the second insulating layer Forming a contact hole reaching the drain region and the drain region, and forming a source electrode and a drain electrode in the drain region and the source region through the contact hole, respectively.

By manufacturing in this way, a single crystal semiconductor layer having a predetermined thickness can be formed over the insulating substrate via the first insulating layer and the insulating layer. As described above, when the non-single-crystal semiconductor layer is provided over the channel region so as to be separated from the source electrode and the drain electrode, patterning of the single-crystal semiconductor layer, formation of the second insulating layer, patterning of the second insulating layer, It is necessary to form a non-single crystal semiconductor layer and pattern the non-single crystal semiconductor layer. On the other hand, according to the manufacturing method of the present invention, the single crystal semiconductor layer and the non-single crystal semiconductor layer can be patterned in a lump. In addition, there is no need to provide a third insulating layer. Moreover, a non-single-crystal semiconductor layer can be formed on the opposite side of the gate electrode so as to cover the channel region of the thin film transistor formed in the single-crystal semiconductor layer as in the above case.
Therefore, the number of steps can be significantly reduced and productivity can be improved as compared with the case where the non-single-crystal semiconductor layer is provided over the channel region so as to be separated from the source electrode and the drain electrode. In addition, even when the channel region of the thin film transistor is in an electrically floating state, an increase in channel potential is prevented by the non-single-crystal semiconductor layer, and the parasitic bipolar phenomenon in the semiconductor device is prevented to improve the electrical characteristics. A semiconductor device exhibiting excellent electrical characteristics can be manufactured.

In the active matrix substrate of the present invention, a plurality of scanning lines and a plurality of data lines are provided on an insulating substrate so as to intersect each other, and a single crystal semiconductor layer is provided in each pixel partitioned by the scanning lines and the data lines. An active matrix substrate provided with a thin film transistor having the gate electrode formed on the insulating substrate, the single crystal semiconductor layer provided on the gate electrode with an insulating layer interposed therebetween, And a non-single-crystal semiconductor layer formed to cover at least a channel region of the single-crystal semiconductor layer on a side opposite to the gate electrode of the single-crystal semiconductor layer.
With this structure, when a high voltage is applied to the drain of the thin film transistor, carriers are accelerated by a high electric field in the vicinity of the drain region of the single crystal semiconductor layer, and the crystal lattice collides with the carriers. Surplus carriers are generated by the impact ionization phenomenon caused by the collision. The generated surplus carriers move to the non-single-crystal semiconductor layer that covers the channel region of the single-crystal semiconductor layer. Surplus carriers that have moved to the non-single-crystal semiconductor layer are captured by crystal defects contained in the non-single-crystal semiconductor layer, and the crystal defects serve as recombination centers for the surplus carriers. Thus, excess carriers are prevented from accumulating in the channel region of the single crystal semiconductor layer, and an increase in channel potential is prevented.
Therefore, even when the channel region of the thin film transistor is in an electrically floating state, the increase in channel potential is prevented by the non-single-crystal semiconductor layer, the parasitic bipolar phenomenon is prevented, and the electrical characteristics of the thin film transistor are improved. Can do. Therefore, an active matrix substrate with high switching element reliability and low power consumption can be obtained.

The electro-optical device of the present invention includes the above active matrix substrate, a counter substrate facing the active matrix substrate, and an electro-optical layer sandwiched between the active matrix substrate and the counter substrate. It is characterized by that.
With this configuration, the reliability of the switching elements of the active matrix substrate constituting the electro-optical device can be improved and the power consumption can be reduced, so that an electro-optical device with high image quality and low power consumption can be obtained. Can do.

According to another aspect of the invention, an electronic apparatus includes the electro-optical device described above.
With this configuration, the image quality of the electro-optical device constituting the electronic apparatus can be improved and the power consumption can be reduced, so that the electronic apparatus can have high image quality and low power consumption.

Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number in each structure.
<First embodiment>
[Liquid Crystal Device]
As shown in FIGS. 1 and 2, a sealing material 52 is provided along the edge of the counter substrate 20 on the active matrix substrate 10 of the liquid crystal device 100, and is parallel to the edge of the counter substrate 20. Thus, a light shielding film 53 (peripheral parting) is provided as a frame. A data line driving circuit 201 and an external circuit connection terminal 202 are provided along one side of the active matrix substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 is provided on two sides adjacent to the one side. It is provided along.

  Furthermore, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the image display area A are provided on the remaining side of the active matrix substrate 10. Further, at least one corner of the counter substrate 20 is provided with a vertical conductive material 106 for establishing electrical continuity between the active matrix substrate 10 and the counter substrate 20. As shown in FIG. 2, the counter substrate 20 having substantially the same contour as the seal material 52 shown in FIG. 1 is fixed to the active matrix substrate 10 by the seal material 52, and the active matrix substrate 10, the counter substrate 20, A liquid crystal layer 50 is sealed between the two. Further, the opening provided in the sealing material 52 shown in FIG. 1 is a liquid crystal injection port 52 a and is sealed by the sealing material 25.

  Further, as shown in FIG. 2, on the upper side (liquid crystal layer 50 side) of the substrate body 10A of the active matrix substrate 10, a pixel electrode 9 made of a transparent conductive material such as ITO (indium tin oxide) is seen in a plan view. A plurality of matrixes are formed. On the upper side of the pixel electrode 9, an alignment film 18 subjected to a predetermined alignment process such as a rubbing process is provided. The alignment film 18 is formed of an organic material such as polyimide. On the other hand, the counter substrate 20 is provided with a common electrode 21 over the entire surface of the substrate body 20A, and a predetermined alignment process is performed on the lower side (the liquid crystal layer 50 side) of the common electrode 21 in the same manner as the alignment film 18. An alignment film 22 is provided. Similar to the pixel electrode 9, the common electrode 21 is also formed of a transparent conductive material such as ITO. The alignment film 22 is also formed of the same organic material as the alignment film 18. Moreover, a polarizer (not shown) is formed on the opposite side of the counter substrate 20 from the liquid crystal layer 50 of the substrate body 20A.

  Between the active matrix substrate 10 and the counter substrate 20, which are configured in this manner and arranged so that the pixel electrode 9 and the common electrode 21 face each other, liquid crystal is sealed in a space surrounded by a seal material 52, A liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 18 and 22 in a state where an electric field from the pixel electrode 9 is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed.

[Active matrix substrate]
As shown in FIGS. 3A and 3B, a plurality of transparent pixel electrodes 9 are provided in a matrix in the image display area A (see FIG. 1) on the active matrix substrate 10. . On the active matrix substrate 10, data lines 6 and scanning lines 3 are provided along the vertical and horizontal boundaries of the pixel electrodes 9. The data lines 6 extend in the y direction, and a plurality of data lines 6 are provided at predetermined intervals in the x direction. Further, a plurality of scanning lines 3 intersecting these data lines 6 and extending in the x direction are provided at predetermined intervals in the y direction. A region surrounded by two adjacent data lines 6 and scanning lines 3 is a pixel region C (a region indicated by a one-dot difference line 9 ′ in the drawing). Such pixel regions C are formed in a matrix on the active matrix substrate 10.

  In each pixel region C, a pixel electrode 9 having a substantially rectangular shape in a plan view made of a transparent conductive material such as ITO is provided. A thin film transistor (hereinafter referred to as TFT 30) is provided in the vicinity of the intersection with the data line 6 and the scanning line 3. The TFT 30 is formed by laminating the single crystal semiconductor layer 1, the data line 6, and the pixel electrode 9 on the gate electrode 26 that is formed by branching in the y direction from the scanning line 3 formed on the substrate body 10 </ b> A. Yes.

  The data line 6 and the pixel electrode 9 are provided so as to protrude in the x direction so as to partially overlap the single crystal semiconductor layer 1 in a planar manner. The data line 6 and the pixel electrode 9 are electrically connected to a source electrode and a drain electrode to be described later via contact holes 5 and 8, respectively. The pixel electrode 9 is electrically connected to the drain region of the single crystal semiconductor layer 1 described later via the drain electrode. The data line 6 is electrically connected to a source region of a single crystal semiconductor layer 1 described later via a source electrode.

[Semiconductor device]
As shown in FIG. 4, a gate electrode 26 is formed on the substrate body 10 </ b> A of the active matrix substrate 10. As described above, the gate electrode 26 is branched from the scanning line 3 and is formed of a conductive material such as metal. The substrate body 10A is made of a transparent insulating material such as quartz, for example. A first insulating layer 11 is formed on the substrate body 10 </ b> A so as to cover the gate electrode 26. The first insulating layer 11 is formed of a transparent insulating material such as SiO ₂ (silicon oxide), for example. A single crystal semiconductor layer 1 is formed on the first insulating layer 11 with an insulating layer 2 interposed therebetween. The insulating layer 2 is formed of, for example, SiO ₂ or the like, and the single crystal semiconductor layer 1 is formed of, for example, single crystal Si (silicon) or the like.

  A portion of the single crystal semiconductor layer 1 facing the gate electrode 26 is a channel region 1 c of the TFT 30. In the single crystal semiconductor layer 1, a source region 1s and a drain region 1d to which a slight amount of impurities are added are formed adjacent to the channel region 1c. The TFT 30 employs an LDD (Lightly Doped Drain) structure, and the source region 1s and the drain region 1d have a high concentration region with a relatively high impurity concentration and a relatively low concentration region (LDD region), respectively. Is formed. That is, the low concentration source region and the high concentration source region formed in order from the channel region 1c side constitute the source region 1s, and the low concentration drain region and the high concentration drain region formed in order from the channel region 1c side are the drain. Region 1d is configured.

A second insulating layer 12 is formed on the insulating layer 2 so as to cover the single crystal semiconductor layer 1. Similarly to the first insulating layer 11, the second insulating layer 12 is formed of a transparent insulating material such as SiO ₂ . The second insulating layer 12 is provided with an opening 12 h that reaches the channel region 1 c of the single crystal semiconductor layer 1. A non-single crystal semiconductor layer 4 is formed in the opening 12h. The non-single crystal semiconductor layer 4 is formed of a semiconductor material including crystal defects such as amorphous silicon and polycrystalline silicon.

A third insulating layer 13 is formed on the second insulating layer 12 so as to cover the non-single-crystal semiconductor layer 4. The third insulating layer 13 is formed of a transparent insulating material such as SiO ₂ as with the first insulating layer 11. Contact holes 14 and 15 are formed that are spaced apart from the non-single crystal semiconductor layer 4 and penetrate the third insulating layer 13 and the second insulating layer 12 to reach the source region 1s and the drain region 1d of the single crystal semiconductor layer 1. Yes. A source electrode 16 and a drain electrode 17 are formed on the opposite side of the single crystal semiconductor layer 1 from the gate electrode 26. The source electrode 16 and the drain electrode 17 are electrically connected to the source region 1s and the drain region 1d of the single crystal semiconductor layer 1 through contact holes 14 and 15, respectively.

As described above, the data line 6 and the pixel electrode 9 are electrically connected to the source electrode 16 and the drain electrode 17 through the contact holes 5 and 8, respectively (see FIG. 3).
As described above, the non-single crystal semiconductor layer 4 is formed on the surface of the single crystal semiconductor layer 1 opposite to the surface on which the gate electrode 26 is formed so as to cover at least the channel region 1c of the single crystal semiconductor layer 1. ing. In this embodiment, in particular, the non-single crystal semiconductor layer 4 is formed on the channel region 1c of the single crystal semiconductor layer 1, and the non-single crystal semiconductor layer 4 is provided apart from the source electrode 16 and the drain electrode 17. Yes.

Next, the operation of this embodiment will be described.
As shown in FIG. 4, when a high voltage is applied to the drain region 1d of the TFT 30, carriers are accelerated by a high electric field in the vicinity of the drain region 1d of the single crystal semiconductor layer 1, and the crystal lattice collides with the carriers. Surplus carriers are generated by the impact ionization phenomenon caused by the collision of the crystal lattice and the carrier. The generated surplus carrier moves to the non-single-crystal semiconductor layer 4 covering the channel region 1c of the single-crystal semiconductor layer 1.

  Surplus carriers that have moved to the non-single-crystal semiconductor layer 4 are captured by crystal defects included in the non-single-crystal semiconductor layer 4, and the crystal defects serve as recombination centers for the surplus carriers. This prevents excess carriers from accumulating in the channel region 1c of the single crystal semiconductor layer 1 and prevents an increase in channel potential. Therefore, even if the single crystal semiconductor layer 1 of the TFT 30 is formed on the insulating layer 2 and the channel region 1c is in an electrically floating state, the increase in channel potential due to the accumulation of surplus carriers is caused by the non-single crystal semiconductor layer 4. Is prevented. Therefore, the parasitic bipolar phenomenon in the TFT 30 can be prevented and the electrical characteristics of the TFT 30 can be improved.

  Further, the source electrode 16 and the drain electrode 17 are connected to the source region 1 s and the drain region 1 d of the single crystal semiconductor layer 1, respectively, and the non-single crystal semiconductor layer 4 is provided apart from the source electrode 16 and the drain electrode 17. ing. Therefore, the single crystal semiconductor layer 1 can function as an active layer of the TFT 30. Further, the non-single-crystal semiconductor layer 4 can be grounded by being connected to a wiring having a ground potential, for example. Thereby, the responsiveness and electrical characteristics of the TFT 30 can be improved, and the increase in channel potential can be prevented more effectively.

[Method for Manufacturing Semiconductor Device]
Next, a manufacturing method of the TFT 30 of this embodiment will be described.
As shown in FIG. 5 (a), one surface side of a single crystal semiconductor substrate 1m formed of a single crystal semiconductor material such as single crystal Si is thermally oxidized in an oxygen atmosphere at about 1000 ° C., for example. _An insulating layer 2 made of 2 is formed. Next, hydrogen ions (H ⁺ ) are implanted into the single crystal semiconductor substrate 1m from the insulating layer 2 side to form a hydrogen ion implanted layer 1b (ion implanted layer).

As a result, as shown in FIG. 5B, an ion implantation layer 1b is formed at a predetermined depth inside the single crystal semiconductor substrate 1m. As hydrogen ion implantation conditions at this time, for example, the acceleration energy is set to 60 to 150 keV, and the dose is set to 5 × 10 ¹⁶ atoms / cm ² to 15 × 10 ¹⁶ atoms / cm ² . Note that the single crystal semiconductor layer 1 having a different thickness can be formed by changing the acceleration voltage of hydrogen ions to change the implantation depth of hydrogen ions.

Next, as shown in FIG. 6A, the gate electrode 26 is formed on the substrate body 10A made of a transparent insulating material such as quartz by, for example, sputtering, photolithography, or the like. Furthermore, the gate electrode 26 is covered on the substrate body 10A, and the first electrode made of a transparent insulating material such as SiO ₂ is formed by, for example, a low pressure chemical vapor deposition method (LPCVD) method or a plasma chemical vapor deposition method (PECVD method). An insulating layer 11 is formed. Next, as shown in FIG. 6B, the surface of the first insulating layer 11 is planarized by, for example, CMP (chemical mechanical polishing).

Next, as shown in FIGS. 7A and 7B, the insulating layer 2 side of the single crystal semiconductor substrate 1m in which the hydrogen ion implantation layer 1b is formed on the first insulating layer 11 side of the substrate body 10A. Then, the single crystal semiconductor substrate 1m is bonded onto the substrate body 10A at, for example, a temperature of about room temperature to 200 ° C. In the present embodiment, the insulating layer 2 and the substrate main body 10A side of the first insulating layer 11 of the single crystal semiconductor substrate 1m side, since each is formed by SiO _2, can be well joined above.

  Next, as shown in FIG. 7C, the single crystal semiconductor substrate 1m is separated at the hydrogen ion implantation layer 1b, and the single crystal semiconductor is provided on the substrate body 10A via the insulating layer 2 and the first insulating layer 11. Layer 1 is formed. Thereby, the single crystal semiconductor layer 1 having a predetermined thickness can be formed on the substrate main body 10A formed of quartz or the like via the first insulating layer 11 and the insulating layer 2. The single crystal semiconductor substrate 1m can be separated by heat treatment. Specifically, the substrate main body 10A and the single crystal semiconductor substrate 1m bonded together as shown in FIG. 7B are heat-treated at, for example, 350 ° C. to 700 ° C. in an inert gas atmosphere such as nitrogen or argon. Apply.

  As a result, ions are implanted into the defect layer region formed in the hydrogen ion implanted layer 1b to form a microcavity, and the bonding of the semiconductor crystal is broken. As a result, the single crystal semiconductor substrate 1m is separated at the peak position of the ion concentration in the hydrogen ion implanted layer 1b. Since unevenness of about several nanometers remains on the surface of the single crystal semiconductor layer 1 after separation, the surface is planarized by using, for example, a touch polish that polishes the surface to a slight amount (less than 10 nm of polishing amount) using the CMP method. .

Next, as shown in FIG. 8A, the planarized single crystal semiconductor layer 1 formed on the substrate body 10A is patterned into an island shape as shown in FIG. 8B by photolithography or the like. To do.
Further, impurity ions serving as donors or acceptors are implanted into the single crystal semiconductor layer 1 using a photoresist as a mask to form a source region 1s and a drain region 1d. Further, the portion facing the gate electrode 26 becomes the channel region 1c. Here, in the source region 1s and the drain region 1d, a high concentration region having a relatively high impurity concentration and a low concentration region (LDD region) having a relatively low impurity concentration are formed.

Next, as shown in FIG. 8C, the second insulating layer 12 is formed of an insulating material such as SiO ₂ by, for example, LPCVD or PECVD so as to cover the patterned single crystal semiconductor layer 1. Next, an opening 12 h reaching the channel region 1 c of the single crystal semiconductor layer 1 is formed in the second insulating layer 12 by, for example, photolithography. Next, crystal defects such as amorphous silicon and polycrystalline silicon are formed by, for example, LPCVD so as to cover the second insulating layer 12 including the channel region 1c of the single crystal semiconductor layer 1 exposed by the opening 12h. A semiconductor material layer is formed.

  Next, as shown in FIG. 9A, the non-single-crystal semiconductor layer 4 is formed by patterning the non-single-crystal semiconductor material layer on the second insulating layer 12 by a photolithography method or the like. Thus, the non-single-crystal semiconductor layer 4 can be formed on the surface of the single crystal semiconductor layer 1 opposite to the surface on which the gate electrode 26 is formed so as to cover the channel region 1c of the single crystal semiconductor layer 1. .

Next, as shown in FIG. 9B, the third insulating layer is formed on the second insulating layer 12 including the non-single crystal semiconductor layer 4 by an insulating material such as SiO ₂ by, for example, LPCVD method or PECVD method. 13 is formed. Next, contact holes 14 and 15 that penetrate the third insulating layer 13 and the second insulating layer 12 and reach the source region 1s and the drain region 1d of the single crystal semiconductor layer 1 are formed by photolithography or the like. Next, a conductive material layer such as a metal is formed on the third insulating layer 13 including the inside of the contact holes 14 and 15 by, for example, a sputtering method or the like, and is patterned by a photolithography method or the like.

  As a result, as shown in FIG. 9C, the source electrode 16 and the drain electrode 17 connected to the source region 1s and the drain region 1d through the contact holes 14 and 15 are formed. Thus, by adjusting the positional relationship between the opening 12 h provided in the second insulating layer 12 and the contact holes 14 and 15 provided in the third insulating layer 13 and the second insulating layer 12, the non-single-crystal semiconductor layer 4 and the source The electrode 16 and the drain electrode 17 can be provided apart from each other.

  As described above, according to the manufacturing method of the present embodiment, the non-single-crystal semiconductor layer 4 covering the channel region 1c of the TFT 30 is formed. Therefore, even if the channel region 1c of the TFT 30 is in an electrically floating state, the increase in channel potential is prevented by the non-single crystal semiconductor layer 4, and the parasitic bipolar phenomenon in the TFT 30 is prevented to improve the electrical characteristics. A TFT 30 exhibiting excellent electrical characteristics can be manufactured. Further, since the non-single-crystal semiconductor layer 4 and the source electrode 16 and the drain electrode 17 can be provided apart from each other, the non-single-crystal semiconductor layer 4 can be grounded by being connected to a wiring having a ground potential, for example. Therefore, it is possible to more effectively prevent the channel potential from increasing.

<Second embodiment>
Next, a second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the non-single crystal semiconductor layer 4 described in the first embodiment is formed so as to include the source region 1s and the drain region 1d of the single crystal semiconductor layer 1, and the source electrode 16 and the drain electrode 17 are not formed. The difference is that it is connected to the single crystal semiconductor layer 4. Since the other points are the same as in the first embodiment, the same parts are denoted by the same reference numerals and description thereof is omitted.

[Semiconductor device]
As shown in FIG. 10, the non-single crystal semiconductor layer 4 includes the channel region 1 c of the single crystal semiconductor layer 1 and the source region 1 s and drain region 1 d of the single crystal semiconductor layer 1 so as to cover the single crystal semiconductor layer 1. Is formed. The source electrode 16 and the drain electrode 17 provided on the side opposite to the surface on which the gate electrode 26 of the single crystal semiconductor layer 1 is formed are connected to the source region 1 s of the single crystal semiconductor layer 1 and the source region 1 s of the single crystal semiconductor layer 1 through the non-single crystal semiconductor layer 4. Each is electrically connected to the drain region 1d.

  Therefore, as in the first embodiment described above, it is possible to prevent excess carriers from accumulating in the channel region 1c by the non-single crystal semiconductor layer 4, and to prevent a parasitic bipolar phenomenon. Further, as compared with the case where the non-single crystal semiconductor layer 4 is provided apart from the source electrode 16 and the drain electrode 17 as in the first embodiment described above, the manufacturing process of the TFT 30 is simplified and the productivity is improved. be able to.

[Method for Manufacturing Semiconductor Device]
Next, a manufacturing method of the TFT 30 of this embodiment will be described.
As shown in FIGS. 5 to 7, similarly to the first embodiment described above, a single crystal semiconductor having a predetermined thickness on a substrate body 10 </ b> A formed of quartz or the like via a first insulating layer 11 and an insulating layer 2. A layer 1 is formed, and as shown in FIG. 11A, the surface of the single crystal semiconductor layer 1 is planarized by using, for example, a CMP method. Next, as shown in FIG. 11B, a non-single-crystal semiconductor layer 4 is formed on substantially the entire surface of the single-crystal semiconductor layer 1 by LPCVD or the like. As in the first embodiment, the non-single-crystal semiconductor layer 4 is formed of a semiconductor material containing crystal defects such as amorphous silicon and polycrystalline silicon.

Next, as shown in FIG. 11C, the single crystal semiconductor layer 1 and the non-single crystal semiconductor layer 4 are collectively patterned by a photolithography method or the like. Next, as in the first embodiment, the source region 1 s, the drain region 1 d, and the channel region 1 c are formed in the single crystal semiconductor layer 1. Thus, the single crystal semiconductor layer 1 is covered with the non-single crystal semiconductor layer 4 including the channel region 1c, the source region 1d, and the drain region 1d. Next, as shown in FIG. 12A, an insulating material such as SiO ₂ is used to cover the patterned single crystal semiconductor layer 1 and non-single crystal semiconductor layer 4 by, for example, LPCVD method or PECVD method. The second insulating layer 12 is formed.

  Next, as shown in FIG. 12B, contact holes 14 and 15 that penetrate the second insulating layer 12 and reach the source region 1s and the drain region 1d of the non-single-crystal semiconductor layer 4 are formed by photolithography or the like. . Then, a conductive material layer such as a metal material is formed on the second insulating layer 12 including the insides of the contact holes 14 and 15 by a sputtering method or the like, and is patterned by a photolithography method or the like. As a result, as shown in FIG. 12C, the source electrode 16 and the drain electrode 17 are formed in the source region 1s and the drain region 1d through the contact holes 14 and 15, respectively.

  By manufacturing in this way, the single crystal semiconductor layer 1 having a predetermined thickness is formed on the substrate main body 10A formed of an insulating material such as quartz as in the first embodiment via the first insulating layer 11 and the insulating layer 2. Can be formed. Further, when the non-single crystal semiconductor layer 4 is provided on the channel region 1c so as to be separated from the source electrode 16 and the drain electrode 17 as in the first embodiment, the patterning of the single crystal semiconductor layer 1 and the second insulating layer 12 It is necessary to individually perform the formation, the patterning of the second insulating layer 12, the formation of the non-single crystal semiconductor layer 4, and the patterning of the non-single crystal semiconductor layer 4.

  On the other hand, according to the manufacturing method of the present embodiment, the single crystal semiconductor layer 1 and the non-single crystal semiconductor layer 4 can be patterned at once. In addition, it is not necessary to provide the third insulating layer 13. Moreover, the non-single-crystal semiconductor layer 4 can be formed on the opposite side of the gate electrode 26 so as to cover the channel region 1c formed in the single-crystal semiconductor layer 1 as in the first embodiment.

  Therefore, compared with the case where the non-single-crystal semiconductor layer 4 is provided on the channel region 1c so as to be separated from the source electrode 16 and the drain electrode 17, the number of steps can be significantly reduced and the productivity can be improved. Further, even when the channel region 1c of the TFT 30 is in an electrically floating state, the increase in channel potential is prevented by the non-single crystal semiconductor layer 4, and the parasitic bipolar phenomenon in the TFT 30 is prevented to improve the electrical characteristics. A TFT 30 exhibiting excellent electrical characteristics can be manufactured.

[Electronics]
Next, an example of an electronic device including the liquid crystal device described in the above embodiment will be described.
As shown in FIG. 13A, the mobile phone 500 includes a liquid crystal display unit 501 using the liquid crystal device 100 described in the above embodiment. Further, as shown in FIG. 13B, an information processing apparatus 600 such as a word processor or a personal computer includes an input unit such as a keyboard 601, an information processing apparatus main body 603, and a liquid crystal display unit using the liquid crystal device 100 described in the above embodiment. 602. As shown in FIG. 13C, the wrist watch 700 includes a liquid crystal display unit 701 using the liquid crystal device 100 described in the above embodiment.

  As described above, the electronic apparatus illustrated in FIGS. 13A to 13C includes the liquid crystal device 100 described in the above embodiment in the display unit. Therefore, the image quality of the display unit is improved, and the display unit is provided. Low power consumption can be achieved. Therefore, each of the electronic devices 500, 600, and 700 described above is a high-quality electronic device with high image quality and low power consumption.

  In the projection type liquid crystal display device (electronic device) 800 shown in FIG. 14, the liquid crystal module including the liquid crystal device 100 described above is employed as the RGB light valves 822, 823, and 824. In this liquid crystal projector 800, when light is emitted from a lamp unit 812 of a white light source such as a metal halide lamp, R, G, and B are reflected by three mirrors 815, 816, 817 and two dichroic mirrors 813, 814. The light components R, G, and B corresponding to the three primary colors are separated and guided to the corresponding light valves 822, 823, and 824 (liquid crystal devices), respectively. At this time, since the optical component B has a long optical path, the light component B is guided through a relay lens system 821 including an incident lens 818, a relay lens 819, and an exit lens 820 in order to prevent light loss. The light components R, G, and B corresponding to the three primary colors respectively modulated by the light valves 822, 823, and 824 are incident on the dichroic prism 825 (light combining means) from three directions and are combined again, and then the projection lens. A color image is projected onto a screen 827 or the like via 826.

  According to the above configuration, since the RGB light valves 822, 823, and 824 including the liquid crystal device 100 described in the above embodiment are provided, the projection type liquid crystal display device improves the quality of the displayed image. be able to.

  The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention uses various electro-optical elements using a reflective liquid crystal display device, electroluminescence (EL), a digital micromirror device (DMD, registered trademark), or fluorescence by plasma emission or electron emission. The present invention can also be applied to an electro-optical device and an electronic apparatus including the electro-optical device.

  Further, as a method for forming an insulating layer on one surface of the single crystal semiconductor substrate, an LPCVD method or a plasma chemical vapor deposition method (PECVD method) may be used instead of the above-described thermal oxidation. In addition, it is desirable that the surface of the first insulating layer formed on the substrate body is flattened as in the above-described embodiment, but if the surface can be sufficiently flat when forming the first insulating layer, the surface is flattened. May be omitted. As a method for planarizing the single crystal semiconductor layer after being separated from the single crystal semiconductor substrate, a hydrogen annealing method in which heat treatment is performed in a hydrogen atmosphere can be used in addition to the above-described CMP. Further, the TFT does not have an LDD (Lightly Doped Drain) structure, and a normal TFT may be formed.

1 is a plan view illustrating a schematic configuration of a liquid crystal device according to a first embodiment of the present invention. It is sectional drawing which follows the H-H 'line | wire of FIG. It is a top view which represents typically the pixel area | region of an active matrix substrate. It is sectional drawing showing schematic structure of the thin-film transistor in 1st embodiment. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is sectional drawing showing schematic structure of the thin-film transistor in 2nd embodiment. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is process sectional drawing which shows the manufacturing method of a thin-film transistor equally. It is a perspective view which shows the example of an electronic device. It is a figure which shows the structure of the projection type liquid crystal display device which is an example of an electronic device.

Explanation of symbols

1 single crystal semiconductor layer, 1b ion implantation layer, 1c channel region, 1d drain region, 1m single crystal semiconductor substrate, 1s source region, 2 insulating layer, 3 scan line, 4 non-single crystal semiconductor layer, 6 data line, 10 active Matrix substrate, 10A substrate body (insulating substrate), 11 first insulating layer (insulating layer), 12 second insulating layer, 12h opening, 13 third insulating layer, 14 contact hole, 15 contact hole, 16 source electrode, 17 Drain electrode, 20 Counter substrate, 26 Gate electrode, 30 TFT (thin film transistor), 50 Liquid crystal layer (electro-optical layer), 100 Liquid crystal device (electro-optical device), 500 Mobile phone (electronic device), 600 Information processing device (electronic device) ), 700 Watch (electronic device), 800 Projector (electronic device), C Pixel area (pixel)

Claims (9)

A semiconductor device including a thin film transistor having a single crystal semiconductor layer over an insulating substrate,
A gate electrode is formed on the insulating substrate, the single crystal semiconductor layer is formed on the gate electrode via an insulating layer, and the surface of the single crystal semiconductor layer opposite to the surface on which the gate electrode is formed And a non-single-crystal semiconductor layer covering at least a channel region of the single-crystal semiconductor layer.   The non-single-crystal semiconductor layer is formed on the channel region of the single-crystal semiconductor layer, and a source electrode and a drain electrode connected to a source region and a drain region of the single-crystal semiconductor layer, respectively, 2. The semiconductor according to claim 1, wherein the semiconductor device is provided on a surface opposite to a surface on which a gate electrode is formed, and the source electrode and the drain electrode are provided apart from the non-single-crystal semiconductor layer. apparatus.   The non-single-crystal semiconductor layer is formed to cover the single-crystal semiconductor layer including the channel region of the single-crystal semiconductor layer and the source and drain regions of the single-crystal semiconductor layer. 2. The source electrode and the drain electrode provided on a side opposite to the gate electrode are electrically connected to the source region and the drain region through the non-single crystal semiconductor layer, respectively. The semiconductor device described.   4. The semiconductor device according to claim 1, wherein the non-single-crystal semiconductor material constituting the non-single-crystal semiconductor layer is amorphous silicon or polycrystalline silicon. Forming an insulating layer on one side of the single crystal semiconductor substrate, and performing ion implantation from the insulating layer side into the single crystal semiconductor substrate to form an ion implantation layer at a predetermined depth;
Forming a gate electrode on an insulating substrate and covering the gate electrode to form a first insulating layer;
After the insulating layer side of the single crystal semiconductor substrate on which the ion implantation layer is formed is bonded to the first insulating layer side of the insulating substrate, the single crystal semiconductor substrate is separated at a portion of the ion implantation layer. Forming a single crystal semiconductor layer on the insulating substrate via the insulating layer and the first insulating layer;
Patterning the single crystal semiconductor layer formed on the insulating substrate;
A second insulating layer covering the patterned single crystal semiconductor layer is formed, an opening reaching the channel region of the single crystal semiconductor layer is formed in the second insulating layer, and at least the opening covers the channel region. Forming a single crystal semiconductor layer;
A third insulating layer is formed on the second insulating layer including the non-single-crystal semiconductor layer, and contacts reaching the source region and the drain region of the single-crystal semiconductor layer on the third insulating layer and the second insulating layer. Forming a hole, and forming a source electrode and a drain electrode through the contact hole in the drain region and the source region;
A method for manufacturing a semiconductor device, comprising: Forming an insulating layer on one side of the single crystal semiconductor substrate, and performing ion implantation from the insulating layer side into the single crystal semiconductor substrate to form an ion implantation layer;
Forming a gate electrode on an insulating substrate and covering the gate electrode to form a first insulating layer;
After bonding the insulating layer side of the single crystal semiconductor substrate on which the ion implantation layer is formed to the first insulating layer side of the insulating substrate, the single crystal semiconductor substrate is separated at a portion of the ion implantation layer. Forming a single crystal semiconductor layer on the insulating substrate via the insulating layer and the first insulating layer;
Forming a non-single-crystal semiconductor layer on the single-crystal semiconductor layer including the channel region, the source region, and the drain region of the single-crystal semiconductor layer;
Patterning the single crystal semiconductor layer and the non-single crystal semiconductor layer together;
A second insulating layer covering the patterned single crystal semiconductor layer and the non-single crystal semiconductor layer is formed, and contact holes reaching the source region and the drain region of the non-single crystal semiconductor layer are formed in the second insulating layer. Forming a source electrode and a drain electrode in the drain region and the source region through the contact holes, respectively.
A method for manufacturing a semiconductor device, comprising: An active matrix substrate in which a plurality of scanning lines and a plurality of data lines are provided on an insulating substrate so as to cross each other, and a thin film transistor having a single crystal semiconductor layer is provided in each pixel defined by the scanning lines and the data lines. There,
The thin film transistor includes a gate electrode formed on the insulating substrate, the single crystal semiconductor layer provided on the gate electrode with an insulating layer interposed therebetween, and the gate electrode of the single crystal semiconductor layer opposite to the gate electrode. An active matrix substrate, comprising: a non-single-crystal semiconductor layer formed so as to cover at least a channel region of the single-crystal semiconductor layer.   An electric matrix comprising: the active matrix substrate according to claim 7; a counter substrate facing the active matrix substrate; and an electro-optic layer sandwiched between the active matrix substrate and the counter substrate. Optical device.   An electronic apparatus comprising the electro-optical device according to claim 8.

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