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JP2008258643A - Semiconductor device - Google Patents

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JP2008258643A
JP2008258643A JP2008131197A JP2008131197A JP2008258643A JP 2008258643 A JP2008258643 A JP 2008258643A JP 2008131197 A JP2008131197 A JP 2008131197A JP 2008131197 A JP2008131197 A JP 2008131197A JP 2008258643 A JP2008258643 A JP 2008258643A
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igbt
base region
electrode
region
semiconductor
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Katsuyuki Torii
克行 鳥居
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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  • Engineering & Computer Science (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To downsize a semiconductor device equipped with a plurality of stacked semiconductor elements. <P>SOLUTION: In the semiconductor device equipped with a first semiconductor element (1) and a second semiconductor element (2) stacked on the first one (1), the second semiconductor element (2) is formed by using an insulated bipolar transistor. A first base region (16) includes a first conductive type (P) and a peripheral base region (27) formed adjacent to a side (31c) of a semiconductor substrate (31). A PN junction diode between an emitter electrode (22) and a collector electrode (23) of the insulated gate bipolar transistor is built through a PN junction formed between the peripheral base region (27) and the first base region (16). The semiconductor device can be downsized without connecting an external diode to the second semiconductor element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

積層した複数の半導体素子を備える半導体装置に関する。   The present invention relates to a semiconductor device including a plurality of stacked semiconductor elements.

近年の電子部品の小型化に対応する一手段として、ブリッジ回路を構成するスイッチング素子を積層したスタックドマルチ構造が半導体装置に適用されている。スタックドマルチ構造を適用した半導体装置は、例えば下記特許文献１により公知である。特許文献１に示す半導体装置によれば、パワー半導体素子を用いたＨ型ブリッジ回路を支持板の占有面積を減少しつつ集積度を向上して形成できる。しかしながら、積層するパワー半導体素子にＭＯＳＦＥＴ（ＭＯＳ型電界効果トランジスタ）を用いると、チップサイズが大きくなり、小型化が達成できない。そのため、チップサイズを小さく形成できるＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）が用いられていた。しかしながら、ＩＧＢＴを使用すると、同時に外付けのダイオードもＨ型ブリッジ回路に組み込まなければならず、結果的に小型化が達成できなかった。また、外付けのダイオードにより製品コストが増加した。   As one means corresponding to the recent miniaturization of electronic components, a stacked multi structure in which switching elements constituting a bridge circuit are stacked is applied to a semiconductor device. A semiconductor device to which a stacked multi structure is applied is known from, for example, Patent Document 1 below. According to the semiconductor device disclosed in Patent Document 1, an H-type bridge circuit using a power semiconductor element can be formed with an improved degree of integration while reducing the area occupied by the support plate. However, if a MOSFET (MOS field effect transistor) is used as the power semiconductor element to be stacked, the chip size becomes large and miniaturization cannot be achieved. Therefore, an IGBT (insulated gate bipolar transistor) that can be formed with a small chip size has been used. However, when an IGBT is used, an external diode must be incorporated into the H-type bridge circuit at the same time, and as a result, miniaturization cannot be achieved. In addition, the product cost increased due to the external diode.

一般的にＭＯＳＦＥＴは、例えば図５に示すように、Ｎ型導電型を有するドレイン領域(51)、Ｐ型導電型を有し且つドレイン領域(51)の上面(51a)に形成されたベース領域(52)、Ｎ型導電型を有し且つベース領域(52)の上面(52a)に形成されたソース領域(53)を備える半導体基板(50)と、ゲート絶縁膜(54)を介してソース領域(53)の上面(53a)に形成されたゲート電極(55)と、ベース領域(52)及びソース領域(53)の上面(52a,53a)に形成されたソース電極(56)と、ドレイン領域(51)の下面(51b)に形成されたドレイン電極(57)とを備える。よって、Ｐ型導電型を有するベース領域(52)とＮ型導電型を有するドレイン領域(51)との間にダイオード(58)が形成され、これを保護用の内蔵ダイオードとして利用できる。   As shown in FIG. 5, for example, a MOSFET generally has a drain region (51) having an N-type conductivity type and a base region having a P-type conductivity type and formed on the upper surface (51a) of the drain region (51). (52) a semiconductor substrate (50) having a source region (53) having an N-type conductivity and formed on the upper surface (52a) of the base region (52), and a source via a gate insulating film (54) The gate electrode (55) formed on the upper surface (53a) of the region (53), the source electrode (56) formed on the upper surface (52a, 53a) of the base region (52) and the source region (53), and the drain A drain electrode (57) formed on the lower surface (51b) of the region (51). Therefore, a diode (58) is formed between the base region (52) having P-type conductivity and the drain region (51) having N-type conductivity, and this can be used as a protective built-in diode.

これに対し、ＩＧＢＴは、図６に示すように、Ｐ型導電型を有するコレクタ領域(61)、Ｎ型導電型を有し且つコレクタ領域(61)の上面(61a)に形成された第１のベース領域(62)、Ｐ型導電型を有し且つ第１のベース領域(62)の上面(62a)に形成された第２のベース領域(63)、Ｎ型導電型を有し且つ第２のベース領域(63)の上面(63a)に形成されたエミッタ領域(64)を備える半導体基板(60)と、ゲート絶縁膜(65)を介して第２のベース領域(63)の上面(63a)に形成されたゲート電極(66)と、第２のベース領域(63)及びエミッタ領域(64)の上面(63a,64a)に形成されたエミッタ電極(67)と、コレクタ領域(61)の下面(61b)に形成されたコレクタ電極(68)とを備える。よって、ＩＧＢＴでは、図６に示すように、Ｐ型導電型を有する第２のベース領域(63)とＮ型導電型を有する第１のベース領域(62)と、Ｐ型導電型を有するコレクタ領域(61)とＮ型導電型を有する第１のベース領域(62)との間にそれぞれダイオード(69)が形成され、逆極性のダイオード(69)が直列接続される。このため、このダイオードを保護用の内蔵ダイオードとして有効利用することが困難であった。出力端子に誘導成分を有する負荷を接続したＨブリッジ回路等では、ＩＧＢＴに負荷の誘導成分により発生した逆起電力が印加され易い。このため、各ＩＧＢＴにダイオードを並列に接続して、逆起電力により発生した逆方向電流（サージ電流）をダイオードを介してバイパスさせる必要がある。   On the other hand, as shown in FIG. 6, the IGBT has a collector region (61) having a P-type conductivity type and a first region formed on the upper surface (61a) of the N-type conductivity type and the collector region (61). A second base region (63) having a P-type conductivity and formed on the upper surface (62a) of the first base region (62), and having an N-type conductivity. A semiconductor substrate (60) having an emitter region (64) formed on the upper surface (63a) of the second base region (63), and an upper surface of the second base region (63) via a gate insulating film (65). A gate electrode (66) formed on 63a), an emitter electrode (67) formed on the upper surface (63a, 64a) of the second base region (63) and emitter region (64), and a collector region (61) And a collector electrode (68) formed on the lower surface (61b). Therefore, in the IGBT, as shown in FIG. 6, the second base region 63 having P-type conductivity, the first base region 62 having N-type conductivity, and the collector having P-type conductivity. Diodes (69) are respectively formed between the region (61) and the first base region (62) having the N-type conductivity type, and diodes (69) of opposite polarity are connected in series. For this reason, it is difficult to effectively use this diode as a protective built-in diode. In an H bridge circuit or the like in which a load having an inductive component is connected to the output terminal, a back electromotive force generated by the inductive component of the load is easily applied to the IGBT. For this reason, it is necessary to connect a diode in parallel to each IGBT and to bypass the reverse current (surge current) generated by the counter electromotive force via the diode.

下記特許文献２は、コレクタ領域の中央側にこれと反対導電型のカソード領域を形成すると共に、カソード領域の上方にＰ型導電型を有するアノード領域を形成し、これによりダイオードを内蔵したＩＧＢＴを開示する。特許文献２のＩＧＢＴによれば、外付けダイオードを省略して、ＩＧＢＴを積層したスタックドマルチ構造の半導体装置を形成することができる。   In Patent Document 2 below, a cathode region having the opposite conductivity type is formed on the center side of the collector region, and an anode region having a P-type conductivity type is formed above the cathode region, whereby an IGBT incorporating a diode is formed. Disclose. According to the IGBT of Patent Document 2, an external diode can be omitted, and a stacked multi-structure semiconductor device in which IGBTs are stacked can be formed.

国際公開第２００５／０１８００１号公報International Publication No. 2005/018001 特開平９−１９１１１０号公報JP-A-9-191110

しかしながら、特許文献２のＩＧＢＴでは、平面方向に対して半導体基板の同位置にアノード領域とカソード領域とを重ねて形成しなければならないため、両半導体領域の位置決めが難しく、生産性の点で問題があった。また、ＩＧＢＴのオン時には、半導体基板の中央側のセル領域に電流が流れるが、半導体装置のオフ時に逆方向電流が発生したときにも、この逆方向電流が半導体基板の中央側を流れるため、電流により発生する熱が半導体基板の中央側に集中して、半導体基板の電気的特性が劣化するおそれがあった。
よって、本発明は、ダイオードを内蔵したＩＧＢＴを積層して、従来より小型化され、且つ生産も容易なスタックドマルチ構造の半導体装置を提供することを目的とする。また、電流により発生する熱が半導体基板の中央側に集中することを防止した半導体装置を提供することを目的とする。 However, in the IGBT of Patent Document 2, since the anode region and the cathode region must be formed at the same position of the semiconductor substrate with respect to the planar direction, it is difficult to position both semiconductor regions, which is problematic in terms of productivity. was there. In addition, when the IGBT is on, a current flows in the cell region on the center side of the semiconductor substrate, but when a reverse current is generated when the semiconductor device is off, the reverse current flows through the center side of the semiconductor substrate. There is a possibility that the heat generated by the current is concentrated on the center side of the semiconductor substrate and the electrical characteristics of the semiconductor substrate are deteriorated.
Therefore, an object of the present invention is to provide a stacked multi-structure semiconductor device that is made smaller than before and is easy to produce by stacking IGBTs with built-in diodes. It is another object of the present invention to provide a semiconductor device that prevents heat generated by current from being concentrated on the center side of the semiconductor substrate.

本発明の半導体装置は、第１の半導体素子(1)と、第１の半導体素子(1)上に積層された第２の半導体素子(2)とを備える。第２の半導体素子(2)は、絶縁ゲート型バイポーラトランジスタであり、第１導電型(P)を有するコレクタ領域(15)、第１導電型(P)とは反対の第２導電型(N)を有し且つコレクタ領域(15)の上面(15a)に形成された第１のベース領域(16)、第１のベース領域(16)に隣接して形成された第１導電型(P)を有する第２のベース領域(17)、第２のベース領域(17)に隣接して形成された第２導電型(N)を有するエミッタ領域(18)を備える半導体基体(31)と、絶縁体(9)を介して第２のベース領域(17)の上面(17a)に形成されたゲート電極(25)と、第２のベース領域(17)及びエミッタ領域(18)の上面(17a,18a)に形成されたエミッタ電極(22)と、コレクタ領域(15)の下面(15b)に形成されたコレクタ電極(23)とを備える。第１のベース領域(16)は、第１導電型(P)を有し且つ半導体基体(31)の側面(31c)に近接して形成される周辺ベース領域(27)を有する。周辺ベース領域(27)と第１のベース領域(16)との間に形成されるＰＮ接合により、絶縁ゲート型バイポーラトランジスタのエミッタ電極(22)とコレクタ電極(23)との間にＰＮ接合ダイオード(21)を形成する。   The semiconductor device of the present invention includes a first semiconductor element (1) and a second semiconductor element (2) stacked on the first semiconductor element (1). The second semiconductor element (2) is an insulated gate bipolar transistor, a collector region (15) having the first conductivity type (P), and a second conductivity type (N) opposite to the first conductivity type (P). ) And the first base region (16) formed on the upper surface (15a) of the collector region (15), the first conductivity type (P) formed adjacent to the first base region (16) A semiconductor base (31) having a second base region (17) having a first conductive region and an emitter region (18) having a second conductivity type (N) formed adjacent to the second base region (17); A gate electrode (25) formed on the upper surface (17a) of the second base region (17) through the body (9), and upper surfaces (17a, 17) of the second base region (17) and the emitter region (18). An emitter electrode (22) formed on 18a) and a collector electrode (23) formed on the lower surface (15b) of the collector region (15). The first base region (16) has a peripheral base region (27) which has the first conductivity type (P) and is formed close to the side surface (31c) of the semiconductor substrate (31). A PN junction diode is formed between the emitter electrode (22) and the collector electrode (23) of the insulated gate bipolar transistor by a PN junction formed between the peripheral base region (27) and the first base region (16). (21) is formed.

第１の半導体素子(1)及び第２の半導体素子(2)は、接続される負荷の誘導成分による逆起電力により、第１の半導体素子(1)及び第２の半導体素子(2)のエミッタ電極(22)からコレクタ電極(23)へ逆方向に誘起される逆方向電流（サージ電流）が発生するが、第１導電型(P)を有する周辺ベース領域(27)と第２導電型(N)を有する第１のベース領域(16)とによりダイオード(21)を形成することによって、第２の半導体素子(2)に外付けのダイオードを接続する必要がなく、半導体装置を小型に形成することができる。半導体装置のオン時には、側面(31c)から離間した半導体基体(31)の中央側に電流が流れるが、半導体装置のオフ時に逆方向電流が発生したとき、逆方向電流が半導体基体(31)の側面(31c)に近接して流れるため、電流により発生する熱が半導体基体(31)の中央側に集中して、半導体基体(31)の電気的特性が劣化することを防止できる。また、半導体基体(31)の側面(31c)に近接してダイオード(21)が形成されるため、ダイオード(21)に流れる逆方向電流により発生する熱は、半導体基体(31)の側面(31c)から良好に外部に放出される。   The first semiconductor element (1) and the second semiconductor element (2) are connected to the first semiconductor element (1) and the second semiconductor element (2) by the back electromotive force due to the inductive component of the connected load. A reverse current (surge current) induced in the reverse direction from the emitter electrode (22) to the collector electrode (23) is generated, but the peripheral base region (27) having the first conductivity type (P) and the second conductivity type. By forming the diode (21) with the first base region (16) having (N), there is no need to connect an external diode to the second semiconductor element (2), and the semiconductor device can be made compact. Can be formed. When the semiconductor device is turned on, a current flows to the center side of the semiconductor substrate (31) spaced apart from the side surface (31c), but when a reverse current is generated when the semiconductor device is turned off, the reverse current is Since it flows close to the side surface (31c), it is possible to prevent the heat generated by the current from being concentrated on the center side of the semiconductor substrate (31) and degrading the electrical characteristics of the semiconductor substrate (31). Further, since the diode (21) is formed close to the side surface (31c) of the semiconductor substrate (31), the heat generated by the reverse current flowing through the diode (21) ) Is released to the outside well.

本発明によれば、より小型化され且つ信頼性の高いスタックドマルチ構造の半導体装置を提供することができる。   According to the present invention, it is possible to provide a stacked multi-structure semiconductor device that is further downsized and highly reliable.

以下、ＩＧＢＴによりＨ型ブリッジ回路を構成した本発明による半導体装置の一実施の形態を図１〜図４について説明する。   An embodiment of a semiconductor device according to the present invention in which an H-type bridge circuit is constituted by an IGBT will be described below with reference to FIGS.

本実施の形態の半導体装置は、図１〜図３に示すように、放熱性を有する銅又はアルミニウム等の金属製の支持板(5)と支持板(5)の上に順次積層されて固着された第１の半導体素子としての第１のＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）(1)及び第２の半導体素子としての第２のＩＧＢＴ(2)を有する第１の半導体素子積層体(7)と、支持板(5)の上に順次積層されて固着された第３の半導体素子としての第３のＩＧＢＴ(3)及び第４の半導体素子としての第４のＩＧＢＴ(4)を有する第２の半導体素子積層体(8)と、第１のＩＧＢＴ(1)から第４のＩＧＢＴ(4)までのスイッチング動作を制御する制御素子(13)とを備え、図４に示すＨ型ブリッジ回路(10)を構成する。   As shown in FIGS. 1 to 3, the semiconductor device of the present embodiment is laminated and fixed on a support plate (5) made of metal such as copper or aluminum having heat dissipation and a support plate (5) in sequence. First semiconductor element stack (7) having a first IGBT (insulated gate bipolar transistor) (1) as a first semiconductor element and a second IGBT (2) as a second semiconductor element And a second IGBT having a third IGBT (3) as a third semiconductor element and a fourth IGBT (4) as a fourth semiconductor element, which are sequentially stacked and fixed on the support plate (5). 4 and the control element (13) for controlling the switching operation from the first IGBT (1) to the fourth IGBT (4), and an H-type bridge circuit ( Configure 10).

第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)の上面電極（エミッタ電極及びゲート電極）と、制御素子(13)の上面電極（制御電極）又は支持板(5)の周囲に配置された複数の外部リード(33)とは、ワイヤ（リード細線）(29)により接続される。第１のＩＧＢＴ(1)のエミッタ電極(22)と第２のＩＧＢＴ(2)のコレクタ電極(23)との接続点(A1)と、第３のＩＧＢＴ(3)のエミッタ電極(22)と第４のＩＧＢＴ(4)のコレクタ電極(23)との接続点(A2)との間には、交流電流により駆動される例えば冷陰極蛍光放電管である負荷(6)が接続される。Ｈ型ブリッジ回路(10)を構成する半導体装置は樹脂封止体(34)により被覆されて一体化されるが、外部リード(33)は樹脂封止体(34)から外部に導出される。この外部リード(33)の一部に負荷(6)が接続される。 The upper surface electrodes (emitter electrode and gate electrode) of the first IGBT (1) to the fourth IGBT (4) and the upper surface electrode (control electrode) of the control element (13) or the support plate (5) are arranged. The plurality of external leads (33) are connected by wires (lead fine wires) (29). The connection point (A 1 ) between the emitter electrode (22) of the first IGBT (1) and the collector electrode (23) of the second IGBT (2), and the emitter electrode (22) of the third IGBT (3) And a connection point (A 2 ) between the collector electrode (23) of the fourth IGBT (4) and a load (6), which is a cold cathode fluorescent discharge tube driven by an alternating current, is connected. . The semiconductor device constituting the H-type bridge circuit (10) is covered and integrated with the resin sealing body (34), but the external lead (33) is led out from the resin sealing body (34). A load (6) is connected to a part of the external lead (33).

第１の半導体素子積層体(7)を構成する第１のＩＧＢＴ(1)及び第２のＩＧＢＴ(2)の一方並びに第２の半導体素子積層体(8)を構成する第３のＩＧＢＴ(3)及び第４のＩＧＢＴ(4)の一方は、Ｈ型ブリッジ回路(10)のハイサイド側スイッチを構成し、第１の半導体素子積層体(7)を構成する第１のＩＧＢＴ(1)及び第２のＩＧＢＴ(2)の他方並びに第２の半導体素子積層体(8)を構成する第３のＩＧＢＴ(3)及び第４のＩＧＢＴ(4)の他方は、Ｈ型ブリッジ回路(10)のローサイド側スイッチを構成する。本実施の形態では、ハイサイド側の第１のＩＧＢＴ(1)と第３のＩＧＢＴ(3)との上に、ローサイド側の第２のＩＧＢＴ(2)と第４のＩＧＢＴ(4)が固着されて第１及び第２の半導体素子積層体(7,8)が構成され、第１の半導体素子積層体(7)と第２の半導体素子積層体(8)との間に設けられる制御素子(13)と共に、半田、ろう材又は銀ペーストから成る接着剤(32)により単一の支持板(5)上に固着される。   One of the first IGBT (1) and the second IGBT (2) constituting the first semiconductor element laminate (7) and the third IGBT (3 constituting the second semiconductor element laminate (8) ) And the fourth IGBT (4) constitute the high-side switch of the H-type bridge circuit (10), and the first IGBT (1) and the first IGBT (1) constituting the first semiconductor element stack (7) The other of the second IGBT (2) and the other of the third IGBT (3) and the fourth IGBT (4) constituting the second semiconductor element stack (8) are the H-type bridge circuit (10). Configure the low-side switch. In the present embodiment, the second IGBT (2) and the fourth IGBT (4) on the low side are fixed on the first IGBT (1) and the third IGBT (3) on the high side. Thus, the first and second semiconductor element stacks (7, 8) are configured, and the control element provided between the first semiconductor element stack (7) and the second semiconductor element stack (8). Together with (13), it is fixed on a single support plate (5) by an adhesive (32) made of solder, brazing material or silver paste.

第２のＩＧＢＴ(2)及び第４のＩＧＢＴ(4)は、平面的に見て、第１のＩＧＢＴ(1)及び第３のＩＧＢＴ(3)の上面(1a,3a)及び下面(1b,3b)と比較して小さい面積の上面(2a,4a)及び下面(2b,4b)を有する。第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)は、図１に示すように、半導体基体としてのシリコン単結晶等から成る半導体基板(31)を備え、各半導体基板(31)は、第１導電型としてのＰ型導電型を有するコレクタ領域(15)と、Ｐ型導電型とは反対の第２導電型としてのＮ型導電型を有し且つコレクタ領域(15)の上面(15a)に形成された第１のベース領域(16)と、Ｐ型導電型を有し且つ第１のベース領域(16)に隣接して上面(16a)側に形成された第２のベース領域(17)と、Ｎ型導電型を有し且つ第２のベース領域(17)に隣接して上面(17a)側に形成されたエミッタ領域(18)とを備える。   The second IGBT (2) and the fourth IGBT (4) are, as viewed in plan, the upper surface (1a, 3a) and the lower surface (1b, 1) of the first IGBT (1) and the third IGBT (3). Compared with 3b), the upper surface (2a, 4a) and the lower surface (2b, 4b) have a smaller area. As shown in FIG. 1, each of the first IGBT (1) to the fourth IGBT (4) includes a semiconductor substrate (31) made of a silicon single crystal or the like as a semiconductor substrate, and each semiconductor substrate (31) A collector region (15) having a P-type conductivity type as a first conductivity type and an N-type conductivity type as a second conductivity type opposite to the P-type conductivity type and an upper surface (15a) of the collector region (15) ) And a second base region (having a P-type conductivity type) and formed on the upper surface (16a) side adjacent to the first base region (16). 17) and an emitter region (18) having an N-type conductivity and formed on the upper surface (17a) side adjacent to the second base region (17).

また、第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)は、絶縁体としてのゲート絶縁膜(9)を介して第２のベース領域(17)の上面(17a)に形成されたゲート電極（制御電極）(25)と、第２のベース領域(17)及びエミッタ領域(18)の上面(17a,18a)に形成されたエミッタ電極（上面電極）(22)と、コレクタ領域(15)の下面(15b)に形成されたコレクタ電極（底面電極）(23)とをそれぞれ備える。エミッタ領域(18)と第１のベース領域(16)との間に挟まれた第２のベース領域(17)の上にゲート絶縁膜(9)を介して形成されるゲート電極(25)により、周知のチャネル領域が形成される。   The first IGBT (1) to the fourth IGBT (4) are gates formed on the upper surface (17a) of the second base region (17) through a gate insulating film (9) as an insulator. An electrode (control electrode) (25), an emitter electrode (upper surface electrode) (22) formed on the upper surface (17a, 18a) of the second base region (17) and the emitter region (18), and a collector region (15 And a collector electrode (bottom electrode) (23) formed on the lower surface (15b). A gate electrode (25) formed on a second base region (17) sandwiched between the emitter region (18) and the first base region (16) via a gate insulating film (9). A well-known channel region is formed.

第２のベース領域(17)は、半導体基板(31)の平面方向に対して、第１のベース領域(16)内に格子状又はストライプ状に並列して配置される。また、エミッタ領域(18)は、第２のベース領域(17)の縁部に沿って互いに対向するように配置される。更に、ゲート電極(25)は、隣り合う第２のベース領域(17)に跨るように第２のベース領域(17)の間にストライプ状に形成される。これにより、半導体素子の活性領域の最小単位であるセル(30)が形成される。第２のベース領域(17)は、第１のベース領域(16)内に島状に形成してもよい。図示しないが、半導体基板(31)の上面(31a)には、ゲート電極(25)と電気的に接続するゲートバスラインが半導体基板(31)の周面に沿って形成される。ゲートバスラインは、アルミニウム等の導電性金属により形成され、ストライプ状に形成されたゲート電極(25)の延長部分を被覆して、ゲート電極(25)と電気的に接続される。   The second base region (17) is arranged in parallel in a lattice shape or a stripe shape in the first base region (16) with respect to the planar direction of the semiconductor substrate (31). The emitter region (18) is disposed so as to face each other along the edge of the second base region (17). Further, the gate electrode (25) is formed in a stripe shape between the second base regions (17) so as to straddle the adjacent second base regions (17). As a result, the cell (30) which is the minimum unit of the active region of the semiconductor element is formed. The second base region (17) may be formed in an island shape within the first base region (16). Although not shown, a gate bus line electrically connected to the gate electrode (25) is formed on the upper surface (31a) of the semiconductor substrate (31) along the peripheral surface of the semiconductor substrate (31). The gate bus line is formed of a conductive metal such as aluminum, covers an extended portion of the gate electrode (25) formed in a stripe shape, and is electrically connected to the gate electrode (25).

導電性の接着剤(32)により、第１のＩＧＢＴ(1)のエミッタ電極(22)と第２のＩＧＢＴ(2)のコレクタ電極(23)とが電気的に接続され、第３のＩＧＢＴ(3)のエミッタ電極(22)と第４のＩＧＢＴ(4)のコレクタ電極(23)とが電気的に接続される。ゲート絶縁膜(9)は、例えば二酸化シリコンにより形成され、ゲート絶縁膜(9)の上面に例えばポリシリコンから成るゲート電極(25)が形成される。また、ゲート電極(25)の周囲には、ゲート電極(25)とエミッタ電極(22)とを電気的に絶縁する例えば二酸化シリコンから成る層間絶縁膜(19)が形成される。エミッタ電極(22)及びコレクタ電極(23)は、例えばアルミニウム又はアルミニウムとニッケルとを積層した積層体により形成される。   By the conductive adhesive (32), the emitter electrode (22) of the first IGBT (1) and the collector electrode (23) of the second IGBT (2) are electrically connected, and the third IGBT ( The emitter electrode (22) of 3) and the collector electrode (23) of the fourth IGBT (4) are electrically connected. The gate insulating film (9) is made of, for example, silicon dioxide, and a gate electrode (25) made of, for example, polysilicon is formed on the upper surface of the gate insulating film (9). Further, an interlayer insulating film (19) made of, for example, silicon dioxide for electrically insulating the gate electrode (25) and the emitter electrode (22) is formed around the gate electrode (25). The emitter electrode (22) and the collector electrode (23) are formed of, for example, aluminum or a laminate in which aluminum and nickel are laminated.

図１に示すように、各ＩＧＢＴ(1,2,3,4)の第１のベース領域(16)は、半導体基板(31)の側面(31c)に近接する周辺部(26)を有し、第１のベース領域(16)の周辺部(26)に隣接して形成されたＰ型導電型を有する周辺ベース領域(27)により、半導体基板(31)の側面(31c)に近接してダイオード(21)が形成される。図示する半導体装置では、第２のベース領域(17)及びエミッタ領域(18)が半導体基板(31)の一角を形成する２つの側面(31c)から離間して素子中央側に形成されるのに対し、第１のベース領域(16)の周辺部(26)及び周辺ベース領域(27)が半導体基板(31)の２つの側面(31c)に隣接して形成される。即ち、図１に示す各ＩＧＢＴ(1,2,3,4)は、半導体基板(31)の側面(31c)側に形成された環状の周辺部(26)と、この周辺部(26)に囲まれて素子中央側に配置された中央部とを有し、周辺部(26)にダイオード(21)が形成され、中央部にセル(30)が形成される。周辺ベース領域(27)は、半導体基板(31)の上面(31a)にホウ素等の不純物を拡散して、第２のベース領域(17)と共に形成することができる。よって、製造コストを増加せず、既存と同一の製造工程により周辺ベース領域(27)を形成できる。本実施の形態では、第２のベース領域(17)に対向する側の周辺ベース領域(27)内にエミッタ領域(18)を形成しているが、周辺ベース領域(27)内にはエミッタ領域(18)を形成しなくてもよい。   As shown in FIG. 1, the first base region (16) of each IGBT (1, 2, 3, 4) has a peripheral portion (26) close to the side surface (31c) of the semiconductor substrate (31). In the vicinity of the side surface (31c) of the semiconductor substrate (31) by the peripheral base region (27) having P-type conductivity formed adjacent to the peripheral portion (26) of the first base region (16). A diode (21) is formed. In the semiconductor device shown in the figure, the second base region (17) and the emitter region (18) are formed on the element center side apart from the two side surfaces (31c) forming one corner of the semiconductor substrate (31). In contrast, the peripheral portion (26) and the peripheral base region (27) of the first base region (16) are formed adjacent to the two side surfaces (31c) of the semiconductor substrate (31). That is, each IGBT (1, 2, 3, 4) shown in FIG. 1 has an annular peripheral portion (26) formed on the side surface (31c) side of the semiconductor substrate (31), and the peripheral portion (26). A diode (21) is formed in the peripheral part (26), and a cell (30) is formed in the central part. The peripheral base region (27) can be formed together with the second base region (17) by diffusing impurities such as boron into the upper surface (31a) of the semiconductor substrate (31). Therefore, the peripheral base region (27) can be formed by the same manufacturing process as the existing one without increasing the manufacturing cost. In the present embodiment, the emitter region (18) is formed in the peripheral base region (27) on the side facing the second base region (17), but the emitter region is formed in the peripheral base region (27). (18) may not be formed.

第１のベース領域(16)の周辺部(26)の上面(26a)に形成されたダイオード電極(24)を備える。図示する半導体装置では、ゲート電極(25)及びエミッタ電極(22)が半導体基板(31)の２つの側面(31c)から離間して形成されるのに対し、ダイオード電極(24)が半導体基板(31)の２つの側面(31c)に隣接して形成される。ダイオード電極(24)とエミッタ電極(22)との間には、間隙(20)が形成され、ダイオード電極(24)とエミッタ電極(22)とを電気的に分離する。ダイオード電極(24)とエミッタ電極(22)との絶縁性を向上するために、ダイオード電極(24)とエミッタ電極(22)との間に二酸化シリコンから成る図示しない絶縁膜を形成してもよい。絶縁膜は、層間絶縁膜(19)を形成する工程時に、層間絶縁膜(19)と共に形成できる。ダイオード電極(24)は、例えばワイヤ(28)を形成するアルミニウムとの接着性の高い同じアルミニウム又はシリコン含有アルミニウムにより形成される。また、ダイオード電極(24)は、平坦に形成された上面(24a)を有し、周知のワイヤボンディング法により、同様に上面が平坦に形成された支持板(5)又は外部リード(33)とワイヤ(28)により結線される。ダイオード電極(24)と外部リード(33)とをワイヤ(28)により結線する工程は、第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)の上面電極と制御素子(13)の上面電極又は外部リード(33)とをワイヤ(29)により結線する工程と同一工程により行うことができるため、製造コストが増加せず、既存と同一の製造工程により半導体装置を製造できる。   A diode electrode (24) formed on the upper surface (26a) of the peripheral portion (26) of the first base region (16) is provided. In the illustrated semiconductor device, the gate electrode (25) and the emitter electrode (22) are formed apart from the two side surfaces (31c) of the semiconductor substrate (31), whereas the diode electrode (24) is formed on the semiconductor substrate (31). 31) formed adjacent to the two side surfaces (31c). A gap (20) is formed between the diode electrode (24) and the emitter electrode (22), and the diode electrode (24) and the emitter electrode (22) are electrically separated. In order to improve insulation between the diode electrode (24) and the emitter electrode (22), an insulating film (not shown) made of silicon dioxide may be formed between the diode electrode (24) and the emitter electrode (22). . The insulating film can be formed together with the interlayer insulating film (19) during the step of forming the interlayer insulating film (19). The diode electrode (24) is made of, for example, the same aluminum or silicon-containing aluminum having high adhesion to the aluminum forming the wire (28). In addition, the diode electrode (24) has a flat upper surface (24a), and, by a well-known wire bonding method, similarly to the support plate (5) or external lead (33) whose upper surface is also formed flat. It is connected by a wire (28). The step of connecting the diode electrode (24) and the external lead (33) with the wire (28) includes the upper surface electrode of the first IGBT (1) to the fourth IGBT (4) and the upper surface electrode of the control element (13). Alternatively, it can be performed by the same process as the process of connecting the external lead (33) by the wire (29), so that the manufacturing cost does not increase and the semiconductor device can be manufactured by the same manufacturing process as the existing one.

第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)のダイオード電極(24)とコレクタ電極(23)とは、それぞれ電気的に接続され、図４に示すように、各ＩＧＢＴ(1,2,3,4)のエミッタとコレクタとの間にはダイオードが並列接続される。ハイサイド側スイッチを構成する第１のＩＧＢＴ(1)及び第３のＩＧＢＴ(3)は、正側端子に接続された外部リード(33)とダイオード電極(24)とをワイヤ(28)で接続することにより、正側端子に接続された別の外部リード(33)及び支持板(5)を通じてダイオード電極(24)とコレクタ電極(23)とが電気的に接続される。ローサイド側スイッチを構成する第２のＩＧＢＴ(2)及び第４のＩＧＢＴ(4)は、接続点(A1,A2)に接続された外部リード(33)とダイオード電極(24)とをワイヤ(28)で接続することにより、接続点(A1,A2)に接続された別の外部リード(33)及びワイヤ(29)を通じてダイオード電極(24)とコレクタ電極(23)とが電気的に接続される。 The diode electrode (24) and the collector electrode (23) of the first IGBT (1) to the fourth IGBT (4) are electrically connected to each other, and as shown in FIG. , 3, 4) are connected in parallel between the emitter and collector. The first IGBT (1) and the third IGBT (3) constituting the high side switch are connected to the external lead (33) connected to the positive terminal and the diode electrode (24) by the wire (28). As a result, the diode electrode (24) and the collector electrode (23) are electrically connected through another external lead (33) connected to the positive terminal and the support plate (5). The second IGBT (2) and the fourth IGBT (4) constituting the low-side switch are connected to the external lead (33) connected to the connection points (A 1 , A 2 ) and the diode electrode (24). by connecting at (28), the connection point (a 1, a 2) connected to a separate external lead (33) and the diode electrode (24) and the collector electrode (23) and is electrically through wires (29) Connected to.

第１のＩＧＢＴ(1)〜第４のＩＧＢＴ(4)には、Ｈ型ブリッジ回路(10)に接続される負荷(6)の誘導成分による逆起電力により、各ＩＧＢＴ(1,2,3,4)のエミッタ電極(22)からコレクタ電極(23)へ逆方向に誘起される逆方向電流（サージ電流）が発生するが、Ｐ型導電型を有する周辺ベース領域(27)とＮ型導電型を有する第１のベース領域(16)の周辺部(26)とによりダイオード(21)を形成し、周辺部(26)の上面(26a)に形成されたダイオード電極(24)とコレクタ電極(23)とを電気的に接続することによって、逆方向電流を周辺ベース領域(27)、第１のベース領域(16)の周辺部(26)及びダイオード電極(24)を通じてコレクタ電極(23)に流すことができる。よって、半導体装置に外付けのダイオードを接続する必要がなく、Ｈ型ブリッジ回路(10)を構成する半導体装置を小型に形成することができる。   The first IGBT (1) to the fourth IGBT (4) have each IGBT (1, 2, 3) by the back electromotive force due to the inductive component of the load (6) connected to the H-type bridge circuit (10). 4), a reverse current (surge current) induced in the reverse direction from the emitter electrode (22) to the collector electrode (23) is generated, but the peripheral base region (27) having P-type conductivity and N-type conductivity A diode (21) is formed by the peripheral portion (26) of the first base region (16) having a mold, and a diode electrode (24) and a collector electrode (on the upper surface (26a) of the peripheral portion (26) are formed. 23) is electrically connected to the collector electrode (23) through the peripheral base region (27), the peripheral portion (26) of the first base region (16) and the diode electrode (24). It can flow. Therefore, it is not necessary to connect an external diode to the semiconductor device, and the semiconductor device constituting the H-type bridge circuit (10) can be formed in a small size.

Ｈ型ブリッジ回路(10)を作動する際に、制御素子(13)により、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)と、第２のＩＧＢＴ(2)及び第３のＩＧＢＴ(3)とを交互にオン・オフ動作させて、スイッチング作動させることにより、接続点(A1)と(A2)との間に交互に逆方向の電流(I1,I2)を流して、負荷(6)を作動させることができる。第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)がオンのとき、第２のＩＧＢＴ(2)及び第３のＩＧＢＴ(3)がオフとなり、負荷(6)に一方向の電流(I1)が流れ、その後、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)がオフに切り換えられ、第２のＩＧＢＴ(2)及び第３のＩＧＢＴ(3)とがオンに切り換えられると、負荷(6)に他方向の電流(I2)が流れて、負荷(6)が交流電流により作動される。一方向の電流(I1)は、第１のＩＧＢＴ(1)、第４のＩＧＢＴ(4)及び支持板(5)に流れ、他方向の電流(I2)は、第２のＩＧＢＴ(2)、第３のＩＧＢＴ(3)及び支持板(5)に流れる。 When the H-type bridge circuit (10) is operated, the first IGBT (1) and the fourth IGBT (4), the second IGBT (2) and the third IGBT ( 3) are alternately turned on and off, and switching operation is performed, so that currents (I 1 , I 2 ) in the opposite direction flow alternately between the connection points (A 1 ) and (A 2 ). The load (6) can be activated. When the first IGBT (1) and the fourth IGBT (4) are on, the second IGBT (2) and the third IGBT (3) are off, and the load (6) has a one-way current (I 1 ) flows, and then the first IGBT (1) and the fourth IGBT (4) are turned off, and the second IGBT (2) and the third IGBT (3) are turned on. The current (I 2 ) in the other direction flows through the load (6), and the load (6) is operated by the alternating current. A current in one direction (I 1 ) flows through the first IGBT (1), the fourth IGBT (4), and the support plate (5), and a current in the other direction (I 2 ) flows into the second IGBT (2 ), Flows to the third IGBT (3) and the support plate (5).

このように、第１のＩＧＢＴ(1)から第４のＩＧＢＴ(4)までのスイッチング動作を行ない、直流電圧源を使用し、接続点(A1)と(A2)との間に接続された冷陰極蛍光放電管を点灯させることができる。半導体装置のオン時には、側面(31c)から離間した半導体基板(31)の中央側に電流が流れるが、半導体装置のオフ時に逆方向電流が発生したときは逆方向電流が半導体基板(31)の側面(31c)に近接して流れる。このため、オン電流の流れる電流通路とサージ電流の流れる電流通路とを分離することができ、電流により発生する熱が半導体基板(31)の中央側に集中して、半導体基板(31)の電気的特性が劣化することを防止できる。また、半導体基板(31)の側面(31c)に近接してダイオード(21)が形成されるため、ダイオード(21)に流れる逆方向電流により発生する熱は、半導体基板(31)の側面(31c)から良好に外部に放出される。図示するＨ型ブリッジ回路(10)では、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)がオンされて第２のＩＧＢＴ(2)及び第３のＩＧＢＴ(3)がオフされた際、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)を構成する半導体基板(31)の中央側に電流が流れる。次に、第２のＩＧＢＴ(2)及び第３のＩＧＢＴ(3)がオンされて、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)がオフされた際、第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)に逆方向電圧が印加される。この逆方向電圧に基づくサージ電流は第１のＩＧＢＴ(1)及び第４のＩＧＢＴ(4)を構成する半導体基板(31)に内蔵されたダイオード(21)をバイパスして流れるが、この電流は上述のように半導体基板(31)の側面(31c)に近接して流れる。 In this way, the switching operation from the first IGBT (1) to the fourth IGBT (4) is performed, and the DC voltage source is used to connect between the connection points (A 1 ) and (A 2 ). The cold cathode fluorescent discharge tube can be turned on. When the semiconductor device is on, a current flows to the center side of the semiconductor substrate (31) separated from the side surface (31c), but when a reverse current is generated when the semiconductor device is off, the reverse current is applied to the semiconductor substrate (31). It flows close to the side surface (31c). Therefore, the current path through which the on-current flows and the current path through which the surge current flows can be separated, and the heat generated by the current is concentrated on the center side of the semiconductor substrate (31), so that the electric current of the semiconductor substrate (31) is concentrated. It is possible to prevent deterioration of the physical characteristics. In addition, since the diode (21) is formed in the vicinity of the side surface (31c) of the semiconductor substrate (31), the heat generated by the reverse current flowing through the diode (21) is generated by the side surface (31c) of the semiconductor substrate (31). ) Is released to the outside well. In the illustrated H-type bridge circuit (10), when the first IGBT (1) and the fourth IGBT (4) are turned on, and the second IGBT (2) and the third IGBT (3) are turned off. A current flows to the center side of the semiconductor substrate (31) constituting the first IGBT (1) and the fourth IGBT (4). Next, when the second IGBT (2) and the third IGBT (3) are turned on and the first IGBT (1) and the fourth IGBT (4) are turned off, the first IGBT (1 ) And the fourth IGBT (4) are applied with a reverse voltage. The surge current based on the reverse voltage flows by bypassing the diode (21) built in the semiconductor substrate (31) constituting the first IGBT (1) and the fourth IGBT (4). As described above, it flows close to the side surface (31c) of the semiconductor substrate (31).

本発明の実施の形態は、前記実施の形態に限定されず、種々の変更が可能である。
図１に示す半導体装置では、周辺ベース領域(27)を半導体基板(31)の角部に形成したが、角部から離間した側面(31c)近傍に形成してもよい。 The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made.
In the semiconductor device shown in FIG. 1, the peripheral base region (27) is formed in the corner portion of the semiconductor substrate (31), but it may be formed in the vicinity of the side surface (31c) separated from the corner portion.

本発明は、複数の半導体素子を積重して形成された半導体装置、冷陰極蛍光放電管の駆動装置に使用されるＨブリッジ回路（フルブリッジ回路）等を構成する半導体装置に良好に適用できる。   INDUSTRIAL APPLICABILITY The present invention can be satisfactorily applied to a semiconductor device formed by stacking a plurality of semiconductor elements, a semiconductor device constituting an H bridge circuit (full bridge circuit) used for a cold cathode fluorescent discharge tube driving device, and the like. .

本発明による半導体装置の一実施の形態を示す部分拡大断面図The partial expanded sectional view which shows one Embodiment of the semiconductor device by this invention 図１の全体図Overall view of FIG. 図２の平面図Plan view of FIG. 図３の回路図Circuit diagram of FIG. 一般的なＭＯＳＦＥＴの断面図Cross section of a typical MOSFET 一般的なＩＧＢＴの断面図Cross section of a typical IGBT

符号の説明Explanation of symbols

(1)・・第１の半導体素子（第１のＩＧＢＴ）、 (2)・・第２の半導体素子（第２のＩＧＢＴ）、 (3)・・第３の半導体素子（第３のＩＧＢＴ）、 (4)・・第４の半導体素子（第４のＩＧＢＴ）、 (5)・・支持板、 (7)・・第１の半導体素子積層体、 (8)・・第２の半導体素子積層体、 (9)・・絶縁体（ゲート絶縁膜）、 (10)・・Ｈ型ブリッジ回路、 (13)・・制御素子、 (15)・・コレクタ領域、 (15a)・・上面、 (15b)・・下面、 (16)・・第１のベース領域、 (16a)・・上面、 (17)・・第２のベース領域、 (17a)・・上面、 (18)・・エミッタ領域、 (18a)・・上面、 (21)・・ダイオード、 (22)・・エミッタ電極、 (23)・・コレクタ電極、 (24)・・ダイオード電極、 (25)・・ゲート電極、 (26)・・周辺部、 (26a)・・上面、 (27)・・周辺ベース領域、 (31)・・半導体基体（半導体基板）、 (31c)・・側面、   (1) ··· First semiconductor element (first IGBT), (2) · · Second semiconductor element (second IGBT), (3) · · Third semiconductor element (third IGBT) (4) ・ ・ Fourth semiconductor device (fourth IGBT), (5) ・ ・ Support plate, (7) ・ ・ First semiconductor device stack, (8) ・ ・ Second semiconductor device stack Body, (9) ・ ・ Insulator (gate insulation film), (10) ・ ・ H type bridge circuit, (13) ・ ・ Control element, (15) ・ ・ Collector region, (15a) ・ ・ Top surface, (15b ) ・ ・ Bottom surface, (16) ・ ・ First base region, (16a) ・ ・ Top surface, (17) ・ ・ Second base region, (17a) ・ ・ Top surface, (18) ・ ・ Emitter region, ( 18a) ・ ・ Top surface, (21) ・ ・ Diode, (22) ・ ・ Emitter electrode, (23) ・ ・ Collector electrode, (24) ・ ・ Diode electrode, (25) ・ ・ Gate electrode, (26) ・ ・Peripheral part, (26a) ・ ・ Top surface, (27) ・ ・ Peripheral base region, (31) ・ ・Conductor substrate (semiconductor substrate), (31c) · · sides,

Claims (2)

第１の半導体素子と、該第１の半導体素子上に積層された第２の半導体素子とを備える半導体装置において、
前記第２の半導体素子は、絶縁ゲート型バイポーラトランジスタであり、
前記第２の半導体素子は、
第１導電型を有するコレクタ領域、第１導電型とは反対の第２導電型を有し且つ前記コレクタ領域の上面に形成された第１のベース領域、前記第１のベース領域に隣接して形成された第１導電型を有する第２のベース領域、前記第２のベース領域に隣接して形成された第２導電型を有するエミッタ領域を備える半導体基体と、
絶縁体を介して前記第２のベース領域の上面に形成されたゲート電極と、
前記第２のベース領域及びエミッタ領域の上面に形成されたエミッタ電極と、
前記コレクタ領域の下面に形成されたコレクタ電極とを備え、
前記第１のベース領域は、第１導電型を有し且つ前記半導体基体の側面に近接して形成される周辺ベース領域を有し、
該周辺ベース領域と前記第１のベース領域との間に形成されるＰＮ接合により、前記絶縁ゲート型バイポーラトランジスタの前記エミッタ電極と前記コレクタ電極との間にＰＮ接合ダイオードを形成することを特徴とする半導体装置。 In a semiconductor device comprising a first semiconductor element and a second semiconductor element stacked on the first semiconductor element,
The second semiconductor element is an insulated gate bipolar transistor;
The second semiconductor element is:
A collector region having a first conductivity type; a first base region having a second conductivity type opposite to the first conductivity type and formed on an upper surface of the collector region; and adjacent to the first base region A semiconductor base comprising a formed second base region having a first conductivity type, an emitter region having a second conductivity type formed adjacent to the second base region;
A gate electrode formed on the upper surface of the second base region via an insulator;
An emitter electrode formed on an upper surface of the second base region and the emitter region;
A collector electrode formed on the lower surface of the collector region,
The first base region has a peripheral base region having a first conductivity type and formed close to a side surface of the semiconductor substrate;
A PN junction diode is formed between the emitter electrode and the collector electrode of the insulated gate bipolar transistor by a PN junction formed between the peripheral base region and the first base region. Semiconductor device. 前記半導体基体の角部で且つ前記周辺ベース領域の上面に電極を形成し、
該電極にリード細線を接続した請求項１に記載の半導体装置。 Forming an electrode on a corner of the semiconductor substrate and on an upper surface of the peripheral base region;
The semiconductor device according to claim 1, wherein a thin lead wire is connected to the electrode.
JP2008131197A 2008-05-19 2008-05-19 Semiconductor device Pending JP2008258643A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219667A (en) * 1986-03-20 1987-09-26 Matsushita Electronics Corp Insulated gate type field-effect transistor
JPH11243200A (en) * 1998-02-26 1999-09-07 Toshiba Corp Semiconductor device
JP2001501043A (en) * 1997-07-19 2001-01-23 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Semiconductor device assembly and circuit
EP1231635A1 (en) * 2001-02-09 2002-08-14 STMicroelectronics S.r.l. Method for manufacturing an electronic power device and a diode in a same package
JP2005072519A (en) * 2003-08-28 2005-03-17 Sanken Electric Co Ltd Insulating gate type semiconductor element and semiconductor integrated circuit device provided therewith

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219667A (en) * 1986-03-20 1987-09-26 Matsushita Electronics Corp Insulated gate type field-effect transistor
JP2001501043A (en) * 1997-07-19 2001-01-23 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Semiconductor device assembly and circuit
JPH11243200A (en) * 1998-02-26 1999-09-07 Toshiba Corp Semiconductor device
EP1231635A1 (en) * 2001-02-09 2002-08-14 STMicroelectronics S.r.l. Method for manufacturing an electronic power device and a diode in a same package
JP2005072519A (en) * 2003-08-28 2005-03-17 Sanken Electric Co Ltd Insulating gate type semiconductor element and semiconductor integrated circuit device provided therewith

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