EP1657750B1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- EP1657750B1 EP1657750B1 EP04745370.9A EP04745370A EP1657750B1 EP 1657750 B1 EP1657750 B1 EP 1657750B1 EP 04745370 A EP04745370 A EP 04745370A EP 1657750 B1 EP1657750 B1 EP 1657750B1
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- European Patent Office
- Prior art keywords
- semiconductor
- semiconductor element
- support plate
- electrically connected
- semiconductor elements
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 158
- 238000005219 brazing Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 7
- 239000008393 encapsulating agent Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 20
- 230000006866 deterioration Effects 0.000 description 4
- 230000005855 radiation Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Definitions
- This invention relates to a semiconductor device, in particular, of the type made in smaller size and provided with a plurality of power semiconductors mounted on a single support plate.
- a single semiconductor device of H-type bridge circuit 10 shown in Figure 3 comprises first and third transistors 1 and 3 of high voltage side and second and fourth transistors 2 and 4 of low voltage side.
- First and second junctions A1 and A2 are provided respectively between an emitter electrode of first transistor 1 and a collector electrode of second transistor 2, and between an emitter electrode of third transistor 3 and a collector electrode of fourth transistor 4, and connected between first and second junctions A1 and A2 is an electric load 6 such as a cold cathode fluorescent lighting discharge tube driven by AC power.
- first and fourth transistors 1 and 4 and second and third transistors 2 and 3 are alternately turned on and off for alternate switching to cause adverse electric currents I1 and I2 to flow by turns through junctions A1 and A2 to activate load 6.
- switching operation of first to fourth transistors 1 to 4 converts DC power into AC power to turn on the discharge tube connected between junctions A1 and A2.
- a prior art single semiconductor device comprised of H-shaped bridge circuit 10 shown in Figure 3 is disadvantageous due to the increased plane size of the device because it requires a support plate (not shown) of larger size to mount all of first to fourth transistors 1 to 4 and a control IC therefor on a common plane of the support plate.
- Japanese Patent Disclosure No. 55-111151 presents a semiconductor device which has two semiconductor elements in the vertically layered structure to reduce the occupation area.
- power semiconductor elements are vertically layered in H-shaped bridge circuit, they inconveniently produces intensive heat during the operation without the desired heat radiation, causing deterioration in electric property of the semiconductor elements.
- an object of the present invention is to provide a semiconductor device which has a plurality of semiconductor elements layered in a smaller occupation area and operable with the desired heat radiation.
- the semiconductor device is defined in claim 1. It comprises a heat-radiative metallic support plate made of copper or aluminum, wherein said support plate comprises a pair of longitudinal side surfaces and a pair of lateral side surfaces.
- a plurality of lead terminals having positive and negative terminals are integrally formed with the support plate and are disposed around and at a certain distance from said support plate. Each positive terminal of said lead terminals is located at a longitudinal side surface of said support plate, at a position adjacent to a corner formed by the intersection of a longitudinal side surface and a lateral side surface of said support plate.
- a first semiconductor stack has first and second semiconductor elements. The first semiconductor element has a bottom electrode electrically connected to said support plate through a brazing material.
- the first semiconductor element further has an upper electrode electrically connected to a lower electrode of said second semiconductor element through a first electrically conductive and radiating layer.
- a second semiconductor stack has third and fourth semiconductor elements.
- the third semiconductor element has a bottom electrode electrically connected to said support plate through a brazing material.
- the third semiconductor element further has an upper electrode electrically connected to a lower electrode of said fourth semiconductor element through a second electrically conductive and radiating layer.
- the first to fourth semiconductor elements contribute to form an H-type bridge circuit.
- Each of said first to fourth semiconductor elements have a switching element.
- the semiconductor device further comprises a control circuit for controlling the switching operation of said first to fourth semiconductor elements so that said first and fourth semiconductor elements and said second and third semiconductor elements are alternately switched, and thereby when said first semiconductor element and said fourth semiconductor element are turned on together, said second semiconductor element and said third semiconductor element are turned off together, and thereby when said first semiconductor element and said fourth semiconductor element are turned off together, said second semiconductor element and said third semiconductor element are turned on together.
- the control circuit is mounted on said support plate between said first and second semiconductor stacks.
- Each of said first to fourth semiconductor elements have a control electrode electrically connected to a respective control electrode in said control circuit through a respective lead wire.
- Each of said second and fourth semiconductor elements have an upper electrode electrically connected to a negative terminal through a lead wire.
- Alternate switching of first and second semiconductor elements controls heat produced from first and second semiconductor elements because one of first and second semiconductor elements is turned on, while the other is turned off.
- first and second semiconductor elements When heavy electric current flows through first and second semiconductor elements, a large amount of heat produced from first and second semiconductor elements can be efficiently and fully discharged to the outside through radiating layer mounted between first and second power semiconductor elements without deterioration in electric characteristics of first and second semiconductor elements.
- first and second power semiconductor stacks are concurrently mounted on a single support plate, sufficient amount of heat can be released outside through first and second radiating layers mounted respectively between first and second semiconductor elements and between third and fourth semiconductor elements, thereby preventing degradation in electric property of first to fourth semiconductor elements.
- first and second radiating layers serve to reduce each conductive path for electric current flowing through first and second power semiconductor stacks because first and second radiating layers are in direct contact to first and second semiconductor elements and to third and fourth semiconductor elements, preventing occurrence of noise and electric power loss resulted from elongated conductive path for electric current.
- a first semiconductor element a first transistor
- a second semiconductor element a second transistor
- a third semiconductor element a third transistor
- (4)... a fourth semiconductor element a fourth transistor
- (5)... a support plate (6)... a load
- (7)... a first power semiconductor stack (8)... a second power semiconductor stack, (10)... a H-type bridge circuit, (11, 12)... radiating layers, (13)... a control circuit, (14, 15, 16, 17, 18, 19)... brazing material (solder),
- the semiconductor device comprises a metallic support plate 5 formed of heat-radiative copper or aluminum; first and second power semiconductor stacks 7 and 8 separately mounted on support plate 5; and a control circuit 13 of a semiconductor integrated circuit mounted on support plate 5 between first and second semiconductor stacks 7 and 8.
- First semiconductor stack 7 comprises first and second transistors (first and second power semiconductor or switching elements) 1 and 2
- second semiconductor stack 8 comprises third and fourth transistors (third and fourth power semiconductor or switching elements) 3 and 4.
- First to fourth transistors 1 to 4 are insulated gate bipolar transistors (IGBT) for forming four power transistors in H-type bridge circuit 10 shown in Figure 3 .
- IGBT insulated gate bipolar transistors
- each of first to fourth transistors 1 to 4 comprises a semiconductor substrate; base and emitter electrodes electrically connected to electrodes on semiconductor substrate; and a collector electrode formed on and electrically connected to a bottom surface. Interlayer insulation films 9 formed between emitter and base electrodes electrically isolate emitter and base electrodes.
- a collector electrode of first transistor 1 is secured on support plate 5 through a brazing material (solder) 14, and an emitter electrode of first transistor 1 is secured to a bottom surface of a first radiating layer 11 through a brazing material 15.
- a collector electrode of second transistor 2 is secured on first radiating layer 11 through a brazing material 16, and an emitter electrode of second transistor 2 is positioned at the uppermost location of first semiconductor stack 7.
- each of first and second radiating layers 11 and 12 comprises a metallic plate made of copper or aluminum which forms a heat sink, also called heat spreader, which can discharge heat generated from mostly second and fourth transistors 2 and 4 to the outside.
- radiating layers 11 and 12 may be formed of relatively thin solder layers.
- Each of emitter, collector and base electrodes in first to fourth transistors 1 to 4 shown in Figure 2 is connected in the circuit configuration shown in Figure 3 which comprises a plurality of lead terminals 20 connected to electrodes of first and second power semiconductor stacks 7 and 8 and control circuit 13.
- the semiconductor device has a plastic encapsulant 21 for sealing the whole circuit assembly and each inner end of lead terminals 20 whose outer ends extend out of plastic encapsulant 21.
- positive terminals of lead terminals 20 electrically connected to support plate 5 are in electric communication with a positive terminal of a DC power source not shown, and each emitter electrode of second and fourth transistors 2 and 4 is led to a negative terminal of DC power source.
- Each base terminal of first to fourth transistors 1 to 4 are connected to control circuit 13 formed of a semiconductor integrated circuit to receive control or drive signals from control circuit 13.
- first and fourth transistors 1 and 4 are turned on, second and third transistors 2 and 3 are turned off to supply a first electric current I1 to load 6.
- first and fourth transistors 1 and 4 are turned off, and second and third transistors 2 and 3 are turned on, electric current I2 flows through load 6 in the reverse direction from that of first electric current I1 to operate load 6 with AC power.
- first to fourth semiconductor elements 1 to 4 may be compound elements including switching elements such as transistors and other semiconductor elements.
- the present invention is applicable to a semiconductor device used in a driver for cold cathode fluorescent lighting discharge tubes.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Inverter Devices (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
- This invention relates to a semiconductor device, in particular, of the type made in smaller size and provided with a plurality of power semiconductors mounted on a single support plate.
- A single semiconductor device of H-
type bridge circuit 10 shown inFigure 3 comprises first andthird transistors fourth transistors first transistor 1 and a collector electrode ofsecond transistor 2, and between an emitter electrode ofthird transistor 3 and a collector electrode offourth transistor 4, and connected between first and second junctions A1 and A2 is anelectric load 6 such as a cold cathode fluorescent lighting discharge tube driven by AC power. - In operation of
bridge circuit 10, first andfourth transistors third transistors load 6. Thus, switching operation of first tofourth transistors 1 to 4 converts DC power into AC power to turn on the discharge tube connected between junctions A1 and A2. - A prior art single semiconductor device comprised of H-
shaped bridge circuit 10 shown inFigure 3 is disadvantageous due to the increased plane size of the device because it requires a support plate (not shown) of larger size to mount all of first tofourth transistors 1 to 4 and a control IC therefor on a common plane of the support plate. To overcome such a disadvantage, for example, Japanese Patent Disclosure No.55-111151 - Document
WO 02/058151 A1 - Accordingly, an object of the present invention is to provide a semiconductor device which has a plurality of semiconductor elements layered in a smaller occupation area and operable with the desired heat radiation.
- The semiconductor device according to the present invention is defined in
claim 1. It comprises a heat-radiative metallic support plate made of copper or aluminum, wherein said support plate comprises a pair of longitudinal side surfaces and a pair of lateral side surfaces. A plurality of lead terminals having positive and negative terminals are integrally formed with the support plate and are disposed around and at a certain distance from said support plate. Each positive terminal of said lead terminals is located at a longitudinal side surface of said support plate, at a position adjacent to a corner formed by the intersection of a longitudinal side surface and a lateral side surface of said support plate. A first semiconductor stack has first and second semiconductor elements. The first semiconductor element has a bottom electrode electrically connected to said support plate through a brazing material. The first semiconductor element further has an upper electrode electrically connected to a lower electrode of said second semiconductor element through a first electrically conductive and radiating layer. A second semiconductor stack has third and fourth semiconductor elements. The third semiconductor element has a bottom electrode electrically connected to said support plate through a brazing material. The third semiconductor element further has an upper electrode electrically connected to a lower electrode of said fourth semiconductor element through a second electrically conductive and radiating layer. The first to fourth semiconductor elements contribute to form an H-type bridge circuit. Each of said first to fourth semiconductor elements have a switching element. The semiconductor device further comprises a control circuit for controlling the switching operation of said first to fourth semiconductor elements so that said first and fourth semiconductor elements and said second and third semiconductor elements are alternately switched, and thereby when said first semiconductor element and said fourth semiconductor element are turned on together, said second semiconductor element and said third semiconductor element are turned off together, and thereby when said first semiconductor element and said fourth semiconductor element are turned off together, said second semiconductor element and said third semiconductor element are turned on together. The control circuit is mounted on said support plate between said first and second semiconductor stacks. Each of said first to fourth semiconductor elements have a control electrode electrically connected to a respective control electrode in said control circuit through a respective lead wire. Each of said second and fourth semiconductor elements have an upper electrode electrically connected to a negative terminal through a lead wire. - Alternate switching of first and second semiconductor elements controls heat produced from first and second semiconductor elements because one of first and second semiconductor elements is turned on, while the other is turned off.
- When heavy electric current flows through first and second semiconductor elements, a large amount of heat produced from first and second semiconductor elements can be efficiently and fully discharged to the outside through radiating layer mounted between first and second power semiconductor elements without deterioration in electric characteristics of first and second semiconductor elements.
- Although first and second power semiconductor stacks are concurrently mounted on a single support plate, sufficient amount of heat can be released outside through first and second radiating layers mounted respectively between first and second semiconductor elements and between third and fourth semiconductor elements, thereby preventing degradation in electric property of first to fourth semiconductor elements. Also, first and second radiating layers serve to reduce each conductive path for electric current flowing through first and second power semiconductor stacks because first and second radiating layers are in direct contact to first and second semiconductor elements and to third and fourth semiconductor elements, preventing occurrence of noise and electric power loss resulted from elongated conductive path for electric current.
- Although heavy current runs through plural semiconductor elements in the semiconductor device according to the present invention, no local excessive heat can be generated, prohibiting deterioration in electric property of the device, extending service life of the device and improving reliability of the device.
- The above-mentioned and other objects and advantages of the present invention will be apparent from the following description in connection with preferred embodiments shown in the accompanying drawings wherein:
- Figure 1
- is a side elevation view of the semiconductor device according to the present invention before packaging by plastic encapsulation;
- Figure 2
- is a plan view showing the interior of the semiconductor device of the present invention sealed by a plastic encapsulant; and
- Figure 3
- is an electric circuit diagram of a prior art H-type bridge circuit.
- (1)... a first semiconductor element (a first transistor), (2)... a second semiconductor element (a second transistor), (3)... a third semiconductor element (a third transistor), (4)... a fourth semiconductor element (a fourth transistor), (5)... a support plate, (6)... a load, (7)... a first power semiconductor stack, (8)... a second power semiconductor stack, (10)... a H-type bridge circuit, (11, 12)... radiating layers, (13)... a control circuit, (14, 15, 16, 17, 18, 19)... brazing material (solder),
- Embodiments of the semiconductor device according to the present invention will be described hereinafter in connection with
Figures 1 and2 of the drawings. Same reference symbols as those shown inFigure 3 are applied to similar portions inFigures 1 and2 . - The semiconductor device comprises a
metallic support plate 5 formed of heat-radiative copper or aluminum; first and second power semiconductor stacks 7 and 8 separately mounted onsupport plate 5; and acontrol circuit 13 of a semiconductor integrated circuit mounted onsupport plate 5 between first and second semiconductor stacks 7 and 8. First semiconductor stack 7 comprises first and second transistors (first and second power semiconductor or switching elements) 1 and 2, and second semiconductor stack 8 comprises third and fourth transistors (third and fourth power semiconductor or switching elements) 3 and 4. First tofourth transistors 1 to 4 are insulated gate bipolar transistors (IGBT) for forming four power transistors in H-type bridge circuit 10 shown inFigure 3 . - Not shown, but each of first to
fourth transistors 1 to 4 comprises a semiconductor substrate; base and emitter electrodes electrically connected to electrodes on semiconductor substrate; and a collector electrode formed on and electrically connected to a bottom surface. Interlayer insulation films 9 formed between emitter and base electrodes electrically isolate emitter and base electrodes. A collector electrode offirst transistor 1 is secured onsupport plate 5 through a brazing material (solder) 14, and an emitter electrode offirst transistor 1 is secured to a bottom surface of a first radiatinglayer 11 through abrazing material 15. A collector electrode ofsecond transistor 2 is secured on first radiatinglayer 11 through abrazing material 16, and an emitter electrode ofsecond transistor 2 is positioned at the uppermost location of first semiconductor stack 7. Similarly, a collector electrode ofthird transistor 3 is secured onsupport plate 5 through a brazing material (solder) 17, and an emitter electrode ofthird transistor 3 is secured to a bottom surface of a second radiatinglayer 12 through a brazing material (solder) 18. A collector electrode offourth transistor 4 is secured on second radiatinglayer 12 through abrazing material 19, and an emitter electrode offourth transistor 4 is positioned at the uppermost location of second semiconductor stack 8. In the illustrated embodiment of the invention, each of first and secondradiating layers fourth transistors layers fourth transistors 1 to 4 shown inFigure 2 is connected in the circuit configuration shown inFigure 3 which comprises a plurality oflead terminals 20 connected to electrodes of first and second power semiconductor stacks 7 and 8 andcontrol circuit 13. The semiconductor device has aplastic encapsulant 21 for sealing the whole circuit assembly and each inner end oflead terminals 20 whose outer ends extend out ofplastic encapsulant 21. - In use, positive terminals of
lead terminals 20 electrically connected to supportplate 5 are in electric communication with a positive terminal of a DC power source not shown, and each emitter electrode of second andfourth transistors fourth transistors 1 to 4 are connected tocontrol circuit 13 formed of a semiconductor integrated circuit to receive control or drive signals fromcontrol circuit 13. When first andfourth transistors third transistors fourth transistors third transistors load 6 in the reverse direction from that of first electric current I1 to operateload 6 with AC power. - The semiconductor device according to the invention has the following features and advantages:
- 1. Second and
fourth transistors third transistors single support plate 5 withcontrol circuit 13 mounted onsupport plate 5 between first and second semiconductor stacks 7 and 8. - 2. First and second metallic radiating layers 11 and 12 are secured respectively between first and
second transistors fourth transistors - 3. First and
fourth transistors third transistors - 4. First and second metallic radiating layers 11 and 12 electrically connect respectively between first and
second transistors fourth transistors - The semiconductor device according to the present invention fulfils the following functions and presents the following effects:
- 1. Position of second or
fourth transistor third transistor support plate 5 and improve the integration degree. Also, alternate switching of first andsecond transistors fourth transistors fourth transistors 1 to 4 to the outside to prevent local heat concentration and thereby excessive elevation of temperature in first or second semiconductor stack 7 or 8. - 2.
Electric load 6 can be driven with AC power converted from DC power by H-type bridge circuit 10 by alternately switching two pairs of switching elements, namely, first andfourth transistors third transistors - 3. Although heat rises in first and
second transistors first radiating layer 11 firmly attached between first andsecond transistors - 4. Although first and second power semiconductor stacks 7 and 8 are mounted together on
single support plate 5, heat produced in said stacks 7 and 8 does not deteriorate the electrical properties of first tofourth transistors 1 to 4 since full amount of heat can be released to the outside through first and second radiating layers 11 and 12 respectively sandwiched between first andsecond transistors fourth transistors - 5. The semiconductor device does not need wire-bonding for electric connection between first and
second transistors fourth transistors second transistors first radiating layer 11 and of third andfourth transistors second radiating layer 12. In other words, the stacked structures can reduce each conductive path length for electric current flowing through first and second power semiconductor stacks 7 and 8, thereby preventing occurrence of noise and electric power loss due to a long conductive path. - The above-mentioned embodiment of the present invention can be further modified as long as the modifications are covered by the terms of the appended claims. For example, in place of IGBT, the device can involve MOS-FETs or other typical or familiar bipolar transistors. Also, first to
fourth semiconductor elements 1 to 4 may be compound elements including switching elements such as transistors and other semiconductor elements. - The present invention is applicable to a semiconductor device used in a driver for cold cathode fluorescent lighting discharge tubes.
Claims (9)
- A semiconductor device comprising a heat-radiative and metallic support plate (5) made of copper or aluminum, wherein said support plate comprises a pair of longitudinal side surfaces (5a, 5b) and a pair of lateral side surfaces (5c, 5d);
a plurality of lead terminals (20) having positive and negative terminals, said positive terminals being integrally formed with the support plate and said negative terminals being disposed around and at a certain distance from said support plate (5);
each positive terminal of said lead terminals being located at a longitudinal side surface of said support plate, at a position adjacent to a corner formed by the intersection of a longitudinal side surface and a lateral side surface of said support plate;
a first semiconductor stack (7) which has first and second semiconductor elements (1, 2), said first semiconductor element (1) having a bottom electrode electrically connected to said support plate through a brazing material (14), said first semiconductor element further having an upper electrode electrically connected to a lower electrode of said second semiconductor element (2) through a first electrically conductive and radiating layer (11); a second semiconductor stack (8) which has third and fourth semiconductor elements (3, 4), said third semiconductor element (3) having a bottom electrode electrically connected to said support plate through a brazing material (17), said third semiconductor element further having an upper electrode electrically connected to a lower electrode of said fourth semiconductor element (4) through a second electrically conductive and radiating layer (12); said first to fourth semiconductor elements contributing to form an H-type bridge circuit (10);
each of said first to fourth semiconductor elements being a switching element;
the semiconductor device further comprising a control circuit (13) for controlling the switching operation of said first to fourth semiconductor elements (1 to 4) so that said first and fourth semiconductor elements (1, 4) and said second and third semiconductor elements (2, 3) are alternately switched, and thereby when said first semiconductor element (1) and said fourth semiconductor element (4) are turned on together, said second semiconductor element (2) and said third semiconductor element (3) are turned off together, and thereby when said first semiconductor element (1) and said fourth semiconductor element (4) are turned off together, said second semiconductor element (2) and said third semiconductor element (3) are turned on together;
said control circuit (13) being mounted on said support plate (5) between said first and second semiconductor stacks (7, 8);
each of said first to fourth semiconductor elements (1, 2, 3, 4) having a control electrode electrically connected to a respective control electrode in said control circuit through a respective lead wire;
each of said second and fourth semiconductor elements (2, 4) having an upper electrode electrically connected to a negative terminal through a lead wire. - The semiconductor device of claim 1, wherein one of said first and second semiconductor elements (1, 2) in the first semiconductor stack (7) and one of third and fourth semiconductor elements (3, 4) in the second semiconductor stack (8) form a switch of high voltage side in the H-type bridge circuit (10); and
the other of said first and second semiconductor elements (1, 2) in the first semiconductor stack (7) and the other of third and fourth semiconductor elements (3, 4) in the second semiconductor stack (8) form another switch of low voltage side in the H-type bridge circuit (10) . - The semiconductor device of claim 1 or 2, wherein, in operation, a first electric current (I1) flows through said first and fourth semiconductor elements (1, 4) and said support plate (5) when said first and fourth semiconductor elements (1, 4) are turned on;
a second electric current (12) flows through said second and third semiconductor elements (2, 3) and said support plate (5) when said second and third semiconductor elements (2, 3) are turned on; and
said first and second electric currents (I1, 12) alternately flow through an electric load (6). - The semiconductor device of claim 1, wherein said first and third semiconductor elements (1, 3) are disposed away from each other a longer distance than a size of said first semiconductor element (1).
- The semiconductor device of claim 4, wherein
said first semiconductor stack (7) is mounted on said support plate (5) near one lateral side surface (5c) thereof; and
said second semiconductor stack (8) is mounted on said support plate (5) near the other lateral side surface (5d) thereof. - The semiconductor device of claim 5, wherein said negative terminals comprises a first negative terminal electrically connected to the upper electrode in said first semiconductor element (1) through a first lead wire,
a second negative terminal electrically connected to the upper electrode in said second semiconductor element (2) through a second lead wire,
a third negative terminal electrically connected to the upper electrode in said third semiconductor element (3) through a third lead wire, and
a fourth negative terminal electrically connected to the upper electrode in said fourth semiconductor element (4) through a fourth lead wires;
said first and third negative terminals are disposed around one longitudinal side surface (5b) of said support plate (5); and
said second and fourth negative terminals are disposed around the other longitudinal side surface (5a) of said support plate (5). - The semiconductor device of claim 1 further comprising a cold cathode fluorescent lighting discharge tube, wherein the upper electrode in said first semiconductor element (1) is electrically connected to the lower electrode in said second semiconductor element (2) at a first junction (A1);
the upper electrode in said third semiconductor element (3) is electrically connected to the lower electrode in said fourth semiconductor element (4) at a second junction (A2) ; wherein said cold cathode fluorescent lighting discharge tube (6) is provided between the first and second junctions (A1) and (A2) for operation of said discharge tube (6) by AC power; and wherein each of said first to fourth semiconductor elements (1 to 4) is a power semiconductor element through which, in operation, heavy electric current flows to operate said discharge tube (6). - The semiconductor device of claim 1, further comprising a plastic encapsulant (21) for sealing the whole semiconductor device with the exception of the outer ends of said lead terminals (20) which extend out of said plastic encapsulant (21).
- The semiconductor device of claim 1, wherein the upper electrode in said first semiconductor element (1) is secured to a bottom surface of said first radiating solder layer (11) through a first brazing material (15) ;
the lower electrode in said second semiconductor element (2) is secured on an upper surface of said first radiating solder layer (11) through a second brazing material (16) ;
the upper electrode in said third semiconductor element (3) is secured to a bottom surface of said second radiating solder layer (12) through a third brazing material (18); and
the lower electrode in said fourth semiconductor element (4) is secured on an upper surface of said second radiating layer (12) through a fourth brazing material (19).
Applications Claiming Priority (2)
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JP2003294208 | 2003-08-18 | ||
PCT/JP2004/007264 WO2005018001A1 (en) | 2003-08-18 | 2004-05-27 | Semiconductor device |
Publications (3)
Publication Number | Publication Date |
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EP1657750A1 EP1657750A1 (en) | 2006-05-17 |
EP1657750A4 EP1657750A4 (en) | 2009-09-02 |
EP1657750B1 true EP1657750B1 (en) | 2018-12-05 |
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EP04745370.9A Expired - Lifetime EP1657750B1 (en) | 2003-08-18 | 2004-05-27 | Semiconductor device |
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US (1) | US7608918B2 (en) |
EP (1) | EP1657750B1 (en) |
JP (3) | JPWO2005018001A1 (en) |
CN (1) | CN100546028C (en) |
WO (1) | WO2005018001A1 (en) |
Cited By (1)
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DE102017217593B4 (en) | 2016-10-06 | 2022-06-02 | Infineon Technologies Americas Corp. | Multi-phase power device, method of constructing a power electronic device package and such device |
Families Citing this family (8)
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JP2007019215A (en) * | 2005-07-07 | 2007-01-25 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
JP2007027432A (en) * | 2005-07-15 | 2007-02-01 | Sanken Electric Co Ltd | Semiconductor device |
JP5481104B2 (en) | 2009-06-11 | 2014-04-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
DE102013008193A1 (en) | 2013-05-14 | 2014-11-20 | Audi Ag | Device and electrical assembly for converting a DC voltage into an AC voltage |
CN103824832B (en) * | 2014-03-13 | 2016-08-24 | 杭州明果教育咨询有限公司 | A kind of integrated six brachium pontis package modules of many MOSFET |
WO2016094718A1 (en) * | 2014-12-10 | 2016-06-16 | Texas Instruments Incorporated | Power field-effect transistor (fet), pre-driver, controller, and sense resistor integration |
JP6770452B2 (en) * | 2017-01-27 | 2020-10-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP7564021B2 (en) * | 2021-03-08 | 2024-10-08 | 株式会社デンソー | A semiconductor module that incorporates semiconductor elements into a circuit board |
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JPH09213877A (en) | 1996-02-02 | 1997-08-15 | Toshiba Corp | Multi-chip module semiconductor device |
US6014413A (en) * | 1997-05-02 | 2000-01-11 | At&T Corp | Time-shifted weighting for signal processing |
KR100632137B1 (en) | 1997-07-19 | 2006-10-19 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Semiconductor device assemblies and circuits |
JP2000164800A (en) * | 1998-11-30 | 2000-06-16 | Mitsubishi Electric Corp | Semiconductor module |
US6259615B1 (en) * | 1999-07-22 | 2001-07-10 | O2 Micro International Limited | High-efficiency adaptive DC/AC converter |
JP2001043985A (en) | 1999-07-30 | 2001-02-16 | Denso Corp | Discharge lamp device |
JP2002026251A (en) * | 2000-07-11 | 2002-01-25 | Toshiba Corp | Semiconductor device |
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US6891739B2 (en) * | 2002-03-04 | 2005-05-10 | International Rectifier Corporation | H-bridge with power switches and control in a single package |
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EP1475836B1 (en) * | 2003-05-08 | 2006-05-03 | Infineon Technologies AG | Circuit module having interleaved groups of circuit chips |
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2004
- 2004-05-27 US US10/567,523 patent/US7608918B2/en not_active Expired - Fee Related
- 2004-05-27 JP JP2005513139A patent/JPWO2005018001A1/en active Pending
- 2004-05-27 EP EP04745370.9A patent/EP1657750B1/en not_active Expired - Lifetime
- 2004-05-27 CN CNB2004800143033A patent/CN100546028C/en not_active Expired - Lifetime
- 2004-05-27 WO PCT/JP2004/007264 patent/WO2005018001A1/en active Application Filing
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- 2008-05-19 JP JP2008131096A patent/JP4844591B2/en not_active Expired - Lifetime
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DE102017217593B4 (en) | 2016-10-06 | 2022-06-02 | Infineon Technologies Americas Corp. | Multi-phase power device, method of constructing a power electronic device package and such device |
Also Published As
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JPWO2005018001A1 (en) | 2007-10-04 |
JP2008199067A (en) | 2008-08-28 |
JP4853493B2 (en) | 2012-01-11 |
CN1795557A (en) | 2006-06-28 |
CN100546028C (en) | 2009-09-30 |
EP1657750A1 (en) | 2006-05-17 |
JP2008199066A (en) | 2008-08-28 |
US20060202228A1 (en) | 2006-09-14 |
JP4844591B2 (en) | 2011-12-28 |
US7608918B2 (en) | 2009-10-27 |
WO2005018001A1 (en) | 2005-02-24 |
EP1657750A4 (en) | 2009-09-02 |
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