JP2008244419A - High electron mobility transistor and method of forming same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high electron mobility transistor which can be formed more easily as compared to a conventional high electron mobility transistor, can control a threshold voltage at high accuracy, and has a normally-on characteristic being similar to a normally-off characteristic or the normally-off characteristic, and to provide a method of forming the same. <P>SOLUTION: The high electron mobility transistor has: a first layer made of a first compound semiconductor; a second layer made of a second compound semiconductor having a spontaneous polarization on the first layer; a third layer being between the second layers as seen from above and on the first layer, containing the second compound semiconductor as a constituent element, and having a lower crystallinity as compared to the second layer; a gate electrode disposed on the third layer; a drain electrode disposed on the second layer; and a source electrode disposed on the second layer so as to sandwich the gate electrode in conjunction with the drain electrode as seen from above. A two-dimensional carrier gas layer is generated adjacent to the interface of the first layer and the second layer. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a high electron mobility transistor and a manufacturing method thereof.

In a high electron mobility transistor (hereinafter referred to as HEMT), a two-dimensional carrier including a two-dimensional electron gas layer (2DEG layer) at the interface by bonding different kinds of semiconductor materials having different band gaps. The gas layer can be generated in an electron transit layer that is not doped with impurities. Thereby, since electrons move without colliding with impurities, the moving speed of electrons increases, and the switching speed and sensitivity can be improved. Note that the HEMT is also called a heterojunction field effect transistor (HFET) because of its structure.
Further, since nitride-based compound semiconductor materials such as GaN, InGaN, and AlInGaN have a larger band gap energy than GaAs-based materials, electronic devices using these materials are superior in pressure resistance, efficiency, and the like.

For example, by forming an AlGaN / GaN heterostructure, a two-dimensional electron gas layer is obtained in the same manner as in a GaAs-based device, and the electron mobility is very high. Due to the synergistic effect of piezo polarization and spontaneous polarization due to lattice distortion generated between AlGaN and GaN, an extremely high concentration of electron gas can be easily obtained. As a result, a low on-resistance that far exceeds the limit of silicon (Si) material is realized.
In the HEMT using GaN shown in FIG. 7A, for example, a buffer layer made of GaN, an electron transit layer 3 made of undoped GaN, and a thinner layer than the electron transit layer 3 are formed on an alumina single crystal substrate 1. It has a heterojunction multilayer structure in which the electron supply layer 4 made of undoped AlGaN is sequentially formed. A source electrode 7, a gate electrode 6 and a drain electrode 8 are formed on the electron supply layer 4.

In the HEMT shown in FIG. 7A, the band gap energy of the electron transit layer 3 made of undoped GaN is smaller than the band gap energy of the electron supply layer 4 made of undoped AlGaN.
On the other hand, undoped GaN is a binary crystal that generates spontaneous polarization and a piezoelectric effect, whereas undoped AlGaN is a ternary crystal that generates spontaneous polarization and a piezoelectric effect, and has a crystal lattice constant different from that of undoped GaN.
For this reason, at the heterojunction interface between the electron transit layer 3 and the electron supply layer 4, the piezoelectric electric field generated by the piezoelectric effect due to crystal distortion based on the difference in the crystal lattice constant, the electron transit layer 3, and the electron supply layer 4 are respectively configured. A synergistic effect of the electric field is generated due to spontaneous polarization of the crystal lattice, and the two-dimensional electron gas layer 200 is formed immediately below the junction interface between the two.

In this HEMT, the electron supply layer 4 functions as a layer for supplying electrons to the electron transit layer 3. Then, by applying a potential difference between the source electrode 7 and the drain electrode 8, electrons supplied to the electron transit layer 3 move at high speed in the two-dimensional electron gas layer 200.
At this time, a predetermined voltage (a voltage equal to or higher than the threshold voltage) is applied to the gate electrode 6, and a two-dimensional electron gas in the electron transit layer 3 is generated by a depletion layer having a desired spread (width) generated immediately below the gate electrode 6. The layer 200 is divided (blocked) to control the flow of electrons traveling between the source electrode 7 and the drain electrode 8.

That is, in a general HEMT, the two-dimensional electron gas layer 200 is always formed on the electron transit layer 3 side of the junction interface of the heterojunction structure of the electron transit layer 3 and the electron supply layer 4 by the action of an electric field due to piezoelectric polarization and spontaneous polarization. As a result, a general HEMT has a normally-on structure. That is, the high electron mobility transistor having the heterojunction structure is a so-called normally-on operation in which a current continues to flow between the source electrode 7 and the drain electrode 8 in a state where a voltage higher than the threshold voltage is not applied to the gate electrode 6. It is carried out.
Therefore, in order to turn off the HEMT, a voltage higher than the threshold voltage is applied to the gate electrode 6 to generate a depletion layer, and the current path of the two-dimensional electron gas layer 200 is blocked. In other words, a so-called normally-off operation in which no current flows between the source electrode 7 and the drain electrode 8 without applying a voltage to the gate electrode 6 cannot be realized.

However, a semiconductor element normally used in a semiconductor circuit or the like using a Si material is a normally-off device, and a HEMT that is normally on cannot be easily replaced with such a semiconductor circuit or the like.
Therefore, as a HEMT having a normally-off structure, the structure shown in FIG. 7B and the following is used (see, for example, Patent Document 1).
An electron supply layer 4 made of a GaN-based compound semiconductor and an electron transit layer 3 are formed on the substrate 1 by heterojunction, and the electron supply layer 4 is formed thinner than the electron transit layer 3. Here, a structure (recess gate structure) is adopted in which the electron supply layer 4 in the region immediately below the gate electrode 6 is formed thinner than the region of the other electron supply layer 4 except immediately below the gate electrode 6.

In the recessed gate structure, the thickness of the electron supply layer 4 immediately below the gate electrode 6 is made thinner than the region of the electron supply layer 4 except just below the gate electrode 6, thereby increasing the pinch-off voltage at that portion. Therefore, in a state where no voltage is applied to the gate electrode 6, the two-dimensional electron gas layer in that portion disappears and is depleted. This realizes a high electron mobility transistor that performs a so-called normally-off operation in which no current flows between the source electrode 7 and the drain electrode 8 when no voltage is applied to the gate electrode.
JP 2005-183733 A

However, in the method of manufacturing a HEMT having a recessed gate structure shown in Patent Document 1, it is necessary to process the electron supply layer immediately below the gate electrode by etching, so that the originally thin electron supply layer is etched to form the electron supply layer. There is a drawback in that the damage to the region directly below and around the gate electrode of the electron transit layer provided below is large, which affects the semiconductor device characteristics.
Further, in order to realize the normally-off operation by the manufacturing method shown in Patent Document 1, an etching technique for controlling the atomic level thickness of the electron supply layer directly under the gate electrode with very high accuracy is necessary and formed. As a result, the thickness of the electron supply layer directly under the gate electrode varies, the HEMT threshold voltage cannot be uniformly controlled, and a HEMT that deviates from the threshold voltage standard or a HEMT that does not operate normally off is created. There is a problem that decreases.

  The present invention has been made in view of such circumstances, and has a normally-on characteristic or a normally-off characteristic close to a normally-off operation that can be easily manufactured as compared to the conventional example and can control the threshold voltage with high accuracy. It is an object of the present invention to provide a high electron mobility transistor and a manufacturing method thereof.

  The high electron mobility transistor of the present invention includes a first layer made of a first compound semiconductor, a second layer made of a second compound semiconductor having spontaneous polarization on the first layer, The second compound semiconductor is included as a constituent element between the second layers and on the first layer as viewed from the second layer, and the crystallinity is lower than that of the second layer. 3, a gate electrode formed on the third layer, a drain electrode formed on the second layer, and the gate electrode sandwiched between the drain electrode when viewed from above And a source electrode formed on the second layer, and a two-dimensional carrier gas layer is formed in the vicinity of the interface between the first layer and the second layer.

  The high electron mobility transistor of the present invention is characterized in that the third layer has a relaxed crystallinity as compared with the second layer.

  The high electron mobility transistor of the present invention includes a first layer made of a first compound semiconductor, a second layer having a spontaneous polarization on the first layer and heterojunction with the first compound semiconductor. A second layer made of a compound semiconductor and a third layer between the second layer as viewed from above and having a relaxed crystallinity on the first layer as compared with the second layer A gate electrode formed on the third layer, a drain electrode formed on the second layer, and a second electrode so as to sandwich the gate electrode with the drain electrode when viewed from above. A two-dimensional carrier gas layer is formed in the vicinity of the interface between the first layer and the second layer.

  A high electron mobility transistor according to the present invention is any of the high electron mobility transistors described above, wherein an insulating film is sandwiched between the third layer and the gate electrode.

  A high electron mobility transistor according to the present invention is the high electron mobility transistor according to any one of the above, wherein a first portion of the second layer is formed between the third layer and the first layer. The first portion of the second layer is thinner than the second portion of the second layer formed so as to sandwich the third layer from the side.

The high electron mobility transistor of the present invention is any one of the high electron mobility transistors described above, wherein the first and second compound semiconductors are nitride-based compound semiconductors, and the third layer is a few. It is characterized by having a thickness of atoms or more.
The high electron mobility transistor of the present invention is the high electron mobility transistor according to any one of the above, wherein the third layer is a crystal having more defects than a polycrystalline layer, an amorphous crystal layer, or a second layer. It is a layer.

  The method for manufacturing a high electron mobility transistor according to the present invention includes a second compound semiconductor that has a spontaneous polarization on a first layer made of a first compound semiconductor and has a heterojunction with the first compound semiconductor. Forming a second layer to be formed, generating a two-dimensional carrier gas layer in the vicinity of the interface between the first layer and the second layer, and reducing the crystallinity of the second layer The third layer is formed so as to be between the second layers when viewed from above, and a two-dimensional carrier gas layer generated on the upper surface side of the first layer immediately below the third layer is formed on the second layer. And a step of reducing the two-dimensional carrier gas layer generated near the interface between the first layer and the first layer, and forming a gate electrode on the third layer and sandwiching the gate electrode between the drain electrode and the source electrode Forming the step.

  The method for manufacturing a high electron mobility transistor according to the present invention includes a second compound semiconductor that has a spontaneous polarization on a first layer made of a first compound semiconductor and has a heterojunction with the first compound semiconductor. Forming a second layer to be formed, generating a two-dimensional carrier gas layer in the vicinity of the interface between the first layer and the second layer, and reducing the crystallinity of the second layer The third layer is formed so as to be between the second layers when viewed from above, and a two-dimensional carrier gas layer generated on the upper surface side of the first layer immediately below the third layer is formed on the second layer. And a step of reducing the two-dimensional carrier gas layer generated near the interface between the first layer and the first layer, and forming a gate electrode on the third layer and sandwiching the gate electrode between the drain electrode and the source electrode Forming the step.

  In the method of manufacturing a high electron mobility transistor according to the present invention, the step of forming the third layer includes providing a thickness control film for controlling the thickness of the third layer on the second layer, The third layer is formed by reducing the crystallinity of the second layer by ion implantation or plasma irradiation so as to penetrate from above the thickness control film.

  The method of manufacturing a high electron mobility transistor according to the present invention includes a step of forming a second layer made of a second compound semiconductor on a first layer made of the first compound semiconductor, Forming a third layer formed so as to decrease the crystallinity of the second layer from above the layer so as to be sandwiched between the second layers, and forming a control electrode on the third layer And a process.

  The method of manufacturing a high electron mobility transistor according to the present invention includes a second compound semiconductor having a spontaneous polarization property, heterojunctioned with the first compound semiconductor on the first layer made of the first compound semiconductor. Forming the second layer at a temperature at which the crystallinity is lowered or relaxed, and the second layer so as to face both sides of the second layer when viewed from above. Annealing the layer to form a two-dimensional carrier gas layer in the vicinity of the interface on the upper surface side of the first layer immediately below the third layer; forming a gate electrode on the third layer; And forming each of the source electrodes on each of the second layers facing each other with the third layer interposed therebetween.

  In the method for manufacturing a high electron mobility transistor of the present invention, the first layer and the second layer are lattice-matched with the first layer and at a temperature higher than that of the second layer. The method further includes the step of forming a fourth layer of the second compound semiconductor.

  According to the present invention, a two-dimensional carrier gas layer is generated in the vicinity of the interface between the first layer and the second layer. Further, the third layer formed on the first layer and between the second layers as viewed from above has lower crystallinity than the second layer. As a result, both the spontaneous polarization of crystals formed in the third layer and the piezo polarization generated between the third layer and the first layer are low. Therefore, the electric field strength based on one or both of piezo polarization and spontaneous polarization is reduced between the third layer and the first layer, and the two-dimensional carrier gas layer generated there is the first layer and the second layer. This is less than the two-dimensional carrier gas layer generated in the vicinity of the interface with the other layer. As a result, by providing the gate electrode on the third layer, it is possible to provide a high electron mobility transistor having a normally-on characteristic or a normally-off characteristic close to a normally-off operation.

  The present invention relates to a high electron mobility transistor including a first and second layers having a heterojunction using a compound semiconductor, and a crystal immediately below the gate electrode in the second layer having spontaneous polarization by ion implantation or plasma irradiation. The third layer is formed by reducing the property of the second layer around the gate electrode, and the spontaneous polarization of the third layer is made less crystalline than the second layer. As a result, the spontaneous polarization and piezoelectric polarization of the third layer are lower than those of the second layer, and the concentration (or width) of the two-dimensional electron gas layer generated near the interface between the third layer and the first layer is reduced. Compared to the vicinity of the interface between the second layer and the first layer, it decreases or disappears.

In addition, the crystallinity of the third layer and the first layer is relaxed more than the crystallinity of the second layer and the first layer by ion implantation or plasma irradiation, and the crystal constituting the third layer is changed. By returning to the original lattice spacing, the third layer is prevented from being distorted. As a result, the piezoelectric polarization of the third layer is lower than that of the second layer, and the concentration (or width) of the two-dimensional electron gas layer generated in the vicinity of the interface between the third layer and the first layer is the second level. Compared to the vicinity of the interface between the layer and the first layer, it decreases or disappears.
In view of the above, a high electron mobility transistor having normally-on characteristics or normally-off characteristics close to normally-off operation is provided by reducing or eliminating the concentration (or width) of the two-dimensional electron gas layer at the interface directly below the gate electrode.

Hereinafter, a high electron mobility transistor according to an embodiment of the present invention will be described with reference to the drawings.
In the following description of the drawings, the same portions are denoted by the same reference numerals. However, the drawings are schematically shown, and the embodiments of the present invention shown below are for embodying the technical idea of the present invention, and various modifications may be made within the scope of the claims. it can.
FIG. 1 is a conceptual diagram showing a cross-sectional structure of a high electron mobility transistor in an embodiment of the present invention.
The substrate 1 is formed of an insulating material such as a silicon-based or compound-based semiconductor such as Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), GaN (gallium nitride), or ceramic such as alumina. ing.
Here, for example, in the embodiment of the present invention, the substrate 1 has a thickness of about 350 μm to 1000 μm, has a small linear expansion coefficient with respect to the buffer layer 2, the electron transit layer 3, and the electron supply layer 4, and has a lattice constant. Are made of single crystal silicon different from the above layers.

The buffer layer (buffer layer) 2 is formed of the substrate 1 and the first semiconductor in order to reduce lattice distortion caused by lattice mismatch between the single crystal silicon substrate 1 and the first semiconductor layer 3 formed of, for example, GaN. It is inserted between the layers 3. Here, the buffer layer 2 has a known low-temperature buffer structure or a multilayer buffer structure in which AlN (aluminum nitride) layers and GaN layers are alternately stacked.
The first semiconductor layer 3 corresponds to the electron transit layer, is formed on the buffer layer 2, and is a layer in which a two-dimensional electron gas layer 200 in which electrons move is generated. The first semiconductor layer 3 is made of, for example, intrinsic GaN to which no impurity is added, and has a thickness of 1 μm to 3 μm.
The first semiconductor layer 3 may be a compound semiconductor other than GaN. The first semiconductor layer 3 may be a compound semiconductor that does not have spontaneous polarization.

The second semiconductor layer 4 corresponds to the electron supply layer and is formed to be a heterojunction with the first semiconductor layer 3. The second semiconductor layer 4 is made of a compound semiconductor having a wider band gap than the first semiconductor layer 3 and having spontaneous polarization. The second semiconductor layer 4 is, for example, a nitride compound semiconductor having a composition satisfying Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). More preferably, AlxGa _1-x N (0.2 ≦ x ≦ 0.4), and further preferably Al _0.3 Ga _0.7 N.
The second semiconductor layer 4 is formed to a thickness of 5 nm to 50 nm, and in the present embodiment, it is formed to a thickness of about 20 nm.

As shown in FIG. 2, the electric field due to piezoelectric polarization due to lattice mismatch between the first semiconductor layer 3 and the second semiconductor layer 4 and / or spontaneous polarization due to the crystallinity of the second semiconductor layer 4 is high electrons. The two-dimensional electron gas layer is generated in the vertical direction of the mobility transistor (element), that is, in the direction from the first semiconductor layer 3 to the second semiconductor layer 4 and in the vicinity of the interface of the first semiconductor layer 3 by this electric field. 200 has occurred.
The second semiconductor layer 4 may further contain an N-type impurity. The second semiconductor layer 4 may be formed of a compound semiconductor having a lattice constant different from that of the compound semiconductor constituting the first semiconductor layer 3, but the same lattice as the compound semiconductor constituting the first semiconductor layer 3. A nitride compound semiconductor having a constant may be used. For example, since the spontaneous polarization is larger than the piezoelectric polarization in the AlInN compound semiconductor, the third semiconductor layer 5 described later can be formed by breaking the crystallinity of the AlInN compound semiconductor and weakening the spontaneous polarization. Even when the second semiconductor layer 4 is formed of an AlInN-based compound semiconductor, two-dimensional electrons are formed in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4 due to spontaneous polarization of the second semiconductor layer 4. A gas layer 200 can be created.

  A third semiconductor layer 5 corresponding to the third layer in the claims is formed on the first semiconductor layer 3 so as to be sandwiched by the second semiconductor layer 4 from the side when viewed from above. The third semiconductor layer 5 has a thickness of several atomic layers or more, for example, a thickness of 10 nm to 50 nm. Note that the third semiconductor layer 5 may have a thickness substantially equal to that of the second semiconductor layer 4. The third semiconductor layer 5 contains an element constituting a compound semiconductor constituting the second semiconductor layer 4, and has lower crystallinity than the second semiconductor layer 4. As a result, the spontaneous polarization and piezoelectric polarization of the third semiconductor layer 5 are lower than those of the second semiconductor layer 4, and a two-dimensional electron gas generated in the vicinity of the interface between the third semiconductor layer 5 and the first semiconductor layer 3. The layer concentration (or width) is lower or disappears than the two-dimensional electron gas layer 200 generated near the interface between the first semiconductor layer 3 and the second semiconductor layer 4.

As will be described later, since the third semiconductor layer 5 is formed by performing ion implantation or plasma irradiation on the second semiconductor layer 4, the ion species (ion source) does not volatilize, and the third semiconductor layer 5. May be a semiconductor layer containing an ion species (ion source) in the second semiconductor layer 4.
Further, the continuous coherent crystal state from the first semiconductor layer 3 to the second semiconductor layer 4 is broken, and the crystals constituting the third semiconductor layer 5 are returned to the original lattice spacing. That is, the lattice distortion with the crystal constituting the first semiconductor layer 3 is relaxed, and the third semiconductor layer 5 is not distorted or is less distorted than the second semiconductor layer 4. As a result, the piezoelectric polarization of the third semiconductor layer 5 is lower than that of the second semiconductor layer 4, and the two-dimensional electron gas layer 200 generated near the interface between the third semiconductor layer 5 and the first semiconductor layer 3. The concentration (or width) is lower or disappears than the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4.

A gate electrode (control electrode) 6 formed of a conductive film such as Al (aluminum) or polysilicon is provided on the third semiconductor layer 5. As shown in FIG. 6, the insulating film 12 may be sandwiched between the third semiconductor layer 5 so that the gate electrode 6 has a MIS structure with the third semiconductor layer 5.
Further, as viewed from above, the source electrode 7 and the drain electrode 8 formed on the second semiconductor layer 4 with the gate electrode 6 interposed therebetween are formed by depositing Al (aluminum) on Ti (titanium), etc. The semiconductor layer 4 is formed in low resistance (ohmic) contact.
Therefore, according to the high electron mobility transistor according to the embodiment of the present invention, the two-dimensional electron gas layer 200 directly under the gate electrode 6 is reduced or eliminated, and the normally-on characteristic structure or the normally-off characteristic is close to the normally-off operation. A high electron mobility transistor having a structure can be provided.

  Note that the high electron mobility transistor of the present embodiment applies the negative voltage larger than the threshold voltage to the gate electrode 6 in a state where a potential difference is applied to the source electrode 7 and the drain electrode 8. Electrons are generated in the vicinity of the interface between the semiconductor layer 3 and the third semiconductor layer 5, so that the high electron mobility transistor can be turned on.

  In addition, since the third semiconductor layer 5 deteriorates the crystallinity, the third semiconductor layer 5 may be polycrystalline, amorphous, or a crystal having more defects than the second semiconductor layer 4 as a result. Good.

  Further, as in the structure of another embodiment of the present invention shown in FIG. 3, the third semiconductor layer 5 and the first semiconductor layer 3 are not in contact with each other, and the second semiconductor layer 4 is sandwiched therebetween. May be. This is because, in the manufacturing method of the present embodiment, which will be described later, the third semiconductor layer 5 has a third depth up to a predetermined depth less than the thickness of the second semiconductor layer 4 so that the lower surface of the third semiconductor layer 5 does not reach the first semiconductor layer 3. The effect of the present invention can also be obtained by leaving part of the second semiconductor layer 4 as the semiconductor layer 5. Furthermore, the damage generated in the first semiconductor layer 3 when the third semiconductor layer 5 is formed is reduced, the crystallinity immediately below and in the vicinity of the third semiconductor layer 5 is secured, and a relatively high electron mobility is obtained. It is possible to provide a high electron mobility transistor having high resistance, that is, a high electron mobility transistor in which an increase in on-resistance is suppressed.

Furthermore, in the structure of another embodiment of the present invention shown in FIG. 3, the pinch-off voltage can be controlled by controlling the thickness of the third semiconductor layer 5 as in the case of the recessed gate structure. Here, the first portion of the second semiconductor layer 4 immediately below the third semiconductor layer 5 is thinner than the second portion of the second semiconductor layer 4 where the third semiconductor layer 5 is not provided immediately below. Is formed.
In addition, when the second semiconductor layer 4 and the third semiconductor layer 5 are formed of the same compound semiconductor layer, a lot of crystallinity is lowered above the vicinity of the interface with the first semiconductor layer 3. Or it is the structure which is either or both of relaxation.

Further, by sandwiching a thin insulating film such as AlN (aluminum nitride) between the first semiconductor layer 3 and the second semiconductor layer 4, the two-dimensional electron gas layer 200 moves to the second semiconductor layer 4 side. The diffusion of the alloy can be suppressed to suppress the diffusion of the alloy, and the mobility of the high electron mobility transistor can be improved.
Further, a compound semiconductor layer 11 made of, for example, GaN to which N-type impurities are added is provided between at least one of the second semiconductor layer 4 and the source electrode 7 and between at least one of the second semiconductor layer 4 and the drain electrode 8. Contact characteristics between the semiconductor layer 4 and the source electrode 7 and between the second semiconductor layer 4 and the drain electrode 8 may be improved.

Next, the manufacturing method of the high electron mobility transistor in the embodiment of the present invention will be described with reference to FIG. FIG. 4 is a conceptual diagram showing a cross-sectional structure for each manufacturing process of the high electron mobility transistor in the embodiment of the present invention.
After the well-known buffer layer 2 is formed on the main surface 1a of the substrate 1, the first semiconductor layer 3 and the second semiconductor layer 4 are sequentially heteroepitaxially grown on the buffer layer 2 (FIG. 4A). .
A conductive material to be the source electrode 7 and the drain electrode 8 is formed on the second semiconductor layer 4 by a sputtering method or a vacuum evaporation method, and after forming a resist pattern by photolithography, sputtering or vacuum evaporation is performed using the resist pattern as a mask. Thus, the source electrode 7 and the drain electrode 8 are formed, and the resist pattern is removed (FIG. 4B).

Next, a resist is applied to the entire surface, separated from the region where the source electrode 7 and the drain electrode 8 are formed by photolithography, and sandwiched between the source electrode 7 and the drain electrode 8 as viewed from above, and the gate electrode 6 A resist pattern 100 is formed so that a portion of the second semiconductor layer 4 to be formed, that is, a portion to be the third semiconductor layer 5 is exposed (FIG. 4C).
Then, with the resist pattern 100 as a mask, an inert gas such as Ar (argon), Ne (neon), Xe (xenon), or an ion species made of a material that insulates the second semiconductor layer 4 is used as the second species. Then, ion implantation or plasma irradiation is performed from the upper surface side of the semiconductor layer 4 to form the third semiconductor layer 5 (FIG. 4D).

  Note that the thickness of the third semiconductor layer 5 cannot be satisfactorily controlled because the defect is deeply penetrated by dry etching, but in the case of ion implantation or plasma irradiation, the crystal in the depth direction can be controlled by controlling the implantation depth. The state of sex can be controlled well. In particular, it is preferable to use an ion implantation method with good controllability, because the thickness (implantation depth) of the third semiconductor layer 5 can be adjusted favorably by controlling the charge to be implanted and the acceleration voltage. In addition, conditions such as acceleration voltage and ion species in ion implantation and bias voltage and ion species in plasma irradiation may be changed according to the thickness and material type of the second and third semiconductor layers 4 and 5. Good. For example, as shown in FIG. 3, a predetermined thickness less than the thickness of the second semiconductor layer 4 from the upper surface of the second semiconductor layer 4 is set so that the lower surface of the third semiconductor layer 5 does not reach the first semiconductor layer 3. The third semiconductor layer 5 may be formed up to a depth of 3 mm, and a part of the second semiconductor layer 4 may be left between the third semiconductor layer 5 and the first semiconductor layer 3.

Next, the resist pattern is removed, a new resist is applied, and a resist pattern for forming the gate electrode 6 by lift-off by photolithography, that is, a resist pattern exposing the upper surface of the third semiconductor layer 5 is formed. . Note that the resist pattern used when forming the third semiconductor layer 5 may be used as it is.
Then, a conductive material to be the gate electrode 6 is formed on the upper surface of the third semiconductor layer 5 by sputtering or the like, and the gate electrode 6 is formed on the third semiconductor layer 5 by lift-off (FIG. 4E). )).

In order to maintain the state in which the crystallinity of the third semiconductor layer 5 is locally lowered or relaxed, the second semiconductor layer 4 except for the third semiconductor layer 5 is locally subjected to heat treatment by laser annealing. Do. Note that the region of the third semiconductor layer 5 may be annealed as long as the crystallinity of the third semiconductor layer 5 can be maintained. For example, only the surface region of the third semiconductor layer 5 may be annealed in a state where the crystallinity of the third semiconductor layer 5 is relaxed.
According to the present invention, since the third semiconductor layer 5 has a thickness of several atoms or more, the first semiconductor layer 1 can be prevented from being damaged, and the threshold voltage can be controlled with high accuracy. , Improve yield and improve productivity.

Further, when the third semiconductor layer 5 is formed, the second semiconductor layer 4 is thin, and ions may reach the first semiconductor layer 3 even with the lowest energy for ion implantation. Therefore, the process from the formation of the source electrode 7 and the drain electrode 8 in FIG. 4B to the formation of the third semiconductor layer 5 in FIG. 4D may be as follows. First, a thickness control film 9 made of an oxide film or the like is formed on the exposed upper surface by sputtering (FIG. 5A).
Then, a resist is applied to almost the entire upper surface of the thickness control film 9, and a resist pattern 100 is formed by photolithography so that the thickness control film 9 on the region where the third semiconductor layer 5 is formed is exposed ( FIG. 5B).

  Next, with the resist pattern 100 as a mask, an inert gas such as Ar (argon), Ne (neon), Xe (xenon), or an ion species made of a material that insulates the third semiconductor layer 5 is formed. Ion implantation or plasma irradiation is performed from the upper surface side of the control film 9, and the region of the second semiconductor layer 4 immediately below the thickness control film 9 becomes the third semiconductor layer 5 (FIG. 5C). Next, the gate electrode 6 is formed as in the case of FIG. That is, the resist pattern 100 is removed, a new resist is applied, and a resist pattern for forming the gate electrode 6 by lift-off is formed by photolithography. Then, a conductive film to be a gate electrode is formed on the entire surface by sputtering, and the resist pattern is removed to form the gate electrode 6 on the region of the thickness control film 9 on the third semiconductor layer 5 (FIG. 5 (d)).

  According to this manufacturing method, by providing the thickness control film 9 on the second semiconductor layer 4 and controlling the thickness of the thickness control film 9, the third semiconductor layer 5 having a preset thickness can be easily formed. Can be formed. Furthermore, it is possible to suppress or suppress damage to the crystal on the upper surface side of the first semiconductor layer immediately below and in the vicinity of the third semiconductor layer 5.

Further, as shown in FIG. 6, a MIS gate structure having an insulating film 12 between the third semiconductor layer 5 and the gate electrode 6 may be used. Here, the manufacturing method of the high electron mobility transistor shown in FIG. 6 is the same as the process up to FIG. 4D. After the third semiconductor layer 5 is formed, the oxide film 10 is formed by sputtering. The semiconductor layer 4 and the third semiconductor layer 5 are formed on almost the entire upper surface.
Then, a resist is applied, and a resist pattern for forming the gate electrode 6 by lift-off, that is, a resist pattern for exposing the oxide film 10 formed on the third semiconductor layer 5 is formed by photolithography.

Then, a conductive film is formed on the entire upper surface by sputtering or the like, and the resist pattern is removed, whereby the insulating film 12 is formed on the third semiconductor layer 5 and the gate electrode 6 is formed on the insulating film 12. . By forming the insulating film 12 between the gate electrode 6 and the third semiconductor layer 5 in this way, a leakage current is generated between the gate electrode 6 and the electron transit layer 3 via the third semiconductor layer 5. Flow can be suppressed.
In the cross-sectional structure of the high electron mobility transistor in the embodiment of the present invention shown in FIGS. 1, 3, and 6, the third semiconductor layer 5 is illustrated so as to be formed over almost the entire region immediately below the gate electrode 6. However, as viewed from above, the third semiconductor layer 5 does not have to be formed over the entire region directly under the gate electrode 6, and may be formed only in a part including directly under the gate electrode 6.

Further, the third semiconductor layer 5 may be the same semiconductor material as that forming the second semiconductor layer 4.
In addition, an example in which the two-dimensional electron gas layer 200 is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4 is shown, but the first semiconductor layer 3 and the second semiconductor layer 4 The effect of the present invention can be obtained even when applied to a high electron mobility transistor in which a two-dimensional hole gas layer is formed in the vicinity of the interface. Therefore, it is suitable for the case where one of the two-dimensional electron gas layer 200 and the two-dimensional hole gas layer, that is, the two-dimensional carrier gas layer, is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4. However, the effect of the present invention can be obtained.

Next, another manufacturing method of the high electron mobility transistor (FIG. 1) in the embodiment of the present invention will be described with reference to FIG. FIG. 8 is a conceptual diagram showing a cross-sectional structure for each manufacturing process of the high electron mobility transistor in the embodiment of the present invention.
After the well-known buffer layer 2 is formed on the main surface 1 a of the substrate 1, the first semiconductor layer 3 is sequentially heteroepitaxially grown on the buffer layer 2. The semiconductor layer 40 is grown.
Here, the first semiconductor layer 3 is, for example, GaN, and is formed at a GaN formation temperature (900 ° C. to 1200 ° C.).

Then, on the first semiconductor layer 3, the semiconductor layer is formed in a structure in which the crystallinity of the amorphous or microcrystalline structure is lowered or relaxed without being crystallized, lower than the GaN formation temperature. The fourth semiconductor layer 40 made of Al _X In _Y Ga _1- XYN is formed at a temperature of, for example, 500 ° C. (FIG. 8A).
In the structure in which the crystallinity of the fourth semiconductor layer 40 is lowered or relaxed, spontaneous polarization due to the crystallinity of the fourth semiconductor layer 40 and / or the first semiconductor layer 3 and the fourth semiconductor layer 40 Since the electric field due to the piezoelectric polarization is low, a two-dimensional electron gas layer is not generated near the interface between the first semiconductor layer 3 and the fourth semiconductor layer 40 or is reduced as compared with the prior art.

  Then, the portion of the region 40A is shielded by the mask 100 so that the region (region 40A) where the gate electrode is formed is not irradiated with light. Then, in a state where the region 40A for forming the gate electrode is protected, the surface of the region 40B of the fourth semiconductor layer 40 is annealed by irradiating a laser beam having a predetermined energy, and the light is irradiated. The region 40B is single-crystallized to form the second semiconductor layer 4.

  Here, in the single crystallization process by annealing in the present embodiment, electron beam irradiation or the like can be used without being limited to laser annealing, as long as it is a means capable of performing annealing for local single crystallization described later. As a result, the region 40A is sandwiched between the regions 40B in a plan view as viewed from the direction perpendicular to the surface of the fourth semiconductor layer 40.

  At this time, in the fourth semiconductor layer 40, since it is crystallized, spontaneous polarization due to the crystallinity of the second semiconductor layer 4 and / or piezoelectric polarization between the first semiconductor layer 3 and the second semiconductor layer 4. The electric field due to is increased compared to before the annealing, and a good two-dimensional electron gas layer 200 is formed in the vicinity of the interface between the second semiconductor layer 4 and the first semiconductor layer 3. The region 40A in which the crystallinity is relaxed or lowered corresponds to the third semiconductor layer 5, and the two-dimensional electron gas layer 200 is formed in the vicinity of the interface between the third semiconductor layer 5 and the first semiconductor layer 3. Not. Alternatively, the concentration or width of the two-dimensional electron gas layer 200 is sufficiently smaller than the vicinity of the interface between the region 40B and the first semiconductor layer 3.

  Next, a conductive material to be the source electrode 7 and the drain electrode 8 is formed on the third semiconductor layer 5 on the third semiconductor layer 5 and the source electrode 7 and the drain electrode 8 on the second semiconductor layer 4, and is formed by photolithography. After forming the resist pattern, the gate electrode 6, the source electrode 7 and the drain electrode 8 are formed by sputtering or vacuum evaporation using the resist pattern as a mask, and the resist pattern is removed (FIG. 8C).

  Here, the light irradiated for the annealing of the single crystallization will be described. Examples of the light source for irradiation include a low-pressure mercury lamp, a high-pressure mercury lamp, an ultrahigh-pressure mercury lamp, a zinc lamp, a halogen lamp, an excimer lamp, and a xenon lamp. In addition, fundamental waves of excimer lasers, argon ion lasers, krypton ion lasers, Nd: YVO4 lasers, Nd: YAG lasers, Nd: YLF lasers, Ti: sapphire lasers, semiconductor lasers, dye lasers, and the fundamentals of the above lasers Light obtained by the nonlinear optical effect of waves can also be used.

Further, it is preferable that the irradiation light is strongly absorbed in the fourth semiconductor layer 40 and converted into thermal energy. For this reason, it is particularly preferable to use light such as an excimer laser, an argon ion laser, or a harmonic of an Nd: YAG laser having a wavelength in the ultraviolet region or the vicinity thereof as the irradiation light.
Here, when the thickness of the fourth semiconductor layer 40 is thin, an excimer laser with a short wavelength is suitable as the light source. Conversely, when the film thickness is large, the second harmonic of the Nd: YAG laser with a long wavelength is used as the light source. In general, a laser beam having a wavelength of 600 nm or less satisfies the above conditions.

The laser beam irradiation is performed, for example, in a nitrogen atmosphere with the temperature of the fourth semiconductor layer 40 being, for example, between about room temperature (25 ° C.) and about 400 ° C.
When the fourth semiconductor layer 40 is irradiated with laser light using a pulse laser, heat is generated by the light energy absorbed in the irradiated region of the fourth semiconductor layer 40, and the temperature is reached in a very short time. A rise occurs.
The pulse width of the irradiated laser is preferably 500 ns or less. Since the heat generated at this time is diffused, the fourth semiconductor layer 40 (region 40B) irradiated with the laser light is cooled in a short time. When the irradiation energy of the laser beam is sufficient to melt the fourth semiconductor layer 40, the region 40B in the fourth semiconductor layer 40 is melted and single-crystallized in the cooling process. Further, when the irradiation energy is increased, it is melted to a deep portion of the region 40B and completely melts at a certain energy or higher.

According to this embodiment, compared with the manufacturing method shown in FIG. 4, the laser annealing process in FIG. 4E can be omitted, and the gate electrode, the source electrode, and the drain electrode can be formed in the same process. Therefore, the number of steps can be reduced to reduce the manufacturing cost, and the HEMT structure of FIG. 3 similar to the manufacturing method of FIG. 4 can be formed.
In addition, an example in which the two-dimensional electron gas layer 200 is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4 is shown, but the first semiconductor layer 3 and the second semiconductor layer 4 The effect of the present invention can be obtained even when applied to a high electron mobility transistor in which a two-dimensional hole gas layer is formed in the vicinity of the interface. Therefore, it is suitable for the case where one of the two-dimensional electron gas layer 200 and the two-dimensional hole gas layer, that is, the two-dimensional carrier gas layer, is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4. However, the effect of the present invention can be obtained.

Next, another manufacturing method of the high electron mobility transistor (FIG. 3) according to another embodiment of the present invention will be described with reference to FIG. FIG. 9 is a conceptual diagram showing a cross-sectional structure for each process of another manufacturing method of the high electron mobility transistor (FIG. 3) according to another embodiment of the present invention.
After the well-known buffer layer 2 is formed on the main surface 1 a of the substrate 1, the first semiconductor layer 3 is grown on the buffer layer 2 in order.
Here, the first semiconductor layer 3 is, for example, GaN, and is formed at a GaN formation temperature (900 ° C. to 1200 ° C.). Subsequently, a fifth semiconductor layer 60 made of Al _X In _Y Ga _1- XYN is heteroepitaxially grown on the first semiconductor layer 3 at a thickness of about 5 to 10 nm at the GaN formation temperature. .
At this time, since the fifth semiconductor layer 60 in contact with the first semiconductor layer 3 has a single crystal structure lattice-matched to the first semiconductor layer 3, the first semiconductor layer 3 and the first semiconductor layer 3 The two-dimensional electron gas layer 200 is generated in the vicinity of the interface with the five semiconductor layers 60.
Here, by controlling the thickness of the fifth semiconductor layer 60, the spontaneous polarization of the fifth semiconductor layer 60 and the intensity of piezo-polarization between the fifth semiconductor layer 60 and the first semiconductor layer 3 are controlled. The concentration of the two-dimensional electron gas layer 200 formed in the vicinity of the interface between the fifth semiconductor layer 60 and the first semiconductor layer 3 can be adjusted.

Next, on the fifth semiconductor layer 60, the temperature is lower than the formation temperature of the fifth semiconductor layer 60 and the first semiconductor layer 3, and the crystallinity is lowered or relaxed without being crystallized. The sixth semiconductor layer 70 made of Al _X In _Y Ga _1- XYN is formed to a thickness of, for example, about 10 to 20 nm at a temperature formed by the structure, for example, a temperature of 500 ° C.

Then, laser light having a predetermined irradiation energy is applied to the sixth semiconductor layer 70 so that the region (region 70A) where the gate electrode is formed is not irradiated (in a state where the region 70A is shielded by the mask 100). Irradiation is performed on the surface, annealing is performed with the energy of the irradiated laser beam, and a single crystallization process is performed on the region 70B irradiated with the laser beam (FIG. 9B).
Here, in the present embodiment, the region 70 </ b> B of the sixth semiconductor layer 70 becomes the second semiconductor layer 4 in the single crystallization process of the sixth semiconductor layer 70 by laser annealing. Further, as shown in FIGS. 9C and 9C, the sixth semiconductor layer 70 and the fifth semiconductor layer 60 may be made of the same semiconductor material, and may be the semiconductor layer 80 having the same single crystal structure.

Further, in the single crystallization process by annealing light irradiation energy in the present embodiment, any means capable of locally annealing for single crystallization described later can be used without being limited to laser annealing. In a plan view viewed from the direction perpendicular to the surface of the sixth semiconductor layer 70 (semiconductor layer 80 and region 70A), the region 70A is narrowed in the region 70B and formed in a stripe shape in the semiconductor region 80.
Therefore, only the portion of the region 70A not irradiated with the laser light remains in a structure in which the crystallinity is lowered or relaxed, and the fifth semiconductor layer 60 (or the second semiconductor layer 4) is directly below the region 70A. Is present.

  For this reason, the thickness of the two-dimensional electron gas layer 200 in the vicinity of the interface in the region of the first semiconductor layer 3 where the region 70 </ b> A is not formed thereon is the same as that of the first semiconductor layer 3 immediately below the third semiconductor layer 5. It is generated higher or thicker than the concentration or width of the two-dimensional electron gas layer 200 in the vicinity of the interface in the region.

  Next, a conductive material to be the source electrode 7 and the drain electrode 8 is formed on the third semiconductor layer 5 on the third semiconductor layer 5 and the source electrode 7 and the drain electrode 8 on the second semiconductor layer 4, and is formed by photolithography. After forming the resist pattern, the gate electrode 6, the source electrode 7 and the drain electrode 8 are formed by sputtering or vacuum evaporation using the resist pattern as a mask, and the resist pattern is removed (FIG. 9C). Here, the gate electrode 6 is sandwiched between the source electrode 7 and the source electrode 8.

  Also in this embodiment, since the piezoelectric polarization of the third semiconductor layer 5 is weaker than that of the second semiconductor layer 4, the second semiconductor layer 4 immediately below the third semiconductor layer 5 where the gate electrode 6 is formed The concentration of the two-dimensional electron gas layer 200 formed near the interface with the first semiconductor layer 3 is formed near the interface between the single-crystallized second semiconductor layer 4 and the first semiconductor layer 3. The two-dimensional electron gas layer 200 is either lowered or disappeared, and the same effect as the HEMT in FIG. 3 can be obtained.

  In addition, an example in which the two-dimensional electron gas layer 200 is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4 is shown, but the first semiconductor layer 3 and the second semiconductor layer 4 The effect of the present invention can be obtained even when applied to a high electron mobility transistor in which a two-dimensional hole gas layer is formed in the vicinity of the interface. Therefore, it is suitable for the case where one of the two-dimensional electron gas layer 200 and the two-dimensional hole gas layer, that is, the two-dimensional carrier gas layer, is generated in the vicinity of the interface between the first semiconductor layer 3 and the second semiconductor layer 4. However, the effect of the present invention can be obtained.

It is a conceptual diagram which shows the cross-sectional structure of the high electron mobility transistor by embodiment of this invention. It is a conceptual diagram explaining the effect which forms the distortion relaxation layer 5 by embodiment of this invention. It is a conceptual diagram which shows the cross-sectional structure of the high electron mobility transistor by embodiment of this invention. It is a conceptual diagram which shows the cross section of an element explaining the manufacturing method of the high electron mobility transistor by embodiment of this invention. It is a conceptual diagram which shows the cross section of an element explaining the other manufacturing method of the high electron mobility transistor by embodiment of this invention. It is a conceptual diagram which shows the cross-section of the high electron mobility transistor by other embodiment of this invention. It is a conceptual diagram which shows the cross-section of the high electron mobility transistor by a prior art example. It is a conceptual diagram which shows the cross section of an element explaining the other manufacturing method of the high electron mobility transistor by embodiment of this invention. It is a conceptual diagram which shows the cross section of an element explaining the other manufacturing method of the high electron mobility transistor by embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 1a ... Main surface 2 ... Buffer layer 3 ... First semiconductor layer 4 ... Second semiconductor layer 5 ... Third semiconductor layer 6 ... Gate electrode 7 ... Source electrode 8 ... Drain electrode 9 ... Thickness control film 10 ... Oxide film 11 ... Compound semiconductor layer 12 ... Insulating film 40 ... Fourth semiconductor layer 40A, 40B, 70A ... Region 60 ... Fifth semiconductor layer 70 ... Sixth semiconductor layer 100 ... Resist 200 ... Two-dimensional electron gas layer

Claims (12)

A first layer made of a first compound semiconductor;
A second layer made of a second compound semiconductor having spontaneous polarization on the first layer;
As viewed from above, between the second layers and on the first layer, the second compound semiconductor is included as a constituent element, and the crystallinity is lower than that of the second layer. A third layer;
A gate electrode formed on the third layer;
A drain electrode formed on the second layer;
A source electrode formed on the second layer so as to sandwich the gate electrode with the drain electrode when viewed from above;
Have
A high electron mobility transistor in which a two-dimensional carrier gas layer is generated in the vicinity of an interface between the first layer and the second layer.   2. The high electron mobility transistor according to claim 1, wherein the third layer has relaxed crystallinity as compared with the second layer. A first layer made of a first compound semiconductor;
A second layer made of a second compound semiconductor heterojunction with the first compound semiconductor and having spontaneous polarization on the first layer;
A third layer between the second layers as viewed from above and having a relaxed crystallinity on the first layer as compared with the second layer;
A gate electrode formed on the third layer;
A drain electrode formed on the second layer;
A source electrode formed on the second layer so as to sandwich the gate electrode with the drain electrode when viewed from above;
Have
A high electron mobility transistor in which a two-dimensional carrier gas layer is generated in the vicinity of an interface between the first layer and the second layer.   The high electron mobility transistor according to claim 1, wherein an insulating film is sandwiched between the third layer and the gate electrode. A first portion of the second layer is formed between the third layer and the first layer;
The first portion of the second layer is thinner than the second portion of the second layer formed so as to sandwich the third layer from the side. A high electron mobility transistor according to claim 1.   The first and second compound semiconductors are nitride-based compound semiconductors, and the third layer has a thickness of several atoms or more. High electron mobility transistor.   The high electron mobility transistor according to claim 1, wherein the third layer is a polycrystalline layer or an amorphous crystal layer. A second layer composed of a second compound semiconductor having a spontaneous polarization is formed on the first layer made of the first compound semiconductor so as to form a heterojunction with the first compound semiconductor and have a spontaneous polarization. Producing a two-dimensional carrier gas layer in the vicinity of the interface between the first layer and the second layer;
A third layer formed by reducing the crystallinity of the second layer is formed so as to be between the second layers when viewed from above, and an upper surface side of the first layer immediately below the third layer A step of reducing a two-dimensional carrier gas layer generated in step 2 to be smaller than a two-dimensional carrier gas layer generated near the interface between the second layer and the first layer;
Forming a gate electrode on the third layer and forming a drain electrode and a source electrode so as to sandwich the gate electrode;
A method of manufacturing a high electron mobility transistor having: A second layer composed of a second compound semiconductor having a spontaneous polarization is formed on the first layer made of the first compound semiconductor so as to form a heterojunction with the first compound semiconductor and have a spontaneous polarization. Producing a two-dimensional carrier gas layer in the vicinity of the interface between the first layer and the second layer;
A third layer formed by relaxing the crystallinity of the second layer is formed so as to be between the second layers when viewed from above, and an upper surface side of the first layer immediately below the third layer A step of reducing a two-dimensional carrier gas layer generated in step 2 to be smaller than a two-dimensional carrier gas layer generated near the interface between the second layer and the first layer;
Forming a gate electrode on the third layer and forming a drain electrode and a source electrode so as to sandwich the gate electrode;
A method of manufacturing a high electron mobility transistor having: The step of forming the third layer includes
After providing a thickness control film for controlling the thickness of the third layer on the second layer,
10. The high electron according to claim 8, wherein the third layer is formed by reducing the crystallinity of the second layer by ion implantation or plasma irradiation so as to penetrate from above the thickness control film. A method for manufacturing a mobility transistor. On the first layer made of the first compound semiconductor, the crystallinity of the second layer made of the second compound semiconductor having a spontaneous polarization property is lowered or relaxed by forming a heterojunction with the first compound semiconductor. Forming at a temperature that results in
The second layer is annealed so as to face both sides of the second layer when the third layer is viewed from above, and 2 near the interface on the upper surface side of the first layer immediately below the third layer. Producing a dimensional carrier gas layer;
Forming a gate electrode on the third layer, and forming each of a drain electrode and a source electrode on each of the second layers facing each other through the third layer;
A method of manufacturing a high electron mobility transistor having:   A fourth layer of the second compound semiconductor is formed between the first layer and the second layer in lattice matching with the first layer and at a temperature higher than that of the second layer. The method of manufacturing a high electron mobility transistor according to claim 11, further comprising a step of:

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