JP2008171843A - Semiconductor electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor electronic device capable of reducing a leakage current further while suppressing warpage in a wafer. <P>SOLUTION: In a field effect transistor 100 having a semiconductor operating layer 4 laminated onto a substrate 1 via buffer layers 2, 3, the buffer layer 3 has a composite layer 10, where a second layer 12 formed by a nitride-based compound semiconductor having an Al composition of not less than 0.8 is laminated on a first layer 11 formed by a nitride-based compound semiconductor having an Al composition of not more than 0.2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor electronic device including a compound semiconductor layer stacked on a substrate via a buffer layer.

  A field effect transistor as a semiconductor electronic device using a nitride-based compound semiconductor, for example, a GaN-based compound semiconductor, has attracted attention as a solid element that operates even in a high temperature environment close to 400 ° C. With GaN compound semiconductors, it is difficult to produce large-diameter single crystal substrates such as Si and GaAs, so electronic devices using GaN compound semiconductors use, for example, alternative substrates made of sapphire or Si. Have been made.

  The Si substrate is a very useful substrate in consideration of mass productivity and cost reduction because it is possible to easily obtain a high-quality and large-diameter wafer as compared with other alternative substrates. However, since there is a large lattice constant difference and a thermal expansion coefficient difference between Si and GaN, a large tensile strain is inherent in the GaN epitaxial film formed on the Si substrate, which deteriorates the crystallinity. At the same time, cracks may occur depending on the magnitude of strain. And the field effect transistor produced on such a GaN crystal had the problem that a favorable characteristic was not acquired.

  Therefore, when manufacturing a field effect transistor using a GaN-based compound semiconductor on a single crystal substrate made of Si, a buffer layer is first formed as a layer for reducing the tensile strain by an epitaxial crystal growth method such as MOCVD. Then, an electron transit layer, an electron supply layer, and a contact layer are sequentially stacked (hereinafter, the electron transit layer, the electron supply layer, etc. are referred to as a semiconductor operation layer), and a source electrode, a drain electrode, and a gate electrode are formed on the surface. . In this case, a GaN layer having a different lattice constant can be epitaxially grown on the Si substrate by forming a GaN layer at a high temperature to form a buffer layer. Conventionally, a superlattice buffer layer or an AlGaN buffer layer has been used as such a buffer layer (see, for example, Patent Document 1).

JP 2003-59948 A

  By the way, in the semiconductor electronic device, it is necessary to increase the resistance of the buffer layer in order to improve the breakdown voltage and reduce the leakage current. However, the conventional buffer layer described above does not necessarily have a sufficiently high resistance characteristic. On the other hand, although the resistance can be increased by increasing the thickness of the buffer layer, in this case, the conventional buffer layer described above has another problem that a large warp is generated in the wafer as a substrate.

  Here, the amount of warping (BOW) of the wafer is indicated by the difference between the peripheral edge height and the central height on the wafer surface, and is required to be 50 μm or less in the processing process of the semiconductor electronic device. For this reason, the conventional buffer layer has a limit in the film thickness that can be formed on the substrate, and there is a problem that the leakage current of the semiconductor electronic device cannot be sufficiently reduced.

  The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor electronic device that can further reduce a leakage current while suppressing warpage of a wafer.

  In order to solve the above-described problems and achieve the object, a semiconductor electronic device according to the present invention is a semiconductor electronic device including a compound semiconductor layer stacked on a substrate via a buffer layer, wherein the buffer layer is made of Al. A second layer formed using a nitride compound semiconductor having an Al composition of 0.8 or more is stacked on the first layer formed using a nitride compound semiconductor having a composition of 0.2 or less. It is characterized by having a composite layer.

  In the semiconductor electronic device according to the present invention as set forth in the invention described above, the thickness of the first layer is 100 to 1000 nm.

  In the semiconductor electronic device according to the present invention as set forth in the invention described above, the growth temperature of the first layer and the second layer is 700 to 1300 ° C., respectively.

  In the semiconductor electronic device according to the present invention as set forth in the invention described above, the thickness of the second layer is 0.5 to 200 nm.

In the semiconductor electronic device according to the present invention as set forth in the invention described above, the carbon concentration of the first layer is 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ .

  In the semiconductor electronic device according to the present invention as set forth in the invention described above, the buffer layer includes five or more composite layers.

In the semiconductor electronic device according to the present invention, the first layer is formed of Al _x1 In _y1 Ga _{1-x1-y1 Asu1} P _v1 N _1-u1-v1 (0 ≦ x1 ≦ 0. 2, 0 ≦ y1, u1, v1 ≦ 1, x1 + y1 ≦ 1, u1 + v1 <1), and the second layer is made of Al _x2 In _y2 Ga _{1 -x2-y2} As. It is formed by a nitride compound semiconductor represented by _u2 P _v2 N _1-u2-v2 (0.8 ≦ x2 ≦ 1, 0 ≦ y2, u2, v2 ≦ 1, x2 + y2 ≦ 1, u2 + v2 <1). Features.

  According to the semiconductor electronic device of the present invention, it is possible to further reduce the leakage current while suppressing the warpage of the wafer.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor electronic device according to the present invention will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment. Moreover, in description of drawing, the same code | symbol is attached | subjected and shown to the same part.

(Embodiment 1)
First, the semiconductor electronic device according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor 100 as a semiconductor electronic device according to the first embodiment. As shown in this figure, in a field effect transistor 100, a buffer layer 2, 3 and a semiconductor operation layer 4 formed by using a nitride-based compound semiconductor are sequentially stacked on a substrate 1 made of Si. A source electrode 8S and a drain electrode 8D made of Ti / Al, and a gate electrode 8G made of Pt / Au are formed.

  The buffer layer 2 is formed of AlN, and the buffer layer 3 has an Al composition of 0.8 or more on the first layer 11 formed using a nitride compound semiconductor having an Al composition of 0.2 or less. The composite layer 10 is formed by stacking the second layers 12 formed using a nitride compound semiconductor. For example, the first layer 11 is made of undoped GaN, and the second layer 12 is made of undoped AlN. As an example, the buffer layer 3 is formed by stacking five composite layers 10.

  The semiconductor operation layer 4 is formed by laminating an electron transit layer 5 made of undoped GaN, an electron supply layer 6 made of Si-doped AlGaN, and a contact layer 7 made of highly doped GaN in this order. The electron supply layer 6 has a larger band gap energy than the electron transit layer 5, and a two-dimensional electron gas layer 5a is formed immediately below the heterojunction interface between the two layers. The source electrode 8S and the drain electrode 8D are formed on the contact layer 7, and the gate electrode 8G is formed on the electron supply layer 6.

  In such a field effect transistor 100, when the source electrode 8S and the drain electrode 8D are operated, the electrons supplied to the electron transit layer 5 through the electron supply layer 6 travel at high speed in the two-dimensional electron gas layer 5a. And move to the drain electrode 8D. At this time, the electron moving from the source electrode 8S to the drain electrode 8D, that is, the drain current is controlled by changing the thickness of the depletion layer formed immediately below the gate electrode 8G according to the voltage applied to the gate electrode 8G. Can do.

Next, the composite layer 10 included in the buffer layer 3 will be described in detail. FIG. 2A shows the amount of warpage (BOW) of the wafer when the field effect transistor 100 is manufactured with respect to the Al composition x1 on the assumption that the first layer 11 is formed of Al _x1 Ga _1-x1 N. It is a graph which shows the result of actual measurement. Similarly, FIG. 2-2 is a graph showing the results of actual measurement of the amount of warpage (BOW) of the wafer with respect to the Al composition x2 on the assumption that the second layer 12 is formed of Al _x2 Ga _1-x2 N. . In these measurements, the thickness and growth temperature of the first layer 11 are 300 nm and 1000 ° C., respectively, and the thickness and growth temperature of the second layer 12 are 20 nm and 1000 ° C., respectively.

  From the results shown in FIGS. 2-1 and 2-2, in the field effect transistor 100, the Al composition x1 of the first layer 11 is 0.2 or less, and the Al composition x2 of the second layer 12 is 0.8 or more. It can be seen that the warpage amount of the wafer can be reduced to 50 μm or less. In FIG. 2A, the warping amount can be minimized by setting the Al composition x1 = 0 of the first layer 11, and in FIG. 2B, the Al composition x2 = 1 of the second layer 12. It can be seen that the amount of warpage can be minimized.

  Based on this, in the field effect transistor 100, the first layer 11 has an Al composition x1 of 0.2 or less, and the second layer 12 has an Al composition x2 of 0.8 or more. As a more preferred example, the first layer 11 is made of GaN, and the second layer 12 is made of AlN. Thereby, in the field effect transistor 100, it is possible to suppress the amount of warpage of the wafer at the time of manufacture. Specifically, even when the thickness of the buffer layer 3 is 3 μm or more, the amount of warpage of the wafer can be reduced. It can be suppressed to 50 μm or less required in the processing process of the electronic device. Therefore, in the field effect transistor 100, it is possible to form the buffer layer 3 sufficiently thicker than the buffer layer according to the related art while suppressing the amount of warpage of the wafer to 50 μm or less, thereby reducing the leakage current as compared with the conventional case. The pressure resistance can be improved.

As a result of actual measurement, it was confirmed that the leakage current can be 10 ⁻⁶ A / mm or less, and can be reduced by one digit or more than the conventional one. Further, it was confirmed that the mobility in the two-dimensional electron gas layer 5a can be about 1200 cm 2 / Vs, which can be improved by about 30% compared to the conventional case. Furthermore, it was confirmed that threading dislocations generated by internal strain can be reduced to about 1/10 to 1/100 of the conventional one.

  On the other hand, FIG. 3 is a graph showing the results of actual measurement of the amount of warpage (BOW) of the wafer with respect to the thickness of the GaN layer as the first layer 11. This graph shows the results of actual measurement of the amount of warpage when the thickness of the substrate 1 made of Si is 525 μm and 700 μm. The second layer 12 is made of AlN, and its thickness and growth temperature are 20 nm and 1100 ° C., respectively.

  From the results shown in FIG. 3, in the field effect transistor 100, the warp amount of the wafer can be minimized by forming the first layer 11 relatively thin. Specifically, the thickness of the first layer 11 can be reduced. It can be seen that the amount of warpage can be minimized by setting the thickness to about 200 nm. Further, it can be seen that the amount of warpage is a minus value at the minimum value, and is a minus value when the thickness of the first layer 11 is about 150 to 500 nm. Furthermore, it can be seen that the amount of warpage is 50 μm or less in absolute value when the thickness of the first layer 11 is about 100 to 1000 nm. Based on this, in the field effect transistor 100, the thickness of the first layer 11 is set to 100 to 1000 nm. FIG. 3 shows the results when the thickness of the substrate 1 made of Si is set to 525 μm and 700 μm, but the dependency of the warpage amount on the thickness of the substrate 1 is not particularly recognized.

  FIG. 4 is a graph showing the results of actual measurement of the amount of warpage (BOW) of the wafer with respect to the growth temperature of the AlN layer as the second layer 12. FIG. 4 shows the results when the thickness of the GaN layer as the first layer 11 is 200 nm. From this result, in the field effect transistor 100, the amount of warpage can be minimized by growing the second layer 12 at a relatively high temperature. Specifically, the growth temperature of the second layer 12 is about 1000. It turns out that it can be minimized by setting it to -1100 degreeC. Further, it can be seen that this warpage amount is a minus value at the minimum value, and is a minus value when the growth temperature of the second layer 12 is about 800 to 1200 ° C. Furthermore, it can be seen that the amount of warping is 50 μm or less in absolute value when the growth temperature of the second layer 12 is about 700 to 1300 ° C. Based on this, in the field effect transistor 100, the growth temperature of the second layer 12 is set to 700 to 1300 ° C.

  On the other hand, the first layer 11 can be grown, for example, in a temperature range of 700 to 1300 ° C. which is a general GaN layer growth temperature. Furthermore, by limiting the growth temperature to 800 to 1200 ° C., the first layer 11 having good crystallinity and flatness can be formed. However, in order to form the first layer 11 with higher accuracy, the growth temperature is preferably limited to 1000 to 1100 ° C.

  The thicknesses of the second layer 12 corresponding to the results shown in FIGS. 2 to 4 are all 20 nm, but the results shown in FIGS. 2 to 4 are the thicknesses of the second layer 12. It has been separately found that the same results as in FIGS. 2 to 4 can be obtained when the dependence on is small and the thickness of the second layer 12 is about 0.5 to 200 nm. In addition, when the thickness of the second layer 12 is made thinner than 0.5 nm, a sufficient effect as the second layer is not exhibited. Conversely, when the thickness is made thicker than 200 nm, excessive stress is applied from this layer. Therefore, it can be said that the thickness of the second layer 12 in the field effect transistor 100 is preferably 0.5 to 200 nm.

(Embodiment 2)
Next, a semiconductor electronic device according to the second embodiment of the present invention will be described. FIG. 5 is a cross-sectional view showing a configuration of a field effect transistor 200 as a semiconductor electronic device according to the second embodiment. As shown in this figure, the field effect transistor 200 includes a buffer layer 23 instead of the buffer layer 3 based on the configuration of the field effect transistor 100. Other configurations are the same as those of the field effect transistor 100, and the same components are denoted by the same reference numerals.

Similar to the buffer layer 3, the buffer layer 23 is formed by stacking a plurality of composite layers 20. Here, as an example, it is assumed that five composite layers 20 are laminated. The composite layer 20 uses the first layer 21 instead of the first layer 11 based on the configuration of the composite layer 10 in the buffer layer 3, and the second layer 12 is laminated on the first layer 21. Is formed. The first layer 21 is formed using a nitride compound semiconductor having an Al composition of 0.2 or less and doped with carbon (C). For example, the first layer 21 is formed of C-doped GaN. The carbon concentration (C concentration) in the first layer 21 is set to 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ . Under other conditions, the first layer 21 is formed in the same manner as the first layer 11 described above.

FIG. 6 is a graph showing results of actually measuring the withstand voltage of the field effect transistor 200 with respect to the carbon concentration of the GaN layer as the first layer 21. From the results shown in this figure, it can be seen that the breakdown voltage of the field effect transistor 200 can be increased by increasing the carbon concentration of the first layer 21. Further, it can be seen that the breakdown voltage of the field-effect transistor 200 rapidly decreases when the carbon concentration of the first layer 21 is about 1 × 10 ¹⁷ cm ⁻³ or less. Based on this, in the field effect transistor 200, the carbon concentration of the first layer 21 is set to 1 × 10 ¹⁷ cm ⁻³ or more, and high breakdown voltage is realized.

On the other hand, it is generally known that when the GaN layer is doped with a carbon concentration of 1 × 10 ²⁰ cm ⁻³ or more, its crystallinity is deteriorated and crystal defects are increased. Therefore, in the field effect transistor 200, the carbon concentration of the first layer 21 is set to 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, and an increase in crystal defects is achieved while achieving high breakdown voltage. It is suppressed.

  In the field effect transistor 200, since the first layer 21 is formed in the same manner as the first layer 11 under conditions other than the carbon concentration, while suppressing the warpage of the wafer, similar to the field effect transistor 100, Leakage current can be reduced and pressure resistance can be improved.

(Embodiment 3)
Next, a semiconductor electronic device according to a third embodiment of the present invention will be described. In the first and second embodiments described above, the field effect transistor (FET) as a semiconductor electronic device according to the present invention has been described as a high electron mobility transistor (HEMT). The present invention is not limited to a high electron mobility transistor, and may be a MOS field effect transistor (MOSFET: Metal Oxide Semiconductor FET).

  FIG. 7 is a cross-sectional view showing a configuration of a field effect transistor 300 as a semiconductor electronic device according to the third embodiment. As shown in this figure, a field effect transistor 300 is formed as a MOS field effect transistor, and based on the configuration of the field effect transistor 100, each of the semiconductor operation layer 4, the source electrode 8S, the gate electrode 8G, and the drain electrode 8D. Instead, the semiconductor operation layer 34, the source electrode 38S, the gate electrode 38G, and the drain electrode 38D are provided. Other configurations are the same as those of the field effect transistor 100, and the same components are denoted by the same reference numerals.

The semiconductor operation layer 34 is formed using a p-type semiconductor layer 35 made of p-GaN and an n-type semiconductor layer 36 made of n ⁺ -GaN. The p-type semiconductor layer 35 is formed on the buffer layer 3 by, for example, the MOCVD method, and the dopant concentration is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ . In the p-type semiconductor layer 35, for example, Mg, C, Zn, or Be is used as a dopant. The n-type semiconductor layer 36 is formed by ion implantation after growing the p-type semiconductor layer 35.

The gate electrode 38G as an insulated gate is formed by laminating an insulating film 38Ga and an electrode layer 38Gb in this order. As the insulating film 38Ga, for example, an insulating film having sufficient dielectric breakdown electric field strength such as SiO ₂ or Al ₂ O ₃ is used. The thickness of the insulating film 38Ga is, for example, about 50 to 100 nm in the case of SiO ₂ . The electrode layer 38Gb is formed using, for example, polysilicon or a metal film such as Ni / Au or WSi. On the other hand, the source electrode 38S and the drain electrode 38D are formed using a metal film that can make ohmic contact with the n-type semiconductor layer 36, such as Ti / Al or Ti / AlSi / Mo.

  In the field effect transistor 300 configured as described above, the inversion layer 35a is formed at the boundary between the p-type semiconductor layer 35 and the insulating film 38Ga by applying a positive voltage equal to or higher than a predetermined potential to the gate electrode 38G. The inversion layer 35a serves as a channel, the two n-type semiconductor layers 36 are electrically connected, and a drain current is conducted between the source electrode 38S and the drain electrode 38D. At this time, the drain current can be controlled by changing the thickness of a depletion layer (not shown) formed immediately below the insulating film 38Ga by the voltage applied to the gate electrode 38G.

  Since the field effect transistor 300 according to the third embodiment is configured by using the same buffer layer 3 as that of the first embodiment described above, the leakage of the wafer while suppressing the warpage of the wafer, as in the first embodiment. The withstand voltage can be improved by reducing the current.

  Up to this point, the best mode for carrying out the present invention has been described as the first to third embodiments. However, the present invention is not limited to the above-described first to third embodiments, and may be within the scope of the present invention. Various modifications are possible.

  For example, in the first to third embodiments described above, the high electron mobility transistor and the MOS field effect transistor have been described as the semiconductor electronic device according to the present invention. However, the present invention is not limited to these, and an insulated gate field effect transistor (MISFET: Metal). The present invention is applicable to various field effect transistors such as an Insulator Semiconductor FET) and a Schottky gate field effect transistor (MESFET: Metal Semiconductor FET).

  In addition to field effect transistors, the present invention is applicable to various diodes such as Schottky diodes. As a diode to which the present invention is applied, for example, a diode in which a cathode electrode and an anode electrode are formed instead of the source electrode 8S, the gate electrode 8G, and the drain electrode 8D provided in the field effect transistor 100 can be realized.

  In the first to third embodiments described above, the substrate 1 made of Si has been described. However, the substrate material is not limited to Si, and various materials such as sapphire, SiC, GaN, or ZnO may be used. it can.

  In the first to third embodiments described above, the semiconductor electronic device according to the present invention has been described as including the semiconductor operation layer 4 or 34 formed using a nitride compound semiconductor, particularly a GaN compound semiconductor. However, the present invention is not necessarily limited to the nitride system and the GaN system, and the present invention can be applied to a semiconductor electronic device including a semiconductor operation layer formed using another compound semiconductor.

In the first to third embodiments described above, the first layer 11 or 21 in the buffer layer 3 or 23 is formed of Al _x1 Ga _1-x1 N (0 ≦ x1 ≦ 0.2), and the second layer 12 is formed by Al _x2 Ga _1-x2 N (0.8 ≦ x2 ≦ 1), but the present invention is not limited to this, and the first layers 11 and 21 are generally made of Al _x1 In by a compound semiconductor represented by _{y1 Ga 1-x1-y1 as} u1 P v1 N 1-u1-v1 (0 ≦ x1 ≦ 0.2,0 ≦ y1, u1, v1 ≦ 1, x1 + y1 ≦ 1, u1 + v1 <1) The second layer can generally be formed of Al _x2 In _y2 Ga _{1 -x2-y2 Asu2} P _v2 N _{1 -u2-v2} (0.8≤x2≤1, 0≤y2, u2, v2≤ 1, x2 + y2 ≦ 1, u2 + v2 <1).

It is sectional drawing which shows the structure of the field effect transistor as a semiconductor electronic device concerning Embodiment 1 of this invention. FIG. 2 is a diagram showing the relationship between the Al composition of the first layer and the amount of warpage of the wafer in the field effect transistor shown in FIG. 1. FIG. 2 is a diagram showing a relationship between the Al composition of a second layer and the amount of warpage of the wafer in the field effect transistor shown in FIG. 1. It is a figure which shows the relationship between the thickness of a 1st layer, and the curvature amount of a wafer. It is a figure which shows the relationship between the growth temperature of a 2nd layer, and the curvature amount of a wafer. It is sectional drawing which shows the structure of the field effect transistor as a semiconductor electronic device concerning Embodiment 2 of this invention. It is a figure which shows the relationship between the carbon concentration of the 1st layer in the field effect transistor shown in FIG. 5, and the proof pressure of a field effect transistor. It is sectional drawing which shows the structure of the field effect transistor as a semiconductor electronic device concerning Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2,3,23 Buffer layer 4 Semiconductor operation layer 5 Electron traveling layer 5a Two-dimensional electron gas layer 6 Electron supply layer 7 Contact layer 8D Drain electrode 8G Gate electrode 8S Source electrode 10, 20 Composite layer 11, 21 First Layer 12 second layer 34 semiconductor operation layer 35 p-type semiconductor layer 35a inversion layer 36 n-type semiconductor layer 38D drain electrode 38G gate electrode 38Ga insulating film 38Gb electrode layer 38S source electrode 100, 200, 300 field effect transistor

Claims (7)

In a semiconductor electronic device comprising a compound semiconductor layer laminated on a substrate via a buffer layer,
The buffer layer is formed on the first layer formed using a nitride compound semiconductor having an Al composition of 0.2 or less using a nitride compound semiconductor having an Al composition of 0.8 or more. A semiconductor electronic device comprising a composite layer in which a second layer is laminated.   The semiconductor electronic device according to claim 1, wherein the thickness of the first layer is 100 to 1000 nm.   3. The semiconductor electronic device according to claim 1, wherein a growth temperature of each of the first layer and the second layer is 700 to 1300 ° C. 3.   The thickness of the said 2nd layer is 0.5-200 nm, The semiconductor electronic device as described in any one of Claims 1-3 characterized by the above-mentioned. The semiconductor electronic device according to claim 1, wherein the carbon concentration of the first layer is 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ .   The semiconductor electronic device according to claim 1, wherein the buffer layer includes five or more composite layers. Said first _{layer, Al x1 In y1 Ga 1-} x1-y1 As u1 P v1 N 1-u1-v1 (0 ≦ x1 ≦ 0.2,0 ≦ y1, u1, v1 ≦ 1, x1 + y1 ≦ 1, formed by a nitride compound semiconductor represented by u1 + v1 <1),
The second layer is made of Al _x2 In _y2 Ga _{1-x2-y2 Asu2} P _v2 N _1-u2-v2 (0.8 ≦ x2 ≦ 1, 0 ≦ y2, u2, v2 ≦ 1, x2 + y2 ≦ 1, The semiconductor electronic device according to claim 1, wherein the semiconductor electronic device is formed of a nitride compound semiconductor represented by u2 + v2 <1).

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