JP2008171016A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device free from a white void in a display area near a gate terminal by blocking an electric field generated by a lead wiring line and preventing potential fluctuation in a counter substrate in an in-plane switching liquid crystal display device. <P>SOLUTION: The liquid crystal display device relating to the present invention includes a gate terminal to apply a voltage to a gate wiring line and a tapered gate wiring section placed to be connected thereto, and a conductive layer disposed over the tapered gate wiring section via an insulating film. The gate terminal 16 to apply a voltage to a gate wiring line 4, and the tapered gate wiring section 14 laid to be connected thereto are provided; and the conductive layer 18 is laid over the tapered gate wiring section 14 via the gate insulating film 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an in-plane response type liquid crystal display device (hereinafter referred to as an IPS (in plane switching) panel). More specifically, the present invention relates to a liquid crystal display device having a structure in which white spots in the vicinity of a gate terminal in a display area are eliminated and display characteristics are improved.

In the conventional IPS panel, the pixel electrode PX generates an electric field between the pixel electrode PX and the counter electrode CT connected to the counter voltage signal line CL, and the light transmittance of the liquid crystal is controlled by this electric field ( For example, see Patent Document 1).
JP 2003-295210 A (page 4-5, FIG. 2)

  In the conventional IPS panel, the lead line connecting the gate signal line GL and the gate terminal on the transparent substrate SUB1, more specifically, the distance between adjacent gate terminals outside the display area is narrower than the distance between adjacent gate lines. A liquid crystal display near the gate terminal is induced by an electric field generated from a lead wiring group (hereinafter referred to as a tapered gate wiring portion) in which the wiring pitch becomes narrower as it is closer to the gate terminal. There was a problem that white spots occurred in AR.

  The present invention has been made to solve the above-described problems. When an IPS panel is used, the electric field generated from the tapered gate wiring portion is shielded, and the potential fluctuation of the counter substrate is prevented. A liquid crystal display device that does not cause white spots in the display region near the gate terminal is obtained.

  In the liquid crystal display device according to the present invention, a gate terminal for applying a voltage to the gate wiring and a tapered gate wiring portion installed to connect to the gate terminal are provided, and an insulating film is provided above the tapered gate wiring portion. A conductive layer is provided.

  According to the present invention, the conductive layer is disposed on the upper layer of the tapered gate wiring portion with an insulating film interposed therebetween, so that the conductive layer shields the electric field generated from the tapered gate wiring portion and prevents the potential fluctuation of the counter substrate. Thus, it is possible to improve the display quality without causing white spots in the display area near the gate terminal.

Embodiment 1 FIG.
1 is an enlarged plan view of the vicinity of a thin film transistor (hereinafter referred to as TFT) of a liquid crystal display device according to Embodiment 1 for carrying out the present invention, and FIG. 2 is an arrow AA line in the vicinity of the TFT shown in FIG. FIG. 3 is a plan view showing an end portion on the gate terminal side of the liquid crystal display device according to the first embodiment for carrying out the present invention, and FIG. 4 is a plan view showing FIG. FIG. 5 is an explanatory view showing a manufacturing process of a partial cross section seen from the line BB in the vicinity of the tapered gate wiring portion shown in FIG. 5, and FIG. 5 shows the vicinity of the tapered gate wiring portion of the liquid crystal display device in the first embodiment for carrying out the present invention. FIG. 6 is an explanatory view showing a manufacturing process of a partial cross section as seen from the CC line in the vicinity of the tapered gate wiring portion shown in FIG.

  In FIG. 1 to FIG. 6, pixels that form a display region 2 are disposed on a first substrate 1 a that is a transparent insulating substrate, and each pixel includes a TFT 3. The gate line 4 intersects with the source line 6 through the gate insulating film 5, and the TFT 3 is formed corresponding to each intersection of the plurality of gate lines 4 and the plurality of source lines 6. The gate electrode 4 a of the TFT 3 is a part of the gate wiring 4, the source electrode 6 a is a part of the source wiring 6, and the drain electrode 6 b is connected to the pixel electrode 8 through the first contact hole 7.

  Comb-like pixel electrodes 8 connected to the TFTs 3 and combs formed in parallel and alternately corresponding to the comb teeth of the pixel electrodes 8 and connected to the common signal line 11 via the second contact holes 9 By applying a voltage between the toothed counter electrode 10, an electric field substantially parallel to the surface of the first substrate 1 a is generated. The pixel electrode 8 is formed of a metal such as chromium (Cr) or a transparent conductive film such as ITO (Indium Tin Oxide).

Since the common voltage is generally applied to the common signal line 11 as a whole display device, a plurality of common signal lines 11 are connected to the connection line 12 arranged outside the display area 2 via the conversion unit 13. Connect in common. The common signal line 11 is made of a metal such as chromium (Cr).
In this example, the source wiring 6, the pixel electrode 8, and the counter electrode 10 are bent once at the center. The bending point is provided at a position corresponding to the common signal line 11. In this way, the bent electrode configuration can provide two directions of liquid crystal driving directions, and can improve the deterioration of viewing angle characteristics that occur in a specific direction in the IPS panel.

  The gate lines 4 and the source lines 6 are drawn from the display area 2 by the tapered gate line part 14 and the tapered source line part 15, respectively. The gate terminal 16 and the source terminal 17 are formed near the end of the first substrate 1a. Are connected to each. The connection line 12 is connected to a common signal line terminal 23 formed in parallel with the gate terminal 16 or the source terminal 17.

  A drive circuit or the like mounted on a film substrate is connected to the gate terminal 16, the source terminal 17, and the common signal line terminal 23 by using a conductive material such as ACF (Anisotropic Conductive Film). .

Hereinafter, a substrate in which the TFT 3 is formed on the first substrate 1a is referred to as an array substrate.
A plurality of spacers are arranged in the gap between the second substrate 1b and the first substrate 1a facing the first substrate 1a, and the two substrates are held at equal intervals. In addition, liquid crystal is sealed by a sealing material and a sealing material that are arranged around the first substrate 1a and the second substrate 1b and are bonded to each other. On the second substrate 1b, a colored layer, a light-shielding layer, an alignment film for imparting initial alignment to the liquid crystal, a polarizing plate for polarizing light, and the like are formed and referred to as a counter substrate by facing the array substrate.

  A conductive layer 18 is formed over the tapered gate wiring portion 14 on the first substrate 1a via an insulating film. In the first embodiment, the insulating film insulates the gate wiring 4 and the source wiring 6 from each other. The gate insulating film 5 and a protective film 21 to be described later, and the conductive layer 18 is formed by the same manufacturing process as the pixel electrode 8, that is, is formed by a conductive film of the same layer.

  Note that the pattern of the conductive layer 18 is disposed in a region that covers the entire tapered gate wiring portion 14 when viewed from the second substrate 1b side, thereby shielding the electric field generated from the tapered gate wiring portion 14 without leakage. However, the pattern of the conductive layer 18 may be narrowed from the gate terminal 16 toward the display region as long as no white spots occur in the display region 2 near the gate terminal 16.

Next, a method for manufacturing the liquid crystal display device according to the first embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIGS. 2 (a), 4 (a) and 6 (a), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. are formed on an insulating substrate. An alloy containing them as a main component, a light-transmitting conductive film such as ITO, or a multilayer film thereof is formed by a sputtering method, a vapor deposition method, etc. 4a, the common signal line 11 and the tapered gate wiring portion 14 are formed.

Next, as shown in FIGS. 2B, 4B, and 6B, a gate insulating film 5 made of silicon nitride or the like is formed, and further, amorphous Si, polycrystalline poly-Si, or the like is formed. In the case of an n-type TFT, a contact film 20 made of n ⁺ amorphous Si, n ⁺ polycrystalline poly-Si or the like doped with an impurity such as P in a high concentration is continuously formed, for example, by plasma. The film is formed by CVD, atmospheric pressure CVD, or reduced pressure CVD.

  Next, the semiconductor film 19 and the contact film 20 are processed into an island shape.

  Next, as shown in FIG. 2 (c), FIG. 4 (c) and FIG. 6 (c), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. and their main components After forming a light-transmitting conductive film such as ITO or a transparent conductive film such as ITO by a sputtering method or a vapor deposition method, the source wiring 6, the source electrode 6 a, the drain are formed by photolithography and fine processing technology. An electrode 6b, a tapered source wiring portion 15, a connection line 12, a storage capacitor electrode, and the like are formed.

  Further, the contact film 20 is etched using the source electrode 6a and the drain electrode 6b or the photoresist on which they are formed as a mask, and removed from the channel region.

Next, as shown in FIGS. 2D, 4D, and 6D, a protective film 21 made of silicon nitride, silicon oxide, an inorganic insulating film, an organic resin, or the like is formed.
Thereafter, a third contact for connecting the first contact hole 7, the second contact hole 9, the tapered gate wiring portion 14 and the gate terminal 16, and the common signal line 11 and the conversion portion 13 by photolithography and subsequent etching. A hole 22 and a fourth contact hole 24 that connects the tapered source wiring portion 15, the source terminal 17, the connection line 12, and the common signal line terminal 23 or the conversion portion 13 are formed.

  Finally, as shown in FIG. 2 (e), FIG. 4 (e) and FIG. 6 (e), Cr, Al, Ti, Ta, Mo, W, Ni, Cu, Au, Ag, etc. and their main components The pixel electrode 8, the counter electrode 10, the gate terminal 16, the source terminal 17, and the conversion unit are formed by patterning after forming a transparent conductive film such as ITO, a transparent conductive film such as ITO, or a multilayer film thereof. 13. Conductive layer 18 and common signal line terminal 23 are formed.

  Through the above steps, the array substrate constituting the IPS panel in this embodiment can be manufactured. Further, a liquid crystal is sandwiched between the array substrate and the counter substrate and bonded with a sealing material. At this time, liquid crystal molecules are aligned at a predetermined angle by a method such as rubbing or photo-alignment. Any known method may be used for aligning the liquid crystal. Further, a liquid crystal display device is manufactured by connecting a gate line driving circuit, a source line driving circuit, and a common signal line power source to the gate wiring 4, the source wiring 6, and the common signal line 11, respectively.

  As described above, in the first embodiment, the conductive layer 18 is disposed on the upper layer of the tapered gate wiring portion 14 via the gate insulating film 5 and the protective film 21, and is generated from the tapered gate wiring portion 14. By shielding the electric field with the conductive layer 18 and preventing the potential fluctuation of the counter substrate, a liquid crystal display device that does not cause white spots in the display region 2 in the vicinity of the gate terminal 16 can be obtained.

  Further, by forming the conductive layer 18 in the same process as the pixel electrode 8, an increase in the number of manufacturing steps due to an increase in the number of masks in the photoengraving for forming the conductive layer 18, and a new material for the conductive layer 18 is added. Thus, a liquid crystal display device can be obtained.

  In the first embodiment, the conductive layer 18 and the conversion part 13 are formed apart from each other. However, as shown in FIG. 7, the conversion part 13 is extended to the gate terminal 16 side so that the conductive layer 18 is formed. The dual use is preferable because the conductive layer 18 can be electrically connected to the common signal line 11 and shielded by a fixed potential. FIG. 7 is an enlarged plan view of the vicinity of a tapered gate wiring portion of another liquid crystal display device according to the first embodiment for carrying out the present invention.

  In the first embodiment, the conductive layer 18 is formed in the same process as the pixel electrode 8, but as shown in FIG. 8, the source wiring 6, the source electrode 6a, the drain electrode 6b, and the tapered source wiring section 15 are formed. Even if the connection line 12 and the storage capacitor electrode are formed in the same process, the conductive layer 18 can shield the electric field generated from the tapered gate wiring portion 14, and thus the same effect can be obtained. FIG. 8 is an explanatory view showing another manufacturing process of the partial cross section viewed along the line BB in the vicinity of the tapered gate wiring portion shown in FIG.

  In the first embodiment, the conductive layer 18 and the connection line 12 are formed apart from each other. However, as shown in FIG. 9, the connection line 12 extends to the gate terminal 16 side so that the conductive layer 18 is formed. The dual use is preferable because the conductive layer 18 can be electrically connected to the common signal line 11 and shielded by a fixed potential. FIG. 9 is an enlarged plan view of the vicinity of a tapered gate wiring portion of another liquid crystal display device according to the first embodiment for carrying out the present invention.

  In the first embodiment, the conductive layer 18 is formed on the array substrate. However, even if the conductive layer 18 is formed in the region corresponding to the tapered gate wiring portion 14 on the counter substrate, the conductive layer 18 is not formed. Since the electric field generated from the tapered gate wiring portion 14 can be shielded, the same effect can be obtained.

It is the top view to which TFT vicinity of the liquid crystal display device in Embodiment 1 for implementing this invention was expanded. It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow AA line of TFT vicinity shown in FIG. It is the top view which showed the edge part by the side of the gate terminal of the liquid crystal display device in Embodiment 1 for implementing this invention. It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow BB line of the taper gate wiring part vicinity shown in FIG. It is the top view to which the taper gate wiring part vicinity of the liquid crystal display device in Embodiment 1 for implementing this invention was expanded. It is explanatory drawing which showed the manufacturing process of the partial cross section seen from the arrow CC line vicinity of the taper gate wiring part shown in FIG. It is the top view to which the taper gate wiring part vicinity of the other liquid crystal display device in Embodiment 1 for implementing this invention was expanded. It is explanatory drawing which showed the other manufacturing process of the partial cross section seen from the arrow BB line of the taper gate wiring part vicinity shown in FIG. It is the top view to which the taper gate wiring part vicinity of the other liquid crystal display device in Embodiment 1 for implementing this invention was expanded.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a 1st board | substrate, 1b 2nd board | substrate, 2 Display area, 3 TFT, 4 Gate wiring, 4a gate electrode, 5 Gate insulating film, 6 Source wiring, 6a Source electrode, 6b Drain electrode, 7 1st contact hole , 8 Pixel electrode, 9 Second contact hole, 10 Counter electrode, 11 Common signal line, 12 Connection line, 13 Conversion part, 14 Tapered gate wiring part, 15 Tapered source wiring part, 16 Gate terminal, 17 Source terminal, 18 Conductive layer, 19 semiconductor layer, 20 contact film, 21 protective film, 22 third contact hole, 23 common signal line, 24 fourth contact hole

Claims (10)

A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed to face the pixel electrode;
A gate terminal for applying a voltage to the gate wiring;
An array substrate having a lead-out line outside the display region connecting the gate line and the gate terminal;
A counter substrate facing the array substrate,
A conductive layer is disposed above the lead-out wiring via an insulating film,
The conductive layer is the same layer as the pixel electrode or the counter electrode,
The liquid crystal display device, wherein the lead-out wiring is formed in a layer different from the pixel electrode. A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed facing the pixel electrode and connected to a common signal line;
A connection line for commonly connecting a plurality of the common signal lines;
A gate terminal for applying a voltage to the gate wiring;
An array substrate having a lead-out line outside the display region connecting the gate line and the gate terminal;
A counter substrate facing the array substrate,
In addition to the connection line, a conductive layer is disposed on the lead wiring via an insulating film,
The conductive layer is the same layer as the pixel electrode or the counter electrode,
The liquid crystal display device, wherein the lead-out wiring is formed in a layer different from the pixel electrode. A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed facing the pixel electrode and connected to a common signal line;
A connection line for commonly connecting a plurality of the common signal lines;
A gate terminal for applying a voltage to the gate wiring;
An array substrate having a lead-out line outside the display region connecting the gate line and the gate terminal;
A counter substrate facing the array substrate,
A conductive layer formed by extending the connection line to the gate terminal side through an insulating film is disposed on the lead wiring,
The conductive layer is the same layer as the pixel electrode or the counter electrode,
The liquid crystal display device, wherein the lead-out wiring is formed in a layer different from the pixel electrode. A thin film transistor formed corresponding to each intersection of a plurality of gate lines and a plurality of source lines;
A pixel electrode connected to the thin film transistor;
A counter electrode formed facing the pixel electrode and connected to a common signal line;
A plurality of common signal lines connected in common by the converter,
A gate terminal for applying a voltage to the gate wiring;
An array substrate having a lead-out line outside the display region connecting the gate line and the gate terminal;
A counter substrate facing the array substrate,
A conductive layer formed in the same layer as the conversion part via an insulating film is disposed on the lead line,
The conductive layer is the same layer as the pixel electrode or the counter electrode,
The liquid crystal display device, wherein the lead-out wiring is formed in a layer different from the pixel electrode. 5. The liquid crystal display device according to claim 4, wherein the conductive layer is formed by extending the conversion portion to the gate terminal side. The liquid crystal display device according to claim 1, wherein the conductive layer is an uppermost layer. 7. The liquid crystal display device according to claim 1, wherein the conductive layer is formed only in a region of the lead-out wiring outside the display region connecting the gate wiring and the gate terminal. 8. The liquid crystal display device according to claim 1, wherein the gate terminal is the same layer as the conductive layer, and is connected to the lead-out wiring through a contact hole provided in the insulating film. 9. The liquid crystal display device according to claim 1, wherein the insulating film includes a gate insulating film formed on the gate wiring and a protective film formed on the source wiring. The liquid crystal display device according to claim 1, wherein the conductive layer has a potential of a counter electrode.

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