JP2007226494A - Data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer system wherein a transfer rate is not reduced without using an excess lane number even when transaction (data transfer) from a plurality of end points to one switch simultaneously occurs. <P>SOLUTION: In this data transfer system, a lane number of a link of a high-speed serial bus forming a data transfer route from the switch 14 to a node (a route complex 13) positioned on an upper side of a tree structure is set as a lane number obtained by adding lane numbers satisfying maximum values of respective data transfer amounts transmitted through the respective data transfer routes from the end points 21-27 to the switch 14. Thereby, because a bottleneck by simultaneous operation can be dissolved, the excess lane number is not used, and the transfer rate is not reduced even when the plurality of the data transfer are overlapped. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer system.

  In general, in an information processing apparatus such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

JP 2001-016382 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  By the way, in a data transfer system using a high-speed serial interface such as IEEE1394 or USB, the performance of the transfer path between nodes is fixed (number of lanes 1). On the other hand, in PCI Express, the performance of each transfer path can be changed by changing the number of lanes. However, there is a trade-off between performance and cost.

  However, in PCI Express, the average transfer rate between nodes via a switch is governed by the performance (link width and number of lanes) of the narrowest transfer path in the path, so there is a bottleneck at one location. However, no effect is obtained no matter how wide the other transfer paths are. The bottleneck needs to consider not only the number of physical lanes but also a plurality of transactions (data transfer) operating simultaneously.

  The present invention has been made in view of the above, and even when transactions (data transfer) from a plurality of endpoints to one switch occur simultaneously, an extra lane number is not used. An object of the present invention is to provide a data transfer system in which the transfer rate does not decrease.

  Another object of the present invention is to optimize cost performance in a data transfer system in which data transfer from each endpoint to a switch is not performed simultaneously.

  In order to solve the above-mentioned problems and achieve the object, the invention according to claim 1 is a tree-structured data communication network in which a point-to-point independent communication channel is established and any number of lanes can be selected. In a data transfer system in which a plurality of end points are connected to one switch by using a high-speed serial bus, and data is transferred from each end point to the switch. The number of lanes of the link of the high-speed serial bus that forms the data transfer path to the node located on the upper side satisfies the maximum value of each data transfer amount transmitted through each data transfer path from the end point to the switch The number of lanes is added to each lane number.

  Further, the invention according to claim 2 uses a high-speed serial bus in which a communication channel independent of transmission and reception is established point-to-point as a tree-structured data communication network, and an arbitrary number of lanes can be selected. In a data transfer system in which a plurality of end points are connected to each other, and data transfer from each end point to the switch is not performed simultaneously, a data transfer path from each end point to the switch and the switch The number of lanes satisfying the maximum value of the data transfer amount transmitted through the data transfer path is the number of all lanes of the link of the high-speed serial bus that forms the data transfer path from the node to the node positioned on the upper side of the tree structure. To unify.

  According to a third aspect of the present invention, in the data transfer system according to the first or second aspect, the high-speed serial bus is a PCI Express standard high-speed serial bus.

  According to the first aspect of the present invention, the number of lanes of the link of the high-speed serial bus that forms the data transfer path from the switch to the node located on the upper side of the tree structure is determined, and each data transfer path from the end point to the switch is determined. This is the case where transactions (data transfer) from multiple endpoints to one switch occur simultaneously by setting the number of lanes to which the maximum value of each data transfer amount to be transmitted is added. However, since the bottleneck due to the simultaneous operation can be eliminated, it is possible to provide a data transfer system in which the transfer rate does not decrease even when a plurality of data transfers overlap without using an extra number of lanes. There is an effect that can be done.

  According to the invention of claim 2, all the links of the high-speed serial bus that form the data transfer path from each end point to the switch and the data transfer path from the switch to the node located on the upper side of the tree structure The number of lanes of all data transfer paths on the data transfer path related to one data transfer is changed to a desired number of lanes by unifying the number of lanes to the number of lanes satisfying the maximum value of the data transfer amount transmitted through the data transfer path. By making the transfer rate equal to the number of lanes from which the transfer rate can be obtained, the cost performance can be optimized.

  According to the invention of claim 3, the high-speed serial bus is a PCI Express standard high-speed serial bus, so that low-voltage differential signal transmission, point-to-point independent transmission and reception communication channels, and packetization It has the effect of having features such as high scalability due to differences in split transactions and link configurations.

  Exemplary embodiments of a data transfer system according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the [Data Transfer System] column for the data transfer system of the present embodiment. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In an existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect a PCI-X bridge 105a to a host bridge 103 to which a CPU 100, AGP graphics 101, and memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double arrows indicate the PCI Express link 114 (or 126), and 142a to 142d indicate ports. Among these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions extended by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Although various form factors (shapes) can be considered as PCI Express, examples of specific examples include an add-in card, a plug-in card (Express Card), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be effectively used by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Data transfer system]
The data transfer system according to the present embodiment includes an image output device such as a printer, an image input device such as a scanner, a digital copier having both of them, and an image forming device such as an MFP (Multi Function Peripheral). The present invention is applied to an image forming system and uses a high-speed serial bus conforming to the PCI Express standard as described above.

  An example of an image forming system to which the data transfer system of this embodiment is applied will be described with reference to FIG. FIG. 16 is a block diagram showing an outline of connections of devices, devices, etc. of an image forming system to which the data transfer system of the present embodiment is applied. The image forming system 1 uses a PCI Express standard bus system for serial data transfer. That is, a CPU 11 that centrally controls each unit of the image forming system 1 and a memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard serial bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices and devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 that stores image data and the like, an image memory unit 22 and a memory unit 23, an image processing unit 24 that performs various image processing, a high-speed network 25 that communicates with an external network, etc. A scanner 26 as an input engine, a plotter 27 as an image output engine, an image input engine, another MFP 28 having an image output engine, and the like.

  According to such a configuration, since the PCI Express system, which is a high-speed serial bus, is used, the data transfer speed can be basically increased. In addition, the PCI Express standard end point (End Point) and Further speeding up of data transfer between the various devices / devices 21 to 27 can be achieved. That is, the PCI Express system between the various devices / devices 21 to 27 is connected through a tree structure having the PCI Express standard switch (or switch network) 14 as the highest level without going through the root complex 13. Since data transfer between 21 to 27 is performed without passing through the route complex 13, high-speed processing is possible.

  4 and 5, the PCI Express standard serial bus 15 that connects the nodes (various devices / devices) 21 to 27 via the switch (or switch network) 14 has performance characteristics. Different ones (for example, the number of lanes indicating the bus width is x8, x4.x2, etc.) can be used, and the performance of each transfer path can be changed. However, in PCI Express, the average transfer rate between the nodes (various devices / devices) 21 to 27 via the switch (or switch network) 14 is the performance of the narrowest transfer path in the path (link width and number of lanes). Therefore, if there is one bottleneck, the effect cannot be obtained no matter how wide the other transfer paths are.

FIG. 17 is a connection example using an unnecessarily large number of lanes. Here, when there are a plurality of data transfer paths that operate simultaneously (data transfer) and one or more serial transfer paths that operate simultaneously are shared, data transfer 1 and data transfer 2 shown below are performed in parallel. Consider the case of processing.
Data transfer 1: Between endpoint 1 and root complex (memory) Data transfer 2: Between endpoint 2 and root complex (memory)

The transfer path in the data transfer 1 is as shown below.

Endpoint 1
↓ Link 1 (lane number x1)
Switch 1
↓ Link 5 (lane number x4)
Root complex

On the other hand, the transfer path in the data transfer 2 is as shown below.

Endpoint 2
↓ Link 2 (lane number x1)
Switch 1
↓ Link 5 (lane number x4)
Root complex

  Thus, when data transfer 1 and data transfer 2 are processed in parallel, both link 1 and link 2 have the number of lanes x1, so even if the link 5 portion operates simultaneously, the link 5 Although the number of lanes is x2, the number of lanes is x4, which increases the cost. Note that when the number of lanes of the link 5 is smaller than x2, the transfer rate decreases.

  Therefore, in the present embodiment, when connecting endpoints (each device / device) that processes a plurality of independent data transfers in parallel as described above, the link width of the upstream PCI Express standard serial bus 15 is connected. And the link width of the downstream PCI Express standard serial bus 15 is determined by the maximum data transfer amount.

FIG. 18 is a connection example using the optimum number of lanes. The transfer path in the data transfer 1 is as shown below.

Endpoint 1
↓ Link 1 (lane number x1)
Switch 1
↓ Link 5 (lane number x2)
Root complex

On the other hand, the transfer path in the data transfer 2 is as shown below.

Endpoint 2
↓ Link 2 (lane number x1)
Switch 1
↓ Link 5 (lane number x2)
Root complex

  When data transfer 1 and data transfer 2 are processed in parallel in this way, both link 1 and link 2 have the number of lanes x1, so when considering the simultaneous operation in the link 5 portion, the link The number of 5 lanes should be x2. That is, the number of lanes of the serial transfer path operating simultaneously is the number of lanes obtained by adding the smallest number of lanes in each data transfer path. When the number of lanes is smaller than x2, the transfer rate decreases, and when the number of lanes is larger than x2, the cost becomes high.

  As described above, according to the present embodiment, the number of lanes of the high-speed serial bus link forming the data transfer path from the switch to the node (switch or root complex) located on the upper side of the tree structure is changed from the end point to the switch. Transactions (data transfer) from multiple endpoints to one switch occur simultaneously by adding the number of lanes that satisfy the maximum value of each data transfer amount sent through each data transfer path leading to Even in such a case, the bottleneck due to the simultaneous operation can be eliminated, so the data that does not decrease the transfer rate even when multiple data transfers overlap without using the extra lane number. A transfer system can be provided.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, a case has been described in which endpoints (each device / device) that process a plurality of independent data transfers in parallel are connected. However, in this embodiment, data transfer occurs simultaneously. A case where endpoints (devices / devices) that are not connected are connected will be described.

  When endpoints (each device / device) that do not generate data transfer at the same time are connected, it is not necessary to consider the simultaneous operation. Therefore, the link width of the upstream PCI Express standard serial bus 15 and the downstream The link width of the serial bus 15 of the PCI Express standard may be determined by the maximum data transfer amount. That is, the number of all lanes on the data transfer path may be equalized with the maximum data transfer amount.

FIG. 19 is a connection example using the optimum number of lanes. The transfer path in the data transfer 1 is as shown below.

Endpoint 1
↓ Link 1 (lane number x1)
Switch 1
↓ Link 5 (lane number x1)
Root complex

On the other hand, the transfer path in the data transfer 2 is as shown below.

Endpoint 2
↓ Link 2 (lane number x1)
Switch 1
↓ Link 5 (lane number x1)
Root complex

  When endpoints (devices / devices) that do not generate data transfer at the same time are connected in this way, both link 1 and link 2 have the number of lanes x1, so the link 5 portion operates simultaneously. Therefore, the number of lanes in the link 5 may be set to x1.

  As described above, according to the present embodiment, a high-speed serial forming a data transfer path from each end point to a switch and a data transfer path from the switch to a node (switch or root complex) positioned on the upper side of the tree structure. By unifying the number of all lanes of the bus link to the number of lanes that satisfy the maximum value of the data transfer amount to be transmitted on the data transfer route, the lanes of all data transfer routes on the data transfer route related to one data transfer Cost performance can be optimized by aligning the numbers equally with the number of lanes at which the desired transfer rate is obtained.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. 1 is a block diagram showing an outline of connections of devices, devices, etc. of an image forming system to which a data transfer system according to a first embodiment of the present invention is applied. It is a schematic diagram which shows the example of a connection using an unnecessarily large number of lanes. It is a schematic diagram which shows the example of a connection using the optimal number of lanes. It is a schematic diagram which shows the example of a connection using the optimal number of lanes of the 2nd Embodiment of this invention.

Explanation of symbols

1 Data transfer system 15 High-speed serial bus 14 Switch 21-27 Endpoint

Claims (3)

As a data communication network with a tree structure, a point-to-point independent transmission / reception channel is established, and multiple endpoints are connected to one switch by using a high-speed serial bus that can select any number of lanes. In the data transfer system for transferring data from the respective endpoints to the switch,
The number of lanes of the link of the high-speed serial bus that forms a data transfer path from the switch to a node positioned on the upper side of the tree structure, and each data transmitted through each data transfer path from the endpoint to the switch The number of lanes that satisfy the maximum transfer amount is added to each lane.
A data transfer system characterized by that. A tree-structured data communication network establishes a point-to-point independent communication channel and uses a high-speed serial bus that can select any number of lanes to connect multiple endpoints to a single switch. In the data transfer system in which data transfer from each endpoint to the switch is not performed simultaneously,
The number of all lanes of the link of the high-speed serial bus that forms a data transfer path from each end point to the switch and a data transfer path from the switch to a node located on the upper side of the tree structure is determined by the data transfer. Unify routes to the number of lanes that meet the maximum amount of data transferred.
A data transfer system characterized by that. The high-speed serial bus is a PCI Express standard high-speed serial bus.
The data transfer system according to claim 1 or 2, characterized in that

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