JP2006092286A - Data transfer device and image forming system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit control of data transfer rate with high degree of flexibility and accuracy, in a data transfer device having an arbitration means for arbitrating priority regarding issuance of packet data for each virtual channel. <P>SOLUTION: The data transfer device is provided with an arbitration means 36 for arbitrating priority regarding issuance of packet data for each virtual channel defined by a standard, a payload size designation means 38 for arbitrarily designating the payload size of packet data to be issued for each virtual channel, and a packet generation means 32 for generating packet data of designated payload size for each virtual channel and outputting the packet data to the arbitration means 36. Thus, by designating the payload size of the packet data through a combination with the priority by the arbitration means 36 for acquiring a necessary data transfer rate, precise data transfer rate can be controlled with a higher degree of flexibility. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer apparatus and an image forming system using a serial bus.

  There is a data transfer apparatus having a virtual channel function for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels and an arbitration function for arbitrating the priority for issuing packet data for each virtual channel . According to the data transfer apparatus having such a mechanism, it is possible to adjust a transfer rate when packet data of a plurality of traffics having different data transfer priorities are to be transferred simultaneously using a serial bus.

  As an example, in the arbitration algorithm of a virtual channel (Virtual Channel) of a serial interface (for example, see Non-Patent Document 1), which is a PCI Express (registered trademark) equivalent to the successor standard of the PCI bus method, a round robin method, There are a weighted round robin method and a strict method, and it is possible to adjust the priority of packets transferred on the serial bus in units of transactions. Although these methods will be described later, the round robin method is a method in which packet data is issued at an equal frequency for each virtual channel VC, and the weighted round robin method can be arbitrarily designated for each virtual channel VC. The method of issuing packet data at a weighted frequency according to the table, the strict method is a method of issuing packet data in a fixed priority order for each virtual channel VC.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, according to the arbitration function of the virtual channel VC of the PCI Express standard, simply specifying the priority of the packet data issue frequency for each virtual channel VC has a low degree of freedom in priority control, and is high for packet data of multiple traffic. It is difficult to accurately control the data transfer rate.

  An object of the present invention is to enable high-precision data transfer rate control with a high degree of freedom in a data transfer apparatus having arbitration means for adjusting the priority of issuing packet data for each virtual channel.

  According to the first aspect of the present invention, virtual channel means for transmitting packet data of a plurality of traffic by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating priority for issuing packet data for each virtual channel A payload size specifying means for specifying the payload size of packet data to be issued for each virtual channel, and generating packet data having a payload size specified for each virtual channel to the arbitration means. Output packet generation means.

  According to a second aspect of the present invention, in the data transfer apparatus according to the first aspect, the algorithm of the arbitration means is a method for issuing packet data at an equal frequency for each virtual channel.

  According to a third aspect of the present invention, in the data transfer apparatus according to the first aspect, the algorithm of the arbitration means is a system for issuing packet data at a weighted frequency for each virtual channel.

  According to a fourth aspect of the present invention, in the data transfer device according to any one of the first to third aspects, the serial bus is a PCI Express standard serial bus.

  According to a fifth aspect of the present invention, in the data transfer device according to the second aspect, the serial bus is a PCI Express standard serial bus, and an algorithm for each virtual channel of the arbitration means is the PCI Express. It is a standard round robin.

  According to a sixth aspect of the present invention, in the data transfer device according to the third aspect, the serial bus is a PCI Express standard serial bus, and an algorithm for each virtual channel of the arbitration means is the PCI Express. It is a standard weighted round robin (Weighted Round Robin).

  An image forming system according to a seventh aspect of the present invention includes at least an image input engine, an image output engine, a controller that controls and drives the image input engine and the image output engine, these controllers, the image input engine, and An interface by a serial data transfer device according to any one of claims 1 to 6, which is connected to the image output engine.

  According to the present invention, in addition to the function of the arbitration means for arbitrating the priority for issuing packet data for each virtual channel specified by the standard, the payload size for specifying the payload size of the issued packet data for each virtual channel Since there is a specification means and a packet generation means for generating packet data of the payload size specified for each virtual channel and outputting it to the arbitration means, the required data transfer rate is obtained for the payload size of the packet data. By specifying in combination with the priority by the arbitration means, it is possible to control the data transfer rate with high accuracy with a higher degree of freedom.

    The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment conforms to PCI Express (registered trademark), which is one of high-speed serial buses. As a premise of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, the transaction layer 153, the data link layer 154, and the physical layer 155 are provided between the uppermost software layer 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled (arbitration means). VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Image forming system]
The data transfer apparatus according to the present embodiment is a high-speed image forming apparatus such as an image output apparatus such as a printer, an image input apparatus such as a scanner, and a digital copying machine having both of them and an image forming apparatus such as an MFP. It is used as a serial interface and conforms to the PCI Express standard as described above.

  An example of an image forming system to which the data transfer apparatus of this embodiment is applied will be described with reference to FIG. FIG. 15 is a block diagram showing an outline of connections of devices, devices, etc. of an image forming system to which the data transfer apparatus of this embodiment is applied. The image forming system 1 uses a PCI Express standard bus system for serial data transfer. That is, a CPU 11 that centrally controls each part of the image forming system 1 and a system memory 12 that is a work area of the CPU 11 are connected to a root complex 13 of the PCI Express standard. A root complex 13 and a PCI Express standard switch (or switch network) 14 are connected via a PCI Express standard general-purpose bus 15. The PCI Express standard switch (or switch network) 14 is connected to various devices and devices serving as PCI Express standard end points. That is, a hard disk (HDD) unit 21 for storing image data, an image memory unit 22 and a memory unit 23, an image processing unit 24 for performing various image processing, a high-speed network 25 for communicating with an external network, A scanner 26 as an input engine, a plotter 27 as an image output engine, an image input engine, another multifunction device 28 having an image output engine, and the like.

[Arbitration standard]
In such an image forming system, since the data transfer rate required for each device / device is different, a highly accurate transfer rate adjustment is required. As a standard for this purpose, priority is given to issuing packet data for each virtual channel VC by using virtual channel means for transmitting packet data of a plurality of traffic by using the serial bus as described above in a time division manner for each virtual channel VC. There is a function to arbitrate (arbitration means).

  FIG. 16 is a schematic block diagram showing a configuration example of a conventional serial transmission circuit (data transfer device) configured according to the arbitration function of the PCI Express standard. The illustrated example shows an example defined in a 4-channel configuration among a maximum of 8 virtual channels VC. The serial transmission circuit 31 receives data 1 to 4 for each channel from the device, and generates packet data 1 to 4 and virtual data for temporarily storing the generated packet data 1 to 4 for each virtual channel VC. The channel buffers (virtual channel means) 33a to 33d and the packet data 1 to 4 stored in the virtual channel buffers 33a to 33d are arbitrated according to the priority defined in advance for each virtual channel VC, and passed through the serial output buffer 34. And an arbitration circuit (arbitration means) 36 for outputting to the signal output circuit 35.

  The illustrated example illustrates the case of an arbitration algorithm for issuing packet data with equal frequency for each virtual channel VC. According to the arbitration, a packet is transmitted from the signal output circuit 35 of the serial transmission circuit 31 to the serial bus. Data 1 to 4 are output equally as shown.

  However, as described above, just by specifying the priority of the packet data issuance frequency for each virtual channel VC as in the arbitration of the virtual channel VC of the PCI Express standard, the degree of freedom of priority control is low, and multiple traffic It is difficult to control the data transfer rate with high accuracy for packet data.

[Data transfer device]
Therefore, in the serial transmission circuit (data transfer apparatus) of the present embodiment, paying attention to the payload size of packet data transmitted for each virtual channel VC, the payload size of the packet data to be issued can be arbitrarily designated for each virtual channel VC. Packet data having a payload size designated for each virtual channel VC is generated and output to the arbitration circuit 36.

  FIG. 17 is a schematic block diagram showing a configuration example of the serial transmission circuit (data transfer device) 37 of the present embodiment. The same parts as those shown in FIG. 16 are denoted by the same reference numerals, and description thereof is also omitted. In the serial transmission circuit 37 of the present embodiment, a payload size determination circuit (payload size designation means) 37 having a logic configuration for designating the payload size of packet data to be transmitted for each virtual channel VC with an arbitrary size is added. The packet generation circuit 32 is provided as packet generation means for generating packet data for each virtual channel VC according to the payload size specified by the payload size determination circuit 38 and outputting the packet data to the arbitration circuit 36. Here, “payload size” means the size of the data portion other than the header information in the size of the entire packet data. In the illustrated example, the payload size of the packet data 1 to 4 for each virtual channel VC is made different by the payload size determination circuit 38 as packet data 1> 2> 3> 4 as indicated by the difference in the square size. It shall be specified. Note that the payload size determination circuit 38 may be realized by program processing by the CPU.

  Therefore, according to the illustrated example, the serial bus output in the case of including adjustment by specifying the payload size of the packet data in addition to the arbitration algorithm with priority for issuing the packet data with equal frequency for each virtual channel VC An example is shown, and the data transfer rate is given so that the data transfer amount is given priority in the order of packet data 1> 2> 3> 4 from the signal output circuit 35 of the serial transmission circuit 37 to the serial bus. Is controlled and output.

  That is, by using a plurality of virtual channels VC in each link, a necessary data transfer rate can be obtained from an arbitration algorithm with priorities for each virtual channel VC and a payload size of packet data for each virtual channel VC. By specifying in combination, it is possible to control the transfer rate with high accuracy between each device / device.

  FIG. 18 is a block diagram showing a simple configuration example of the image forming system, and FIG. 19 is an explanatory diagram showing a state of transfer rate adjustment accompanying the payload size change. The effect of the present embodiment will be described with reference to a simple example shown in FIG. In FIG. 18, an MFP engine 43 (corresponding to the MFP 28 in FIG. 15) having a scanner 41 and a plotter 42 and a controller 44 are connected via a switch 14 by a single link 15 (high-speed serial bus). The MFP engine 43 and the controller 44 are physically connected to the different ports 0 and 1 of the switch 14 by one port A and B, respectively. It is necessary to adjust the packet data transfer rate. In this case, as described above, even if the round-robin (RR) that issues packet data with equal frequency is supported by the standard as an arbitration algorithm for the virtual channel VC, as described above, for example, from the scanner 41 By appropriately specifying the payload size of the packet data, which is the write data transmitted to the controller 44, the frequency at which the read request packet data transmitted from the plotter 42 to the controller 44 is issued can be finely adjusted.

  For example, FIG. 19A shows an example in which three read requests from the plotter 42 are issued when the payload size of the write data from the scanner 41 is increased, and FIG. When the payload size of the write data from is reduced, four read requests from the plotter 42 are issued. Accordingly, when it is desirable to make the read request arrive at the controller 44 as soon as possible, the payload per packet data of the write request from the scanner 41 even if the arbitration algorithm of the virtual channel VC is designated as round robin (RR). By specifying the size so that the size becomes smaller as shown in FIG. 19B, the transfer rate of the write data and the read request can be adjusted as desired.

  In the above description, the arbitration algorithm of the virtual channel VC has been described with the PCI Express standard round robin as an arbitration algorithm. However, the arbitration algorithm is weighted for each virtual channel. A method of issuing packet data at a frequency (weighted round robin if it is on the PCI Express standard), a method of issuing packet data with a fixed priority for each virtual channel (on the PCI Express standard) If there is, there is a strict. The arbitration algorithm of these virtual channels VC will be described.

  FIG. 20 is a characteristic diagram showing an example of basic characteristics of each method of these arbitration algorithms. In addition, since it is necessary to observe the dynamic fluctuation | variation for the measurement result of arbitration characteristics, it shows as a data integration figure in FIG. In the figure, the horizontal axis represents time, and the vertical axis represents the amount of transferred data (integrated value). Note that all four types of payload sizes are measurement examples fixed at 128 bytes (about 8000). FIG. 20 (a) shows a strict characteristic, which is an algorithm that simply flows data in order. FIG. 20B shows a round robin (RR) characteristic, which is an algorithm in which four types of data are flowed while being equally divided in order. In the drawing, the four types of characteristics are represented by overlapping one characteristic. ing. FIG. 20 (c) shows an example of characteristics when weighted round robin (WRR) characteristics are set so that data transfer is performed at a ratio of 1: 2: 4: 8 for four types. Data transfer of one traffic class Is completed, the data is transferred while changing the ratio of the remaining traffic class, such as 8: 4: 2 and further 8: 4.

  FIG. 21 shows the basic characteristics of the payload when measured with a strict algorithm. FIG. 21 shows an example in which the designation of the payload size of each traffic is changed in order from the left side, such as 8, 16, 32, and 64 Bytes. According to FIG. 21, paying attention to the inclinations of the four traffics, it can be seen that the smaller the payload size, the slower the transfer rate, and the larger the payload size, the larger the transfer rate. Such payload characteristics are the same when other arbitration algorithms are used. That is, it can be seen that the traffic adjustment can be performed more finely by combining the setting of the arbitration algorithm of the virtual channel VC and the designation of the payload size.

  FIG. 22 is a characteristic diagram for explaining the interaction between the payload size and the arbitration algorithm of the virtual channel VC. As described above, since the transfer rate changes depending on the combination of the payload size and the arbitration algorithm of the virtual channel VC, they affect each other. The influence will be described with reference to a typical example shown in FIG.

  FIG. 22A shows a case where the arbitration algorithm is round robin (RR) and the payload size is fixed to 8 bytes. FIG. 22B shows the arbitration algorithm is round robin (RR) and the payload sizes are in order. FIG. 22 (c) shows a weighted round robin (WRR) weighted with an arbitration algorithm of 1: 2: 4: 8. This shows a case where the payload size is specified non-uniformly in order, such as 8, 16, 32, and 64 bytes.

  First, FIG. 22 (a) and FIG. 22 (b) show an example in which only the payload size of the traffic allocated to the four virtual channels VC is different, but there is a great difference in the characteristics. In particular, in the setting example shown in FIG. 22B, although the arbitration algorithm is round robin (RR), the weighted round robin (WRR) which is an arbitration algorithm when the payload size of each traffic is the same is used. It becomes equivalent to the characteristic of the case.

  Further, FIG. 22B and FIG. 22C show an example in which only the arbitration algorithm is different, but the characteristics are clearly different in each 8 kB data transfer section.

  Contrary to the above case, the parameter settings are completely different, but may have similar characteristics. FIG. 22A and FIG. 22C show examples in which the payload size and the arbitration algorithm are different. In other words, all the settings are separate, but the slopes of the four traffics are almost equal (although in the example shown in FIG. 22 (c), a header overhead difference occurs).

  As described above, there are a plurality of designation methods for obtaining a target average transfer rate. By effectively utilizing this degree of freedom of selection, even if there are other structural design constraints (for example, buffer size, number of tag stages, etc.), target traffic control can be performed. In order to change the arbitration algorithm setting of the virtual channel VC, it is necessary to change the arbitration table of the virtual channel VC with config write. However, according to the change of payload size designation, it depends on how the user logic is created. Fast change is possible. As a result, for example, dynamic change in the average rate can be handled by changing the payload size that can be handled at high speed, and change in the static average rate can be done by changing the arbitration algorithm of the virtual channel VC. It becomes possible.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. 1 is a block diagram schematically showing a configuration example of an image forming system of an embodiment. It is a schematic block diagram which shows the structural example of the conventional serial transmission circuit comprised according to the arbitration function of the PCI Express specification. It is a schematic block diagram which shows the structural example of the serial transmission circuit of this Embodiment. 1 is a block diagram illustrating a simple configuration example of an image forming system. It is explanatory drawing which shows the mode of the transfer rate adjustment accompanying a payload size change. It is a characteristic view which shows the example of a basic characteristic of each system of the algorithm of arbitration. It is a basic characteristic diagram of a payload when measured by a strict algorithm. It is a characteristic view for demonstrating interaction with a payload size and the arbitration algorithm of virtual channel VC.

Explanation of symbols

32 packet generation means 33a to 33d virtual channel means 36 arbitration means 38 payload size designation means 41 image input means 42 image output means 44 controller

Claims (7)

In a data transfer apparatus having virtual channel means for transmitting packet data of a plurality of traffics by using a serial bus in a time division manner in units of virtual channels, and arbitration means for arbitrating the priority for issuing packet data for each virtual channel,
Payload size specifying means for specifying the payload size of the packet data to be issued for each virtual channel;
Packet generating means for generating packet data of a payload size designated for each virtual channel and outputting the packet data to the arbitration means;
A data transfer device comprising:   2. The data transfer apparatus according to claim 1, wherein the algorithm of the arbitration means is a method of issuing packet data at an equal frequency for each virtual channel.   2. The data transfer apparatus according to claim 1, wherein the algorithm of the arbitration means is a method of issuing packet data at a weighted frequency for each virtual channel.   4. The data transfer device according to claim 1, wherein the serial bus is a PCI Express standard serial bus.   The serial bus is a PCI Express standard serial bus, and an algorithm for each virtual channel of the arbitration means is the PCI Express standard round robin. 2. The data transfer device according to 2.   The serial bus is a PCI Express standard serial bus, and the algorithm for each virtual channel of the arbitration means is a weighted round robin of the PCI Express standard. The data transfer device according to claim 3. And at least an image input engine, an image output engine, a controller for controlling and driving the image input engine and the image output engine, and the controller, the image input engine, and the image output engine. An image forming system comprising: an interface by the serial data transfer device according to any one of 1 to 6.

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