JP2007200042A - Circuit designing method and circuit designing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set the margin of a power source change path connecting the separated regions of a power source under the consideration of the influence of a power source noise for every region, neither too much nor too little. <P>SOLUTION: The fluctuation width of a voltage is estimated for each of a transmission side region and a reception side region obtained by separating a power source (step S1). Delay coefficients for timing verification are obtained for each of the transmission side region and the reception side region based on the fluctuating width of the voltage (step S2). A power source change path connecting the transmission side region to the reception side region is extracted (step S3). A cell connected to the power source change path in the transmission side region is multiplied by the delay coefficients of the transmission side region, and the cell connected to the power source change path is multiplied by the delay coefficients of the reception side region in the reception side region so that a script for timing verification of the power source change path can be generated (step S4). Thus, it is possible to perform timing verification by an STA tool by using the script (step S5). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a circuit design method and a circuit design program for performing a design in which a semiconductor integrated circuit is divided into a plurality of regions and a power source is separated for each region.

  In general, a semiconductor integrated circuit is designed in consideration of power supply noise in a chip at the design stage so that the noise does not become excessive. Then, for each cell arranged on the chip, a voltage applied to the cell is obtained in consideration of IR drop, and timing verification is performed using a delay coefficient calculated from the voltage. As a method for obtaining the delay value corresponding to the delay coefficient, the fluctuation rate with respect to the delay value in the standard state is obtained based on the distance from the power bump to the cell and the voltage applied to the power bump, and the delay value in the standard state and its A method for obtaining a delay value in consideration of a voltage estimated to be actually applied to a cell based on a variation rate is known (see, for example, Patent Document 1).

JP 2003-271696 A

  In the case of a design in which the semiconductor integrated circuit is divided into a plurality of regions and the power supply is separated for each region, even if the power supply is separated by the same voltage, the voltage differs in each region due to the influence of IR drop, resonance noise, etc. There is. For example, the voltage may increase in one region due to power supply noise, and the voltage may decrease in the other region. If the voltage difference between the two regions is larger than the normally considered on-chip variation (OCV), an error may occur due to insufficient timing margin. Conversely, if the voltage difference between the two regions is smaller than the normally considered OCV, an excess timing margin is guaranteed.

  Generally, when performing timing verification, a static timing analysis tool (hereinafter referred to as STA tool) or a logic simulator is used. These tools do not take into account the effects of noise between regions where the power supplies are separated. The method disclosed in the above patent document is the same. A power supply transfer path that connects different regions where power is separated is designed to have a sufficient timing margin, but it is difficult to design with sufficient margin in all paths.

  In order to eliminate the above-described problems caused by the conventional technology, the present invention considers the influence of power supply noise for each region where the power is separated in a design in which the power is separated for each of a plurality of regions in the semiconductor integrated circuit. An object of the present invention is to provide a circuit design method capable of setting a margin of a power supply transfer path connecting between the regions without excess or deficiency, and a circuit design program for causing a computer to execute the circuit design method.

  In order to solve the above-described problems and achieve the object, the present invention has the following features. Of the plurality of regions divided in the semiconductor integrated circuit, the fluctuation range of the voltage is estimated for each of the transmission side region and the reception side region. Based on the estimated voltage fluctuation range on the transmitting side, a delay coefficient for timing verification for the transmitting side region is obtained. Similarly, for the reception side area, a delay coefficient for timing verification is obtained based on the estimated fluctuation range of the voltage on the reception side.

  Also, a power supply transfer path connecting the transmission side area and the reception side area is extracted. In the transmission side area, the delay coefficient of the transmission side area is applied to the cells connected to the power transfer path. Similarly, for the reception side area, the delay coefficient of the reception side area is applied to the cells connected to the power supply transfer path. In this way, a script for performing the timing verification of the power transfer path is generated, and the timing verification is performed by using, for example, the STA tool. Alternatively, the timing verification of the power transfer path may be performed directly by the STA tool without generating a script.

  Further, the cells connected to both ends of the power supply transfer path may be constituted by flip-flop circuits. In this case, the delay fluctuation of the flip-flop circuit in the transmission side area is obtained based on the fluctuation width of the voltage on the transmission side, and the hold of the flip-flop circuit in the reception side area is calculated based on the fluctuation width of the voltage on the reception side. Find the margin variation. Then, the variation in delay on the transmission side and the variation in hold margin on the reception side are added to the hold margin considered in the timing analysis.

  In addition, when using a flip-flop circuit as a cell connected to both ends of the power transfer path, the maximum voltage fluctuation range is determined in advance for each of the transmission side area and the reception side area, and the voltage fluctuation range on the transmission side is determined. A flip-flop circuit is prepared that has a hold margin to which the fluctuation amount of the delay on the transmission side when is the maximum and the fluctuation amount of the hold margin on the reception side when the fluctuation range of the voltage on the reception side is the maximum. Then, the flip-flop circuit to which the hold margin is added may be pre-libraryed as a reception-side flip-flop circuit.

  Further, a flip-flop circuit may be used as the power source transfer path. In this case, the latch in the previous stage of the flip-flop circuit is arranged in the transmission area, and the power in the transmission area is supplied to the latch in the previous stage. In addition, a latch at the rear stage of the flip-flop circuit is arranged in the reception side area, and power of the reception side area is supplied to the latch at the rear stage. The margin between the latches at the preceding stage and the latter stage of this flip-flop circuit is a margin for estimating the change in delay caused by the voltage fluctuation width of the transmission side area and the voltage fluctuation width of the reception side area.

  Alternatively, among the transistors constituting the latch at the subsequent stage of the flip-flop circuit, the threshold value of the high-side transistor takes into account the fluctuation range of the voltage at the transmitting side of the transistor constituting the latch at the preceding stage of the flip-flop circuit. Make it lower than the voltage. Such a flip-flop circuit is made into a library as a power transfer cell, and circuit design is performed using this library. In any of the above-described methods, as a result of estimating the fluctuation range of the voltage in each of the transmission-side area and the reception-side area, the voltage difference between the transmission-side area and the reception-side area cannot be transmitted / received through the power transfer path. If so, redesign.

  Further, at the time of circuit design, an allowable range is determined in advance for each of the voltage fluctuation range of the transmission side region and the voltage fluctuation range of the reception side region. At the time of timing verification, timing verification may be performed using the maximum voltage fluctuation range. According to the present invention, the timing verification can be performed on the power supply switching path connecting the transmission side area and the reception side area in consideration of the voltage fluctuation range of the transmission side area and the voltage fluctuation range of the reception side area. it can.

  According to the circuit design method and the circuit design program according to the present invention, when performing the design for separating the power supply for each of the plurality of regions in the semiconductor integrated circuit, the timing verification can be performed on the power supply transfer path. There is an effect that it is possible to set the margin of the power supply transfer path connecting between the regions in consideration of the influence of the power source noise for each region where the power source is separated.

  Exemplary embodiments of a circuit design method and a circuit design program according to the present invention will be explained below in detail with reference to the accompanying drawings. In the first to fourth embodiments, for example, the power transfer path connecting the transmission side area and the reception side area is a path from the flip-flop circuit arranged in the transmission side area to the flip-flop circuit arranged in the reception side area. Suppose there is. In this case, the transmission-side flip-flop circuit belongs to the transmission-side area, and the reception-side flip-flop circuit belongs to the reception-side area. Further, in the fifth and sixth embodiments, it is assumed that the power supply transfer path is configured by a flip-flop circuit, and the preceding stage latch of this flip-flop circuit belongs to the transmission side area and the latter stage latch belongs to the reception side area.

(Embodiment 1)
FIG. 1 is a flowchart showing a circuit design method according to the first exemplary embodiment of the present invention. As shown in FIG. 1, wiring capacity information 1, circuit scale information 2, operating frequency information 3, and other necessary information 4 such as transistor characteristics are read, and the transmission side region and the reception connected to each other via the power supply transfer path For each of the side regions, power supply noise is estimated, and a voltage fluctuation range (noise voltage) ΔPower is obtained (step S1). For example, when the reference voltage of the transmission side region and the reception side region is 1.2 V, the voltage fluctuation range ΔPower1 of the transmission side region is 0.05 V, and the voltage fluctuation range ΔPower2 of the reception side region is 0.1 V. It is requested as follows.

  Next, the STA delay coefficient ΔDelay is calculated based on the noise voltage information 5 of the transmission side area and the reception side area obtained in step S1 (step S2). Each voltage of the transmission side region and the reception side region may swing in a rising direction or a decreasing direction due to power supply noise. Therefore, in step S2, the delay coefficient ΔDelay when the voltage rises and falls is obtained.

  For example, as in the example described above, when the voltage fluctuation range ΔPower1 of the transmission side region is 0.05V, the delay coefficient ΔDelay1 of the transmission side region obtained from [Power1 + ΔPower1] is 0.95 times. However, Power1 is a reference voltage (for example, 1.2 V) in the transmission side region. The delay coefficient ΔDelay1 obtained from [Power1−ΔPower1] is 1.06 times.

  Similarly, when the fluctuation range ΔPower2 of the voltage in the receiving side region is 0.1V, the delay coefficient ΔDelay2 in the receiving side region obtained from [Power2 + ΔPower2] is 0.90 times. However, Power2 is the reference voltage (for example, 1.2V) of the receiving side area. Further, the delay coefficient ΔDelay2 obtained from [Power2−ΔPower2] is 1.15 times.

  Note that the delay coefficient can also be obtained including the IR drop. In this case, the delay coefficient is obtained based on [Power−ΔPower_IRD ± ΔPower] obtained by adding or subtracting the voltage fluctuation range ΔPower to the value obtained by subtracting the IR drop voltage ΔPower_IRD from the reference voltage Power. In this way, STA delay coefficient information 6 is obtained in step S2.

  On the other hand, the logic circuit information 7 and the power supply circuit information 8 are read, and the power supply transfer path is extracted (step S3). Based on the obtained power transfer path information 9, among the cells connected to both ends of the power transfer path, the cells belonging to the transmission side area are multiplied by the delay coefficient ΔDelay 1, and the cells belonging to the reception side area are delayed. By applying the coefficient ΔDelay2, a STA script for performing timing verification is created (step S4).

  Then, the generated STA script is output. Up to this point, the STA script creation program is executed by the computer. The STA tool is executed using the output STA script information 10, and the timing of the power transfer path is verified (step S5). By doing as described above, it is possible to perform the timing verification for only the power supply transfer path. Accordingly, a margin can be set for the power supply transfer path in consideration of a necessary and sufficient amount of noise.

(Embodiment 2)
FIG. 2 is a flowchart showing a circuit design method according to the second exemplary embodiment of the present invention. As shown in FIG. 2, in the second embodiment, the STA tool does not create a script for the STA, and the timing verification of the power supply switching path is performed in the STA tool in consideration of the delay factors of the transmission side area and the reception side area. It is.

  The wiring capacity information 1, circuit scale information 2, operating frequency information 3, logic circuit information 7, power supply circuit information 8 and the like are read into the STA tool. Then, for each of the transmission side area and the reception side area, the power supply noise is estimated for each of the transmission side area and the reception side area by using the STA tool to obtain voltage fluctuation ranges ΔPower1 and ΔPower2 (step S1), and the STA delay coefficient ΔDelay1. , ΔDelay2 is calculated (step S2).

  On the other hand, the power supply transfer path is extracted by the STA tool. The timing of the power transfer path is obtained by multiplying the cell in the transmission side area by the delay coefficient ΔDelay1 of the transmission side area and multiplying the cell in the reception side area by the delay coefficient ΔDelay2 of the reception side area connected to the power transfer path. Verification is performed (step S5). As described above, since the timing verification can be performed directly on the power transfer path only by the STA tool, the necessary and sufficient noise amount is taken into consideration for the power transfer path as in the first embodiment. Margins can be set.

(Embodiment 3)
FIG. 3 is a flowchart showing a circuit design method according to the third exemplary embodiment of the present invention. As shown in FIG. 3, in the third embodiment, the delay variation is treated as a hold margin of the flip-flop circuit connected to the power supply switching path, and the timing of the power supply switching path is verified. No cell is arranged between the flip-flop circuit in the transmission side region and the flip-flop circuit in the reception side region connected to the power supply transfer path.

  The wiring capacity information 1, the circuit scale information 2, the operating frequency information 3, the logic circuit information 7, the power supply circuit information 8 and the like are read into the STA tool, and each of the transmitting side area and the receiving side area is read by the STA tool according to the first embodiment. In the same manner as described above, power supply noise is estimated, and voltage fluctuation ranges ΔPower1 and ΔPower2 are obtained (step S1). Next, a margin to be added to the hold margin of the flip-flop circuit connected to the power supply transfer path is calculated based on the noise voltage information 5 of the transmission side region and the reception side region obtained in step S1 (step S6).

  At this time, the case where the delay value becomes small is considered in the flip-flop circuit in the transmission side region, and the case where the hold margin becomes large in the flip-flop circuit in the reception side region is considered. A change [Cell_Delay1−Cell_Delay1 · ΔDelay1] of the delay value on the transmission side obtained from the delay Cell_Delay1 of the cell on the transmission side and [Power1 + ΔPower1] is estimated. Also, a change [Hold_Margin2 · ΔDelay2−Hold_Margin2] of the hold margin on the receiving side obtained from the hold margin Hold_Margin2 and [Power2−ΔPower2] of the cell on the receiving side is estimated.

  Then, the delay value change [Cell_Delay1−Cell_Delay1 · ΔDelay1] on the transmission side and the hold margin change [Hold_Margin2 · ΔDelay2−Hold_Margin2] on the reception side are combined and added to the hold margin considered by the STA. Timing verification is performed using the setup / hold margin information 11 obtained by this calculation as the setup / hold margin of the flip-flop circuit (step S5). In this way, the setup and hold margin of the flip-flop circuit is set in consideration of the case where the delay value is reduced on the transmitting side and the hold margin is increased on the receiving side. Even in such a case, it is possible to secure a margin that has no influence.

  As in the first embodiment, the STA script creation program creates and outputs the STA script using the setup / hold margin information 11 obtained in step S6, and gives the script to the STA tool. It may be. A buffer may be inserted between the flip-flop circuit on the transmission side and the flip-flop circuit on the reception side. In that case, in step S6, a margin including the inserted buffer is calculated.

(Embodiment 4)
FIG. 4 is a flowchart showing a circuit design method according to the fourth embodiment of the present invention. As shown in FIG. 4, the fourth embodiment performs timing verification by uniformly defining the delay variation to the hold margin of the flip-flop circuit connected to the power supply transfer path. No cell is arranged between the flip-flop circuit of the transmission side circuit and the flip-flop circuit of the reception side circuit connected to the power supply transfer path.

  The maximum amount of noise allowed in each of the transmission side area and the reception side area when the chip is designed is determined in advance. Then, in the same manner as in the third embodiment, a change in the hold margin of the flip-flop circuit when the noise becomes maximum in each of the transmission side region and the reception side region is obtained. A dedicated cell is prepared as a flip-flop circuit of the receiving side circuit, and this cell is made into a library and used as dedicated timing library information 12. A hold margin when noise becomes maximum is added to this dedicated cell.

  The wiring capacity information 1, circuit scale information 2, and operating frequency information 3 are read into the STA tool, and the STA tool estimates the power supply noise for each of the transmission side area and the reception side area in the same manner as in the first embodiment. Voltage fluctuation ranges ΔPower1 and ΔPower2 are obtained (step S1). The amount of noise is determined based on the obtained noise voltage information 5, and the noise voltages in the transmission side region and the reception side region obtained in step S1 are the noises allowed in the transmission side region and the reception side region, respectively. It is determined whether or not the maximum value is exceeded (step S7). When both the noise in the transmission side area and the noise in the reception side area do not exceed the maximum noise value (step S7: OK), the timing verification is performed using the dedicated timing library information 12 (step S5).

  If at least one of the noise in the transmission side area and the noise in the reception side area exceeds the maximum noise value (step S7: NG), redesign is performed so as not to exceed (step S8). In this way, a flip-flop circuit to which a hold margin is added when the noise is maximized in each of the transmission side area and the reception side area is prepared as a dedicated flip-flop circuit of the reception side circuit. By performing the timing design using the cell, it is possible to consider the timing variation when noise occurs by applying it only to the power supply transfer path. Further, since the redesign is performed when the noise exceeds a preset maximum value, the noise can be suppressed to a range that does not affect the noise.

(Embodiment 5)
FIG. 5 is a circuit diagram showing an example of a power supply transfer path dedicated cell used in the circuit design method according to the fifth embodiment of the present invention. As shown in FIG. 5, the fifth embodiment uses a flip-flop circuit 21 with a countermeasure against timing violation as a dedicated cell constituting a power supply switching path when designing a chip. The flip-flop circuit 21 includes a front-stage latch 22 and a rear-stage latch 23. The preceding-stage latch 22 is arranged in the transmission side area and is supplied with power from the transmission side area. The latter-stage latch 23 is arranged in the reception side area and is supplied with power from the reception side area. Although a D type flip-flop circuit is shown in FIG. 5, it is not limited to the D type.

  FIG. 6 is a flowchart showing a procedure for creating a power transfer path dedicated cell in the fifth embodiment of the present invention. As shown in FIG. 6, first, a flip-flop circuit 21 in which the power of the transmission side region is supplied to the cell in which power is separated in the cell, that is, the latch 22 at the previous stage and the power of the reception side region is supplied to the latch 23 at the subsequent stage. Is formed (step S9). Then, timing adjustment of the created cell is performed (step S10). On the other hand, the maximum amount of noise allowed in each of the transmission side area and the reception side area is determined in advance. The maximum potential difference is defined from the maximum value of the allowable power supply noise and the voltage effect assumed in the transmission side region and the reception side region (between the power supply regions) (step S11).

  Then, timing verification is performed based on the cell information 13 obtained in step S10, the maximum potential difference information 14 defined in step S11, and the normally considered variation information 15 (step S12). As a result of the verification, if no timing violation occurs even when the difference between the voltage in the transmission side region and the voltage in the reception side region is the maximum (step S12: OK), a cell library is created (step S13).

  On the other hand, if a timing violation occurs (step S12: NG), the timing adjustment in step S10 and the timing verification in step S12 are repeated until the timing violation does not occur. When performing timing adjustment, the clock skew is increased between the preceding stage and the subsequent stage or the data delay from the preceding stage to the subsequent stage is increased so that a hold error does not occur between the preceding stage latch 22 and the subsequent stage latch 23. .

  FIG. 7 is a flowchart showing a procedure for using the power transfer path dedicated cell according to the fifth embodiment of the present invention. As shown in FIG. 7, based on the netlist information or RTL (register transfer level) information 16 of the logic circuit and the power supply circuit information 8, a normal one power supply cell is converted in the cell by a replacement script or logic synthesis CAD. The cell is separated from the power source, that is, the flip-flop circuit 21 in which the power supply in the transmission side region is supplied to the latch 22 in the previous stage and the power supply in the reception side region is supplied to the latch 23 in the subsequent stage (step S14).

  As a result, the logic circuit information 7 using the flip-flop circuit 21 driven by the two power sources as the power transfer path dedicated cell described above is obtained. It should be noted that when the chip is designed, the predetermined maximum noise value is not exceeded in each of the transmission side area and the reception side area. In this way, by using the power transfer path dedicated cell to which the countermeasure for timing violation is taken, it is possible to prevent the timing violation from occurring in the power transfer path.

(Embodiment 6)
Problems that may occur due to power supply noise include malfunction due to voltage level in addition to malfunction due to timing violation. FIG. 8 is a schematic diagram illustrating a voltage level for explaining a malfunction due to the voltage level, and the vertical axis represents the voltage. As shown in the schematic diagram 80 in the normal state on the left side of FIG. 8, if the output voltage VOH of the transmission side transistor (transmission Tr.) Is higher than the threshold value VthH of the reception side high transistor (reception Tr.), The reception side Does not cause malfunction.

  However, as shown in the schematic diagram 81 of the malfunction state on the right side of FIG. 8, when the voltage on the transmission side decreases and the voltage on the reception side rises due to the influence of power supply noise, the output voltage VOH of the transmission side transistor becomes high on the reception side. It may be lower than the threshold value VthH of the side transistor. In such a case, a malfunction occurs on the receiving side. When the receiving side is constituted by a CMOS transistor, the output of the CMOS transistor becomes indefinite and a large through current flows between the power supply and the ground or the CMOS transistor does not operate.

  Therefore, in the sixth embodiment, when designing a chip, a flip-flop circuit with a signal transfer countermeasure is used as a dedicated cell constituting a power supply transfer path. In this flip-flop circuit, of the transistors constituting the preceding latch, the part of the transistor connected to the latter latch is called the transmitting side transistor, and among the transistors constituting the latter latch, it is connected to the preceding latch. This part of the transistor is called a receiving transistor.

  The configuration of the flip-flop circuit and the supply of power are the same as those of the flip-flop circuit constituting the power transfer path dedicated cell of the fifth embodiment. However, in the flip-flop circuit according to the sixth embodiment, a margin is ensured so as not to cause a timing violation (fifth embodiment). Instead, as shown in FIG. Even when the absolute value of the threshold value VthH of the transistor is low and the output voltage VOH of the transmission side transistor is low, a transistor satisfying [VOH> VthH] is used.

  FIG. 9 is a schematic diagram showing the voltage level of the power transfer path dedicated cell used in the circuit design method according to the sixth embodiment of the present invention. It is a schematic diagram explaining that it operates normally even if there is a fluctuation in voltage level, and the vertical axis represents voltage. In FIG. 9, the left diagram is a schematic diagram 90 in a state where there is no voltage level variation, and the right diagram is a schematic diagram 91 in a state where the voltage level varies. In this way, even when the voltage fluctuates in one or both of the transmission side region and the reception side region, a signal is received on the reception side without malfunction by using a transistor having [VOH> VthH] on the reception side. Can do.

  FIG. 10 is a flowchart showing a procedure for creating a power transfer path dedicated cell in the sixth embodiment of the present invention. As shown in FIG. 10, first, a cell in which power is separated in the cell, that is, a flip-flop circuit in which the power in the transmission side region is supplied to the latch in the previous stage and the power in the reception side region is supplied to the latch in the subsequent stage is created. (Step S9). Then, the transistor (Tr.) Constituting the created flip-flop circuit is selected from the previously prepared transistor group or created (step S15). On the other hand, the maximum amount of noise allowed in each of the transmission side area and the reception side area is determined in advance, and the maximum allowable power supply noise value and the transmission side area and the reception side area (between the power supply areas) are assumed. The maximum potential difference is defined based on the voltage effect (step S11).

  Then, based on the cell information 13 obtained in step S15, the maximum potential difference information 14 defined in step S11, and the normally considered variation information 15, the output value and the power supply leak value are verified (step S16). As a result of the verification, if there is no problem in either the output value or the power supply leak value (step S16: OK), a cell library is created (step S13). On the other hand, if there is a problem with at least one of the output value and the power supply leak value (step S16: NG), the selection or creation of the transistor at step S15 and the output value and the power supply leak value at step S16 until the problem disappears. Repeat the verification. The procedure for using the power transfer path dedicated cell is as described in the fifth embodiment, and the flowchart is as shown in FIG.

  Note that the flip-flop circuit that is used as a power transfer path dedicated cell and has a signal transfer measure is not limited to the above-described configuration. Here, another configuration of the flip-flop circuit in which signal transfer countermeasures are taken will be described. FIG. 11 is a circuit diagram showing an example of a power supply transfer path dedicated cell used in the circuit design method according to the sixth embodiment of the present invention. As shown in FIG. 11, a flip-flop circuit configured to apply the power supply voltage VDD1 of the transmission-side transistor to the back bias Vbsp2 of the high-side transistor pMOS2 of the reception-side transistors may be used. Note that FIG. 11 shows only a connection portion between the transmission side transistor and the reception side transistor of the flip-flop circuit.

  In FIG. 11, pMOS1 and nMOS1 are the high-side and low-side transistors of the transmission-side transistor, respectively, and nMOS2 is the low-side transistor of the reception-side transistor. VDD2 is the power supply voltage of the receiving transistor, and VSS is the ground. Vbsp1 is the back bias of the high-side transistor pMOS1 of the transmission side transistors, and Vbsn is the back bias of the low-side transistor nMOS1 on the transmission side and the low-side transistor nMOS2 on the reception side.

  Among the receiving side transistors, regarding the high side transistor pMOS2, when the power supply voltage VDD1 of the transmitting side transistor is applied to the back bias, the change in threshold value is ΔPower1_B, and the threshold value is VthH. When the transmission side voltage VDD1 rises, the absolute value of the threshold value of the reception side transistor rises to [VthH + ΔPower1_B]. On the other hand, when the transmission-side voltage VDD1 decreases, the absolute value of the threshold value of the reception-side transistor decreases to [VthH−ΔPower1_B]. Assuming that the output voltage of the transmission side transistor is VOH and the fluctuation range of the transmission side voltage VDD1 is ΔPower1, a signal is received on the reception side without malfunctioning by satisfying the relationship [VOH ± ΔPower1> VthH ± ΔPower1_B]. be able to.

(Embodiment 7)
FIG. 12 is a flowchart showing a circuit design method according to the seventh embodiment of the present invention. As shown in FIG. 12, the seventh embodiment is a method of redesigning when the voltage difference becomes so large that a signal cannot be passed through the power transfer path, and the first, second, third, fifth, or 6 is applicable.

  The power supply voltage of the reception side transistor in which the reception side transistor malfunctions is obtained in advance with respect to the output voltage of the transmission side transistor when the power supply voltage of the transmission side transistor changes due to noise in the power supply transfer path. Then, when designing the chip, the power supply noise is estimated in the same manner as in the first embodiment for each of the transmission side area and the reception side area based on the wiring capacity information 1, the circuit scale information 2, the operating frequency information 3, and the like. Then, voltage fluctuation ranges ΔPower1 and ΔPower2 are obtained (step S1).

  The amount of noise is determined based on the obtained noise voltage information 5, and the noise voltages in the transmission side region and the reception side region obtained in step S1 are the noises allowed in the transmission side region and the reception side region, respectively. It is determined whether it is less than the maximum value and smaller than the amount of noise that causes the receiving side transistor to malfunction (step S17). If both the noise in the transmission side area and the noise in the reception side area are equal to or less than the maximum noise value and smaller than the noise amount at which the reception side transistor malfunctions (step S17: OK), the design is continued (step S17). S18).

  If at least one of the noise in the transmission side area and the noise in the reception side area exceeds the maximum value of noise, or more than the noise amount at which the reception side transistor malfunctions (step S17: NG), redesign is performed. (Step S8). Assuming that ΔPower1 and ΔPower2 are the fluctuation ranges of the voltages on the transmission side and the reception side, the amount of noise at which the reception-side transistor does not malfunction is defined as [ΔPower1 <x1] and [ΔPower2 <x2] on the transmission side and the reception side. It may be expressed as a separate function.

  Alternatively, the amount of noise that does not cause the reception side transistor to malfunction may be expressed as one function, such as [ΔPower1 + ΔPower2 <x3]. However, x1, x2, and x3 are obtained in advance from cell characteristics simulation or actual measurement. By doing so, a signal can be received on the receiving side without malfunction. Further, by performing the redesign, the noise can be suppressed to a range where there is no influence.

(Embodiment 8)
FIG. 13 is a flowchart showing a circuit design method according to the eighth embodiment of the present invention. As shown in FIG. 13, in the eighth embodiment, the upper limit of noise is determined for each of the transmission side region and the reception side region, and the timing verification is performed by applying a delay coefficient uniformly from the upper limit of the noise. It is applicable to the form 1 or 2.

  Similarly to the seventh embodiment, the amount of noise that does not malfunction is defined in advance as [ΔPower1 <x1] and [ΔPower2 <x2]. Then, based on the wiring capacity information 1, the circuit scale information 2, the operating frequency information 3, etc., the power supply noise is estimated for each of the transmission side region and the reception side region in the same manner as in the first embodiment, and the voltage fluctuation range ΔPower1 and ΔPower2 are obtained (step S1).

  The amount of noise is determined based on the obtained noise voltage information 5, and the noise voltages in the transmission side area and the reception side area obtained in step S1 are the noises allowed in the transmission side area and the reception side area, respectively. It is determined whether it is below the maximum value and below the amount of noise that does not malfunction (step S19). When both the noise in the transmission side area and the noise in the reception side area are less than the maximum value of noise and less than the noise amount that does not malfunction (step S19: OK), [ΔPower1 = x1] and [ΔPower2 = x2 ], The STA delay coefficient ΔDelay is calculated (step S2).

  Thereafter, the processing after step S4 in FIG. 1, that is, the STA script may be output and the STA may be executed. If processing is performed in the STA tool from the beginning, the processing in FIG. The process of step S5 is performed. On the other hand, when at least one of the noise in the transmission side area and the noise in the reception side area exceeds the maximum value of noise or exceeds the amount of noise that does not malfunction (step S19: NG), redesign is performed (step S19: NG). Step S8). In this way, the timing can be satisfied with a voltage amplitude that does not malfunction.

  The circuit design method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Appendix 1) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates the power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
A coefficient calculation step for obtaining a delay coefficient for timing verification based on the fluctuation range of the voltage estimated in the estimation step for each of the transmission side region and the reception side region;
A path extraction step of extracting a power supply transfer path connecting the transmission side area and the reception side area;
For the cell connected to the power transfer path extracted in the path extraction step in the transmission side region, the delay factor of the transmission side region calculated in the coefficient calculation step is applied, and in the reception side region, A script generation step of generating a script for performing timing verification of the power transfer path by multiplying a cell connected to the power transfer path by the delay coefficient of the receiving side area calculated in the coefficient calculation step When,
A circuit design method comprising:

(Appendix 2) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates a power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
A coefficient calculation step for obtaining a delay coefficient for timing verification based on the fluctuation range of the voltage estimated in the estimation step for each of the transmission side region and the reception side region;
A power supply transfer path connecting the transmission side area and the reception side area is extracted, and the cell of the transmission side area is connected to the power supply transfer path. The timing of the power transfer path is determined by applying a delay coefficient and multiplying the cell connected to the power transfer path in the receiving area by the delay coefficient of the receiving area calculated in the coefficient calculating step. A verification process for performing the verification;
A circuit design method comprising:

(Appendix 3) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates a power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
The delay of the flip-flop circuit connected to the power source transfer path connecting the transmission side region and the reception side region in the transmission side region based on the fluctuation range of the voltage on the transmission side estimated in the noise estimation step Variation of the hold margin of the flip-flop circuit connected to the power supply transfer path in the reception-side region based on the variation width of the reception-side voltage estimated in the noise estimation step. A verification step for performing timing verification by adding the delay variation on the transmission side and the variation in the hold margin on the reception side to the hold margin considered in the timing analysis,
A circuit design method comprising:

(Appendix 4) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates a power source for each region,
For each of the transmission side region and the reception side region, the maximum value of the fluctuation range of the voltage is determined, and the flip-flop circuit connected to the power supply transfer path connecting the transmission side region and the reception side region of the transmission side region, While obtaining the fluctuation of the delay when the fluctuation width of the voltage on the transmission side is maximum, the fluctuation width of the voltage on the reception side of the flip-flop circuit connected to the power supply transfer path in the reception side area is the maximum. A library creation step of creating a flip-flop circuit having a hold margin obtained by adding a fluctuation amount of the delay on the transmission side and a fluctuation amount of the hold margin on the reception side, obtaining a fluctuation amount of the hold margin at a certain time,
A verification step for performing timing verification by using the flip-flop circuit created in the library creation step for the flip-flop circuit on the receiving side connected to the power supply transfer path;
A circuit design method comprising:

(Appendix 5) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates a power source for each region,
A flip-flop circuit is used as a power source transfer path connecting the transmission side region and the reception side region, the latch in the previous stage of the flip flop circuit is arranged in the transmission side region, and the power of the transmission side region is supplied to the latch in the previous stage And a latch at the rear stage of the flip-flop circuit is arranged in the reception side area, the power supply for the reception side area is supplied to the latch at the subsequent stage, and the voltage fluctuation range of the transmission side area and the voltage of the reception side area A library creating process for creating a flip-flop circuit having a margin for estimating a change in delay caused by a fluctuation range of
A design process for designing a circuit, using the flip-flop circuit created in the library creation process, as a cell for switching the power source connecting the transmission side area and the reception side area,
A circuit design method comprising:

(Appendix 6) In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates a power source for each region,
A flip-flop circuit is used as a power source transfer path connecting the transmission side region and the reception side region, the latch in the previous stage of the flip flop circuit is arranged in the transmission side region, and the power of the transmission side region is supplied to the latch in the previous stage A latch at the rear stage of the flip-flop circuit is disposed in the reception side area, the power of the reception side area is supplied to the latch at the rear stage, and a high-level transistor among the transistors constituting the latch at the rear stage of the flip-flop circuit is provided. Library creating step of creating a flip-flop circuit in which the threshold of the transistor on the side is lower than the output voltage of the transistor constituting the latch in the previous stage of the flip-flop circuit, taking into account the voltage fluctuation range of the transmission side region;
A design process for designing a circuit, using the flip-flop circuit created in the library creation process, as a cell for switching the power source connecting the transmission side area and the reception side area,
A circuit design method comprising:

(Supplementary note 7) As a result of estimating the fluctuation range of the voltage in each of the transmission side region and the reception side region, the voltage difference between the transmission side region and the reception side region can be transmitted and received through the power transfer path. The circuit design method according to any one of appendices 1 to 6, wherein redesign is performed when the size is too large.

(Supplementary Note 8) For each of the transmission side area and the reception side area, an allowable range of voltage fluctuation range is determined in advance at the time of design, and timing verification is performed using the maximum voltage fluctuation range at the time of timing verification. The circuit design method according to any one of appendices 1 to 7, wherein:

(Supplementary note 9) A circuit design program for causing a computer to execute the circuit design method according to any one of supplementary notes 1 to 8.

  As described above, the circuit design method and the circuit design program according to the present invention are useful for timing analysis tools for integrated circuits, and are particularly suitable for tools for performing static timing analysis.

3 is a flowchart showing a circuit design method according to the first exemplary embodiment; 6 is a flowchart showing a circuit design method according to the second exemplary embodiment; 10 is a flowchart showing a circuit design method according to the third exemplary embodiment; 10 is a flowchart showing a circuit design method according to a fourth exemplary embodiment; FIG. 10 is a circuit diagram illustrating an example of a power supply transfer path dedicated cell used in the circuit design method according to the fifth exemplary embodiment; 10 is a flowchart showing a procedure for creating a power transfer path dedicated cell in the fifth embodiment. 16 is a flowchart showing a procedure for using a power transfer path dedicated cell in the fifth embodiment. It is a schematic diagram which shows a voltage level in order to demonstrate the malfunctioning by a voltage level. It is a schematic diagram which shows the voltage level of the cell only for a power supply transfer path used in the circuit design method concerning Embodiment 6. 18 is a flowchart showing a procedure for creating a power transfer path dedicated cell in the sixth embodiment. FIG. 10 is a circuit diagram illustrating an example of a power supply transfer path dedicated cell used in the circuit design method according to the sixth embodiment; 10 is a flowchart illustrating a circuit design method according to a seventh embodiment; 10 is a flowchart illustrating a circuit design method according to an eighth embodiment;

Explanation of symbols

S1 Noise estimation step S2 Coefficient calculation step S3 Path extraction step S4 Script creation step S5 Verification step S13 Library creation step

Claims (5)

In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates the power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
A coefficient calculation step for obtaining a delay coefficient for timing verification based on the fluctuation range of the voltage estimated in the estimation step for each of the transmission side region and the reception side region;
A path extraction step of extracting a power supply transfer path connecting the transmission side area and the reception side area;
For the cell connected to the power transfer path extracted in the path extraction step in the transmission side region, the delay factor of the transmission side region calculated in the coefficient calculation step is applied, and in the reception side region, A script generation step of generating a script for performing timing verification of the power transfer path by multiplying a cell connected to the power transfer path by the delay coefficient of the receiving side area calculated in the coefficient calculation step When,
A circuit design method comprising: In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates the power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
A coefficient calculation step for obtaining a delay coefficient for timing verification based on the fluctuation range of the voltage estimated in the estimation step for each of the transmission side region and the reception side region;
A power supply transfer path connecting the transmission side area and the reception side area is extracted, and the cell of the transmission side area is connected to the power supply transfer path. The timing of the power transfer path is determined by applying a delay coefficient and multiplying the cell connected to the power transfer path in the receiving area by the delay coefficient of the receiving area calculated in the coefficient calculating step. A verification process for performing the verification;
A circuit design method comprising: In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates the power source for each region,
A noise estimation process for estimating a voltage fluctuation range for each of the transmission side area and the reception side area;
The delay of the flip-flop circuit connected to the power source transfer path connecting the transmission side region and the reception side region in the transmission side region based on the fluctuation range of the voltage on the transmission side estimated in the noise estimation step Variation of the hold margin of the flip-flop circuit connected to the power supply transfer path in the reception-side region based on the variation width of the reception-side voltage estimated in the noise estimation step. A verification step for performing timing verification by adding the delay variation on the transmission side and the variation in the hold margin on the reception side to the hold margin considered in the timing analysis,
A circuit design method comprising: In designing a circuit that divides a semiconductor integrated circuit into a plurality of regions and separates the power source for each region,
For each of the transmission side region and the reception side region, the maximum value of the fluctuation range of the voltage is determined, and the flip-flop circuit connected to the power supply transfer path connecting the transmission side region and the reception side region of the transmission side region, While obtaining the fluctuation of the delay when the fluctuation width of the voltage on the transmission side is maximum, the fluctuation width of the voltage on the reception side of the flip-flop circuit connected to the power supply transfer path in the reception side area is the maximum. A library creation step of creating a flip-flop circuit having a hold margin obtained by adding a fluctuation amount of the delay on the transmission side and a fluctuation amount of the hold margin on the reception side, obtaining a fluctuation amount of the hold margin at a certain time,
A verification step for performing timing verification by using the flip-flop circuit created in the library creation step for the flip-flop circuit on the receiving side connected to the power supply transfer path;
A circuit design method comprising: A circuit design program for causing a computer to execute the circuit design method according to claim 1.

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