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JP2007281288A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2007281288A
JP2007281288A JP2006107541A JP2006107541A JP2007281288A JP 2007281288 A JP2007281288 A JP 2007281288A JP 2006107541 A JP2006107541 A JP 2006107541A JP 2006107541 A JP2006107541 A JP 2006107541A JP 2007281288 A JP2007281288 A JP 2007281288A
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substrate
semiconductor device
manufacturing
insulating
thin body
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JP4615475B2 (en
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Hideyuki Wada
英之 和田
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which enables to use an ESC (electrostatic chuck) method as a means for fixing an insulating substrate in a dry process and can process to an external periphery without causing a dead space on a semiconductor substrate stuck on this insulating substrate. <P>SOLUTION: This manufacturing method of the semiconductor device 1 is sequentially provided with a step of forming devices on one surface 2a of a first substrate 2 having semiconductors; a step of sticking one surface 3a of an insulating second substrate 3 on the first substrate using a first adhesive 4, so as to cover the formed devices; a step of sticking a conductive thin plate 5, so as to cover the other surface 3b of the second substrate; and a step of applying dry process for the other surface 2b of the first substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置の製造方法に係り、詳しくは、ドライプロセスにおいて基板上の外周域まで加工を施した半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which processing is performed up to an outer peripheral region on a substrate in a dry process.

CCDデバイスに代表される光学半導体デバイスなどのウエハレベルパッケージを作製する際、シリコンなどの半導体からなる半導体基板側に形成されたデバイスやレンズなどの保護のために、この半導体基板に対してガラスなどの絶縁性を有する部材からなる絶縁性基板などが貼り合わせられることがある。そして、この半導体基板と絶縁性基板とを貼り合せた基板の半導体基板側に対し、貫通配線などを後に形成する場合には、たとえばプラズマ処理などのドライプロセスにより、微細孔を形成し、絶縁層を形成し、絶縁層をエッチングするなどの工程が存在する。   When manufacturing a wafer level package such as an optical semiconductor device typified by a CCD device, glass or the like is used to protect the semiconductor substrate and a device formed on the semiconductor substrate side made of a semiconductor such as silicon. An insulating substrate made of a member having the above insulating properties may be attached. When a through wiring or the like is to be formed later on the semiconductor substrate side of the substrate on which the semiconductor substrate and the insulating substrate are bonded, a fine hole is formed by a dry process such as plasma processing, and the insulating layer. There are processes such as forming the insulating layer and etching the insulating layer.

これらのドライプロセスでは、プラズマ処理の場合、プラズマ照射による加熱で基板温度が上昇し、形成されたデバイスに影響を及ぼすことがある。そのため、基板冷却を行なって所要の温度に制御する必要がある。一般的に基板冷却は、チラー・サーキュレータなどにより基板が配置される装置ステージを冷却し、冷却されたステージと基板の間に冷却用Heガスなどを封止することで行なわれている。すなわち、Heガスが、冷却されたステージと基板との間に封止されることによって冷却され、さらに、その冷却されたHeガスが、基板の裏面に直接接触することにより基板が冷却される。そして、この冷却のためのHeガスを封止し、基板を固定する方法として、静電チャックを用いる方法(以下、ESC(Electro Static Chuck)法と呼ぶ。)と、メカニカルクランプという方法が存在する。   In these dry processes, in the case of plasma processing, the substrate temperature rises due to heating by plasma irradiation, which may affect the formed device. Therefore, it is necessary to cool the substrate and control it to a required temperature. In general, substrate cooling is performed by cooling an apparatus stage on which a substrate is placed by a chiller circulator or the like and sealing a cooling He gas or the like between the cooled stage and the substrate. That is, the He gas is cooled by being sealed between the cooled stage and the substrate, and further, the substrate is cooled by the cooled He gas being in direct contact with the back surface of the substrate. As a method for sealing the He gas for cooling and fixing the substrate, there are a method using an electrostatic chuck (hereinafter referred to as an ESC (Electro Static Chuck) method) and a method called a mechanical clamp. .

このESC法は、基板に電圧をかけ稼動イオンを移動させることで、静電気的に基板を引き付け(静電吸引し)、基板冷却用のHeガスを封止し、基板を冷却する方法である(たとえば、特許文献1、2参照)。
また、メカニカルクランプは、基板外周域を物理的に押さえ込むことによって、基板冷却用のHeガスを封止し、基板を冷却する方法である(たとえば、特許文献3参照)。この方法は、基本的に基板中の稼動イオンの量に関わらず、絶縁性基板のようなものでも使用することができる。
This ESC method is a method in which a substrate is electrostatically attracted (electrostatically attracted) by applying a voltage to the substrate and moving operating ions, sealing He gas for cooling the substrate, and cooling the substrate ( For example, see Patent Documents 1 and 2).
Further, the mechanical clamp is a method of sealing the substrate cooling He gas by physically pressing down the substrate outer peripheral region and cooling the substrate (for example, see Patent Document 3). This method can be used with an insulating substrate basically regardless of the amount of working ions in the substrate.

また、一対の基板が対向して貼り合わされてなる電子光学装置の製造方法において、一方の基板の背面側に、導電部材を設ける方法が提案されている(特許文献4参照)。   In addition, in a method of manufacturing an electro-optical device in which a pair of substrates are bonded to each other, a method of providing a conductive member on the back side of one substrate has been proposed (see Patent Document 4).

しかしながら、ESC法の場合、使用する基板に稼動イオンなどが含まれていないと吸着できないため、金属や半導体などでは吸着することができるが、絶縁性基板では稼動イオンが非常に少ないため吸着は困難である。したがって、裏面側に絶縁性基板が貼り合わされている基板に使用することはできないという問題がある。
また、メカニカルクランプの場合、基板加工面の外周域を3〜5mm程度押さえ込む必要があるため、クランプにより押さえ込まれる部分であるクランプエリアがデットスペースになり、加工することができなくなってしまう。そのため、基板の加工エリアが小さくなってチップの取れ数が少なくなるという問題がある。また、加工面にクランプによる段差があるため、この構造体によりプラズマが歪められ、プロセスに影響を与える問題がある。
However, in the case of the ESC method, if the substrate used does not contain working ions, it cannot be adsorbed, so it can be adsorbed by metals or semiconductors, but it is difficult to adsorb by an insulating substrate because there are very few working ions. It is. Therefore, there exists a problem that it cannot use for the board | substrate with which the insulating board | substrate is bonded by the back side.
Further, in the case of the mechanical clamp, it is necessary to press the outer peripheral area of the substrate processing surface by about 3 to 5 mm, so that the clamp area that is pressed by the clamp becomes a dead space and cannot be processed. Therefore, there is a problem that the processing area of the substrate is reduced and the number of chips taken is reduced. Further, since there is a step due to the clamp on the processed surface, the structure is distorted by plasma, and there is a problem of affecting the process.

また、特許文献4に記載の技術は、電子光学装置の製造方法に関し、ドライプロセスを施す基板を保持する半導体装置の製造方法に関するものではない。しかも、特許文献4に記載の技術は、貼り合わせ工程におけるガラス基板の損傷を抑止することを主たる目的とするため、導電部材は、ガラス基板は搬送手段等と機械的に接触する部分に設けられていれば良く、必ずしもガラス基板の表面を全て覆う必要は無いものであり、目的が相違する半導体装置の製造方法に容易に応用できるものではない。したがって、ドライプロセスにおいて半導体からなる基板上の外周域まで加工することができるように、この基板を固定して半導体装置の製造を可能とする有効な手段に関する提案は見出されていない。
特開平3−89745号公報 特開平3−91234号公報 特開平4−128308号公報 特開2004−133110号公報
The technique described in Patent Document 4 relates to a method for manufacturing an electro-optical device, and does not relate to a method for manufacturing a semiconductor device that holds a substrate subjected to a dry process. Moreover, since the technique described in Patent Document 4 is mainly intended to suppress damage to the glass substrate in the bonding process, the conductive member is provided in a portion where the glass substrate mechanically contacts the conveying means or the like. It is not always necessary to cover the entire surface of the glass substrate, and it cannot be easily applied to a method of manufacturing a semiconductor device having a different purpose. Accordingly, no proposal has been found regarding an effective means for fixing the substrate so that the semiconductor device can be manufactured so that the outer peripheral region on the substrate made of semiconductor can be processed in the dry process.
Japanese Patent Laid-Open No. 3-89745 Japanese Patent Laid-Open No. 3-91234 JP-A-4-128308 JP 2004-133110 A

本発明は、上記事情に鑑みてなされたものであって、ドライプロセスにおいて絶縁性基板を固定する手段としてESC法を用いることを可能とし、この絶縁性基板と貼り合わされた半導体基板上にデットスペースを生じること無く外周域まで加工を施すことが可能な半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and it is possible to use the ESC method as a means for fixing an insulating substrate in a dry process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform processing up to the outer peripheral region without causing any problems.

本発明の請求項1に係る半導体装置の製造方法は、半導体からなる第一基板の一方の面にデバイスを形成する工程と、前記第一基板に対して、前記デバイスを覆うように、絶縁性の第二基板の一方の面を第一の接着材を用い貼り合せる工程と、前記第二基板の他方の面を覆うように、導電性の薄体を貼り合せる工程と、前記第一基板の他方の面に対してドライプロセスを施す工程と、を順に備えることを特徴とする。   The method for manufacturing a semiconductor device according to claim 1 of the present invention includes a step of forming a device on one surface of a first substrate made of a semiconductor, and an insulating property so as to cover the device with respect to the first substrate. A step of bonding one surface of the second substrate using a first adhesive, a step of bonding a conductive thin body so as to cover the other surface of the second substrate, and A step of performing a dry process on the other surface in order.

本発明の請求項2に係る半導体装置の製造方法は、請求項1において、前記薄体を貼り合せる工程は、該薄体として、紫外線を透過する部材を、前記第二基板に対して該薄体を貼り合せるために、紫外線剥離型の第二の接着材を、それぞれ用いることを特徴とする。   According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the step of laminating the thin body includes, as the thin body, a member that transmits ultraviolet rays as the thin substrate. In order to bond the bodies, an ultraviolet peeling type second adhesive is used.

本発明の半導体装置の製造方法にあっては、半導体からなる第一基板と、その一方の面が貼り合わされた絶縁性の第二基板の他方の面を覆うように、導電性の薄体を貼り合せる工程を有している。ゆえに、薄体と貼り合わされた絶縁性の第二基板は、その内周域と同様にその外周域までESC法による吸着(静電吸引)が可能となる。
したがって、ドライプロセスにおいて、第二基板と貼り合わされた第一基板上にデットスペースを生じること無く、外周域まで表面全面を処理(加工)することができ、加工エリアが広がってウエハ一枚当たりのチップの取れ数を増加させる半導体装置の製造方法を提供することができる。しかも、薄体によって第二基板の他方の面を保護することもできる。
In the method for manufacturing a semiconductor device of the present invention, a conductive thin body is formed so as to cover the other surface of the first substrate made of semiconductor and the insulating second substrate to which one surface thereof is bonded. It has the process of bonding. Therefore, the insulating second substrate bonded to the thin body can be adsorbed (electrostatic suction) by the ESC method up to the outer peripheral area in the same manner as the inner peripheral area.
Therefore, in the dry process, the entire surface can be processed (processed) up to the outer peripheral area without generating a dead space on the first substrate bonded to the second substrate, and the processing area is widened to increase the per-wafer size. A method of manufacturing a semiconductor device that increases the number of chips can be provided. In addition, the other surface of the second substrate can be protected by the thin body.

以下、本発明の一実施形態について説明する。
本発明は、ドライプロセスにおいて基板を固定する手段としてESC法を用い、基板の外周域まで加工することを可能とする半導体装置の製造方法について提案する。
具体的に、本実施形態では、第一基板と第二基板とを貼り合せ、さらに、第二基板を覆うように導電性の薄体を貼り合わせることにより、ESC法での基板の吸着固定を可能とし、第一基板上にドライプロセスによる加工を施すことを可能とするものである。
本発明に係る半導体装置の製造方法の一例を、図面に基づいて説明する。
図1(a)乃至(c)は、本発明に係る半導体装置の製造方法の一例を工程順に示す概略断面模式図である。
Hereinafter, an embodiment of the present invention will be described.
The present invention proposes a method of manufacturing a semiconductor device that uses the ESC method as a means for fixing a substrate in a dry process and enables processing to the outer peripheral region of the substrate.
Specifically, in this embodiment, the first substrate and the second substrate are bonded together, and further, the conductive thin body is bonded so as to cover the second substrate, whereby the substrate is fixed by the ESC method. The first substrate can be processed by a dry process.
An example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
1A to 1C are schematic cross-sectional schematic views showing an example of a method for manufacturing a semiconductor device according to the present invention in the order of steps.

はじめに、図1(a)に示すように、第一基板2を準備する。第一基板2は、たとえばシリコンやガラス、シリコン−ガラス貼合せ基板などの半導体を含む各種基板である。この第一基板2の厚さは、100μmから800μmの範囲とするのが望ましい。
そして、この第一基板2の一方の面2aに、CCD、CMOS、圧力センサ、加速度センサ、ジャイロセンサなどのデバイスを形成する。
First, as shown in FIG. 1A, the first substrate 2 is prepared. The first substrate 2 is a variety of substrates including semiconductors such as silicon, glass, and silicon-glass bonded substrate. The thickness of the first substrate 2 is desirably in the range of 100 μm to 800 μm.
A device such as a CCD, a CMOS, a pressure sensor, an acceleration sensor, or a gyro sensor is formed on one surface 2a of the first substrate 2.

次いで、図1(b)に示すように、第一基板2の一方の面2aに形成されたデバイスを覆うように、第一基板2に対して、第一の接着材4を介して第二基板3を貼り合せ固定する。第二基板3は、第一基板2側に形成されたデバイスなどを保護したり、第一基板2を補強したりするものであり、たとえば石英ガラスやセラミック、SiCなどの絶縁性の部材よりなる絶縁性基板である。この第二基板3の厚さは、100μmから800μmの範囲とするのが望ましい。   Next, as shown in FIG. 1 (b), the second substrate 2 is interposed via the first adhesive 4 so as to cover the device formed on the one surface 2a of the first substrate 2. The substrate 3 is bonded and fixed. The second substrate 3 protects a device or the like formed on the first substrate 2 side or reinforces the first substrate 2, and is made of an insulating member such as quartz glass, ceramic, or SiC. It is an insulating substrate. The thickness of the second substrate 3 is desirably in the range of 100 μm to 800 μm.

第一の接着材4は、第一基板2と第二基板3とを貼り合せ固定する部材であり、たとえばアクリル系樹脂、エポキシ系樹脂、シリコーン系樹脂などが挙げられる。
また、この第一の接着材4は、図示するように、デバイスが形成された第一基板2の一方の面2aの所定の領域に空間4aを設けるように配しても良い。この空間4aは、キャビティや溝のような3次元空間であり、余分な接着材4をその内に止め、はみ出しを防止して固着できるようにすることができる。したがって、第一基板2に対して第二基板3を固着する際、接着材4は押しつぶされて空間4a内に広がり、周縁部へのはみ出しが防止される。
また、空間4aは、接合した場合における応力をこの空間4aにて吸収させて緩和することもできる。
The 1st adhesive material 4 is a member which bonds and fixes the 1st board | substrate 2 and the 2nd board | substrate 3, For example, acrylic resin, an epoxy resin, silicone resin etc. are mentioned.
Further, as shown in the figure, the first adhesive 4 may be arranged so as to provide a space 4a in a predetermined region of the one surface 2a of the first substrate 2 on which the device is formed. This space 4a is a three-dimensional space such as a cavity or a groove, and an extra adhesive material 4 can be stopped in the space 4a to prevent sticking and prevent sticking. Therefore, when the second substrate 3 is fixed to the first substrate 2, the adhesive 4 is crushed and spreads in the space 4a, and the protrusion to the peripheral edge is prevented.
Moreover, the space 4a can also absorb and relieve | moderate the stress at the time of joining in this space 4a.

さらに、図1(c)に示すように、第二基板3の他方の面3bを覆うように、導電性の薄体5を貼り合わせる。この薄体5は、後に剥離可能となるように、第二の接着材4を用いて貼り合せる。
この薄体5を第二基板3に貼り合わせることで、これまでESC法では使用できなかった石英ガラスなどの絶縁性基板をESC法で第二基板3を吸着固定することができる。したがって、第二基板3と第一の接着材4を用いて貼り合わされた第一基板2も固定されるものとなる。
Furthermore, as shown in FIG.1 (c), the electroconductive thin body 5 is bonded together so that the other surface 3b of the 2nd board | substrate 3 may be covered. The thin body 5 is bonded using the second adhesive 4 so that it can be peeled later.
By bonding the thin body 5 to the second substrate 3, an insulating substrate such as quartz glass that has not been used in the ESC method can be adsorbed and fixed by the ESC method. Therefore, the first substrate 2 bonded using the second substrate 3 and the first adhesive 4 is also fixed.

薄体5は、具体的には、たとえば図2に示すように、透明基材11と、第二の接着材12と、透明導電層13との3層からなる導電性シート5Aとすることができる。   Specifically, for example, as shown in FIG. 2, the thin body 5 may be a conductive sheet 5 </ b> A composed of three layers of a transparent base material 11, a second adhesive 12, and a transparent conductive layer 13. it can.

透明基材11は、第二の接着材12と透明導電層13を成膜するための透明な基材であり、極力薄くし、かつ、基材が切れたりしないようにある程度の強度を要する。透明基材11としては、たとえばポリエチレンテレフタレート(PET)やアクリルなどのフィルム状の薄厚部材が挙げられる。この透明基材11の厚さは、5〜100μm程度が望ましい。
この透明基材11は、紫外線を透過する材料より構成しても良い。
The transparent base material 11 is a transparent base material for forming the second adhesive material 12 and the transparent conductive layer 13, and is required to have a certain degree of strength so that it is as thin as possible and the base material is not cut. Examples of the transparent substrate 11 include thin film-like members such as polyethylene terephthalate (PET) and acrylic. As for the thickness of this transparent base material 11, about 5-100 micrometers is desirable.
The transparent substrate 11 may be made of a material that transmits ultraviolet rays.

また、透明基材11は、薄厚のフィルム状基材に限らず、ガラスなどの比較的厚い基板であっても良い。
これにより、反りが大きい基板に対し透明基材11を貼り合せることで、基板の反りを緩和させ、ESC法による吸着を可能とすることができるものとなる。
The transparent substrate 11 is not limited to a thin film-like substrate, and may be a relatively thick substrate such as glass.
Thereby, by sticking the transparent base material 11 to a substrate having a large warp, the warp of the substrate can be relaxed and adsorption by the ESC method can be performed.

第二の接着材12は、第一基体2の他方の面2bに加工を施した後、第二基板3の他方の面3bから薄体5の剥離が可能となる材料よりなる。
この第二の接着材12は、紫外線剥離型の接着材とすると良い。ダイシングシート等で実績がある紫外線剥離型の接着材を用いることで、第二基板3を汚染することなく、処理することができる。
これにより、後に薄体5としての導電性シート5Aが不要となったときに、紫外線を照射することで簡単に導電性シート5Aを剥離することが可能となる。
The second adhesive 12 is made of a material that enables the thin body 5 to be peeled from the other surface 3 b of the second substrate 3 after processing the other surface 2 b of the first base 2.
The second adhesive 12 is preferably an ultraviolet peeling type adhesive. By using a UV peelable adhesive that has a proven record in dicing sheets or the like, the second substrate 3 can be processed without being contaminated.
As a result, when the conductive sheet 5A as the thin body 5 becomes unnecessary later, the conductive sheet 5A can be easily peeled off by irradiating with ultraviolet rays.

透明導電層13は、ESC法によって吸着のための部材であり、たとえばITO(スズ添加酸化インジウム)膜、ITO/FTO(スズ添加酸化インジウムとフッ素添加スズを組み合わせた構成)膜、有機導電膜などの導電性を有する透明な薄膜より構成される。
この際、透明導電層13は、紫外線を透過する材料より構成すると良い。
The transparent conductive layer 13 is a member for adsorption by the ESC method. For example, an ITO (tin-added indium oxide) film, an ITO / FTO (combination of tin-added indium oxide and fluorine-added tin) film, an organic conductive film, etc. It is comprised from the transparent thin film which has the electroconductivity.
At this time, the transparent conductive layer 13 is preferably made of a material that transmits ultraviolet rays.

また、薄体5は、図3に示すように、透明導電基材21と、紫外線剥離型の第二の接着層12との2層からなるも導電性シート5Bとすることもできる。
この透明導電基材21は、導電性を有する透明なシート状基材であり、紫外線を透過する材料より構成される。
これにより、後に薄体5としての導電性シート5Bが不要となったときに、紫外線を照射することで簡単に導電性シート5Bを剥離することが可能となる。
Further, as shown in FIG. 3, the thin body 5 may be a conductive sheet 5 </ b> B including two layers of a transparent conductive base material 21 and an ultraviolet peelable second adhesive layer 12.
The transparent conductive substrate 21 is a transparent sheet-like substrate having conductivity, and is made of a material that transmits ultraviolet rays.
Thereby, when the conductive sheet 5B as the thin body 5 becomes unnecessary later, the conductive sheet 5B can be easily peeled off by irradiating with ultraviolet rays.

そして、薄体5を貼り合せた後、図示しないが、たとえば真空チャンバ内においてESC法によって基板を吸着し、プラズマ処理などのドライプロセスによって第一基板2の他方の面2bに貫通配線を作製するなど加工を施す。ドライプロセスによる加工は、具体的には、シリコンエッチング、導体・絶縁層の成膜やエッチング、アッシング、表面処理などである。この際、薄体5が、加工時の第二基板3側の保護として機能する。   Then, after bonding the thin body 5, although not shown, for example, the substrate is adsorbed by an ESC method in a vacuum chamber, and a through wiring is formed on the other surface 2b of the first substrate 2 by a dry process such as plasma processing. And so on. Specifically, the dry process includes silicon etching, conductor / insulating layer deposition and etching, ashing, surface treatment, and the like. At this time, the thin body 5 functions as protection on the second substrate 3 side during processing.

これにより、第一基板2と第二基板3とを貼り合せ、ESC法によって第二基板3を吸着固定し、デットスペースを生じること無く、この第一基板2の他方の面2bの外周域までその内周域と同様に全面的に加工を施した半導体装置1を製造することが出来る。
したがって、本発明においては、デットスペースを生じするメカニカルクランプを必要としないため、メカニカルクランプによって加工エリアが縮小することは無く、基板の外周域まで表面全面の処理(加工)ができ、加工領域が広がってチップの取れ数を増加させるように半導体装置を製造することができる。しかも、基板の外周域と内周域との加工バラツキを少なくすることが可能となる。
また、本発明においては、第二基板3の他方の面3bに段差や構造物があり、そのままではESC法によって吸着することができない基板に対しても、薄体5を貼り合せることが可能であり、ESC法によって吸着することができるものとなる。
Thereby, the first substrate 2 and the second substrate 3 are bonded together, the second substrate 3 is sucked and fixed by the ESC method, and the outer surface of the other surface 2b of the first substrate 2 is reached without causing a dead space. Similar to the inner peripheral region, the semiconductor device 1 that has been processed entirely can be manufactured.
Therefore, in the present invention, since a mechanical clamp that generates a dead space is not required, the processing area is not reduced by the mechanical clamp, and the entire surface can be processed (processed) up to the outer peripheral area of the substrate. A semiconductor device can be manufactured so as to spread and increase the number of chips. In addition, processing variations between the outer peripheral area and the inner peripheral area of the substrate can be reduced.
Further, in the present invention, the thin body 5 can be bonded even to a substrate that has a step or a structure on the other surface 3b of the second substrate 3 and cannot be adsorbed by the ESC method as it is. Yes, it can be adsorbed by the ESC method.

本発明に係る半導体装置の製造方法の一例を工程順に示す概略断面模式図である。It is a schematic cross-sectional schematic diagram which shows an example of the manufacturing method of the semiconductor device which concerns on this invention in process order. 本発明に係る半導体装置の絶縁性基材を覆うように貼り合せる導電性シートの一例を示す概略断面図である。It is a schematic sectional drawing which shows an example of the electroconductive sheet bonded so that the insulating base material of the semiconductor device which concerns on this invention may be covered. 本発明に係る半導体装置の絶縁性基材を覆うように貼り合せる導電性シートの他の一例を示す概略断面図である。It is a schematic sectional drawing which shows another example of the electroconductive sheet bonded together so that the insulating base material of the semiconductor device concerning this invention may be covered.

符号の説明Explanation of symbols

1 半導体装置、2 第一基板(半導体基板)、3 第二基板(絶縁性基板)、4 第一の接着層材、5 薄体、5A,5B 導電性シート、11 透明基材、12 第二の接着材、13 透明導電層、21 透明導電基材。
DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 1st board | substrate (semiconductor board | substrate) 3 2nd board | substrate (insulating board | substrate) 4 1st contact bonding layer material, 5 thin body, 5A, 5B electroconductive sheet, 11 transparent base material, 12 2nd Adhesive material, 13 transparent conductive layer, 21 transparent conductive substrate.

Claims (2)

半導体からなる第一基板の一方の面にデバイスを形成する工程と、
前記第一基板に対して、前記デバイスを覆うように、絶縁性の第二基板の一方の面を第一の接着材を用い貼り合わせる工程と、
前記第二基板の他方の面を覆うように、導電性の薄体を貼り合わせる工程と、
前記第一基板の他方の面に対してドライプロセスを施す工程と、
を順に備えることを特徴とする半導体装置の製造方法。
Forming a device on one surface of the first substrate made of a semiconductor;
Bonding one surface of the insulating second substrate to the first substrate using a first adhesive so as to cover the device;
Bonding the conductive thin body so as to cover the other surface of the second substrate;
Applying a dry process to the other surface of the first substrate;
In order. The manufacturing method of the semiconductor device characterized by the above-mentioned.
前記薄体を貼り合わせる工程は、
該薄体として、紫外線を透過する部材を、
前記第二基板に対して該薄体を貼り合わせるために、紫外線剥離型の第二の接着材を、
それぞれ用いることを特徴とする請求項1に記載の半導体装置の製造方法。
The step of laminating the thin body includes
As the thin body, a member that transmits ultraviolet rays,
In order to bond the thin body to the second substrate, an ultraviolet peelable second adhesive material is used.
The method of manufacturing a semiconductor device according to claim 1, wherein each method is used.
JP2006107541A 2006-04-10 2006-04-10 Semiconductor device and manufacturing method of semiconductor device Expired - Fee Related JP4615475B2 (en)

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US20220148904A1 (en) * 2017-08-14 2022-05-12 Watlow Electric Manufacturing Company Method for joining quartz pieces and quartz electrodes and other devices of joined quartz

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US20220148904A1 (en) * 2017-08-14 2022-05-12 Watlow Electric Manufacturing Company Method for joining quartz pieces and quartz electrodes and other devices of joined quartz
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