JP2007130834A - Drive circuit for piezoelectric element and liquid ejector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a drive circuit for a piezoelectric element. <P>SOLUTION: The drive circuit for a piezoelectric element comprises a transistor creating a main drive signal for operating a piezoelectric element by amplifying a reference signal inputted to a control terminal and delivering the main drive signal from an output terminal, a circuit for supplying a first auxiliary drive signal to the current supply terminal of the transistor in order to amplify the reference signal, and a circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor in order to amplify the reference signal when the potential difference between the first auxiliary drive signal inputted to the current supply terminal and the reference signal inputted to the control terminal is less than a predetermined value. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit for a piezoelectric element that generates a drive signal for driving a piezoelectric element, and a liquid ejection apparatus.

  Inkjet printers are provided with piezoelectric elements that perform the operation of ejecting ink from nozzles. The piezoelectric element is used in various other devices besides the ink jet printer. Various devices including an ink jet printer provided with such a piezoelectric element are provided with a drive circuit for driving the piezoelectric element.

This drive circuit for a piezoelectric element generally generates a drive signal for driving the piezoelectric element and outputs it to the piezoelectric element. This drive circuit includes a transistor for generating a drive signal for driving the piezoelectric element, and generates a drive signal by performing current amplification with the transistor (see Patent Documents 1, 2, and 3).
JP-A 63-25049 JP 11-320872 A JP 2000-238264 A

  However, when current amplification is performed by a transistor in order to generate a drive signal in this way, the following problem has occurred. That is, it is a problem that the power consumption of the drive circuit, more specifically, the transistor is very large. In short, if the power consumption of the drive circuit is large, the power consumption of the device will increase, and there will be a problem with the device itself that the power supply must be made strong, and there is a possibility of affecting the environment. In addition, when the power consumption of the transistor is large, there is a risk that a great amount of heat is generated from the transistor, and the surroundings become a high temperature state and adversely affects.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce the power consumption of the drive circuit of the piezoelectric element.

The main invention for achieving the object is as follows:
A transistor that amplifies a reference signal input to the control terminal, generates a main drive signal for operating the piezoelectric element, and outputs it from the output terminal;
A first auxiliary drive signal generating circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor for amplifying the reference signal;
To amplify the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor;
A drive circuit for a piezoelectric element.

  Other features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  At least the following matters will become apparent from the description of the present specification and the accompanying drawings.

A transistor that amplifies a reference signal input to the control terminal, generates a main drive signal for operating the piezoelectric element, and outputs it from the output terminal;
A first auxiliary drive signal generating circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor for amplifying the reference signal;
To amplify the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor;
A drive circuit for a piezoelectric element, comprising:

  In this piezoelectric element drive circuit, the first auxiliary drive signal generated by the first auxiliary drive signal generation circuit is supplied to the current supply terminal of the transistor, so that the power consumption of the transistor can be reduced. . Further, when the potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal falls below a predetermined value, the second auxiliary drive signal is applied to the current supply terminal. By supplying the current, the current can be reliably supplied to the current supply terminal of the transistor.

  In such a piezoelectric element drive circuit, the first auxiliary drive signal generation circuit generates a signal having a potential waveform determined to reduce power consumption of the transistor as the first auxiliary drive signal. Also good. By generating such a signal by the first auxiliary drive signal generation circuit, the power consumption of the transistor can be further reduced.

  In the piezoelectric element drive circuit, the first auxiliary drive signal generation circuit increases the potential prior to the potential increase of the reference signal as the first auxiliary drive signal, and the reference signal A signal whose potential drops may be generated prior to the potential drop. The generation of such a signal by the first auxiliary drive signal generation circuit can sufficiently reduce the power consumption of the transistor.

  In the piezoelectric element drive circuit, the first auxiliary drive signal may have a potential waveform approximate to the potential waveform of the reference signal. If the first auxiliary drive signal has such a potential waveform, the power consumption of the transistor can be further reduced.

  In the piezoelectric element drive circuit, the first auxiliary drive signal generation circuit includes an LC resonance circuit in which an inductance and a capacitor are connected in series. The resonance of the LC resonance circuit causes the first auxiliary drive signal generation circuit to include the LC resonance circuit. An auxiliary drive signal may be generated. By having such an LC resonance circuit, the power consumption of the transistor can be easily reduced.

  In the piezoelectric element driving circuit, the voltage across the capacitor may be supplied to the current supply terminal of the transistor as the auxiliary driving signal. When the voltage across the capacitor is supplied to the current supply terminal of the transistor as the first auxiliary drive signal in this way, the first auxiliary drive signal generated by the resonance of the LC circuit is simply supplied to the current supply terminal of the transistor. can do.

  In addition, the piezoelectric element drive circuit may include a pair of transistors connected complementarily as the transistor. With such a transistor pair, the reference signal can be sufficiently amplified.

  In the piezoelectric element drive circuit, the transistor pair may be composed of an NPN transistor and a PNP transistor whose emitter terminals are connected to each other. With such a configuration, the reference signal can be amplified efficiently.

  In the piezoelectric element driving circuit, the transistor may be a bipolar transistor. As described above, since the transistor is a bipolar transistor, the reference signal can be easily amplified.

  In the piezoelectric element drive circuit, the second auxiliary drive signal generation circuit may generate the second auxiliary drive signal based on the reference signal. When the second auxiliary drive signal is generated in this way, the potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal falls below a predetermined value. In addition, current can be reliably supplied to the current supply terminal of the transistor.

  In the piezoelectric element drive circuit, the second auxiliary drive signal generation circuit increases the potential when the potential of the reference signal rises as the second auxiliary drive signal and when the potential of the reference signal drops. A signal whose potential drops may be generated. If such a second auxiliary drive signal is generated, the potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal falls below a predetermined value. In addition, current can be reliably supplied to the current supply terminal of the transistor.

  In the piezoelectric element drive circuit, the second auxiliary drive signal may be a signal having a predetermined potential difference from the reference signal. As described above, since the second auxiliary drive signal is a signal having a predetermined potential difference from the potential of the reference signal, the potential of the first auxiliary drive signal input to the current supply terminal and the reference signal input to the control terminal When the potential difference from the potential falls below a predetermined value, current can be reliably supplied to the current supply terminal of the transistor.

  In the piezoelectric element drive circuit, the second auxiliary drive signal generation circuit may include a transistor for generating the second auxiliary drive signal. If the second auxiliary drive signal generation circuit includes such a transistor, the second auxiliary drive signal can be easily generated.

  In the piezoelectric element drive circuit, the second auxiliary drive signal generation circuit may include two or more transistors connected in Darlington as the transistor. If two or more transistors connected in Darlington are provided as described above, the second auxiliary drive signal can be easily generated.

  In the driving circuit for the piezoelectric element, the piezoelectric element may be an element that performs an operation of discharging a liquid from a nozzle. In this way, when the piezoelectric element is an element that performs an operation of discharging liquid from the nozzle, it is possible to reduce the power consumption of the transistor of the driving circuit of the piezoelectric element. Further, when the potential difference between the potential of the first auxiliary drive signal input to the current supply terminal of the transistor and the potential of the reference signal input to the control terminal falls below a predetermined value, the second auxiliary drive signal is supplied to the current supply terminal. By supplying the drive signal, current can be reliably supplied to the current supply terminal of the transistor.

(A) a transistor that amplifies a reference signal input to the control terminal, generates a main drive signal for operating the piezoelectric element, and outputs the main drive signal from the output terminal;
(B) a first auxiliary drive signal generation circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor to amplify the reference signal;
(C) The reference signal is amplified when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor,
(D)
(E) The first auxiliary drive signal generation circuit generates a signal having a potential waveform defined as the first auxiliary drive signal in order to reduce power consumption of the transistor,
(F) The first auxiliary drive signal generation circuit, as the first auxiliary drive signal, the potential increases prior to the potential increase of the reference signal, and the potential decreases prior to the potential decrease of the reference signal. Generate a signal to
(G) the first auxiliary drive signal has a potential waveform approximate to the potential waveform of the reference signal;
(H) The first auxiliary drive signal generation circuit includes an LC resonance circuit in which an inductance and a capacitor are connected in series, and generates the first auxiliary drive signal by resonance of the LC resonance circuit,
(I) A voltage across the capacitor is supplied to the current supply terminal of the transistor as the auxiliary drive signal;
(J) The transistor includes a pair of transistors connected in a complementary manner,
(K) The transistor pair includes an NPN transistor and a PNP transistor whose emitter terminals are connected to each other,
(L) the transistor is a bipolar transistor;
(M) The second auxiliary drive signal generation circuit generates the second auxiliary drive signal based on the reference signal,
(N) The second auxiliary drive signal generation circuit generates, as the second auxiliary drive signal, a signal that increases in potential when the potential of the reference signal increases and decreases in potential when the potential of the reference signal decreases,
(O) the second auxiliary drive signal is a signal having a predetermined potential difference from the potential of the reference signal;
(P) The second auxiliary drive signal generation circuit includes a transistor for generating the second auxiliary drive signal,
(Q) The second auxiliary drive signal generation circuit includes two or more transistors connected in Darlington as the transistors,
(R) The piezoelectric element drive circuit, wherein the piezoelectric element is an element that performs an operation of discharging a liquid from a nozzle.

A piezoelectric element that performs an operation of discharging liquid from a nozzle;
A transistor that amplifies a reference signal input to a control terminal, generates a main drive signal for causing the piezoelectric element to perform the operation, and outputs the main drive signal from an output terminal;
A first auxiliary drive signal generating circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor for amplifying the reference signal;
To amplify the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor;
A liquid ejection apparatus comprising:

=== Configuration of Printing System 100 ===
<Overall configuration>
First, the printing apparatus will be described together with a printing system. Here, FIG. 1 is a diagram illustrating the configuration of the printing system 100. The illustrated printing system 100 includes a printer 1 as a printing apparatus and a computer 110 as a printing control apparatus. Specifically, the printing system 100 includes a printer 1, a computer 110, a display device 120, an input device 130, and a recording / reproducing device 140. The printer 1 prints an image on a medium such as paper, cloth, or film. This medium corresponds to an object to which liquid is ejected. In the following description, a sheet that is a typical medium will be described as an example. The computer 110 is communicably connected to the printer 1. In order to cause the printer 1 to print an image, the computer 110 outputs print data corresponding to the image to the printer 1. Computer programs such as application programs and printer drivers are installed in the computer 110. The display device 120 has a display. The display device 120 is for displaying a user interface of a computer program, for example. The input device 130 is a keyboard 131 or a mouse 132, for example. The recording / reproducing device 140 is, for example, a flexible disk drive device 141 or a CD-ROM drive device 142.

=== Computer 110 ===
<Configuration of Computer 110>
FIG. 2 is a block diagram illustrating configurations of the computer 110 and the printer 1. First, the configuration of the computer 110 will be briefly described. The computer 110 includes the recording / reproducing device 140 and the host-side controller 111 described above. The recording / reproducing apparatus 140 is communicably connected to the host-side controller 111, and is attached to the housing of the computer 110, for example. The host-side controller 111 performs various controls in the computer 110, and the display device 120 and the input device 130 described above are also connected to be communicable. The host-side controller 111 includes an interface unit 112, a CPU 113, and a memory 114. The interface unit 112 is interposed between the printer 1 and exchanges data. The CPU 113 is an arithmetic processing unit for performing overall control of the computer 110. The memory 114 is used to secure an area for storing a computer program used by the CPU 113, a work area, and the like, and includes a RAM, an EEPROM, a ROM, a magnetic disk device, and the like. The computer program stored in the memory 114 includes the application program and printer driver described above. The CPU 113 performs various controls according to the computer program stored in the memory 114.

  The print data is data in a format that can be interpreted by the printer 1. The print data includes various command data and pixel data. Here, the command data is data for instructing the printer 1 to execute a specific operation. The command data includes, for example, command data for instructing paper feed, command data for indicating the carry amount, and command data for instructing paper discharge. The pixel data is data related to the pixels constituting the image to be printed. Here, the pixel data is constituted by data (for example, gradation values) relating to dots formed on the paper corresponding to each pixel constituting the printed image. In the present embodiment, the pixel data is composed of 2-bit data. Specifically, the pixel data includes data [00] corresponding to no dot (no ink ejection), data [01] corresponding to the formation of small dots, and data [10] corresponding to the formation of medium dots. And data [11] corresponding to the formation of large dots. That is, in the printer 1, an image is formed with four gradations for one pixel.

=== Printer 1 ===
<Configuration of Printer 1>
Next, the configuration of the printer 1 will be described. Here, FIG. 3A is a diagram illustrating a configuration of the printer 1 of the present embodiment. FIG. 3B is a side view illustrating the configuration of the printer 1 of the present embodiment. In the following description, FIG. 2 is also referred to. As shown in FIG. 2, the printer 1 includes a paper transport mechanism 20, a carriage moving mechanism 30, a head unit 40, a drive signal generation circuit 50, a detector group 60, and a printer-side controller 70. The drive signal generation circuit 50 and the printer-side controller 70 are mounted on a common controller board CTR. The head unit 40 includes a head control unit HC and a head 41. In the printer 1, the control target unit, that is, the paper transport mechanism 20, the carriage moving mechanism 30, the head unit 40 (head controller HC, head 41), and the drive signal generation circuit 50 are controlled by the printer-side controller 70. That is, the printer-side controller 70 controls the control target unit based on the print data received from the computer 110 and prints an image on the paper S. At this time, each detector of the detector group 60 detects the state of each part in the printer 1 and outputs the detection result to the printer-side controller 70. Upon receiving the detection results from each detector, the printer-side controller 70 controls the control target unit based on the detection results.

<Paper transport mechanism>
The paper transport mechanism 20 corresponds to a medium transport unit that transports a medium. The paper transport mechanism 20 feeds the paper S as a medium to a printable position, or transports the paper S by a predetermined transport amount in the transport direction. This transport direction is a direction that intersects the carriage movement direction described below. 3A and 3B, the paper transport mechanism 20 includes a paper feed roller 21, a transport motor 22, a transport roller 23, a platen 24, and a paper discharge roller 25. The paper feed roller 21 is a roller for automatically feeding the paper S inserted into the paper insertion opening into the printer 1 and has a D-shaped cross section in this example. The carry motor 22 is a motor for carrying the paper S in the carrying direction, and its operation is controlled by the printer-side controller 70. The transport roller 23 is a roller for transporting the paper S sent by the paper feed roller 21 to a printable area. The platen 24 is a member for supporting the paper S from the back side. The paper discharge roller 25 is a roller for carrying the paper S that has been printed.

<Carriage moving mechanism>
The carriage moving mechanism 30 is for moving the carriage CR to which the head unit 40 is attached in the carriage moving direction. The carriage movement direction includes a movement direction from one side to the other side and a movement direction from the other side to the one side. The head unit 40 has a head 41. Therefore, the carriage movement direction corresponds to the head movement direction (predetermined direction) in which the head 41 moves. The carriage moving mechanism 30 corresponds to a head moving unit that moves the head 41 in a predetermined direction. The carriage moving mechanism 30 includes a carriage motor 31, a guide shaft 32, a timing belt 33, a driving pulley 34, and a driven pulley 35. The carriage motor 31 corresponds to a drive source for moving the carriage CR. The operation of the carriage motor 31 is controlled by the printer-side controller 70. A drive pulley 34 is attached to the rotation shaft of the carriage motor 31. The drive pulley 34 is disposed on one end side in the carriage movement direction. A driven pulley 35 is disposed on the other end side in the carriage movement direction on the opposite side to the drive pulley 34. The timing belt 33 is connected to the carriage CR and is spanned between a driving pulley 34 and a driven pulley 35. The guide shaft 32 supports the carriage CR in a movable state. The guide shaft 32 is attached along the carriage movement direction. Accordingly, when the carriage motor 31 operates, the carriage CR moves along the guide shaft 32 in the carriage movement direction. Along with this, the head 41 also moves in the head moving direction.

<Head unit>
The head unit 40 is for ejecting ink toward the paper S. The head unit 40 includes a head 41 and a head controller HC. Here, FIGS. 4A to 4C describe the head 41. FIG. 4A is an external view of the head 41. FIG. 4B is a cross-sectional view for explaining the structure of the head 41. FIG. 4C is a cross-sectional view showing a part of the head 41 in an enlarged manner. For convenience, the head 41 will be described here, and the head controller HC will be described later.

  As shown in FIG. 4A, the head 41 includes a nozzle row composed of a plurality of nozzles # 1 to # 180 for each of yellow (Y), magenta (M), cyan (C), and black (K), that is, A cyan nozzle row 211C, a magenta nozzle row 211M, a yellow nozzle row 211Y, and a black nozzle row 211K are provided.

  The nozzles # 1 to # 180 of the nozzle rows 211C, 211M, 211Y, and 211K are arranged in a line in a straight line at intervals from each other along a predetermined direction (here, the transport direction of the paper S). ing. The nozzle rows 211C, 211M, 211Y, and 211K are arranged in parallel with each other at a predetermined interval along the moving direction of the head 41. Each nozzle # 1 to # 180 is provided with a piezo element (not shown) as a drive element for ejecting ink droplets. This piezo element corresponds to a piezoelectric element.

  When a voltage having a predetermined time width is applied between the electrodes provided at both ends of the piezoelectric element, the piezoelectric element expands according to the voltage application time and deforms the side wall of the ink flow path. As a result, the volume of the ink flow path contracts in accordance with the expansion and contraction of the piezo element, and the ink corresponding to this contraction becomes ink droplets, and each nozzle # 1 of each color nozzle row 211C, 211M, 211Y, 211K. It is discharged from ~ # 180.

<Structure of head 41>
As shown in FIG. 4B, the head 41 includes a case 411, a flow path unit 412, and a piezo element unit 413. The case 411 is a block-shaped member in which an accommodation chamber 411a for accommodating the piezo element unit 413 is formed. The piezo element unit 413 is attached to each of the nozzle rows 211C, 211M, 211Y, and 211K. For this reason, the case 411 is provided with four storage chambers 411a, and the four piezoelectric element units 413 are stored in the storage chambers 411a.

  As shown in FIG. 4C, the flow path unit 412 is bonded to the flow path forming plate 412a, the elastic plate 412b bonded to one surface of the flow path forming plate 412a, and the other surface of the flow path forming plate 412a. Nozzle plate 412c. The flow path forming plate 412a is made of a silicon wafer, a metal plate, or the like. The flow path forming plate 412a is formed with a groove portion serving as a pressure chamber 412d, a through hole serving as a nozzle communication port 412e, a through port serving as a common ink chamber 412f, and a groove portion serving as an ink supply path 412g. The elastic plate 412b has a support frame 412h and an island portion 412j to which the tip of the piezo element PZT is joined. An elastic region is formed by the elastic film 412i around the island portion 412j.

  The piezo element unit 413 includes a piezo element group 413a and an adhesive substrate 413b. The piezo element group 413a has a comb shape, and each comb-like portion corresponds to the piezo element PZT. The piezo element group 413a includes a number of piezo elements PZT corresponding to the nozzles Nz (nozzles # 1 to # 180). That is, here, since the number of nozzles Nz (nozzles # 1 to # 180) is 180, the piezo element group 413a has 180 piezo elements PZT. The bonding substrate 413b is a rectangular plate. The piezoelectric element group 413a is bonded to one surface, and the other surface is bonded to the case 411. The piezo element PZT is deformed by applying a potential difference between opposing electrodes. In this example, it expands and contracts in the longitudinal direction of the element. The amount of expansion / contraction is determined according to the potential of the piezo element PZT. The potential of the piezo element PZT is determined by the applied main drive signal COM. The main drive signal COM will be described in detail later. Accordingly, the piezo element PZT expands and contracts according to the potential of the applied main drive signal COM.

  When the piezo element PZT expands and contracts, the island portion 412j is pushed toward the pressure chamber 412d or pulled in the opposite direction. At this time, since the elastic film 412i around the island portion 412j is deformed, ink can be efficiently discharged from the nozzles Nz (nozzles # 1 to # 180).

<Head control unit HC>
Next, the head controller HC will be described. Here, FIG. 5 is a block diagram for explaining the configuration of the head controller HC. The head controller HC includes a first shift register 81A, a second shift register 81B, a first latch circuit 82A, a second latch circuit 82B, a decoder 83, a control logic 84, and a head side switch 85. . Each part excluding the control logic 84, that is, the first shift register 81A, the second shift register 81B, the first latch circuit 82A, the second latch circuit 82B, the decoder 83, and the head-side switch 85 are respectively provided for each piezo element PZT. That is, it is provided for each nozzle Nz (nozzles # 1 to # 180).

  The head controller HC controls the operation of the head 41 to eject ink based on the pixel data SI from the printer controller 70. Specifically, the printer-side controller 70 transmits pixel data SI to the head controller HC. The head controller HC receives the pixel data SI sent from the printer-side controller 70, and sequentially stores the pixel data SI in the first shift register 81A or the second shift register 81B. Then, the head controller HC sequentially transfers the pixel data SI stored in the first shift register 81A or the second shift register 81B to the first latch circuit 82A or the second latch circuit 82B. The decoder 83 generates a switch control signal SW for controlling the head-side switch 85 based on the pixel data SI transferred to the first latch circuit 82A or the second latch circuit 82B. The switch control signal SW generated here is output to the head-side switch 85. The switch control signal SW is used to selectively apply a necessary portion of the main drive signal COM to the piezo element PZT, and the head-side switch 85 is turned on / off according to the switch control signal SW. As a result, the head controller HC controls the application of the main drive signal COM to the piezo element PZT.

<Main drive signal COM>
FIG. 6 is a diagram illustrating the main drive signal COM. As shown in FIG. 6, the main drive signal COM is generated in the first waveform section SS1 generated in the period T1 in the repetition period T, the second waveform section SS2 generated in the period T2, and the first waveform section SS2 generated in the period T3. 3 waveform portions SS3. The first waveform section SS1 has a drive pulse PS1. The second waveform section SS2 has a drive pulse PS2, and the third waveform section SS3 has a drive pulse PS3. Here, the drive pulse PS1, the drive pulse PS2, and the drive pulse PS3 are used when ink is ejected from the nozzles Nz (nozzles # 1 to # 180), and have the same waveform. These drive pulses PS1 to PS3 correspond to a waveform portion for operating the piezo element PZT, and the potential waveform thereof is determined based on the operation to be performed by the piezo element PZT. Therefore, the potential waveform of the included drive pulse, the number included in the repetition period T, and the like can be determined as appropriate.

<Application control of main drive signal COM>
Next, application control of the main drive signal COM by the head controller HC will be described. Here, FIG. 7 is a timing chart for explaining the application control of the main drive signal COM. In the following description, FIG. 5 is also referred to. In the printer 1, the pixel data SI is composed of 2 bits, and the content is determined for each nozzle Nz (for each piezo element PZT). The pixel data SI is sent to the head controller HC in synchronization with the transfer clock CLK. The upper bit group of the pixel data SI is set in each first shift register 81A, and the lower bit group is set in each second shift register 81B. A first latch circuit 82A is connected to the first shift register 81A, and a second latch circuit 82B is connected to the second shift register 81B. Here, when the latch signal LAT from the printer-side controller 70 becomes H level, each first latch circuit 82A latches the upper bit of the corresponding pixel data SI, and each second latch circuit 82B holds the lower bit of the pixel data SI. Latch. Pixel data SI (a set of upper bits and lower bits) latched by the first latch circuit 82A and the second latch circuit 82B is input to the decoder 83, respectively.

  The decoder 83 performs decoding based on the upper and lower bits of the pixel data SI and outputs a switch control signal SW for controlling the head side switch 85. That is, the control logic 84 simultaneously outputs selection data q0 to q3 corresponding to the amount of ink to be ejected, and the decoder 83 converts one selection data out of these selection data q0 to q3 into pixel data SI. Is selected and output as a switch control signal SW. Here, the selection data q0 is selection data for no dot. That is, the selection data q0 is selection data that becomes the switch control signal SW when dots are not formed on the paper S. The selection data q1 is selection data for small dots. That is, the selection data q1 is selection data that becomes the switch control signal SW when forming small dots on the paper S. Similarly, selection data q2 is selection data for medium dots, and selection data q3 is selection data for large dots. Accordingly, when the pixel data SI is data [00] indicating no dot, the decoder 83 uses the selection data q0 as the switch control signal SW, and when the pixel data SI is data [01] indicating formation of a small dot, the selection data Let q1 be the switch control signal SW. The same applies to the formation of medium dots and large dots.

  Further, the control logic 84 updates the contents of the selection data q0 to q3 at a timing determined by the latch signal LAT and the change signal CH. For example, the selection data q0 is data [0] in a period (corresponding to the period T1) from the timing when the latch signal LAT becomes H level to the time when the first change signal CH becomes H level. The data [0] is a period (corresponding to the period T2) from the timing when the first change signal CH becomes H level to the time when the second change signal CH becomes H level. Similarly, data [0] in a period (corresponding to the period T3) from the timing when the second change signal CH becomes H level to the time when the latch signal LAT of the next repetition period T becomes H level. Similarly, the selection data q1 is updated in the order of [0], [1], [0], and the selection data q2 is updated in the order of [1], [1], [0]. The selected data q3 is updated in the order of [1], [1], [1].

  The switch control signal SW output from the decoder 83 is input to the head side switch 85. The head-side switch 85 applies the main drive signal COM to the piezo element PZT during the ON period. Therefore, the main drive signal COM from the drive signal generation circuit 50 is applied to the input side of the head side switch 85, and the piezo element PZT is connected to the output side of the head side switch 85. When the switch control signal SW is data [1], the head-side switch 85 is turned on and the main drive signal COM is applied to the piezo element PZT. When the switch control signal SW is data [0], the head-side switch 85 is turned off, so that the main drive signal COM is not applied to the piezo element PZT. As described above, the piezo element PZT maintains the potential immediately before the stop when the application of the main drive signal COM is stopped. Therefore, during the period in which the application of the main drive signal COM is stopped, the piezo element PZT maintains the deformed state immediately before the application of the main drive signal COM is stopped.

<Detector group>
The detector group 60 is for monitoring the status of the printer 1. As shown in FIGS. 3A and 3B, the detector group 60 includes a linear encoder 61, a rotary encoder 62, a paper detector 63, and a paper width detector 64. The linear encoder 61 is for detecting the position of the carriage CR in the carriage movement direction. The rotary encoder 62 is for detecting the rotation amount of the transport roller 23. The paper detector 63 is for detecting the paper S to be printed. The paper width detector 64 is for detecting the width of the paper S to be printed.

<Printer side controller>
The printer-side controller 70 controls each unit included in the printer 1. For example, the printer-side controller 70 alternately performs an operation of transporting the paper S by a predetermined transport amount and an operation of intermittently ejecting ink while moving the carriage CR (head 41). Is printing an image. Therefore, the printer-side controller 70 controls the conveyance of the paper S by controlling the rotation amount of the conveyance motor 22. The printer-side controller 70 controls the movement of the carriage CR by controlling the rotation of the carriage motor 31. Furthermore, the pixel data SI is output to the head controller HC to perform control for ejecting ink. In addition, the printer-side controller 70 also performs control to output a DAC value (potential designation information, which will be described later) as generation information for the main drive signal COM to the drive signal generation circuit 50.

  As shown in FIG. 2, the printer-side controller 70 includes an interface unit 71, a CPU 72, a memory 73, and a control unit 74. The interface unit 71 exchanges data with the computer 110 which is an external device. The CPU 72 is an arithmetic processing unit for performing overall control of the printer 1. The memory 73 is for securing an area for storing a program of the CPU 72, a work area, and the like, and is configured by a storage element such as a RAM, an EEPROM, or a ROM. Then, the CPU 72 controls each control target unit in accordance with the computer program stored in the memory 73. For example, the CPU 72 controls the paper transport mechanism 20 and the carriage movement mechanism 30 via the control unit 74. For example, control signals for the transport motor 22 and the carriage motor 31 are output. Further, the CPU 72 outputs a head control signal (clock CLK, pixel data SI, latch signal LAT, change signal CH, see FIG. 6) for controlling the operation of the head 41 to the head controller HC, or DAC. A value and a PWM control signal are output to the drive signal generation circuit 50.

<Drive signal generation circuit>
The drive signal generation circuit 50 that generates the main drive signal COM will be described. FIG. 8A illustrates an example of the drive signal generation circuit 50. The drive signal generation circuit 50 includes a waveform generation circuit 91 and a current amplification circuit 92 as shown in FIG. FIG. 8B is a diagram for explaining the relationship between the DAC value input to the waveform generation circuit 91 and the output voltage output from the waveform generation circuit 91.

  The waveform generation circuit 91 includes a D / A converter 911 and a voltage amplification circuit 912. The D / A converter 911 is a circuit that outputs an analog signal ANG corresponding to the DAC value. This DAC value is information for instructing a voltage to be output from the voltage amplifier circuit 912 (hereinafter also referred to as output voltage), and is output from the CPU 72 based on the waveform data stored in the memory 73. In the present embodiment, the DAC value is composed of 10-bit data, but for the sake of convenience, it is represented in hexadecimal in the figure.

  The voltage amplification circuit 912 amplifies the analog signal ANG from the D / A converter 911 to a voltage suitable for the operation of the piezo element PZT. In the voltage amplification circuit 912 of this embodiment, the output voltage from the D / A converter 911 is amplified to a maximum of 40 volt. The amplified output voltage is output to the current amplifier circuit 92 as the reference signal SQ.

  For example, when the DAC value input from the CPU 72 to the D / A converter 911 is “24Eh” in hexadecimal (in the case of “1001001110” in binary), the output voltage after being amplified by the voltage amplification circuit 912 is 25V. It becomes. When the DAC value input from the CPU 72 to the D / A converter 911 is “0h” in hexadecimal (in the case of “0000000” in binary), the output voltage after being amplified by the voltage amplification circuit 912 is 1. When the input DAC value is “3FF” in hexadecimal (in the case of “1111111111” in binary), the output voltage after being amplified by the voltage amplification circuit 912 is 42.32V. That is, the minimum output voltage of the waveform generation circuit 91 is 1.4V, and when the DAC value input from the CPU 72 increases by one, the output voltage of the waveform generation circuit 91 increases by 0.04V.

  FIG. 9 is a conceptual diagram for explaining the generation of the analog signal ANG by the D / A converter 911. In the example of FIG. 9, the CPU 72 outputs a DAC value corresponding to the potential V1 at timing t (n). Thereby, in the update cycle τ (n), the analog signal ANG output from the D / A converter 911 becomes the potential V1. The DAC values corresponding to the potential V1 are sequentially output until the update period τ (n + 4). For this reason, the analog signal ANG maintains the potential V1. Further, at the timing t (n + 5), the DAC value corresponding to the potential V2 is output. Thereby, the analog signal ANG falls from the potential V1 to the potential V2 in the update cycle τ (n + 5). Similarly, at the timing t (n + 6), the DAC value corresponding to the potential V3 is output. Thereby, the analog signal ANG drops from the potential V2 to the potential V3 in the update cycle τ (n + 6). Similarly, since the DAC value is output in the same manner, the potential of the analog signal ANG gradually decreases. Then, the analog signal ANG becomes the potential V4 in the update cycle τ (n + 10). When the waveform generation circuit 91 having such a D / A converter 911 is used, the potential of the analog signal ANG can be changed by designating the DAC value, so that the main drive signal COM suitable for the ink to be ejected can be easily generated. be able to.

  As shown in FIG. 8A, the current amplifier circuit 92 is a circuit for supplying a sufficient current so that a large number of piezo elements PZT can operate without any trouble. The current amplifier circuit 92 includes a transistor pair 921. The transistor pair 921 includes an NPN transistor Q1 and a PNP transistor Q2 whose emitter terminals are connected to each other. The NPN transistor Q1 is a transistor that operates when the voltage of the drive signal increases. The NPN transistor Q1 has a collector terminal connected to the power supply side and an emitter terminal connected to the drive signal output signal line side. The PNP transistor Q2 is a transistor that operates when the voltage drops. The PNP transistor Q2 has its collector terminal connected to the ground (earth) side and its emitter terminal connected to the output signal line side of the drive signal. Note that the voltage at the portion where the emitters of the NPN transistor Q1 and the PNP transistor Q2 are connected to each other (the voltage of the main drive signal COM) is fed back to the voltage amplifier circuit 912, as indicated by the symbol FB. .

  The operation of the current amplification circuit 92 is controlled by the output voltage from the waveform generation circuit 91. For example, when the output voltage is in the rising state, the NPN transistor Q1 is turned on by the reference signal SQ. Along with this, the current I1 flows and the voltage of the main drive signal COM also rises. On the other hand, when the output voltage is in a drop state, the PNP transistor Q2 is turned on by the reference signal SQ. Along with this, the current I2 flows and the voltage of the main drive signal COM also drops. Note that when the output voltage is constant, both the NPN transistor Q1 and the PNP transistor Q2 are turned off. As a result, the main drive signal COM becomes a constant voltage.

  The base terminals of the transistors Q1 and Q2 correspond to “control terminals” of the transistors. The emitter terminals of the transistors Q1 and Q2 correspond to “output terminals” of the transistors. The collector terminals of the transistors Q1 and Q2 correspond to “current supply terminals” of the transistors.

  Here, the case where two types of bipolar transistors, ie, an NPN type transistor Q1 and a PNP type transistor Q2 are provided as transistors has been described as an example. However, in the current amplification circuit 92, an electric field is used as a transistor. An effect transistor (FET: field effect transistor) may be provided. In this case, the gate of the field effect transistor (FET) corresponds to the “control terminal”. The source of the field effect transistor (FET) corresponds to the “output terminal”. The drain of the field effect transistor (FET) corresponds to a “current supply terminal”. In addition, any type of transistor may be used as long as the transistor generates a main drive signal by amplifying the reference signal SQ.

=== Conventional problems ===
However, such a drive signal generation circuit 50 has the following problems. That is, there is a problem that the power consumption of the transistors Q1 and Q2 of the transistor pair 921 is large. This is because the collector terminal of the transistor Q1 is set to a potential higher than the maximum potential of the main drive signal COM in order to operate the transistors Q1 and Q2 normally, and the collector terminal of the transistor Q2 is set to the main drive signal COM. This is because the potential is set lower than the minimum potential. The power consumption of each transistor Q1, Q2 is mainly determined by the product of the collector current and the collector-emitter voltage. When the potential difference between the collector terminal and the emitter terminal increases due to the potential change of the main drive signal COM, the power consumption in the transistor Q1 or transistor Q2 increases, and the high temperature state occurs due to the heat generated in the transistor Q1 or transistor Q2. Sometimes occurred.

=== Solution ===
In the present embodiment, in order to solve such a problem, an auxiliary drive signal generation circuit that generates an auxiliary drive signal is provided, and the auxiliary drive signal generated by the auxiliary drive signal generation circuit is used as a transistor of the drive signal generation circuit 50. The power is supplied to the collector terminals of Q1 and Q2, thereby reducing the power consumption of the transistors Q1 and Q2. Here, the auxiliary drive signal is a signal generated in order to reduce the power consumption of the transistors Q1 and Q2. Here, as the auxiliary drive signal, a signal whose potential changes prior to the change of the signal level of the reference signal SQ input to the base terminals of the transistors Q1 and Q2 is generated. That is, a signal having a signal waveform approximate to the signal waveform of the reference signal SQ is generated as an auxiliary drive signal. The auxiliary drive signal generation circuit generates such an auxiliary drive signal and supplies the auxiliary drive signal to the collector terminals of the transistors Q1 and Q2, so that the connection between the collector terminals of the transistors Q1 and Q2 and the emitter terminals of the transistors Q1 and Q2 is performed. The potential difference can be reduced. As a result, power consumption of the transistors Q1 and Q2 can be reduced.

=== Auxiliary drive signal ===
Here, an example of the auxiliary drive signal generated by the auxiliary drive signal generation circuit will be described. FIG. 10 shows an example of signal waveforms of the auxiliary drive signal SV and the reference signal SQ.

  The reference signal SQ is a signal for operating a piezoelectric element, here, a piezoelectric element provided in each of the nozzles # 1 to # 180. As shown in the figure, the reference signal SQ of the present embodiment includes a first interval P1 in which the potential gradually increases linearly from the minimum potential VL to the intermediate potential VM, and a second interval P2 in which the intermediate potential VM is held. The third section P3 in which the potential gradually increases linearly from the intermediate potential VM to the maximum potential VH, the fourth section P4 in which the maximum potential VH is held, and the potential suddenly from the maximum potential VH to the minimum potential VL. It has the 5th section P5 which falls and the 6th section P6 in which minimum electric potential VL is held. Here, the minimum potential VL, the intermediate potential VM, and the maximum potential VH are respectively predetermined potentials. The reference signal SQ is generated by repeating the period with the first period P1 to the sixth period P6 as one period.

  On the other hand, the auxiliary drive signal SV is a signal generated by the auxiliary drive signal generation circuit 52 in order to reduce the potential difference between the collector terminals of the transistors Q1 and Q2 and the emitter terminals of the transistors Q1 and Q2. . The auxiliary drive signal SV generated here is generated as a signal whose potential changes prior to the change in potential of the reference signal SQ. That is, the signal waveform of the auxiliary drive signal SV is formed according to the signal waveform of the reference signal SQ.

  Here, the auxiliary drive signal SV is a first potential in which the potential gradually increases from the first potential V1 slightly lower than the minimum potential VL of the reference signal SQ to the second potential V2 slightly higher than the intermediate potential VM of the reference signal SQ. The first section D1, the second section D2 in which the second potential V2 is held, and the third potential in which the potential gradually increases from the second potential V2 to the third potential V3 that is slightly higher than the maximum potential VH of the reference signal SQ. A section D3, a fourth section D4 in which the third potential V3 is held, a fifth period D5 in which the potential gradually drops from the third potential V3 and reaches a potential V4 lower than the first potential V1, and a reference signal And a sixth section D6 in which a potential lower than the minimum potential VL of SQ is held.

  The first section D1 is formed corresponding to the first section P1 of the reference signal SQ. The second section D2 is formed corresponding to the second section P2 of the reference signal SQ. The third section D3 is formed corresponding to the third section P3 of the reference signal SQ. The fourth section D4 is formed corresponding to the fourth section P4 of the reference signal SQ. The fifth section D5 is formed corresponding to the fifth section P5 of the reference signal SQ. The sixth section D6 is formed corresponding to the sixth section P6 of the reference signal SQ.

  In the first section D1 to the fourth section D4, the potential of the auxiliary drive signal SV is formed to be slightly higher than the potential of the reference signal SQ. On the other hand, in the fifth section D5 to the sixth section D6, the potential of the auxiliary drive signal SV is formed to be slightly lower than the potential of the reference signal SQ. This is for the following reason. That is, the NPN transistor Q1 of the transistor pair 921 is operated between the first section D1 and the fourth section D4. In order to operate the NPN transistor Q1, it is necessary to supply a signal having a potential higher than that of the reference signal SQ to the collector terminal of the transistor Q1 as the auxiliary drive signal SV. In addition, the PNP transistor Q2 of the transistor pair 921 is operated between the fifth section D5 and the sixth section D6. In order to operate the PNP transistor Q2, it is necessary to supply a signal having a potential lower than that of the reference signal SQ to the collector terminal of the transistor Q2 as the auxiliary drive signal SV.

  By generating the auxiliary drive signal SV having such a waveform, between the collector terminals of the transistors Q1 and Q2 to which the auxiliary drive signal SV is input and the emitter terminals of the transistors Q1 and Q2 to which the reference signal SQ is input. The potential difference can be reduced. As a result, power consumption generated in the transistors Q1 and Q2 can be suppressed.

=== Auxiliary Drive Signal Generation Circuit ===
Next, an example of an auxiliary drive signal generation circuit that generates such an auxiliary drive signal SV will be described. This auxiliary drive signal generation circuit has an LC resonance circuit in which an inductance and a capacitor are connected in series. The auxiliary drive signal generation circuit generates an auxiliary drive signal by resonance of the LC resonance circuit. Specifically, in this auxiliary drive signal generation circuit, current is supplied to the capacitor through the inductance, and the capacitor is gradually charged. Then, the charge accumulated in the capacitor by this charging is discharged through the inductance, and the capacitor is discharged. The voltage between the terminals of the capacitor is supplied as an auxiliary drive signal to the collector terminals of the transistors Q1 and Q2 of the drive signal generation circuit. As a result, the auxiliary drive signal generation circuit generates a signal whose potential changes prior to the change in the signal level of the signal waveform of the reference signal SQ input to the base terminals of the transistors Q1 and Q2.

<Specific circuit configuration>
FIG. 11 illustrates an embodiment of the auxiliary drive signal generation circuit 52. The auxiliary drive signal generation circuit 52 includes capacitors C1, C2, C3, and C4, inductances L1, L2, and L3, switch elements M1, M2, and M3, diodes D1, D2, D3, D4, and D5, and a resistor R1. , R2, R3, and R4. Here, the switch elements M1, M2, and M3 are configured by field effect transistors (FETs). Specifically, the switch elements M1 and M2 are configured by P-channel field effect transistors. On the other hand, the switch element M3 is composed of an N-channel field effect transistor. The switch elements M1 and M2 correspond to the first switch element. The switch element M3 corresponds to a second switch element. The diodes D1, D2, D3, D4, and D5 are Schottky barrier diodes.

  In addition, the capacitor | condenser Cz in a figure shows the electrostatic capacitance of a piezoelectric element (piezo element). That is, in the present embodiment, the main drive signal COM is generated by one drive signal generation circuit 50 for the piezoelectric elements provided in the nozzles # 1 to # 180, and therefore the capacitor Cz has 1 to 180 piezoelectric elements. It represents the capacitance of the element. The capacitance of the capacitor Cz varies each time depending on the number of nozzles that eject ink. Further, IN1, IN2, and IN3 in the figure are signals for turning ON / OFF the respective switch elements M1, M2, and M3.

  The switch element M1, the inductance L1, the inductance L3, and the switch element M3 are sequentially connected in series between the power supply (here 42V) side and the ground (ground) side. The switch element M2 and the inductance L2 are connected in series with each other, and are connected in parallel to the switch element M1 and the inductance L1. The capacitor C4 is connected in parallel to the inductance L3 and the switch element M3.

  Furthermore, a diode D1 is interposed between the switch element M1 and the inductance L1 and between the ground (ground) side. Here, the cathode terminal of the diode D1 is connected between the switch element M1 and the inductance L1, and the anode terminal thereof is connected to the ground (ground) side. A diode D2 is interposed between the switch element M2 and the inductance L2 and between the ground (ground). Here, the cathode terminal of the diode D2 is connected between the switch element M2 and the inductance L2, and the anode terminal thereof is connected to the ground (ground) side. A diode D5 is interposed between the inductance L3 and the switch element M3 and between the power source (42V in this case). Here, the cathode terminal of the diode D5 is connected to the power source (42V in this case), and the anode terminal thereof is connected between the inductance L3 and the switch element M3.

  The inductance L1 and the inductance L2 have different constants, and the inductance L1 is larger. Therefore, as will be described later, when resonating with the capacitor C4, the resonance period is longer when the inductance L1 is used. Here, the inductance L3 is the same inductance as the inductance L2.

  Furthermore, a resistor R1 and a capacitor C1 are connected in series to the inductance L1, and are connected in parallel to the inductance L1. In addition, a resistor R2 and a capacitor C2 are connected in series to the inductance L2, and are connected in parallel to the inductance L2. In addition, a resistor R3 and a capacitor C3 are connected in series to the inductance L3, and are connected in parallel to the inductance L3. These resistors R1, R2, and R3 and capacitors C1, C2, and C3 are connected between the terminals of the respective inductances L1, L2, and L3 when the current flowing through the respective inductances L1, L2, and L3 is cut off due to a change in current (dI / dt). Although the voltage suddenly becomes zero, the voltage between the terminals of the inductances L1, L2, and L3 vibrates at a high frequency because there is actually a stray capacitance. The vibration capacitors C1, C2, and C3 are provided to lower the vibration frequency and the resistors R1, R2, and R3 are used to quickly attenuate the vibration. That is, the resistor R1 and the capacitor C1 are provided in order to suppress the oscillation of the voltage across the inductance L1. Further, the resistor R2 and the capacitor C2 are provided in order to suppress the vibration of the inter-terminal voltage of the inductance L2. Further, the resistor R3 and the capacitor C3 are provided in order to suppress the vibration of the voltage between the terminals of the inductance L3.

  The terminal on the power source side of the capacitor C4 is connected to the collector terminals of the transistors Q1 and Q2 via diodes D3 and D4, respectively. That is, the voltage across the capacitor C4 is input to the collector terminals of the transistors Q1 and Q2 as the auxiliary drive signal SV. The diode D3 is interposed between the power supply side terminal of the capacitor C4 and the collector terminal of the transistor Q1. Specifically, the diode D3 has its anode terminal connected to the power supply side terminal of the capacitor C4 and its cathode terminal connected to the collector terminal of the transistor Q1. The diode D4 is interposed between the power supply side terminal of the capacitor C4 and the collector terminal of the transistor Q2. Specifically, the diode D4 has an anode terminal connected to the collector terminal of the transistor Q2, and a cathode terminal connected to the power supply side terminal of the capacitor C4. These diodes D3 and D4 define the direction of current flowing between the collector terminals of the transistors Q1 and Q2 and the power supply side terminal of the capacitor C4.

  When the switch element M1 is turned on, a current flows through the inductance L1, charges are accumulated in the capacitor C4, and the capacitor C4 is charged. Therefore, the voltage across the capacitor C4 gradually increases. That is, the inductance L1 and the capacitor C4 constitute an LC resonance circuit. When the switch element M2 is turned on, a current flows through the inductance L2, charges are accumulated in the capacitor C4, and the capacitor C4 is charged. Thereby, the voltage between terminals of the capacitor C4 gradually increases. That is, the inductance L2 and the capacitor C4 constitute an LC resonance circuit. On the other hand, when the switch element M3 is turned on, a current flows from the capacitor C4 through the inductance L3, and electric charge is discharged from the capacitor C4. That is, the capacitor C4 is discharged. Thereby, the voltage between terminals of the capacitor C4 gradually decreases. That is, the inductance L3 and the capacitor C4 constitute an LC resonance circuit.

<Auxiliary drive signal generation method>
Next, a method for generating the auxiliary drive signal SV by the auxiliary drive signal generation circuit 52 will be described. FIG. 12 illustrates a method for generating the auxiliary drive signal SV. Here, a method of generating the auxiliary drive signal SV will be described with reference to FIG.

  First, the first section D1 will be described. The first section D1 corresponds to the first section P1, but the first section P1 is used in two cases. That is, (1) When printing is not performed, the auxiliary drive signal SV is set to the ground level and the reference signal SQ is set to the potential VL, but the reference signal SQ is set to the potential VM that is a potential at the start of the repetition period of FIG. I will lift it up. (2) Prior to the end of the sections T1, T2, and T3 in FIG. 6, the reference signal SQ is raised from the potential VL to the potential VM.

  In the first section D1, the switch element M1 is turned on here (see FIG. 12). The switching element M1 is turned on in response to an operation in which the potential of the reference signal SQ starts to rise from the minimum potential VL to the intermediate potential VM. The timing for turning on the switch element M1 is set to a timing slightly earlier than the timing at which the potential of the reference signal SQ starts to rise. The other switch elements M2 and M3 are left off here. When the switch element M1 is turned on, as shown in FIG. 11, a current flows from the power source side (42V in this case) to the inductance L1 through the switch element M1, and the current is supplied to the capacitor C4. For this reason, electric charge is accumulated in the capacitor C4, and the capacitor C4 is charged. As a result, the voltage across the terminals of the capacitor C4 (hereinafter referred to as “C potential”) gradually increases prior to the fluctuation of the potential of the reference signal SQ.

  The switch element M1 is turned off after a predetermined time T1 has elapsed since it was turned on. Even after the switch element M1 is turned off, current continues to flow through the inductance L1. This is due to the energy to flow the current stored in the inductance L1. The current flowing through the inductance L1 is supplied from the ground side through the diode D1. As a result, a current is supplied to the capacitor C4 even after the switch element M1 is turned off, and the voltage across the terminals of the capacitor C4 (“C potential”) further increases.

  Thereafter, the magnitude of the current flowing through the inductance L1 gradually decreases. For this reason, the voltage between the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. In this way, the first section D1 of the signal waveform of the auxiliary drive signal SV is formed (see FIG. 12). Here, when the current flowing through the inductance L1 is cut off, the rate of change (dI / dt) of the current suddenly becomes 0, and a large potential fluctuation (ground → “C potential”) occurs at the power supply side terminal of the inductance L1. Even if this occurs, the resistance R1 and the capacitor C1 can suppress the vibration of the voltage across the terminal of the inductance L1.

  The terminal voltage (“C potential”) of the capacitor C4 is kept constant (potential V2) for a while. As a result, a second section D2 of the signal waveform of the auxiliary drive signal SV is formed (see FIG. 12). The length of the second section D2 may vary depending on the situation. That is, when the voltage is increased from the potential VL of the reference signal SQ when printing is not performed to the potential VM that is the potential at the start of the repetition period T, and the flat portions at the boundaries of the sections T1, T2, and T3, respectively. The length of can be different.

  Thereafter, the switch element M2 is turned on. The switch element M2 is turned on in advance before the potential of the reference signal SQ starts to rise from the intermediate potential VM to the maximum potential VH (see FIG. 12). When the switch element M2 is turned on in this way, a current flows from the power supply side (42V in this case) to the inductance L2 through the switch element M2, and the current is supplied to the capacitor C4. For this reason, electric charge is accumulated in the capacitor C4, and the capacitor C4 is charged. The voltage between the terminals of the capacitor C4 (“C potential”) further increases prior to the fluctuation of the potential of the reference signal SQ. Here, since the inductance L2 is an inductance smaller than the inductance L1, the resonance period with the capacitor C4 is short. That is, the rising direction of the “C potential” in the third section D3 is steeper than that in the first section D1. This is because the reference signal SQ is steeper in the third section P3 than in the first section P1.

  The switch element M2 is turned off after a predetermined time T2 has elapsed since it was turned on. Even after the switch element M1 is turned off, current continues to flow through the inductance L2. This is due to the energy to flow the current stored in the inductance L2. The current flowing through the inductance L1 is supplied from the ground side through the diode D2. As a result, a current is supplied to the capacitor C4 even after the switch element M2 is turned off, and the voltage across the terminals of the capacitor C4 (“C potential”) further increases.

  The magnitude of the current flowing through the inductance L2 gradually decreases, and the voltage between the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. Thereafter, the terminal voltage (“C potential”) of the capacitor C4 is kept constant. In this way, the third section D3 of the signal waveform of the auxiliary drive signal SV is formed (see FIG. 12). Here, when the current flowing through the inductance L2 is cut off, the rate of change of current (dI / dt) suddenly becomes 0, and a large potential fluctuation (ground → “C potential”) occurs at the power supply side terminal of the inductance L2. Even if this occurs, the resistance R2 and the capacitor C2 can suppress the oscillation of the voltage across the terminal of the inductance L2.

  The voltage between the terminals of the capacitor C4 (“C potential”) is kept constant for a while. As a result, a fourth section D4 of the signal waveform of the auxiliary drive signal SV is formed (see FIG. 12).

  Thereafter, the switch element M3 is turned on. The switch element M3 is turned on in advance before the potential of the reference signal SQ starts to drop from the maximum potential VH to the minimum potential VL (see FIG. 12). When the switch element M3 is turned on in this way, the electric charge accumulated in the capacitor C4 flows as a current into the inductance L3 and is discharged to the ground side via the inductance L3. As a result, the capacitor C4 is gradually discharged, and the voltage across the terminals of the capacitor C4 (“C potential”) drops abruptly prior to the fluctuation of the potential of the reference signal SQ.

  The switch element M3 is turned off after a predetermined time T3 has elapsed since it was turned on. Even after the switch element M3 is turned off, current continues to flow through the inductance L3. This is due to the energy to flow the current stored in the inductance L3. The current flowing through the inductance L3 is discharged to the power supply side (42V here) through the diode D5.

  The magnitude of the current flowing through the inductance L3 gradually decreases, and the voltage between the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. In this way, the fifth section D5 of the signal waveform of the auxiliary drive signal SV is formed (see FIG. 12). Here, when the current flowing through the inductance L3 is cut off, the rate of change (dI / dt) of the current suddenly becomes 0, and a large potential fluctuation (power supply (+ 42V)) occurs at the ground (ground) side terminal of the inductance L3. → "C potential"), the oscillation of the voltage across the terminal of the inductance L3 can be suppressed by the resistor R3 and the capacitor C3.

  After that, the voltage between the terminals of the capacitor C4 ("C potential") gradually increases from a potential lower than the minimum potential VL of the reference signal SQ to the ground level until the first section D1 starts again, and the auxiliary drive A sixth section D6 of the signal waveform of the signal SV is formed (see FIG. 12). In the sixth section D6, it is originally desirable that the auxiliary drive signal is always at the ground level, but the accuracy of the inductance and capacitance constants, the accuracy of the ON times T1, T2, and T3 of the switch elements M1, M2, and M3, Further, it is difficult to always make the ground level exactly because of the change of the capacitor Cz that cannot be avoided (which varies greatly depending on the number of ejection nozzles). Therefore, it is almost at the ground level. At this time, when the capacitor Cz is the maximum, it is only necessary to be at the ground level. Then, when the capacitor Cz is not the maximum, the auxiliary drive signal SV becomes lower than the ground at the end of the fifth section D5 (when the capacitor Cz is large, an effect close to that the capacitor Cz is in parallel with the capacitor C4). As a result, the current hardly flows from the capacitor C4, and the potential of the auxiliary drive signal SV in the fifth section D5 rises. When the auxiliary drive signal SV falls below the ground level, current flows from the ground to the capacitor C4 through the diode D1 and the inductance L1, and the potential of the auxiliary drive signal SV gradually approaches the ground level. In this way, the potential of the auxiliary drive signal SV at the end of the sixth section D6, and thus at the start of the first section D1, can be kept within an appropriate range.

  By inputting such an auxiliary drive signal SV to the collector terminals of the transistors Q1 and Q2, the potential difference between the collector terminals of the transistors Q1 and Q2 and the emitter terminals of the transistors Q1 and Q2 is reduced. Thereby, the power consumption of the transistors Q1 and Q2 can be significantly suppressed. The auxiliary drive signal generation circuit 52 is also ideally a circuit made up of an inductance, a capacitor, and a switch, and power consumption is zero.

  The capacitance of the capacitor C4 is preferably sufficiently larger than the total capacitance of the piezo elements PZT (piezoelectric elements) (here, the total capacitance of 180 piezo elements PZT). For example, the capacitance of the capacitor C4 is preferably set to 10 times or more the total capacitance of the piezo elements PZT (piezoelectric elements). This is because if the capacitance of the capacitor C4 is small, the auxiliary drive signal SV is greatly affected by fluctuations in the number of piezo elements PZT (piezoelectric elements) that are actually operated. If the capacitance of the capacitor C4 is set too large, power loss is caused in circuit elements and paths, which is not preferable.

  Further, by adjusting the times T1, T2, and T3 when the switch elements M1, M2, and M3 are turned on, the amount of fluctuation of the voltage between the terminals of the capacitor C4 (“C potential”) can be adjusted. That is, if the times T1, T2, and T3 when the switch elements M1, M2, and M3 are turned on are lengthened, the amount of variation in the voltage between the terminals of the capacitor C4 (“C potential”) increases, and the potential of the auxiliary drive signal SV It can be changed dynamically. Further, if the times T1, T2, and T3 when the switch elements M1, M2, and M3 are turned on are shortened, the amount of fluctuation in the voltage between the terminals of the capacitor C4 (“C potential”) is also small, and the potential fluctuation of the auxiliary drive signal SV. Can be suppressed.

  Further, the timing at which the voltage between the terminals of the capacitor C4 (“C potential”) fluctuates can be changed by changing the timing at which the switch elements M1, M2, and M3 are turned on. Thereby, the timing at which the potential of the auxiliary drive signal SV fluctuates can be changed.

  Further, by appropriately changing the magnitudes of the induction coefficients of the inductances L1, L2, and L3, it is possible to adjust the gradient of the potential change of the auxiliary drive signal SV. That is, if the induction coefficients of the inductances L1, L2, and L3 are increased, the slope of the potential change of the auxiliary drive signal SV can be made gentle. On the other hand, if the induction coefficients of the inductances L1, L2, and L3 are reduced, the gradient of the potential change of the auxiliary drive signal SV can be made steep.

  As described above, the times T1, T2, and T3 when the switch elements M1, M2, and M3 are turned on, the timing when the switch elements M1, M2, and M3 are turned on, and the induction coefficients of the inductances L1, L2, and L3 are appropriately changed. Thus, the auxiliary drive signal SV having a desired signal waveform can be generated.

  Here, the auxiliary drive signal generation circuit 52 includes the three inductances L1, L2, and L3 as the inductance of the LC resonance circuit, but the number of inductances is one or two. It may also be four or more.

  Similarly, the auxiliary drive signal generation circuit 52 includes one capacitor C4 as a capacitor of the LC resonance circuit here, but the number of capacitors may be two or more.

=== Second auxiliary driving signal generation circuit ===
<Problem>
By the way, in the auxiliary drive signal generation circuit 52 that generates the auxiliary drive signal SV described above, a waveform different from a desired waveform is generated due to an external factor such as a temperature or a surrounding environment, a variation in the configuration of the head 41, or the like. The reference signal SQ may be input to the base terminals of the transistors Q1 and Q2. Further, the reference signal SQ may be changed in setting, and a reference signal SQ having a different waveform may be input to the base terminals of the transistors Q1 and Q2. When the reference signals SQ having different waveforms are input to the base terminals of the transistors Q1 and Q2, as described above, a sufficient current is supplied to the collector terminals of the transistors Q1 and Q2 by the auxiliary auxiliary drive signal SV generated by the auxiliary drive signal generation circuit 52. There was a case where it could not be supplied.

  FIG. 13 illustrates an example in which a reference signal SQ having a different waveform is input to the collector terminals of the transistors Q1 and Q2. The auxiliary drive signal SV is the same signal as described with reference to FIG. Here, the maximum potential VH of the reference signal SQ is set to “about 25 V”, which is lower than the maximum potential VH (“38 (V)”) of the signal described in FIG. As described above, when the maximum potential VH of the reference signal SQ is lowered, in the fifth section D5 of the auxiliary drive signal SV, the potential of the auxiliary drive signal SV is higher than the potential of the reference signal SQ prior to the potential drop of the reference signal SQ. However, the auxiliary drive signal SV has a higher potential than the reference signal SQ. For this reason, no current flows through the collector terminal of the transistor Q2 (PNP transistor). Therefore, a period Tq in which the transistor Q2 does not perform a desired operation occurs in the fifth section D5.

  Thus, if the auxiliary drive signal SV having a predetermined potential for operating the transistors Q1 and Q2 is not input to the collector terminals of the transistors Q1 and Q2, respectively, the main drive signal COM cannot be generated properly. As a result, the piezoelectric element cannot be driven smoothly.

<Solution>
Therefore, in the piezoelectric element drive circuit of the present embodiment, the transistor Q1 when the potential of the auxiliary drive signal SV generated by the auxiliary drive signal generation circuit 52 does not fluctuate smoothly prior to the reference signal SQ. In order to supply a sufficient current to the collector terminal of Q2, a second auxiliary drive signal generation circuit is provided in addition to the above-described auxiliary drive signal generation circuit. The second auxiliary drive signal generation circuit generates an auxiliary drive signal different from the auxiliary drive signal SV generated by the auxiliary drive signal generation circuit 52. Hereinafter, the above-described auxiliary drive signal generation circuit 52 is referred to as a “first auxiliary drive signal generation circuit”. The second auxiliary drive signal generation circuit is referred to as a “second auxiliary drive signal generation circuit”. The auxiliary drive signal SV generated by the first auxiliary drive signal generation circuit 52 is referred to as a “first auxiliary drive signal” (SV). The auxiliary drive signal generated by the second auxiliary drive signal generation circuit is referred to as “second auxiliary drive signal” (ST1, ST2).

<Circuit configuration>
A circuit configuration of the second auxiliary drive signal generation circuit will be described. FIG. 14 shows an embodiment of the second auxiliary drive signal generation circuit 56. Here, the second auxiliary drive signal generation circuit 56 is configured by two circuit blocks, that is, a power supply side second auxiliary drive signal generation circuit 561 and a ground side second auxiliary drive signal generation circuit 562. The power supply side second auxiliary drive signal generation circuit 561 includes transistors Q3 and Q4, a resistor R6, a capacitor C6, and diodes D9 and D10. On the other hand, the ground side second auxiliary drive signal generation circuit 562 includes transistors Q5 and Q6, a resistor R7, a capacitor C7, and diodes D11 and D12. Among these, the diodes D10 and D12 are constituted by Zener diodes (constant voltage diodes). The diodes D9 and D11 are constituted by rectifier diodes. The transistors Q3 and Q4 are configured by NPN transistors. The transistors Q5 and Q6 are PNP transistors. Further, these transistors Q3, Q4, Q5, Q6 are each constituted by a bipolar transistor.

  In the power supply side second auxiliary drive signal generation circuit 561, the transistor Q3 is interposed between the collector terminal of the transistor Q1 and the power supply (42 V in this case) side. Here, the collector terminal of the transistor Q3 is connected to the power supply (42V in this case) side, and the emitter terminal is connected to the collector terminal of the transistor Q1. Further, the emitter terminal of the transistor Q4 is connected to the base terminal of the transistor Q3 via a diode D9 (rectifier diode). Diode D9 has its cathode terminal connected to the base terminal of transistor Q3 and its anode terminal connected to the emitter terminal of transistor Q4. The collector terminal of the transistor Q4 is connected to the collector terminal of the transistor Q3. That is, the collector terminal of the transistor Q4 is connected to the power supply (42V here) side. Thus, the transistor Q3 and the transistor Q4 are configured to be Darlington connected to each other. On the other hand, the base terminal of the transistor Q4 is connected to the signal line of the reference signal SQ via the Zener diode D10. Here, the Zener diode D10 has its cathode terminal connected to the base terminal of the transistor Q4 and its anode terminal connected to the signal line Lq of the reference signal SQ. As a result, a signal based on the reference signal SQ is input to the base terminal of the transistor Q4. Here, the Zener diode D10 is configured to hold a voltage of 3.6V. A capacitor C6 is connected in parallel with the Zener diode D10. A resistor R6 is connected as a bias resistor between the base terminal and the collector terminal of the transistor Q4.

  On the other hand, in the ground side second auxiliary drive signal generation circuit 562, the transistor Q5 is interposed between the collector terminal of the transistor Q2 and the ground (earth) side. Here, the transistor Q5 has its collector terminal connected to the ground (earth) side and its emitter terminal connected to the collector terminal of the transistor Q2. Further, the emitter terminal of the transistor Q6 is connected to the base terminal of the transistor Q5 via a diode D11 (rectifier diode). The diode D11 has an anode terminal connected to the base terminal of the transistor Q5 and a cathode terminal connected to the emitter terminal of the transistor Q6. The collector terminal of the transistor Q6 is connected to the collector terminal of the transistor Q5. That is, the collector terminal of the transistor Q6 is connected to the ground (earth) side. Thus, the transistor Q5 and the transistor Q6 are configured to be Darlington connected to each other. On the other hand, the base terminal of the transistor Q6 is connected to the signal line of the reference signal SQ via the Zener diode D12. Here, the Zener diode D12 has its anode terminal connected to the base terminal of the transistor Q6 and its cathode terminal connected to the signal line of the reference signal SQ. Here, the Zener diode D12 is configured to hold a voltage of 3.6V. Thus, a signal based on the reference signal SQ is input to the base terminal of the transistor Q6. A capacitor C6 is connected in parallel to the Zener diode D12. A resistor R6 is connected as a bias resistor between the base terminal and the collector terminal of the transistor Q6.

<Circuit operation>
The operation of the second auxiliary signal generation circuit 56 will be described. FIG. 15A is a diagram illustrating the circuit operation of the power supply side second auxiliary drive signal generation circuit 561. FIG. 15B is a diagram illustrating the circuit operation of the ground-side second auxiliary drive signal generation circuit 562.

  First, the circuit operation of the power supply side second auxiliary drive signal generation circuit 561 will be described. In the power supply side second auxiliary drive signal generation circuit 561, as shown in FIG. 15A, the base terminal of the transistor Q4 is connected to the signal line Lq of the reference signal via the Zener diode D10. On the other hand, the Zener diode D10 is supplied with current from the power source (here, 42V) via the resistor R6, and current flows. As a result, the terminal voltage (anode-cathode voltage) of the Zener diode D10 is held at the predetermined voltage Vd10. Therefore, a potential that is higher than the potential of the reference signal SQ by the inter-terminal voltage Vd10 of the Zener diode D10 is input to the base terminal of the transistor Q4.

  Transistor Q4 and transistor Q3 are connected to each other by Darlington via a diode D9. In order for both the transistor Q4 and the transistor Q3 to operate, the potential of the emitter terminal of the transistor Q3 needs to be sufficiently lower than the base terminal of the transistor Q4.

Here, the potential Ve of the emitter terminal of the transistor Q3 necessary for the operation of both the transistor Q4 and the transistor Q3 can be obtained by the following equation (1). Here, the potential of the reference signal SQ is assumed to be “Vsq”. The voltage across the Zener diode D10 is “Vd10”. Further, the voltage drop between the base and emitter of the transistor Q4 is assumed to be “Vq4”. Further, the voltage drop between the base and the emitter of the transistor Q3 is assumed to be “Vq3”. Further, the voltage drop between the terminals of the diode D9 (between the anode and cathode terminals) is assumed to be “Vd9”.
Ve1 = Vsq + Vd10-Vq4-Vd9-Vq3 ............ Formula (1)

  When the potential input to the collector terminal of the transistor Q1 by the first auxiliary drive signal SV (“C potential”) supplied from the first auxiliary drive signal generation circuit 52 via the diode D3 is higher than “Ve1”. These transistors Q4 and Q3 do not operate. On the other hand, the potential input to the collector terminal of the transistor Q1 by the first auxiliary drive signal SV (“C potential”) supplied from the first auxiliary drive signal generation circuit 52 via the diode D3 is higher than “Ve1”. When it is low, both the transistor Q4 and the transistor Q3 operate.

  When the transistor Q3 operates, a current flows between the collector and the emitter of the transistor Q3 from the power supply (42V here) side, and the current can be supplied to the collector terminal of the transistor Q1.

  The diode D9 is inserted to prevent a large reverse bias from being applied between the base and emitter of the transistors Q3 and Q4 when the base potential of the transistor Q4 is higher than the emitter potential of the transistor Q3. .

  Next, the circuit operation of the ground side second auxiliary drive signal generation circuit 562 will be described. The ground side second auxiliary drive signal generation circuit 562 also performs the same circuit operation as the power source side second auxiliary drive signal generation circuit 561. That is, in the ground side second auxiliary drive signal generation circuit 562, as shown in FIG. 15B, the base terminal of the transistor Q6 is connected to the signal line Lq of the reference signal via the Zener diode D12. On the other hand, current is supplied to the Zener diode D12 from the ground side via the resistor R7, and current flows. As a result, the terminal voltage (anode-cathode voltage) of the Zener diode D12 is held at a predetermined voltage. Therefore, a potential that is lower than the potential of the reference signal SQ by the voltage across the Zener diode D12 is input to the base terminal of the transistor Q6. Transistor Q6 and transistor Q5 are Darlington connected to each other via a diode D11. In order for both the transistor Q6 and the transistor Q5 to operate, the potential of the emitter terminal of the transistor Q5 needs to be sufficiently higher than the base terminal of the transistor Q6.

Here, the potential Ve of the emitter terminal of the transistor Q5 necessary for the operation of both the transistor Q6 and the transistor Q5 can be obtained by the following equation (2). Here, the potential of the reference signal SQ is assumed to be “Vsq”. The voltage across the Zener diode D12 is “Vd12”. The voltage drop between the base and emitter of the transistor Q6 is assumed to be “Vq6”. Further, the voltage drop between the base and emitter of the transistor Q5 is assumed to be “Vq5”. Further, the voltage drop between the terminals of the diode D11 (between the anode and cathode terminals) is assumed to be “Vd11”.
Ve2 = Vsq-Vd12 + Vq6 + Vd11 + Vq5 Equation (2)

  When the potential input to the collector terminal of the transistor Q2 by the first auxiliary drive signal SV (“C potential”) supplied from the first auxiliary drive signal generation circuit 52 via the diode D4 is lower than “Ve2”. In this case, the transistor Q6 and the transistor Q5 do not operate. On the other hand, the potential input to the collector terminal of the transistor Q2 by the first auxiliary drive signal SV (“C potential”) supplied from the first auxiliary drive signal generation circuit 52 via the diode D4 is higher than “Ve2”. When it is high, both the transistor Q6 and the transistor Q5 operate.

  When the transistor Q5 operates, the electric charge accumulated in the capacitor Cz flows as a current to the ground side via the collector-emitter of the transistor Q3. That is, a current can be supplied to the collector terminal of the transistor Q2.

  The diode D11 is inserted to prevent a large reverse bias from being applied between the base and emitter of the transistors Q6 and Q5 when the base potential of the transistor Q6 becomes lower than the emitter potential of the transistor Q5. .

<Second auxiliary drive signal>
Here, the second auxiliary drive signals ST1 and ST2 generated by the power supply side second auxiliary drive signal generation circuit 561 and the ground side second auxiliary drive signal generation circuit 562 will be described. FIG. 16 illustrates the second auxiliary drive signal ST1 generated by the power supply side second auxiliary drive signal generation circuit 561 and the second auxiliary drive signal ST2 generated by the ground side second auxiliary drive signal generation circuit 562. It is. Here, description will be made assuming that the first auxiliary drive signal SV from the first auxiliary drive signal generation circuit 52 is not input to the collector terminals of the transistors Q1 and Q2. That is, only the second auxiliary drive signals ST1 and ST2 generated by the power supply side second auxiliary drive signal generation circuit 561 and the ground side second auxiliary drive signal generation circuit 562 are input to the collector terminals of the transistors Q1 and Q2. .

  First, the second auxiliary drive signal ST1 generated by the power supply side second auxiliary drive signal generation circuit 561 will be described. As described with reference to FIG. 15A, the signal input to the base terminal of the transistor Q4 of the power supply side second auxiliary drive signal generation circuit 561 is the voltage drop of the Zener diode D10 with respect to the potential of the reference signal SQ (“Vd10 ]) Is a signal having a higher potential. Furthermore, if the transistor Q1 is not cut off, the signal output from the emitter terminal of the transistor Q3 of the power supply side second auxiliary drive signal generation circuit 561, that is, the second auxiliary drive signal ST1 is the base terminal of the transistor Q4. The voltage between the base and emitter of the transistor Q4 ("Vq4"), the voltage between the terminals of the diode D9 ("Vd9"), and the voltage between the base and emitter of the transistor Q3 ("Vq3" )) Is subtracted. These voltages Vq4, Vd9, and Vq3 are almost constant. The voltage between the terminals of the Zener diode D10 (“Vd10”) is set to a voltage higher than the voltage obtained by adding these voltages Vq4, Vd9, and Vq3. From these facts, if the transistor Q1 is not cut off, the second auxiliary drive signal ST1 generated by the power supply side second auxiliary drive signal generation circuit 561 is compared with the reference signal SQ as shown in FIG. Thus, the signal is held at a potential higher by a predetermined potential difference ΔVt1. That is, a section in which the transistor Q1 is not OFF, that is, a section in which the reference signal SQ is rising overlaps the “lower limit of the second auxiliary drive signal ST1” indicated by the solid line in FIG. If the transistor Q1 is OFF, the potential of Ve1 is indefinite, but if the time is short, the potential at the time when the transistor Q1 is OFF is maintained by the stray capacitance.

  Note that the voltage (“Vd10”) between the terminals of the Zener diode D10 is set according to the potential difference ΔVt1. That is, the potential difference ΔVt1 can be increased by setting a large voltage (“Vd10”) between the terminals of the Zener diode D10. Further, if the voltage between the terminals of the Zener diode D10 (“Vd10”) is set to be small, the potential difference ΔVt1 can be reduced. The predetermined potential difference ΔVt1 corresponds to a “predetermined value”.

  Next, the second auxiliary drive signal ST2 generated by the ground side second auxiliary drive signal generation circuit 562 will be described. As described with reference to FIG. 15B, the signal input to the base terminal of the transistor Q6 of the ground side second auxiliary drive signal generation circuit 562 is the voltage drop (“Vd12” of the Zener diode D12 with respect to the potential of the reference signal SQ. ]) Is a low potential signal. Further, if the transistor Q2 is not cut off, the signal output from the emitter terminal of the transistor Q5 of the ground side second auxiliary drive signal generation circuit 562, that is, the second auxiliary drive signal ST2 is the base terminal of the transistor Q6. The voltage between the base and emitter of the transistor Q6 ("Vq6"), the voltage between the terminals of the diode D11 ("Vd11"), and the voltage between the base and emitter of the transistor Q5 ("Vq5") ) And the potential. These voltages Vq4, Vd9, and Vq3 are almost constant. Further, the voltage (“Vd12”) between the terminals of the Zener diode D12 is set to a voltage higher than the voltage obtained by adding these voltages Vq4, Vd9, and Vq3. Therefore, if the transistor Q2 is not cut off, the second auxiliary drive signal ST2 generated by the ground side second auxiliary drive signal generation circuit 562 is equal to the reference signal SQ as shown in FIG. Thus, the signal is held at a potential lower by a predetermined potential difference ΔVt2. That is, a section in which the transistor Q2 is not turned off, that is, a section in which the reference signal SQ is falling overlaps with the “upper limit of the second auxiliary drive signal ST2” of the dotted line in FIG. If the transistor Q2 is OFF, the potential of Ve2 is indefinite, but if the time is short, the potential at the time when the transistor Q2 is OFF is maintained by the stray capacitance.

  The voltage between the terminals of the Zener diode D12 (“Vd12”) is set according to this potential difference ΔVt2. That is, if the voltage between the terminals of the Zener diode D12 (“Vd12”) is set large, the potential difference ΔVt2 can be increased. Further, if the voltage (“Vd12”) between the terminals of the Zener diode D10 is set small, the potential difference ΔVt2 can be reduced. The predetermined potential difference ΔVt2 corresponds to a “predetermined value”.

<Signal switching>
The timing at which the first auxiliary drive signal SV and the second auxiliary drive signals ST1 and ST2 are switched will be described. FIG. 17A illustrates the switching timing from the first auxiliary drive signal SV to the second auxiliary drive signal ST1. FIG. 17B illustrates the switching timing from the second auxiliary drive signal ST2 to the first auxiliary drive signal SV.

  For example, as shown in FIG. 17A, the potential of the first auxiliary drive signal SV supplied from the first auxiliary drive signal generation circuit 52 is the second auxiliary drive signal generation circuit (here, the power supply side second auxiliary drive signal generation). In a section higher than the potential of the second auxiliary drive signal ST1 supplied by the circuit 561) (left section in the figure), the first auxiliary drive signal SV is supplied to the collector terminal of the transistor Q1. When the potential of the reference signal SQ rises and the lower limit potential of the second auxiliary drive signal ST1 rises and exceeds the potential of the first auxiliary drive signal SV, the signal supplied to the collector terminal of the transistor Q1. Are switched from the first auxiliary drive signal SV to the second auxiliary drive signal ST1 (see the switching timing “Δ” in the figure). This switching is performed by the transistor Q3 and the diode D3. That is, when the lower limit potential of the second auxiliary drive signal ST1 rises and exceeds the potential of the first auxiliary drive signal SV, the transistor Q3 is turned on. As a result, the second auxiliary drive signal ST1 is supplied to the collector terminal of the transistor Q1. On the other hand, when the potential of the second auxiliary drive signal ST1 exceeds the potential of the first auxiliary drive signal SV, the diode D3 is turned off and the supply of the first auxiliary drive signal SV is cut off. In practice, the potential of the first auxiliary drive signal SV when switching to the second auxiliary drive signal ST1 takes into account the voltage across the diode D3 and the voltage drop. On the other hand, the transistor Q3 is turned on, and the second auxiliary drive signal ST1 is supplied to the collector terminal of the transistor Q1.

  Again, when the potential of the first auxiliary drive signal SV becomes higher than the potential of the second auxiliary drive signal ST1, the signal supplied to the collector terminal of the transistor Q1 is changed from the second auxiliary drive signal ST1 to the first auxiliary drive signal ST1. Switch to SV.

  Next, switching from the second auxiliary drive signal ST2 to the first auxiliary drive signal SV will be described. As shown in FIG. 17B, the second auxiliary drive signal ST2 (a signal generated by the ground side second auxiliary drive signal generation circuit 562) is generated when the potential of the reference signal SQ starts to drop from the maximum potential VH. 1 is switched from the auxiliary drive signal SV and supplied to the collector terminal of the transistor Q2. During this time, the potential of the first auxiliary drive signal SV is much higher than the potential of the second auxiliary drive signal ST2. When the potential of the first auxiliary drive signal SV gradually decreases and falls below the upper limit potential of the second auxiliary drive signal ST2, the signal supplied to the collector terminal of the transistor Q2 is changed from the second auxiliary drive signal ST2 to the second auxiliary drive signal ST2. 1 is switched to the auxiliary drive signal SV (see the switching timing “『 ”in the figure). This switching is performed by the transistor Q5 and the diode D4. That is, when the potential of the first auxiliary drive signal SV drops and falls below the potential of the second auxiliary drive signal ST2, the diode D4 is turned on. As a result, the first auxiliary drive signal SV is supplied to the collector terminal of the transistor Q2. On the other hand, when the potential of the first auxiliary drive signal SV is lower than the upper limit potential of the second auxiliary drive signal ST2, the transistor Q5 is turned off and the supply of the second auxiliary drive signal ST2 is shut off. Actually, the potential of the first auxiliary drive signal SV when switching from the second auxiliary drive signal ST2 takes into account the voltage across the diode D4 and the voltage drop. On the other hand, the transistor Q5 is turned off, and the supply of the second auxiliary drive signal ST2 to the collector terminal of the transistor Q1 is stopped.

=== Summary ===
As described above, in the present embodiment, the first auxiliary drive signal SV whose potential fluctuates prior to the fluctuation of the signal level of the signal waveform of the reference signal SQ is generated, and the collectors of the transistors Q1 and Q2 are generated. By supplying the voltage to the terminal, the potential difference between the collector and the emitter of the transistors Q1 and Q2 can be reduced, so that the power consumption of the transistors Q1 and Q2 can be significantly suppressed. On the other hand, even when the reference signal SQ having a waveform different from that in FIG. 12 is input to the base terminals of the transistors Q1 and Q2 and the first auxiliary drive signal SV does not change in potential prior to the reference signal SQ, Since the second auxiliary drive signal generation circuit 56 can generate the second auxiliary drive signal and supply it to the collector terminals of the transistors Q1 and Q2, it is possible to avoid a period (Tq) in which the transistors Q1 and Q2 do not operate. can do.

=== Another Configuration Example of the First Auxiliary Drive Signal Generation Circuit ===
Hereinafter, other embodiments of the first auxiliary drive signal generation circuit will be described.

<Circuit configuration>
FIG. 18 illustrates another embodiment of the first auxiliary drive signal generation circuit 54. The first auxiliary drive signal generation circuit 54 includes switch elements M4 and M5, an inductance L5, a resistor R5, capacitors C4 and C5, and diodes D6 and D7. Here, the switch elements M4 and M5 are configured by field effect transistors. Specifically, the switch element M4 is composed of a P-channel field effect transistor. On the other hand, the switch element M5 is composed of an N-channel field effect transistor. The switch element M4 corresponds to a first switch element. The switch element M5 corresponds to a second switch element. The diodes D6 and D7 are configured by Schottky barrier diodes. In addition, the capacitor | condenser Cz in a figure shows the electrostatic capacitance of a piezoelectric element (piezo element). The capacitance of the capacitor Cz varies each time depending on the number of nozzles that eject ink.

  The inductance L5 in FIG. 18 is equal to that of the smallest inductance among the inductances L1, L2, and L3 in FIG. In FIG. 11, since the inductances L2 and L3 are the same constant and are smaller than the inductance L1, the inductance L5 is equal to the inductance L2 or the inductance L3.

  The switch element M4, the inductance L5, and the capacitor C4 are connected in series between the power supply (42V here) side and the ground (ground) side in order. The switch element M5 is interposed between the switch element M4 and the inductance L5 and between the ground (ground) side. A diode D6 is interposed between the switch element M4 and the inductance L5 and between the power supply (42V in this case). Here, the cathode terminal of the diode D6 is connected to the power supply side, and the anode terminal thereof is connected between the switch element M4 and the inductance L5. A diode D7 is interposed between the switch element M4 and the inductance L5 and between the ground (ground) side. The diode D7 has a cathode terminal connected between the switch element M4 and the inductance L5, and an anode terminal connected to the ground (ground) side.

  Furthermore, a resistor R5 and a capacitor C5 are connected in series to the inductance L5, and are connected in parallel to the inductance L5. The resistor R5 and the capacitor C5 are provided to suppress the vibration of the voltage across the terminal of the inductance L5 when the current flowing through the inductance L5 is cut off.

  The terminal on the power source side of the capacitor C4 is connected to the collector terminals of the transistors Q1 and Q2 via diodes D3 and D4, respectively. That is, the inter-terminal voltage of the capacitor C4 is input to the collector terminals of the transistors Q1 and Q2 as the first auxiliary drive signal SV.

  When the switch element M4 is turned on, a current flows through the inductance L5, charges are accumulated in the capacitor C4, and the capacitor C4 is charged. Therefore, the voltage across the capacitor C4 gradually increases. On the other hand, when the switch element M5 is turned on, a current flows from the capacitor C4 through the inductance L5, and charges are discharged from the capacitor C4. That is, the capacitor C4 is discharged. Thereby, the voltage between terminals of the capacitor C4 gradually decreases. That is, the inductance L5 and the capacitor C4 constitute an LC resonance circuit.

<Generation of first auxiliary drive signal>
Next, a method of generating the first auxiliary drive signal SV by the first auxiliary drive signal generation circuit 54 will be described. FIG. 19 illustrates a method for generating the first auxiliary drive signal SV. Here, a method of generating the first auxiliary drive signal SV will be described with reference to FIG.

  First, here, the switch element M4 is turned ON (see FIG. 18). The timing at which the switch element M4 is turned ON is set to a timing slightly earlier than the timing at which the potential of the reference signal SQ starts to rise. The other switch element M5 is left OFF here. When the switch element M4 is turned ON, as shown in FIG. 18, a current flows from the power supply side (here 42V) to the inductance L5 through the switch element M4, and the current is supplied to the capacitor C4. For this reason, electric charge is accumulated in the capacitor C4, and the capacitor C4 is charged. As a result, the voltage across the terminals of the capacitor C4 (hereinafter referred to as “C potential”) gradually increases prior to the fluctuation of the potential of the reference signal SQ.

  The switch element M4 is turned off after a predetermined time T4 has elapsed since it was turned on. Even after the switch element M4 is turned off, current continues to flow through the inductance L5. This is due to the energy stored in the inductance L5 to flow current. The current flowing through the inductance L5 is supplied from the ground side through the diode D7. As a result, a current is supplied to the capacitor C4 even after the switch element M4 is turned off, and the voltage across the terminals of the capacitor C4 (“C potential”) further precedes the fluctuation of the potential of the reference signal SQ. To rise. Here, since the inductance L5 is smaller than the inductance L1 of FIG. 11, the way of increasing the “C potential” is larger than that of FIG. Therefore, the predetermined time T4 is shorter than the predetermined time T1 (FIG. 12).

  Thereafter, the magnitude of the current flowing through the inductance L5 gradually decreases. Therefore, the switch element M4 is turned on again (see FIG. 19). Then, again, a current flows from the power supply side (here, 42 V) to the inductance L5 through the switch element M4, and the current is supplied to the capacitor C4 (see FIG. 18). For this reason, electric charge is accumulated in the capacitor C4, and the capacitor C4 is charged. As a result, the inter-terminal voltage of the capacitor C4 (hereinafter referred to as “C potential”) further increases.

  The switch element M4 is turned off after a predetermined time T5 has elapsed since it was turned on. For a while after the switch element M4 is turned off, a current flows through the inductor L5 through the diode D7, and the capacitor C4 is charged. As a result, the inter-terminal voltage of the capacitor C4 (hereinafter referred to as “C potential”) further increases prior to the fluctuation of the potential of the reference signal SQ. Thereafter, the magnitude of the current flowing through the inductance L5 gradually decreases, and the voltage across the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. In this way, the first section D1 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19). Here, when the current flowing through the inductance L5 is cut off, the rate of change (dI / dt) of the current suddenly becomes 0, and a large potential fluctuation (ground → “C potential”) occurs at the power supply side terminal of the inductance L5. Even if this occurs, the resistance R5 and the capacitor C5 can suppress the oscillation of the voltage across the terminal of the inductance L5.

  In the first section D1, the charging is performed twice at predetermined times T4 and T5 in order to reduce the potential difference between the reference signal SQ and the auxiliary drive signal SV as much as possible.

  The voltage between the terminals of the capacitor C4 (“C potential”) is kept constant for a while. As a result, a second section D2 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19).

  Thereafter, the switch element M4 is turned on again. The switch element M4 is turned on in advance before the potential of the reference signal SQ starts to rise from the intermediate potential VM to the maximum potential VH (see FIG. 19). When the switch element M4 is turned on in this way, a current flows again from the power source side (here, 42V) through the switch element M4 to the inductance L5, and the current is supplied to the capacitor C4. As a result, the capacitor C4 is charged, and the voltage across the terminals of the capacitor C4 (“C potential”) further rises prior to the fluctuation of the potential of the reference signal SQ.

  The switch element M4 is turned off after a predetermined time T6 has elapsed since it was turned on (see FIG. 19). Here, the predetermined time T6 is set to a very long time compared to the predetermined times T4 and T5 in the case of forming the first section D1 of the signal waveform of the first auxiliary drive signal SV (see FIG. 19). . That is, the switch element M4 continues to be turned on for a longer time than when the first section D1 of the signal waveform of the first auxiliary drive signal SV is formed. As a result, a current is supplied to the inductance L5 from the power source (here, 42V) side through the switch element M4 for a long time. For this reason, the voltage between the terminals of the capacitor C4 (“C potential”) increases rapidly (see FIG. 19). For a while after the switch element M4 is turned off, a current flows through the inductor L5 through the diode D7, and the capacitor C4 is charged (see FIG. 18). As a result, the inter-terminal voltage of the capacitor C4 (hereinafter referred to as “C potential”) further increases. Thereafter, the magnitude of the current flowing through the inductance L5 gradually decreases, and the voltage across the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. In this way, the third section D3 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19). Here, when the current flowing through the inductance L5 is cut off, the rate of change (dI / dt) of the current suddenly becomes 0, and a large potential fluctuation (ground → “C potential”) occurs at the power supply side terminal of the inductance L5. Even if this occurs, the resistance R5 and the capacitor C5 can suppress the oscillation of the voltage across the terminal of the inductance L5.

  The voltage between the terminals of the capacitor C4 (“C potential”) is kept constant for a while. As a result, a fourth section D4 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19).

  Thereafter, the switch element M5 is turned on. The switch element M5 is turned on in advance before the potential of the reference signal SQ starts to drop from the maximum potential VH to the minimum potential VL (see FIG. 19). When the switch element M5 is turned on in this way, the electric charge accumulated in the capacitor C4 is discharged to the ground side through the inductance L5. As a result, the capacitor C4 is gradually discharged, and the voltage across the terminals of the capacitor C4 (“C potential”) drops abruptly prior to the fluctuation of the potential of the reference signal SQ.

  The switch element M5 is turned off after a predetermined time T7 has elapsed since it was turned on. Even after the switch element M5 is turned off, current continues to flow through the inductance L5. This is due to the energy to flow the current stored in the inductance L5. The current flowing through the inductance L5 is discharged to the power supply side (42 V here) through the diode D6.

  The magnitude of the current flowing through the inductance L5 gradually decreases, and the voltage between the terminals of the capacitor C4 (“C potential”) gradually shifts to a stable state. In this way, the fifth section D5 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19). Here, when the current flowing through the inductance L5 is cut off, the rate of change (dI / dt) of the current suddenly becomes 0, and a large potential fluctuation (power supply (+ 42V) → “C” occurs at the power supply side terminal of the inductance L5. Even if the “potential” is generated, the resistance R5 and the capacitor C5 can suppress the oscillation of the voltage across the terminal of the inductance L5.

  Thereafter, the voltage between the terminals of the capacitor C4 (“C potential”) is held at a potential lower than the minimum potential VL of the reference signal SQ until the potential of the reference signal SQ starts to rise from the minimum potential VL again. . As a result, a sixth section D6 of the signal waveform of the first auxiliary drive signal SV is formed (see FIG. 19).

  Such a first auxiliary drive signal SV is input to the collector terminals of the transistors Q1 and Q2, thereby reducing the potential difference between the collector terminals of the transistors Q1 and Q2 and the emitter terminals of the transistors Q1 and Q2. Thereby, the power consumption of the transistors Q1 and Q2 can be significantly suppressed.

  In FIG. 12, the number of times the switch element is turned on is three, but in FIG. 19, it is four. At the time of switching, a finite resistance is generated and a so-called switching loss occurs. Therefore, it is advantageous that the number of times of switching is small, and the circuit of FIG. 18 is disadvantageous compared to the circuit of FIG. However, the circuit is simple and advantageous in this respect.

=== Other Embodiments ===
As described above, the printing apparatus such as a printer according to the present invention has been described based on one embodiment. However, the above-described embodiment is for facilitating the understanding of the present invention, and the present invention is limited and interpreted. Not meant to be The present invention can be changed or improved without departing from the gist thereof, and needless to say, the present invention includes equivalents thereof. In particular, even the embodiments described below are included in the printing apparatus according to the present invention.

<About piezoelectric elements>
In the above-described embodiment, the “piezoelectric element” is described as an example of an element (piezo element PZT) that is provided in an ink jet printer and performs an operation of ejecting ink. Is not limited to an element that is provided in such an ink jet printer and performs an operation of ejecting ink. That is, piezoelectric elements provided in various types of devices other than ink jet printers are also included in the “piezoelectric elements” herein.

<Main drive signal>
In the above-described embodiment, as the “main drive signal”, the main drive signal having a waveform as shown in FIG. 6 or FIG. 7 has been described as an example. However, in the “main drive signal” here, It is not limited to a signal having such a waveform. That is, a signal having any waveform as long as it is a signal for operating the piezoelectric element is included in the “main drive signal” here.

<About the first auxiliary drive signal generation circuit>
In the above-described embodiment, the “first auxiliary drive signal generation circuit” is described by taking, as an example, a circuit including an LC resonance circuit in which an inductance and a capacitor are connected in series as shown in FIG. 11 and FIG. However, the “first auxiliary drive signal generation circuit” here does not necessarily need to be a circuit including such an LC resonance circuit. In other words, any circuit that supplies a signal for amplifying the reference signal to the collector terminal of the transistor is included in the “first auxiliary drive signal generation circuit”.

<About the first auxiliary drive signal>
In the above-described embodiment, the first auxiliary drive signal SV having the waveforms shown in FIGS. 10, 12, 13, and 19 has been described as an example of the “first auxiliary drive signal”. The “first auxiliary drive signal” is not limited to a signal having such a waveform. That is, a signal having any waveform is included in the “first auxiliary drive signal” as long as it is a signal supplied to the collector terminal of the transistor to amplify the reference signal.

<Second Auxiliary Drive Signal Generation Circuit>
In the above-described embodiment, as the “second auxiliary drive signal generation circuit”, the power supply side second auxiliary drive signal generation circuit 561, the ground side second auxiliary signal generation circuit 561 as shown in FIG. 14, FIG. 15A, FIG. The circuit configured by two circuit blocks with the auxiliary drive signal generation circuit 562 has been described as an example. However, the “second auxiliary drive signal generation circuit” does not necessarily need to have such a circuit configuration. Absent. That is, when the potential difference between the potential of the first auxiliary drive signal SV input to the collector terminals of the transistors Q1 and Q2 and the potential of the reference signal SQ input to the base terminals of the transistors Q1 and Q2 falls below a predetermined value. Any circuit may be used as long as it supplies the second auxiliary drive signals ST1 and ST2 to the collector terminals of the transistors Q1 and Q2 in order to amplify the reference signal SQ.

  In the “second auxiliary drive signal generation circuit”, the Darlington-connected transistors Q3, Q4, Q5, Q6 and Zener diodes as shown in FIG. 14, FIG. 15A, FIG. 15B, and FIG. It is not necessary to have a configuration including D10 and D12.

<About the second auxiliary drive signal>
In the above-described embodiment, the “second auxiliary drive signal” has been described by taking a signal as shown in FIG. 16 as an example. However, the “second auxiliary drive signal” described here is not necessarily limited to such a signal. It is not limited to signals. That is, the “second auxiliary drive signal” is a signal supplied to the collector terminals of the transistors Q1 and Q2 so as to amplify the reference signal input to the base terminals of the transistors Q1 and Q2. Any signal is included in the “second auxiliary drive signal”.

<About the predetermined value>
In the above-described embodiment, as the “predetermined value”, the voltage between the terminals of the Zener diode D10 (“Vd10”), the voltage between the base and the emitter of the transistor Q4 (“Vq4”), and the voltage between the terminals of the diode D9 ( "Vd9") and the voltage difference ΔVt1 defined by the base-emitter voltage of transistor Q3 ("Vq3"), the voltage between terminals of Zener diode D12 ("Vd12"), and the base-emitter of transistor Q6 The potential difference ΔVt2 defined by the inter-voltage (“Vq6”), the voltage between the terminals of the diode D11 (“Vd11”), and the base-emitter voltage (“Vq5”) of the transistor Q5 has been described as an example. The “predetermined value” here is not necessarily defined by such a method. That is, the “predetermined value” here is not a fixed value as described above, but may be a value that is sequentially changed according to various conditions. That is, as long as the signal input to the collector terminals of the transistors Q1 and Q2 is a value set based on the condition for switching between the first auxiliary drive signal SV and the second auxiliary drive signals ST1 and ST2, what is the value? It may be defined by various methods.

<About the reference signal>
In the above-described embodiment, the reference signal having the waveform as shown in FIG. 10, FIG. 12, FIG. 13, FIG. 16, or 19 has been described as an example of the “reference signal”. Is not limited to a signal having such a waveform. That is, any signal having any waveform as long as it is a reference signal for generating the main drive signal is included in the “reference signal” here.

<About transistors>
In the above-described embodiment, the case where a transistor pair in which an NPN transistor Q1 and a PNP transistor Q2 are complementarily connected is provided as an example has been described. Thus, it is not necessarily required to be configured as a transistor pair in this way, and may be configured as a single unit, or may be configured by using three or more units.

<About switch elements>
In the above-described embodiment, the field effect transistor (FET) is used as the switch element. However, in the “switch element” referred to here, it is not always necessary to use such a field effect transistor. Various other types of well-known elements can be used, such as the above transistors.

<About liquid>
In the above-described embodiment, the case where ink is used as the “liquid” has been described as an example. However, the “liquid” here is not limited to such an ink, but other liquids such as, for example, Various liquids such as metal materials, organic materials (for example, polymer materials), magnetic materials, conductive materials, wiring materials, film forming materials, electronic inks, various processing liquids, and gene solutions may be discharged instead of ink.

1 is a diagram illustrating a configuration of a printing system. 2 is a block diagram illustrating configurations of a computer and a printer. FIG. FIG. 3 is a diagram illustrating a configuration of a printer. FIG. 3 is a side view illustrating the configuration of a printer. Explanatory drawing of a structure of the nozzle row of a head. Sectional drawing for demonstrating the structure of a head. Sectional drawing which expands and shows a part for demonstrating the structure of the principal part of a head. The block diagram for demonstrating the structure of a head control part. The figure explaining the synthetic | combination drive signal produced | generated by the drive signal production | generation circuit. The timing chart for demonstrating the application control of a drive signal. Explanatory drawing explaining an example of a drive signal generation circuit. Explanatory drawing of the relationship between the DAC value input into a waveform generation circuit, and the output voltage from a waveform generation circuit. Explanatory drawing of the production | generation of the analog signal by a D / A converter. FIG. 3 is a circuit diagram illustrating an embodiment of an auxiliary drive signal generation circuit (first auxiliary drive signal generation circuit). Explanatory drawing explaining an example of an auxiliary drive signal (1st auxiliary drive signal). Explanatory drawing of the generation method of the auxiliary drive signal by an auxiliary drive signal generation circuit (1st auxiliary drive signal generation circuit). Explanatory drawing about the case where the signal waveform of a reference signal changes. Explanatory drawing explaining an example of a 2nd auxiliary | assistant drive signal generation circuit. Explanatory drawing of the power supply side 2nd auxiliary drive signal generation circuit. Explanatory drawing of the ground side 2nd auxiliary drive signal generation circuit. An explanatory view of an example of the 2nd auxiliary drive signal. Explanatory drawing of an example of the switching timing from a 1st auxiliary drive signal to a 2nd auxiliary drive signal. Explanatory drawing of an example of the switching timing from a 2nd auxiliary drive signal to a 1st auxiliary drive signal. The circuit diagram which shows other embodiment of the auxiliary | assistant drive signal generation circuit. Explanatory drawing of the production | generation method of the auxiliary drive signal by the auxiliary drive signal generation circuit of other embodiment.

Explanation of symbols

1 printer, 20 paper transport mechanism, 21 paper feed roller,
22 transport motors, 23 transport rollers, 24 platens,
25 paper discharge roller, 30 carriage moving mechanism,
31 Carriage motor, 32 guide shaft,
33 Timing belt, 34 Drive pulley, 35 Drive pulley,
40 head units, 41 heads, 411 case,
411a storage chamber, 412 flow path unit, 412a flow path forming plate,
412b elastic plate, 412c nozzle plate, 412d pressure chamber,
412e nozzle communication port, 412f common ink chamber,
412 g ink supply path, 412 h support frame, 412 i elastic membrane,
412j island, 413 piezo element unit,
413a piezo element group, 413b bonding substrate,
50 drive signal generation circuit,
52 auxiliary drive signal generation circuit (first auxiliary drive signal generation circuit),
54 auxiliary drive signal generation circuit (first auxiliary drive signal generation circuit),
56 second auxiliary drive signal generation circuit,
561 power supply side second auxiliary drive signal generation circuit;
562 second auxiliary drive signal generation circuit on the ground side,
60 detector groups, 61 linear encoder,
62 rotary encoder, 63 paper detector, 64 paper width detector,
70 printer side controller, 71 interface section,
72 CPU, 73 memory, 74 control unit,
81A first shift register, 81B second shift register,
82A first latch circuit, 82B second latch circuit, 83 decoder,
84 control logic, 85 head side switch, 100 printing system,
91 waveform generation circuit, 92 current amplification circuit,
911 D / A converter, 912 voltage amplification circuit,
921 transistor pair,
110 computers, 111 host-side controllers,
112 interface unit, 113 CPU, 114 memory,
120 display devices, 130 input devices, 131 keyboards,
132 mouse, 140 recording and playback device,
141 flexible disk drive device,
142 CD-ROM drive device,
211C cyan nozzle row, 211M magenta nozzle row,
211Y yellow nozzle row, 211K black nozzle row,
S paper, CLK clock,
SI pixel data, LAT latch signal, CH change signal,
CTR controller board, HC head controller, CR carriage,
PZT piezo element, Nz nozzle, COM main drive signal, SQ reference signal,
SV first auxiliary drive signal (auxiliary drive signal), ST1 second auxiliary drive signal,
ST2 Second auxiliary drive signal, Q1 transistor, Q2 transistor,
Q3 transistor, Q4 transistor, Q5 transistor, Q6 transistor,
SS1 first waveform section, SS2 second waveform section, SS3 third waveform section,
PS1 to PS3 drive pulse, q0 to q3 selection data,
SW switch control signal, LAT latch signal, CH change signal,
τ Update cycle

Claims (17)

A transistor that amplifies a reference signal input to the control terminal, generates a main drive signal for operating the piezoelectric element, and outputs it from the output terminal;
A first auxiliary drive signal generating circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor for amplifying the reference signal;
To amplify the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor;
A drive circuit for a piezoelectric element, comprising:   2. The piezoelectric device according to claim 1, wherein the first auxiliary drive signal generation circuit generates a signal having a potential waveform determined as the first auxiliary drive signal in order to reduce power consumption of the transistor. Element drive circuit.   The first auxiliary drive signal generation circuit generates, as the first auxiliary drive signal, a signal whose potential increases prior to the potential increase of the reference signal and whose potential decreases prior to the potential decrease of the reference signal. The piezoelectric element drive circuit according to claim 1, wherein the piezoelectric element drive circuit is generated.   The piezoelectric element drive circuit according to claim 1, wherein the first auxiliary drive signal has a potential waveform approximate to the potential waveform of the reference signal.   The first auxiliary drive signal generation circuit includes an LC resonance circuit in which an inductance and a capacitor are connected in series, and the first auxiliary drive signal is generated by resonance of the LC resonance circuit. The drive circuit of the piezoelectric element of any one of 1-4.   6. The piezoelectric element drive circuit according to claim 5, wherein a voltage between terminals of the capacitor is supplied to a current supply terminal of the transistor as the auxiliary drive signal.   The piezoelectric element drive circuit according to claim 1, further comprising a pair of transistors connected in a complementary manner as the transistor.   8. The piezoelectric element driving circuit according to claim 7, wherein the transistor pair includes an NPN transistor and a PNP transistor whose emitter terminals are connected to each other.   The piezoelectric element drive circuit according to claim 1, wherein the transistor is a bipolar transistor.   The piezoelectric element drive circuit according to claim 1, wherein the second auxiliary drive signal generation circuit generates the second auxiliary drive signal based on the reference signal.   The second auxiliary drive signal generation circuit generates, as the second auxiliary drive signal, a signal that increases in potential when the potential of the reference signal increases and decreases in potential when the potential of the reference signal decreases. The drive circuit of the piezoelectric element of any one of Claims 1-10.   The piezoelectric element drive circuit according to claim 1, wherein the second auxiliary drive signal is a signal having a predetermined potential difference from the potential of the reference signal.   The piezoelectric element drive circuit according to claim 1, wherein the second auxiliary drive signal generation circuit includes a transistor for generating the second auxiliary drive signal.   The piezoelectric element drive circuit according to claim 13, wherein the second auxiliary drive signal generation circuit includes two or more transistors connected in Darlington as the transistors.   The piezoelectric element drive circuit according to claim 1, wherein the piezoelectric element is an element that performs an operation of discharging a liquid from a nozzle. (A) a transistor that amplifies a reference signal input to the control terminal, generates a main drive signal for operating the piezoelectric element, and outputs the main drive signal from the output terminal;
(B) a first auxiliary drive signal generation circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor to amplify the reference signal;
(C) Amplifying the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal falls below a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor,
(D)
(E) The first auxiliary drive signal generation circuit generates a signal having a potential waveform defined as the first auxiliary drive signal in order to reduce power consumption of the transistor,
(F) The first auxiliary drive signal generation circuit, as the first auxiliary drive signal, the potential increases prior to the potential increase of the reference signal, and the potential decreases prior to the potential decrease of the reference signal. Generate a signal to
(G) the first auxiliary drive signal has a potential waveform approximate to the potential waveform of the reference signal;
(H) The first auxiliary drive signal generation circuit includes an LC resonance circuit in which an inductance and a capacitor are connected in series, and generates the first auxiliary drive signal by resonance of the LC resonance circuit,
(I) A voltage across the capacitor is supplied to the current supply terminal of the transistor as the auxiliary drive signal;
(J) The transistor includes a pair of transistors connected in a complementary manner,
(K) The transistor pair includes an NPN transistor and a PNP transistor whose emitter terminals are connected to each other,
(L) the transistor is a bipolar transistor;
(M) The second auxiliary drive signal generation circuit generates the second auxiliary drive signal based on the reference signal,
(N) The second auxiliary drive signal generation circuit generates, as the second auxiliary drive signal, a signal that increases in potential when the potential of the reference signal increases and decreases in potential when the reference signal decreases.
(O) the second auxiliary drive signal is a signal having a predetermined potential difference from the potential of the reference signal;
(P) The second auxiliary drive signal generation circuit includes a transistor for generating the second auxiliary drive signal,
(Q) The second auxiliary drive signal generation circuit includes two or more transistors connected in Darlington as the transistors,
(R) The piezoelectric element drive circuit, wherein the piezoelectric element is an element that performs an operation of discharging a liquid from a nozzle. A piezoelectric element that performs an operation of discharging liquid from a nozzle;
A transistor that amplifies a reference signal input to a control terminal, generates a main drive signal for causing the piezoelectric element to perform the operation, and outputs the main drive signal from an output terminal;
A first auxiliary drive signal generating circuit for supplying a first auxiliary drive signal to a current supply terminal of the transistor for amplifying the reference signal;
To amplify the reference signal when a potential difference between the potential of the first auxiliary drive signal input to the current supply terminal and the potential of the reference signal input to the control terminal is less than a predetermined value. A second auxiliary drive signal generating circuit for supplying a second auxiliary drive signal to the current supply terminal of the transistor;
A liquid ejection apparatus comprising:

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