JP2006320103A - Controller of series multiplex power conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the power consumption of a plurality of single-phase power converters without deteriorating a harmonic wave suppressing effect, and to secure safe and stable operation, in a series multiplex power conversion device. <P>SOLUTION: This controller is capable of outputting (2n+1) pieces of electric potentials at the maximum by connecting in series AC output terminals of n (an integer of 2 or larger) pieces of the single-phase power converters connected to a DC power supply circuit which is provided with an AC power source, a multiplex-winding transformer connected to the AC power source, and an n pieces of diode rectifiers each connected between n pieces of windings at the output side of the transformer and n pieces of the single-phase power converters, and applied to the series multiplex power conversion device that suppresses harmonic waves by providing phase differences to output voltages of n pieces of the windings. The controller is provided with calculation means 101, 102 that generate PWM signals synchronized with voltage commands, and an equalization calculation means 105 that interchanges timing when the PWM signals change among single-phase inverter units 11 to 15 to equalize voltage output periods. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a serial multiple power conversion device capable of generating a multi-level voltage by connecting AC output terminals of a plurality of single-phase power converters in series. Specifically, the power consumption of each single-phase power converter is calculated. The present invention relates to a power converter that is equalized.

FIG. 11 shows a main circuit configuration of a conventional serial multiple power converter. In the figure, 1 is a serial multiple power converter, 11-15 is a single-phase inverter unit as a single-phase power converter, 41-45 are DC power supplies (batteries) of the units 11-15, and 1R is a unit 11 It is a power converter for R phase one phase (henceforth a R phase power converter) formed by connecting in series 15 to 15 AC output terminals.
Similarly, 1S is an S-phase power conversion device composed of single-phase inverter units 21-25, 1T is a T-phase power conversion device composed of single-phase inverter units 31-35, 51-55 and 61-65 are DC power supplies, and 8 is It is a load such as an AC motor.

In the serial multiple power converter 1, one output terminal of each phase power converter 1R, 1S, 1T is connected to a common neutral point O, and the other output terminal R, S, T is connected to a load 8. A three-phase inverter is configured as a star connection.
The number of levels (number of potentials) of the output voltage in such a configuration can output three levels of positive, negative, and zero per unit when the single-phase inverter unit is a single-phase two-level inverter unit. Therefore, if the number of single-phase inverter units connected in series is n, the maximum number of levels per phase is 2n + 1. Therefore, since the number of single-phase inverter units in the serial multiple power converter 1 of FIG. 11 is five for each phase, the maximum number of levels per phase is eleven.

  Next, an operation example of the single-phase inverter unit constituting the series multiple power conversion apparatus 1 will be described. FIG. 12A shows one single-phase inverter unit (single-phase two-level inverter unit) and its DC power supply. For example, the most neutral point O side in the R-phase power converter 1R of FIG. The single-phase inverter unit 11 and the DC power supply 41 are extracted.

In FIG. 12A, Q1 to Q4 are semiconductor switching elements such as IGBT, C is a DC smoothing capacitor, and V _Ed is the magnitude of the DC voltage. 11G _p is a PWM signal indicating the switching state of the switching elements Q1 and Q2 (element on / off state). When 11G _p = 1, Q1 is on (Q2 is off), and 11G _p = 0. Q2 is on (Q1 is off). Similarly, 11G _n is a PWM signal for the switching elements Q3 and Q4. When 11G _n = 1, Q4 is on (Q3 is off), and when 11G _n = 0, Q4 is off (Q3 is on). . The logic “1, 0” of the PWM signals 11G _p and 11G _p may be reversed. In short, the current path is connected between the DC power supply 41 and the load 8 via any switching element without short-circuiting the upper and lower arms. It suffices if switching can be performed so as to be formed.
FIG. 12B is a circuit diagram showing a single-phase three-level inverter unit and its DC power supply as another example of the single-phase inverter unit. The single-phase three-level inverter unit is the same as that of the present invention. It will be described in the embodiment.

FIG. 13 shows a state in which the voltage _VR1 is generated by controlling the conduction period of the switching element of the single-phase inverter unit shown in FIG. 12A by the phase angle θ. As is apparent from FIG. 13, the PWM signals 11G _p and 11G _n have waveforms that repeat 0 and 1 for each electrical angle π [rad]. Here, if the phase angle θ is set to an appropriate value, a phase difference occurs between the PWM signals 11G _p and 11G _n , and this result is applied to the AC output terminal of the single-phase inverter unit 11 in FIG. It will appear as voltage _VR1 .

Since the configuration as shown in FIG. 11 has five single-phase inverter units _per phase, five types of phase angles (θ ₁ , θ ₂ , θ ₃₎ are used to control the conduction period of the switching elements in each unit. , Θ ₄ , θ ₅ ) are required. As this example illustrates how to generate a voltage V _R of the sinusoidal by R-phase power converter in FIG. 14.

In FIG. 14, V _R ^* indicated by a broken line is an R-phase voltage command. If five types of phase angles corresponding to the five single-phase inverter units 11 to 15 are determined along this waveform, the output phase voltage is determined. it is possible to generate a sinusoidal voltage as V _R.
This state will be described for a period in which the phase angle θ is 0 to π / 2 [rad]. When the phase angle becomes θ ₁ with the output phase voltage V _R = 0 as the starting point at the time of the phase angle 0, the single-phase inverter unit 11 Outputs a positive voltage V _R1 = V _Ed , and an output phase voltage V _R = + V _Ed is obtained. Next, the single-phase inverter unit 12 outputs a voltage _V R2 _{= V Ed} of positive when the phase angle is theta _2, the output phase voltage _V R = + _{2V Ed.}
Thereafter, when the phase angle becomes θ ₃ and θ ₄ , the output phase voltage increases by V _Ed, and when the phase angle θ ₅ is reached, V _R = + 5V _Ed . By changing the voltage over one cycle in such a procedure, the magnitude and frequency of each phase output voltage can be controlled.

Next, FIG. 15 shows a control block diagram of the R-phase power converter 1R in FIG.
In FIG. 15, individual PWM signals 11G _p , 11G _n , 12G _p , 12G _n , 13G _p , 13G _n , 14G _p , 14G _n , 15G _p , and 15G _n are input to the single phase inverter units 11 to 15, respectively. ing. Each unit 11-15 is connected to a DC power source as shown in FIG. 11, but these are not shown in FIG.

Reference numeral 101 in FIG. 15 denotes an R-phase voltage command calculation means. The R-phase PWM signal calculation means 102 calculates the phase angle θ as shown in FIG. 13 based on the voltage command determined by the calculation means 101, and these The calculation results are output as individual PWM signals 11G _p , 11G _n , 12G _p , 12G _n , 13G _p , 13G _n , 14G _p , 14G _n , 15G _p , 15G _n for each unit 11-15.

Here, a method for determining the phase angle in the R-phase PWM signal calculation means 102 will be described.
As the voltage V _R of FIG. 14, to represent the output voltage waveform whose level changes at phase angle theta ₁ through? ₅ in the formula, a Fourier series such as Formula 1.

When Formula 1 is expanded and a Fourier coefficient indicating the magnitude of the harmonic is normalized with respect to V _Ed , Formula 2 is obtained.

In order to express the method of determining the phase angles θ _{1 to} θ ₅ by an equation, a condition for removing the fifth, seventh, eleventh, and thirteenth harmonics and a condition for determining the magnitude of the voltage by the coefficient M are added. A simultaneous transcendental equation such as Equation 3 is established.

[Equation 3]
_{cos (5θ 1) + cos (} 5θ 2) + cos (5θ 3) + cos (5θ 4) + cos (5θ 5) = 0
_{cos (7θ 1) + cos (} 7θ 2) + cos (7θ 3) + cos (7θ 4) + cos (7θ 5) = 0
_{cos (11θ 1) + cos (} 11θ 2) + cos (11θ 3) + cos (11θ 4) + cos (11θ 5) = 0
_{cos (13θ 1) + cos (} 13θ 2) + cos (13θ 3) + cos (13θ 4) + cos (13θ 5) = 0
cos (θ ₁ ) + cos (θ ₂ ) + cos (θ ₃ ) + cos (θ ₄ ) + cos (θ ₅ ) = 5M

As an example, when the phase angle at M = 0.8 is obtained, θ ₁ = 6.57 °, θ ₂ = 18.94 °, θ ₃ = 27.18 °, θ ₄ = 45.15 °, θ ₅ = 62.24 °.
The circuit configuration and PWM method of the above-described serial multiple power converter are described in Non-Patent Document 1, Non-Patent Document 2, and the like described later.

Next, FIG. 16 shows the operation for one phase of R phase (operation of R phase power converter 1R) in which five single-phase inverter units 11 to 15 are connected in series as shown in FIG. The waveform displayed over the period is shown.
In Figure _16, V R1 _{~V R5} is a five output voltage of the single-phase inverter unit 11 to 15, the phase voltage waveform of the result of the sum of these is _{V R.} As is apparent from the waveforms of V _{R1 to} V _R5 , an imbalance occurs in the voltage output period of the units 11 to 15, and when a current is passed through the load, the units 11 to 15 The power consumption becomes unbalanced between them.
As a countermeasure for such a problem, Non-Patent Document 2 reports a method of replacing the PWM signal of each inverter unit every half cycle of the voltage command.

FIG. 17 is an operation waveform showing a method reported in Non-Patent Document 2 as a countermeasure for solving the above-described power consumption imbalance. In the figure, _V R1 _{~V R5} Similarly to FIG. 16 is a five output voltage of the single-phase inverter unit 11 to 15, the phase voltage waveform of the result of the sum of these is _{V R.}

In this operation, each single-phase inverter unit outputs a normal voltage without replacing the PWM signal in the first half cycle. The next half cycle performs switching of the PWM signal, the output voltage output period for the V _R1 outputs a maximum voltage as V _R5. The remaining V _{R2 to} V _R4 are respectively set as V _{R3 to} V _R5 , and the voltage to be output is shifted one by one.
By repeating such an operation for each half cycle of the voltage command, if attention is paid to each half cycle, the voltage output periods of the units 11 to 15 still vary, but each unit 11 for a plurality of cycles of the voltage command. The sum of the voltage output periods (conduction periods) of ˜15 can be made equal, thereby making it possible to average the power consumption of each unit 11-15.

Next, FIG. 18 shows a control block diagram for realizing the PWM system for one R phase as shown in FIG. 17, which is configured by adding a PWM signal averaging calculation means 103 to FIG. is there.
In FIG. _{18, (11G p), (} 11G n), (12G p), (12G n), (13G p), (13G n), (14G p), (14G n), (15G p), ( 15G _n ) is a PWM signal output from the R-phase PWM signal calculation means 102. These signals are replaced and averaged by the PWM signal averaging calculation means 103 as shown in FIG. 17, and the PWM signals 11G _p , _{11G n, 12G p, 12G n} , 13G p, 13G n, 14G p, 14G n, 15G p, applied to single-phase inverter units 11 to 15 as a 15G _n.

Now, in general, a serial multiple power converter can output a relatively high voltage such as 3.3 [kV], 6.6 [kV], and therefore ranges from several hundred [kW] to several thousand [kW]. A large capacity AC motor is often used as a load. In other words, in the case of the same capacitive load, the current can be reduced by increasing the voltage supplied by the power converter, and as a result, the loss can be reduced and the efficiency can be improved.
As described above, the DC power supply circuit of the series multiple power converter used for the purpose of outputting a high voltage requires equipment for supplying the DC power supply voltage via a diode rectifier in which the AC power supply is insulated by a transformer. As the transformer in this case, a multi-winding transformer having a phase difference in the output voltage is often used for the purpose of suppressing harmonics.

FIG. 19 is a main circuit configuration diagram of another serial multiple power conversion device 2 including the above-described DC power supply circuit.
In FIG. 19, 5 is an AC power source, 4 is a multi-winding transformer having windings equal to the total number of single-phase inverter units on the output side, 71 to 75, 81 to 85, 91 to 95 are R phase, S phase, T It is a diode rectifier for individually supplying direct current to the single-phase inverter units 11 to 15, 21 to 25, 31 to 35 of the phase (the ones with “C” as shown in 71C and 72C are the corresponding diodes. Shows rectifier connector). These diode rectifiers have, for example, a bridge circuit configuration as shown in FIG. 20, and the input side of the diode rectifier is insulated from the AC power supply 5 by the multiple winding transformer 4.
As described above, the configuration in which the multiple winding transformer and the diode rectifier are used in the DC power supply circuit of the series multiple power converter and the phase difference is provided in the output voltage of the multiple winding transformer is described in Non-Patent Document 3 and the like. Yes.

  On the other hand, in the serial multiple power converter, a selection signal synchronized with the carrier wave that generates the PWM signal is generated, and the PWM signal is distributed to each inverter unit according to the magnitude of the voltage command based on the selection signal. Patent Document 1 below discloses a control device that prevents loss concentration and heat generation by equalizing power sharing by alternately switching the power.

`` A Multilebel Voltage-Source Inverter with Separate DC Sources for Static Var Generation '' (Conference Record of the IEEE IAS Annual Meeting, 1995, p1144-1150) `` Multilevel Converters for Large Electric Drives '' (IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO.3, JANUARY / FEBRUARY 1999) `` Multilevel Converter for High Power AC Drives: a Review '' (Conference IEEE ISIE, 1993, p1993-1996) JP 2002-58257 A (paragraphs [0018] to [0021], FIG. 1, FIG. 5 to FIG. 8 etc.)

  As shown in FIG. 19, the serial multiple power converter using the multi-winding transformer 4 is controlled by the PWM method that averages the voltage output period over a plurality of cycles of the voltage command for each inverter unit as shown in FIG. In this case, it is possible to average the power consumption of each unit 11 to 15 for a plurality of cycles of the voltage command, but there is a difference in the voltage output period of each unit 11 to 15 within the half cycle of the voltage command. Therefore, their power consumption is still unbalanced.

Next, in order to further clarify power consumption imbalance, a detailed description will be given with reference to FIGS. 21, 22, 23, and 24. FIG.
FIG. 21 is an example of a waveform when the output voltage is reduced in the operation method of FIG. 16, and is the case where the number of levels of the R-phase output voltage is seven. In FIG. 21, only three single-phase inverter units 11 to 13 output voltages as shown by voltages V _{R1 to} V _R3 , and the remaining two single-phase inverter units 14 and 15 output voltages. There is no power consumption due to a state of no (zero voltage).
FIG. 22 shows a waveform when the method of Non-Patent Document 2 is applied to this state and the output voltage is switched between the units. In FIG. 22, the single-phase inverter unit that outputs zero voltage is replaced every half cycle of the voltage command.

  FIG. 23 is a waveform example when the output voltage is further reduced in the operation method of FIG. 16, and is the case where the number of levels of the R-phase output voltage is 3. In this case, only one single-phase inverter unit 11 outputs a voltage, and the remaining four single-phase inverter units 12 to 15 have zero voltage output and no power consumption occurs. Note that when the method of Non-Patent Document 2 is applied to this state and the output voltage is switched between the units, the waveform in FIG. 24 is obtained.

Here, when a series multiple power converter and a multiple winding transformer are combined and a phase difference is provided in the output voltage for the purpose of suppressing harmonics, it is desirable that the power consumption of all windings of the transformer be equal. . However, if the power output is unbalanced between the units due to the difference in the voltage output period of the single-phase inverter unit in a short period such as a half cycle of the voltage command, it is difficult to suppress the expected harmonics. There is. Further, if the average value of the positive side voltage and the average value of the negative side voltage during one cycle of the voltage command are different, a DC voltage is generated.
If such a state continues for a long time, abnormalities due to demagnetization occur in the multi-winding transformer and it becomes impossible to operate as a transformer, or some windings generate heat and burn out in the worst case. There is also a possibility.

  Note that the prior art described in Patent Document 1 described above merely discloses a serial multiple power conversion device that uses a DC power supply such as a battery, and uses a DC power supply circuit including a multiple winding transformer. In this case, no means for solving the imbalance of the power consumption between the single-phase inverter units and the heat generation of the multi-winding transformer caused by this is disclosed.

  Therefore, a problem to be solved by the present invention is to equalize power consumption among a plurality of single-phase inverter units without impairing the effect of suppressing harmonics, and to ensure safe and stable operation.

In order to solve the above-mentioned problem, the invention according to claim 1 is configured such that the AC output terminals of n (n is an integer of 2 or more) single-phase power converters connected to the DC power supply circuit are connected in series and In a serial multiple power converter capable of outputting 2n + 1 potentials or 4n + 1 potentials at maximum,
Means for calculating a PWM signal synchronized with a voltage command for the serial multiple power converter;
Means for equalizing the voltage output periods of these single-phase power converters by switching the timing at which the PWM signal changes between the n single-phase power converters;
It is equipped with.

  According to a second aspect of the present invention, in the first aspect, the PWM signal is replaced every half cycle of the voltage command.

In the invention described in claim 3, the AC output terminals of n (n is an integer of 2 or more) single-phase power converters connected to the DC power supply circuit are connected in series, and a maximum of 2n + 1 potentials, or In a serial multiple power converter that can output a maximum of 4n + 1 potentials,
Means for calculating a PWM signal synchronized with a voltage command for the series multiple power converter, division calculation means for dividing the voltage command into a plurality of sections according to the number n of serially connected single-phase power converters, and the division Means for equalizing the voltage output periods of these single-phase power converters by replacing the PWM signal among the n single-phase power converters based on the section divided by the calculation means and the magnitude of the voltage command; , With.

  According to the present invention, the voltage output by the individual single-phase power converters is made by replacing the timing at which the PWM signal changes with a short period between a plurality of single-phase power converters to equalize the voltage output period. The period can be equalized, and the power consumption of each winding of the multi-winding transformer provided in the DC power supply circuit can be equalized. For this reason, it is possible to perform a safe and stable series multiple power conversion operation without heat generation or burning of the transformer without impairing the harmonic suppression effect by the multiple winding transformer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a control block diagram of one phase of R phase (for example, the R phase power conversion device in FIGS. 15, 18, 19 and the like) in the first embodiment of the present invention. The configurations of the other S-phase and T-phase main circuits and control blocks are the same as those in FIG.
In FIG. 1, the same components as those in FIGS. 15 and 18 are denoted by the same reference numerals, 1R is a R-phase power converter, 11 to 15 are single-phase inverter units in which AC output terminals are connected in series, Reference numeral 101 denotes an R-phase voltage command calculation means, and reference numeral 102 denotes an R-phase PWM signal calculation means.

Reference numeral 105 denotes PWM signals (11G _p ), (11G _n ), (12G _p ), (12G _n ), (12G _n ) for the units 11 to 15 in order to equalize the voltage output periods of the single-phase inverter units 11 to 15. 13G _p), a _{(13G n), (14G p} ), (14G n), (15G p), (PWM signal equalizing calculation means for replacing the 15G _n) for each half cycle of the voltage command as described later.
Although not shown, the DC power supply circuit of the single-phase inverter units 11 to 15 includes an AC power supply 5 and a multiple winding transformer 4 connected to the AC power supply 5, as shown in FIG. And five diode rectifiers 71 to 75 connected between the five windings on the output side of the multiple winding transformer 4 and the five single-phase inverter units 11 to 15, respectively. A harmonic is suppressed by providing a phase difference in the output voltage of the winding. Here, the multiple winding transformer 4 has 15 windings including other S-phase power converters and T-phase power converters.

The operation when the control block of FIG. 1 is realized as an operation by an electric circuit or software will be described with reference to the waveform diagram of FIG.
The control block diagram of FIG. 1 is an example in which five single-phase inverter units are used. In FIG. 2, for ease of understanding, the voltage output as a unit when the PWM signal equalization calculation means 105 is not used. how to replace the longest single-phase inverter unit 11 (output period of V _R1) period, between the shortest single-phase inverter unit 15 (output period of V _R5) voltage output period, the timing at which the PWM signal changes Is shown.

2, (A) and (B) are waveforms for the single-phase inverter units 15 and 11, respectively, and PWM signals (15G _p ), (15G _n ), (11G _p ) without using the PWM signal equalization calculation means 105. ) And (11G _n ) as they are, the output voltages of the single-phase inverter units 15 and 11 are shown as (V _R5 ) and (V _R1 ), respectively.
On the other hand, (C) and (D) in FIG. 2 are waveforms obtained as a result of performing the equalization calculation using the PWM signal equalization calculation means 105 and exchanging the PWM signals between the single-phase inverter units 15 and 11. _{, 15G p, 15G n, 11G} p, 11G n is PWM signal after _{interchange, V R5,} V _R1 is an output voltage of the single-phase inverter units 15 and 11 as a result of the switching based on the PWM signal after replacement.

The operation will be described in increments of ¼ period (π / 2 [rad]) with respect to one period of the voltage command (electrical angle 2π [rad]). In the first period of 0 to π / 2 [rad], a) and (C), the same waveform without differences both between (B) and (D), _{V R1} outputs a _{+ V Ed} by θ _{1, V R5} also outputs the _{+ V Ed} in theta ₅ .
Next, in the period of π / 2 to π [rad], the waveform is replaced by the PWM signal equalization calculation unit 105, and before equalization, V _R5 at the timing of π−θ ₅ [rad] in (A). what but had changed to zero from _{+ V Ed,} after equalization alters to zero _{V R1} from _{+ V Ed} as (D). Similarly, at the timing of π−θ ₁ [rad], V _R1 changed from + V _Ed to zero in (B). After equalization, VR ₅ is changed from + V _Ed as shown in (C). Change to zero.
Thereafter, similarly, the operation for one cycle of the voltage command is completed by switching the timing at which the PWM signal changes between the single-phase inverter units connected in series.

3, the output voltage _V R1 _{~V R5} single-phase inverter units 11 to 15 of the result of the PWM pulse equalization operation as described above, the output voltage _{V R} of the R-phase one phase is a total of these It is a waveform. As is clear from the figure, the voltage output periods of all the single-phase inverter units 11 to 15 are equal (particularly, the voltage output periods within the half cycle of the voltage command are substantially the same in all the units 11 to 15). In FIG. 16 and FIG. 17, the unbalance that the voltage output period of the single-phase inverter units 11 to 15 had is eliminated.
For this reason, even in a series multiple power converter that uses a multi-winding transformer to give a phase difference to the output voltage in order to suppress harmonics, the power consumption of all the windings of the transformer is made substantially equal. The desired harmonic suppression effect can be obtained without causing any heat generation or burning accident.

Next, FIG. 4 is a control block diagram for one R phase showing the second embodiment of the present invention. The configurations of the other S-phase and T-phase main circuits and control blocks are the same as in FIG.
In FIG. 4, reference numeral 106 denotes a section for dividing the PWM signal into a plurality of sections according to the number n of single-phase inverter units (that is, the number n of multiplex power converters) based on the R-phase voltage command. A division interval calculation means 107 for calculating, is a PWM signal equalization calculation means for evenly distributing the PWM signal to the intervals based on the magnitude of the R-phase voltage command and the calculation result of the interval division, and other components are the same as in FIG. It is.
The operation when such a control block is realized as an operation by an electric circuit or software will be described below with reference to the waveform diagrams of FIGS.

FIG. 5 shows that only one of the five single-phase inverter units 11 to 15 (in the illustrated example, the unit 11 before equalization of the PWM signal) is + V _Ed or −V in one cycle of the R-phase voltage command. _{In this} example, the output voltage (number of levels = 3) is small as in the case of outputting the voltage of _Ed . In the figure, the section number is a value output as a result of calculating the divided section from the R-phase voltage command by the section dividing calculating means 106. In this case, since there are five inverter units, an example is shown in which the PWM signal is divided into 20 sections that are four times as long as one period of the R-phase voltage command.

Before the equalization of the PWM signal, the inverter unit 11 outputs a voltage of + V _Ed between the sections 0 to 9, and outputs −V _Ed between the sections 10 to 19, but after the equalization, the equalization calculation is performed. Thus, the inverter units that output voltage are sequentially switched by switching the PWM signal for each section.
Although the state of the front and rear sections equalization in 0 are the same, the process proceeds from the interval 0 to zone 1, the voltage V _R1 of the inverter unit 11 becomes zero, instead of the voltage V _R2 of the inverter unit 12 is + V _Ed. When the section 1 is shifted to the section 2, the voltage _VR2 of the inverter unit 12 becomes zero, and instead, the voltage _VR3 of the inverter unit 13 becomes + V _Ed .
In this way, the output voltage of each inverter unit in the section 9 from the interval 0 in turn + V _Ed, the output voltage V _R of one phase as a result is the same as before equalization operation. Similarly, in the section 19 from the section 10 by the inverter unit 11 to 15 to output a voltage of -V _Ed sequentially, the output voltage V _R of one phase as a result is the same as before equalization operation.

FIG. 6 is an example of outputting a voltage (number of levels = 7) larger than that in FIG. 5, and a maximum of three inverter units (in the illustrated example, before equalization of the PWM signal) in one cycle of the R-phase voltage command. The units 11 to 13) in FIG.
The operation for each section will be described. In the state of section 0, the state before and after equalization is the same. When the output voltage for one phase is + V _{Ed as in} the section transition from 0 to 1, each inverter The units 11 to 15 sequentially operate to output a voltage of + V _Ed . Next, when the section 1 is shifted to the section 2, since the magnitude of the output voltage per phase does not change at first, the voltage _VR2 of the inverter unit 12 becomes zero, and instead the voltage _VR3 of the inverter unit 13 becomes + V. _Ed . When time elapses from this state, the output voltage per phase becomes + 2V _Ed from the middle of the section 2, and the two inverter units 13 and 14 each output a voltage of + V _Ed . In this case, the voltage V _R4 of the inverter unit 14 becomes + V _{Ed while} the voltage V _R3 of the inverter unit 13 remains + V _Ed , so that the output voltage per phase of the R phase becomes + 2V _Ed from the middle of the section 2.

When transitioning from section 2 to section 3, the voltage V _R3 of the inverter unit 13 and the voltage V _R4 of the inverter unit 14 simultaneously become zero, and instead the voltage V _R5 of the inverter unit 15 and the voltage V _{R1 of the} inverter unit 11 At the same time, the output voltage per R phase is + 2V _Ed by becoming + V _Ed .
When moving from section 3 to section 4, the output voltage _{V R1} due to the voltage _{V R5} and the inverter unit 11 by the inverter unit 15, by switching by the voltage _{V R2} and the inverter unit 13 by the inverter unit 12 to the output of the voltage _{V R3} The voltage per R phase is maintained at + 2V _Ed . In section 4, voltage VR ₄ of inverter unit 14 becomes + V _Ed in the middle, so that three inverter units 12 to 14 each output a voltage of + V _Ed , and the voltage per phase of R phase is in the section From the middle of 4, it becomes + 3V _Ed .
When the section 4 is shifted to the section 5, the voltage V _R4 of the inverter unit 14, the voltage V _R2 of the inverter unit 12, and the voltage V _{R3 of the} inverter unit 13 that output the voltage + V _{Ed in} the middle of the section 4 become zero simultaneously. Instead, the voltage V _R5 of the inverter unit 15 and the voltage V _R1 of the inverter unit 11 become + V _Ed at the same time, so that the voltage per R phase is set to + 3V _Ed .

Thereafter, sections 5 to section 9 shows an operation when changing voltage per R-phase one phase from + _{3V Ed} to _{+ V Ed.} Sections 10 to 19 are operations when the voltage per R phase changes between −V _Ed and −3V _Ed . Since the basic operation of these sections is the same as that of sections 0 to 5, detailed description thereof is omitted.

  FIG. 7 is an example in which all of the five inverter units 11 to 15 output voltage in one cycle of the R-phase voltage command in order to output a voltage (number of levels = 11) larger than that in FIG. Since the basic operation is the same as in FIG. 6, detailed description thereof is omitted.

Further, FIGS. 8 to 10 show the operation waveforms of FIGS. 5 to 7 described above over a plurality of periods. FIG. 8 is shown in FIG. 5, FIG. 9 is shown in FIG. Equivalent to.
8 to 10 are compared with FIGS. 16, 17, and 21 to 24, according to the present embodiment, the voltage output between the inverter units regardless of the magnitude of the output voltage per phase. It is clear that the periods are equalized.

  In addition, as a structure of the single phase inverter units 11-15 in each embodiment of this invention, not only the single phase 2 level inverter unit shown to Fig.12 (a) but single phase as shown in FIG.12 (b) is shown. It is also possible to use a three-level inverter unit 11 ′. The single-phase three-level inverter unit 11 ′ is composed of DC smoothing capacitors C1 and C2, semiconductor switching elements Q1 to Q8 and diodes D1 to D4. By connecting n inverter units 11 ′ in series, the maximum Thus, 4n + 1 potentials can be output.

  Further, as the DC power supply circuit in each embodiment, not only a diode rectifier as shown in FIG. 19 but also a thyristor rectifier having a voltage control function, a PWM rectifier including an IGBT or the like may be used.

It is a control block diagram for the R phase and one phase in the first embodiment of the present invention. It is a wave form diagram which shows the operation | movement of FIG. It is a wave form diagram which shows the output voltage of the single phase inverter unit by 1st Embodiment, and the output voltage for R phase 1 phase. It is a control block diagram for one R phase in the second embodiment of the present invention. In 2nd Embodiment, it is a wave form diagram which shows the output voltage of the single phase inverter unit before and after equalization of a voltage output period, and the output voltage for R phase 1 phase. In 2nd Embodiment, it is a wave form diagram which shows the output voltage of the single phase inverter unit before and after equalization of a voltage output period, and the output voltage for R phase 1 phase. In 2nd Embodiment, it is a wave form diagram which shows the output voltage of the single phase inverter unit before and after equalization of a voltage output period, and the output voltage for R phase 1 phase. FIG. 6 is a waveform diagram illustrating the waveform of FIG. 5 over a plurality of cycles. FIG. 7 is a waveform diagram illustrating the waveform of FIG. 6 over a plurality of cycles. FIG. 8 is a waveform diagram illustrating the waveform of FIG. 7 over a plurality of cycles. It is a main circuit block diagram of the conventional serial multiple power converter. FIG. 12 is a circuit diagram showing a single-phase inverter unit and its DC power supply for one unit in FIG. 11. It is explanatory drawing of the switching operation | movement and output voltage of the single phase inverter unit in Fig.12 (a). It is explanatory drawing of a mode that a sine wave-like R phase voltage is generated with the structure of FIG. FIG. 12 is a control block diagram of the R-phase power converter in FIG. 11. It is the wave form diagram which displayed the operation | movement for R phase one phase in FIG. 15 over several cycles of a voltage command. It is an operation | movement waveform diagram which shows the PWM system described in the nonpatent literature 2. FIG. 18 is a control block diagram for realizing the PWM method of FIG. 17. It is a main circuit block diagram of the other conventional serial multiple power converter. It is a block diagram of the diode rectifier in FIG. It is a wave form diagram when making output voltage smaller than FIG. FIG. 22 is a waveform diagram when the output voltage is switched between inverter units by applying the method of Non-Patent Document 2 in FIG. 21. It is a wave form diagram when making output voltage smaller than FIG. FIG. 24 is a waveform diagram when the output voltage is switched between inverter units by applying the method of Non-Patent Document 2 in FIG. 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1R: R phase power converter 1S: S phase power converter 1T: S phase power converter 2: Serial multiple power converter 4: Multiple winding transformer 5: AC power supply 8: Loads 11-15, 21-25, 31 -35: Single-phase inverter unit (single-phase power converter)
71-75, 81-85, 91-95: Diode rectifier 101: R-phase voltage command calculation means 102: R-phase PWM signal calculation means 105, 107: PWM signal equalization calculation means 106: Section division calculation means

Claims (3)

Connect AC output terminals of n single-phase power converters connected to the DC power supply circuit in series to output a maximum of 2n + 1 potentials or a maximum of 4n + 1 potentials In a possible series multiple power converter,
Means for calculating a PWM signal synchronized with a voltage command for the serial multiple power converter;
Means for equalizing the voltage output periods of these single-phase power converters by switching the timing at which the PWM signal changes between the n single-phase power converters;
A control device for a serial multiple power conversion device. In the control apparatus of the serial multiple power conversion device according to claim 1,
The control apparatus for a serial multiple power converter, wherein the PWM signal is switched every half cycle of the voltage command. Connect AC output terminals of n single-phase power converters connected to the DC power supply circuit in series to output a maximum of 2n + 1 potentials or a maximum of 4n + 1 potentials In a possible series multiple power converter,
Means for calculating a PWM signal synchronized with a voltage command for the serial multiple power converter;
Division calculation means for dividing the voltage command into a plurality of sections according to the number n of serially connected single-phase power converters;
The PWM signal is exchanged between the n single-phase power converters based on the section divided by the division calculation means and the magnitude of the voltage command to equalize the voltage output periods of these single-phase power converters. Means,
A control device for a serial multiple power conversion device.

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