JP2006227498A - Image processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing system of a line buffer system, and an image processing system which is superior in drawing performance to an image processing system of a frame buffer system. <P>SOLUTION: The image processing system 1 is internally provided with line buffers (18a, 18b). A sprite processing circuit 17 draws the data of the sprite patterns for one sprite component stored in a video memory 3 in the line buffers 18. After the drawing for the one line component is completed, the buffers 18 for drawing and transfer are switched and the storage contents of the line buffers 18 switched for transfer are written in the frame buffer for drawing of the video memory 3. A pixel data controller 20 outputs the display data stored into the frame buffer for display of the video memory 3 to DACs 21a to 21c. The display data is converted to analog signals by the DACs 21a to 21c, which are then outputted to the CRT display device 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus that displays sprites.

  Sprites are patterns such as figures and characters that can be freely moved on the screen and are indispensable for computer game machines, and are often used as a graphic function in personal computers.

  One of the systems used for displaying sprites is a line buffer system, which will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a conventional image processing apparatus that performs sprite display by a line buffer method.

  In FIG. 1, 101 is a line buffer type image processing apparatus, 102 is a CPU (Central Control Unit) that controls image display, and 103 is a bit map that stores a large number of sprite pattern data (image data). A pattern memory 104 is a CRT (Cathode Ray Tube) display device. In addition to the CRT display device, the display device may be an LCD (Liquid Crystal Display) or the like. The same applies to the frame buffer system of FIG. 3 described later and the embodiment of the present invention described later of FIG.

  In the image processing apparatus 101, reference numeral 111 denotes a CPU interface that controls data exchange with the CPU 102. A pattern memory interface 112 manages data exchange with the pattern memory 103. B is a bus. A clock generator 113 generates a clock pulse and outputs it to each unit.

  Reference numeral 114 denotes a color palette for converting dot data by color code into RGB (red / green / blue) color data. Reference numeral 115 denotes a sprite attribute table that stores sprite pattern attribute data for each sprite pattern to be displayed, such as a sprite pattern display position, sprite pattern size, enlargement / reduction ratio, and address on the pattern memory 103 of the sprite pattern. A register 116 temporarily stores various data necessary for the operation (data indicating the read position of the sprite attribute table 115, the number of scanning lines of the CRT display device 104, etc.). The color palette 114, sprite attribute table 115, and register 116 are written by the CPU.

  Reference numeral 117 denotes a sprite processing circuit. The sprite processing circuit 117 reads the attribute data from the sprite attribute table 115, obtains the address (for one line) of the pattern memory 103 of the sprite pattern to be drawn (written) in the line buffer 118 according to the attribute data, and from the pattern memory 103. The dot data at the determined address is extracted. The sprite processing circuit 117 is obtained by converting the extracted dot data into RGB color data using the color palette 114, and subjecting the converted RGB color data to processing based on the sprite attribute data in the sprite attribute table 115. Color data (display data) is written into the line buffer 118.

  The line buffer 118 is a buffer memory having a storage slot corresponding to each display dot of the horizontal display line of the CRT display device 104, and is composed of two line buffers 118a and 118b (double buffer configuration). The two line buffers 118a and 118b are alternately used as a drawing (writing) buffer and a display (reading) buffer in line units.

  A CRT controller 119 generates various pulse signals for driving the CRT display device 104 based on the clock pulse output from the clock generator 113, that is, a horizontal scanning pulse, a vertical scanning pulse, and the like. Output to the pixel data controller 120. The pixel data controller 120 reads the color data from the line buffer 118 and outputs it to the DACs (digital / analog converters) 121a to 121c in accordance with the horizontal scanning pulse input from the CRT controller 119. The DACs 121 a to 121 c convert color data into analog signals and output the analog signals to the CRT display device 104.

  An outline of the operation of the conventional image processing apparatus that performs sprite display by the line buffer method of FIG. 1 will be described. The CPU 102 sets RGB color data corresponding to the color code in the color palette 114, attribute data in the sprite attribute table 115, and various data necessary for operation in the register 116. Further, the CPU 102 stores the sprite pattern data in the pattern memory 103.

  The sprite processing circuit 117 obtains the address (one line) of the pattern memory 103 in which the sprite pattern to be drawn is stored according to the attribute data of the sprite attribute table 115 and extracts the dot data of the obtained address from the pattern memory 103. The sprite processing circuit 117 converts the extracted dot data into RGB color data using the color palette 114, and performs processing based on the sprite attribute data in the sprite attribute table 115 on the converted RGB color data. Color data is drawn in a drawing line buffer (line buffer 118a or line buffer 118b). This is performed for all sprite patterns to be displayed.

  The drawing and display line buffers 118a and 118b are switched, and the pixel data controller 120 reads the color data from the line buffer switched for display and outputs it to the DACs 121a to 121c. It is output to the display device 104. Data of the next line is drawn in the line buffer switched for drawing during this period.

  Further, drawing and display in the line buffer method will be described with reference to FIG. 2A and 2B are diagrams for explaining drawing and display in the line buffer system. FIG. 2A is a display screen of the CRT display device 104, and FIG. 2B is line buffers 118a and 118b. The “0” line to the “N” line are sequentially displayed on the CRT display device 104. In the line buffer system, as described above, there are two line buffers 118a and 118b for storing color data for one line, and the drawing and display are sequentially switched.

For example, the color data of the “1” line is drawn in the line buffer 118 b while the “0” line of the CRT display device 104 is displayed using the color data of the line buffer 118 a. When the display of the “0” line is finished, the drawing and display line buffers are switched, and the CRT is made using the color data drawn in the line buffer 118b while the “0” line is displayed. The “1” line of the display device 104 is displayed, and the color data of the “2” line is drawn in the line buffer 118 a switched for drawing during that time.
Note that Patent Document 1 and Patent Document 2 are cited as related to the line buffer system.

There is a frame buffer system as a system different from the line buffer system, and the frame buffer system will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of a conventional image processing apparatus that performs sprite display by a frame buffer method.
In FIG. 3, 201 is a frame buffer type image processing apparatus, 202 is a CPU for controlling image display, 203 is a video memory for storing a large number of sprite pattern data (image data) as bitmaps, and 204 is a CRT display apparatus. is there. The video memory 203 is also used as a frame buffer and has a double buffer configuration (not shown). These two frame buffers are alternately written (drawing) buffers and reading (display) buffers in units of frames. Used as.

  In the image processing apparatus 201, reference numeral 211 denotes a CPU interface for exchanging data with the CPU 202, 212 is a video memory interface for exchanging data with the video memory 203, and B is a bus. A clock generator 213 generates a clock pulse and outputs it to each unit.

  Reference numeral 214 denotes a color palette for converting dot data based on a color code into RGB color data. A sprite attribute table 215 stores sprite pattern attribute data such as a sprite pattern display position, sprite pattern size, enlargement / reduction ratio, and sprite pattern address on the video memory 203 for each sprite pattern to be displayed. A register 216 temporarily stores various data necessary for the operation (data indicating the read position of the sprite attribute table 215, the number of scanning lines of the CRT display device 204, etc.). The color palette 214, sprite attribute table 215, and register 216 are written by the CPU 202.

  Reference numeral 217 denotes a sprite processing circuit. The sprite processing circuit 217 reads the attribute data from the sprite attribute table 215, obtains the address (for one frame) of the video memory 203 of the sprite pattern to be drawn (written) in the video memory 203 according to the attribute data, and the attribute data Accordingly, the address (one frame) of the video memory (drawing frame buffer) 203 for drawing the color data is obtained. The sprite processing circuit 217 takes out dot data at the obtained address from the video memory 203. The sprite processing circuit 217 converts the extracted dot data into RGB color data using the color palette 214, and after processing the converted RGB color data based on the sprite attribute data in the sprite attribute table 215, the video memory Write to the address obtained by (frame buffer) 203.

  A CRT controller 219 generates various pulse signals for driving the CRT display device 204 based on clock pulses output from the clock generator 213, that is, a horizontal scanning pulse, a vertical scanning pulse, and the like. Output to the pixel data controller 219. The pixel data controller 219 reads the color data from the video memory (frame buffer) 203 and outputs it to the DACs (digital / analog converters) 220a to 220c in accordance with the horizontal scanning pulse and the vertical scanning pulse input from the CRT controller 218. The DACs 220 a to 220 c convert the color data into analog signals and output them to the CRT display device 204.

  An outline of the operation of the conventional image processing apparatus that performs sprite display by the frame buffer method of FIG. 3 will be described. The CPU 202 sets RGB color data corresponding to the color code in the color palette 214, attribute data in the sprite attribute table 215, and various data necessary for operation in the register 216. Further, the CPU 202 stores sprite pattern data in the video memory 203.

  The sprite processing circuit 217 obtains the address (one frame) of the video memory 203 of the sprite pattern to be drawn according to the attribute data of the sprite attribute table 215, and also the video memory (frame buffer for drawing) that draws color data according to the attribute data. ) 203 address (for one frame) is obtained. The sprite processing circuit 217 takes out dot data at the obtained address from the video memory 203. The sprite processing circuit 217 converts the extracted dot data into RGB color data using the color palette 214, and performs processing based on the sprite attribute data in the sprite attribute table 215 for the converted RGB color data. The color data is drawn at the address obtained by the video memory (frame buffer for drawing) 203. This is performed for all sprite patterns to be displayed.

The drawing and display frame buffers are switched, and the pixel data controller 219 reads the color data from the video memory (frame buffer switched for display) 203 and outputs it to the DACs 220a to 220c, which are converted into analog signals by the DACs 220a to 220c. To the CRT display device 204. During this period, the data of the next frame is drawn in the video memory (frame buffer switched for drawing) 203.
Note that Patent Documents 3 to 5 can be cited as related to the frame buffer system.
JP 61-162084 A Japanese Patent Laid-Open No. 02-275990 JP 02-116894 A Japanese Unexamined Patent Publication No. 05-027745 JP 2002-341859 A

  In the line buffer type image processing apparatus 101 described with reference to FIGS. 1 and 2, a line buffer for drawing and a line buffer for display are switched for each line. For this reason, if the sprites to be drawn are concentrated on the same line, for example, if the sprites S1 to S5 are concentrated on the same line as shown in FIG. Sprite drawing is not in time. As a result, there is a problem that drawing performance as a surface is deteriorated.

  In the frame buffer type image processing apparatus 201 described with reference to FIG. 3, the number of accesses to the video memory 203 increases, and access to the video memory 203 becomes a problem when rendering performance is increased. As types of access to the video memory 203 in the frame buffer system, as shown in FIG. 5, “reading of sprite pattern”, “drawing to frame buffer”, “reading of display data (color data) from the frame buffer (1) There are three types.

Here, in order to compare the drawing performance with the image processing apparatus of the present invention, an example of the drawing performance of the conventional frame buffer method is shown. However, the transfer speed is 200 Mdot / s (the transfer speed when the video memory speed is 100 MHz, the video memory bus width is 16 bits, and the number of bits of one dot is 8 bits), and the display size is 640 × 480 (one line is 640 dots) The number of lines is 480), and the frame frequency is 60 Hz.
The drawing performance in the conventional frame buffer system of FIG. 3 is obtained by subtracting the band used for “reading display data from the frame buffer (one side)” from the transfer speed (band of the video memory), and obtaining the remaining band. This is the number of sprite patterns that can be read out and drawn in the frame buffer in the remaining band. Therefore,
Drawing performance =
(Transfer speed-Display size x Frame frequency) / (2 x Display size x Frame frequency)
In the case of the above setting,
(200M−640 × 480 × 60) / (2 × 640 × 480 × 60) = 4.8 (surface)
It becomes.

  SUMMARY An advantage of some aspects of the invention is that it provides an image processing device that has better drawing performance than the above-described line buffer image processing device and the above-described frame buffer image processing device.

  The present invention is an image processing apparatus that is used as a frame buffer for drawing and display, and that is connected to a storage device that stores data of a plurality of sprite patterns to be displayed on the display device so as to be able to exchange data. A line buffer and sprite pattern data to be displayed on the display device are read from the storage device, display data based on the data is drawn on the line buffer, and the drawn display data is drawn on the frame for drawing in the storage device. An image comprising: a sprite processing circuit for drawing in a buffer; and a display processing circuit for extracting display data from a display frame buffer of the storage device and performing display based on the display data on the display device. It is a processing device.

  In the above image processing circuit, the line buffer includes two line buffers.

  According to the present invention, since the line buffer is provided in the image processing apparatus, the display data for one line is held in the line buffer, and the drawing to the frame buffer is performed thereafter, the drawing performance of the image processing apparatus is improved. .

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
First, the apparatus configuration of the image processing apparatus according to the embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the image processing apparatus according to this embodiment.
In FIG. 6, 1 is an image processing apparatus according to the present embodiment, 2 is a CPU for controlling image display, 3 is a video memory for storing a large number of sprite pattern data (image data) as a bitmap, and 4 is a CRT display apparatus. It is. The video memory 3 is also used as a frame buffer and has a double buffer configuration (not shown). These two frame buffers are alternately written (drawing) buffers and reading (display) buffers in units of frames. Used as.

  In the image processing apparatus 1, reference numeral 11 denotes a CPU interface for exchanging data with the CPU 2, 12 is a video memory interface for exchanging data with the video memory 3, and B is a bus. Reference numeral 13 denotes a clock generator that generates clock pulses and outputs the clock pulses to each unit constituting the image processing apparatus 1.

  Reference numeral 14 denotes a color palette for converting dot data based on a color code into RGB color data. A sprite attribute table 15 stores sprite pattern attribute data for each sprite pattern to be displayed, such as a sprite pattern display position, sprite pattern size, enlargement / reduction ratio, and address of the sprite pattern on the video memory 3. 16 temporarily stores various data necessary for operation (data indicating the reading position of the sprite attribute table 15, the number of scanning lines of the CRT display device 4, the address of an area used as a frame buffer of the video memory 3). Register. The color palette 14, the sprite attribute table 15, and the register 16 are written by the CPU 2 via the CPU interface 11 and the bus B.

  Reference numeral 17 denotes a sprite processing circuit. The sprite processing circuit 17 reads the attribute data from the sprite attribute table 15, and uses the sprite pattern display position, size, enlargement / reduction ratio, etc. of the attribute data and the address of the sprite pattern on the video memory 3 to The address (one line) of the video memory 3 of the sprite pattern to be drawn (written) in the buffer 18 is obtained. Further, the sprite processing circuit 17 uses the display position of the sprite pattern of the attribute data and the address of the frame buffer for drawing in the video demo memory 3 to address the video memory (frame buffer for drawing) 3 (drawing frame buffer) ( 1 line). The sprite processing circuit 17 takes out dot data at the obtained address from the video memory 3. The sprite processing circuit 17 converts the extracted dot data into RGB color data using the color palette 14, and performs processing based on the sprite attribute data in the sprite attribute table 15 on the converted RGB color data. Color data is written in the line buffer 18 for drawing. When the drawing for one line in the line buffer 18 is completed, the sprite processing circuit 17 converts the color data stored in the line buffer switched from drawing (writing) to transferring to the video memory (frame buffer for drawing) 3. Write to the address requested. The sprite processing circuit 17 holds information for determining which of the two frame buffers is used as a drawing frame buffer, and changes this information when the display of one frame is completed.

  The line buffer 18 is a buffer memory having a storage slot corresponding to each display dot of the horizontal display line of the CRT display device 104, and is composed of two line buffers 18a and 18b (double buffer configuration). The two line buffers 18 a and 18 b are alternately used as a line buffer for drawing (writing) and a line buffer for transferring to the video memory 3 in line units. The line buffer 18 is a line buffer for drawing after the drawing of color data for one line is completed in the line buffer for drawing by a control circuit (not shown), and the line buffer for transfer is for drawing. Switch to line buffer.

  Reference numeral 19 denotes a CRT controller, which generates various pulse signals for driving the CRT display device 4 based on the clock pulses output from the clock generator 13, that is, horizontal scanning pulses, vertical scanning pulses, etc. Output to the pixel data controller 20. The pixel data controller 20 reads the color data from the video memory (buffer memory for display) 3 and outputs it to the DACs 21 a to 21 c according to the horizontal scanning pulse and the vertical scanning pulse input from the CRT controller 19. The pixel data controller 20 holds information for determining which of the two frame buffers is used as a display frame buffer, and changes this information when the display of one frame is completed. The DACs 21 a to 21 c convert the color data into analog signals and output them to the CRT display device 4.

  An outline of the operation of the image processing apparatus according to the present embodiment shown in FIG. 6 will be described. The CPU 2 sets RGB color data corresponding to the color code in the color palette 14, attribute data in the sprite attribute table 15, and various data necessary for operation in the register 16. Further, the CPU 2 stores the sprite pattern data in the video memory 3.

  The sprite processing circuit 17 obtains the address (one line) of the video memory 3 of the sprite pattern to be drawn according to the attribute data of the sprite attribute table 15, and also the video memory (drawing frame for drawing color data according to the attribute data etc. Buffer) 3 addresses (for one line) are obtained. The sprite processing circuit 17 takes out dot data at the obtained address from the video memory 3. The sprite processing circuit 17 converts the extracted dot data into RGB color data using the color palette 14, performs processing based on the sprite attribute data in the sprite attribute table 15 on the converted RGB color data, and performs post-processing. Color data is drawn in a line buffer for drawing (line buffer 18a or line buffer 18b). This is performed for all sprite patterns to be displayed.

  The drawing and transfer line buffers 18 a and 18 b are switched, and the sprite processing circuit 17 writes the color data of the line buffer switched for transfer to the address obtained by the video memory (frame buffer for drawing) 3.

  The pixel data controller 20 takes out the color data from the video memory (frame buffer for display) 3 and outputs it to the DACs 21a to 21c. The color data of the next frame is drawn in the video memory (drawing frame buffer) switched for drawing during this period.

  According to the image processing apparatus 1 of the present embodiment described above, the line buffer 18 is provided in the image processing apparatus 1, and color data for one line of the sprite pattern to be displayed is drawn on the line buffer 18, and after drawing The color data for one line stored in the line buffer 18 is rendered in the video memory (frame buffer for rendering) 3. For this reason, drawing on the line buffer 18 does not need to be synchronized with the display line of the CRT display device 4, and the sprite pattern is concentrated on the same line as in the conventional image processing device 101 of the line buffer type in FIG. There will be no loss of drawing.

Further, in order to compare with the drawing performance of the conventional frame buffer system of FIG. 3, an example of the drawing performance of the image processing apparatus of the present embodiment is shown. Here, as the types of access to the video memory 3 in the image processing apparatus 1 of the present embodiment, as shown in FIG. 7, “reading of sprite pattern”, “drawing to frame buffer (one side)”, “frame” There are three types of “reading display data from buffer (one side)”.
As in the case of the conventional frame buffer system of FIG. 3, the transfer speed is 200 Mdot / s (transfer speed when the video memory speed is 100 MHz, the video memory bus width is 16 bits, and the number of bits of one dot is 8 bits), The display size is 640 × 480 (one line is 640 dots, the number of lines is 480), and the frame frequency is 60 Hz.
The drawing performance is calculated by subtracting the bandwidth used for “reading display data from the frame buffer (1 side)” and “drawing to the frame buffer (1 side)” from the transfer rate (video memory bandwidth). It is calculated how many sprite patterns can be read out in the remaining band. Therefore,
Drawing performance =
(Transfer speed-2 x Display size x Frame frequency) / (Display size x Frame frequency)
In the case of the above setting,
(200M−2 × 640 × 480 × 60) / (640 × 480 × 60) = 8.8 (surface)
Thus, it can be seen that the drawing performance of the image processing apparatus 1 of the present embodiment is improved as compared with the drawing performance of 4.9 (surface) in the conventional frame buffer system of FIG.

  Although the best embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various design changes can be made as long as they are described in the claims. For example, two line buffers 18a and 18b are provided in the image processing apparatus 1 so as to switch between drawing and transfer for each line. However, the present invention is not limited to this, and one line buffer is used. Provided to draw one line in one line buffer, transfer the drawn line color data to the video memory (drawing buffer memory) 3, and draw the next line color data in the line buffer after the transfer is completed. It may be.

The block diagram which shows the structure of the conventional image processing apparatus which performs sprite display by a line buffer system. The figure for demonstrating the drawing and display in a line buffer system. The block diagram which shows the structure of the conventional image processing apparatus which performs sprite display by a frame buffer system. The figure for demonstrating the problem in the conventional line buffer system. The figure which shows the access pattern to the video memory in the conventional frame buffer system. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. The figure which shows the access pattern to the video memory in the system of this Embodiment.

Explanation of symbols

1 image processing device, 2 CPU, 3 video memory, 4 CRT display device, 11 CPU interface, 12 video memory interface, 13 clock generator, 14 color palette, 15 sprite attribute table, 16 register, 17 sprite processing circuit, 18 and 18a , 18b Line buffer, 19 CRT controller, 20 pixel data controller, 21a-21c DAC

Claims (2)

In an image processing apparatus that is used as a frame buffer for drawing and display, and that is connected to a storage device that stores data of a plurality of sprite patterns to be displayed on the display device, in such a manner that data can be exchanged,
A line buffer;
Data of a sprite pattern to be displayed on the display device is read from the storage device, display data based on the data is drawn in the line buffer, and the drawn display data is drawn in a drawing frame buffer of the storage device. A sprite processing circuit;
A display processing circuit that extracts display data from a display frame buffer of the storage device and performs display based on the display data on the display device;
An image processing apparatus comprising: The image processing apparatus according to claim 1, wherein the line buffer includes two line buffers.

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