JP2005128689A - Image drawing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image drawing device that enlarges an image at high speed. <P>SOLUTION: A control part 41 outputs a writing signal. A comparator 46 outputs a line finish signal every time line data are written. An X increment circuit 42 generates an X address incremented by 1/K in succession upon every writing signal input, and outputs its integral part X1. A Y increment circuit 45 generates a Y address incremented by 1/K in succession upon every line finish signal input, and outputs its integral part Y1. An X increment circuit 43 generates and outputs a second X address incremented by 1 in succession upon every writing signal input. A Y increment circuit 44 generates and outputs a second Y address incremented by 1 in succession upon every line finish signal input. Data in the address specified by X1 and Y1 are read from a buffer A, and original image data are rendered to a frame buffer 19 in dependence on the second X address and second Y address. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image drawing apparatus used for a game machine or the like.

In display processing of game machines and the like, character (sprite) enlargement / reduction processing is often performed. Conventionally, when the original sprite is enlarged and drawn in the frame buffer, as shown in FIG. 6, the color data of each pixel constituting the original sprite is transferred to the storage position after the enlargement of the frame buffer, and then written. Processing was performed to fill the space between each color data. However, such enlargement processing has a problem that processing takes time.
In addition, the prior art document corresponding to this invention has not been found.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an image drawing apparatus capable of performing image enlargement processing at high speed.

  The present invention has been made to solve the above-described problems. The invention according to claim 1 is a second embodiment in which the original image data in the first storage means is enlarged / reduced K times (K is a positive real number). In the image drawing device to be written in the storage means, a first signal output means for outputting a write signal, a second signal output means for outputting a row end signal every time writing of row data is completed, and the write signal First X address generating means for generating an X address which is incremented by 1 / K each time the data is received and outputting the integer part as the first X address; A first Y address generating means for generating a Y address that increases one by one and outputting the integer part as a first Y address, and a second X address that increases one by one each time the write signal is received Output X address generating means, and second Y address generating means for generating and outputting a second Y address that is incremented by one each time the row end signal is received, and the first X address And reading the original image data from the first storage means by the first Y address, and drawing the original image data in the second storage means by the second X address and the second Y address. It is characterized by.

  According to a second aspect of the present invention, in the image drawing apparatus according to the first aspect, the second X address generation unit includes a count unit that up-counts the write signal, and an output of the image display position at the output of the count unit. A second adder for generating an X-coordinate, wherein the second Y-address generating means includes a count means for up-counting the row end signal, and a Y-coordinate of an image display position at the output of the count means. And a second adding circuit for adding.

  According to the present invention, there is an effect that the processing time of the enlargement process can be shortened.

Embodiments of the present invention will be described below with reference to the drawings.
In the present embodiment, as shown in FIG. 2, the original image A and the image B enlarged K times are incremented in proportion to the original image side and the enlarged image side rasterizer, obtain. Here, when the enlarged image side is incremented, the original image side is incremented by 1 / K in synchronization therewith. As a result, if the integer part of the address on the original image side is the same, the enlarged pixel is also determined to have the same color as the original image. This is repeated, and when the address on the original image side exceeds 1, the color of the original image changes, and thus the color on the enlargement side also changes. In the case of reduction, the image data on the original image side is skipped and read, and the color changes with each increment.

  FIG. 3 is a block diagram showing the configuration of the image drawing apparatus according to the present embodiment. In FIG. 3, reference numeral 11 denotes a character ROM (Read Only Memory) in which sprite compressed image data is stored. Reference numeral 12 denotes a FIFO (First In First Out) memory in which the compressed image data of the sprite read from the character ROM 11 is temporarily stored.

  Reference numeral 13 denotes a decompression engine, which decompresses the compressed image data given from the character ROM 11 via the FIFO memory 12 and returns the image data to a pre-compression image data (color code or YUV format pixel value). Next, when the image data is a color code, the color code is converted into RGB (red, green, blue) color data by the color palette 14 and is transferred to the sprite buffer A or B on the two sides via the flip-flop 15. Write. When the decompressed image data is a pixel value in YUV (luminance / color difference) format, it is converted into RGB color data by the YUV decoder 16 and written into the sprite buffer A or B via the flip-flop 15. In this case, control data indicating which of the sprite buffers A and B is to be written is output from the decompression engine 13.

  A drawing engine 18 reads the RGB color data of the sprite from the sprite buffer A or B according to an instruction from the controller 17, and performs rotation, enlargement / reduction, etc. based on the instruction data output from the controller 17 to the read RGB color data. The transformation process is performed, and then the RGB color data after the transformation process is written to the address of the frame buffer 19 indicated by the position data output from the controller 17. The frame buffer 19 is composed of two banks and is alternately used as a drawing buffer and a display buffer.

  The controller 17 writes various instructions (sprite attribute data) output from the CPU (not shown) and supplied via the CPU interface block 20 to the sprite attribute table 22 via the SRAM interface block 21 and the written data. The decompression engine 13 and the drawing engine 18 are controlled based on the sprite attribute data. Further, the controller 17 reads the RGB color data from the frame buffer 19 and outputs it to the display device (not shown) via the display interface block 23.

  Next, the operation of the above-described embodiment will be described with reference to the flowchart shown in FIG. The flowchart of FIG. 4 shows an example in which N sprites are drawn in the frame buffer 19. In step SA1, the controller 17 in FIG. 3 sets one of the two banks of the frame buffer 19 for drawing and the other for display. Next, in step SA2 to step SA6, the controller 17 sequentially processes all the sprites shown in the sprite attribute table 23 of FIG.

  That is, the controller 17 first writes data “1” in the internal register SPNO (not shown) (step SA2). Next, the sprite attribute table 23 is accessed, and the attribute data corresponding to the data in the register SPNO (in this case “1”), that is, the attribute data of the sprite 1 is fetched (step SA3). Next, the character ROM 11 is accessed based on the address of the character of the sprite 1 indicated by the attribute data, and the character of the sprite 1 is read (step SA4). The read character is stored in the FIFO 12.

  Next, the controller 17 outputs a decompression instruction to the decompression engine 13, and then outputs the attribute data of the sprite 1 to the rendering engine 18 to instruct rendering (step SA5). The rendering engine 18 renders the RGB color data decompressed by the decompression engine 13 and written in the sprite buffers A and B, and performs rendering processing such as enlargement, reduction, and rotation indicated by the attribute data, and then is included in the attribute data. Based on the displayed display position data, the data is written into the drawing bank of the frame buffer 19. When the writing is completed, the controller 17 checks whether or not the data in the register SPNO is “N” (step SA6). If not, the data in the register SPNO is “ 1 "is added (step SA7), and the process returns to step SA3.

Thereafter, the drawing process for sprites 2 to N is performed by the same process as described above. The outline of the drawing process described above is the same as that of a conventional drawing apparatus.
Next, the sprite enlargement / reduction process performed in the drawing engine 18 that is unique to this embodiment will be described in detail.

  FIG. 1 is a block diagram showing the configuration of a rasterizer that performs sprite enlargement / reduction processing, and this rasterizer is provided in the rendering engine 18. Of course, this rasterizer may be realized by software of a microprocessor.

  In FIG. 1, reference numeral 41 denotes a control unit that controls each unit, 42 denotes an X increment circuit, and 45 denotes a Y increment circuit. The X increment circuit 42 adds 1 / K (K: a constant output from the control unit 41) (see FIG. 5) to the data in the internal register at the timing of the synchronization signal S output from the control unit 41. The integer part of the addition result is stored in the register, and the integer part is output to the address terminal of the sprite buffer A (or B). The Y increment circuit 45 adds 1 / K (K: a constant output from the control unit) to the data in the internal register at the timing of the signal C1 output from the comparator 46, and the addition result is stored in the register. At the same time, the integer part is output to the address terminal of the sprite buffer A (or B).

The X increment circuit 43 includes a counter, and counts up the synchronization signal S output from the control unit 41 and outputs the count output to the adder circuit 48. Further, it is reset by the output signal C1 of the comparator 46. The Y increment circuit 44 is also a counter, and counts up the output signal C1 of the comparator 46 and outputs the count output to the adder circuit 49. Further, it is reset by the output signal C2 of the comparator 47.
The comparator 46 compares the output of the X increment circuit 43 with the character size a (see FIG. 5), which is the horizontal size of the character after enlargement (reduction), and if they match, the comparator 46 compares the pulse signal with the X increment circuit. The reset signal is output to the reset terminal 43 and the clock terminal of the Y increment circuit 44. The comparator 47 compares the output of the Y increment circuit 44 with the character size b (see FIG. 5) which is the vertical size of the enlarged (reduced) character. 45, output to each reset terminal of the Y increment circuit 44 and the control unit 41.
The adder circuit 48 adds the output of the X increment circuit 43 and the X coordinate of the display position (see FIG. 5), and outputs the addition result to the address terminal of the frame buffer 19. The adder circuit 49 adds the output of the Y increment circuit 44 and the Y coordinate (see FIG. 5) of the display position, and outputs the addition result to the address terminal of the frame buffer 19.

Next, the operation of the circuit described above will be described.
When the drawing command and the sprite attribute table (FIG. 5) are output from the controller 17 of FIG. 1 to the drawing engine 18, the control unit 41 (FIG. 1) receives it and temporarily stores the contents of the sprite attribute table in an internal register. To do. Next, the control unit 41 outputs the magnification K specified in the sprite attribute table (hereinafter described as K = 4) to the X increment circuit 42 and the Y increment circuit 45, and then the X increment circuit 42. 43, and Y increment circuits 44 and 45 are reset, then the X and Y coordinates are output to the adder circuits 48 and 49, and the character sizes a and b are output to the comparators 46 and 49, respectively.

  When the X increment circuit 42 and the Y increment circuit 45 are reset, “0, 0” is output to the address terminal of the sprite buffer A, whereby the color data in the address “0, 0” of the sprite buffer A is read. And output to the data input terminal of the frame buffer 19. When the X increment circuit 43 and the Y increment circuit 44 are reset and the X and Y coordinates are output to the adder circuits 48 and 49, “X, Y] is output to the address terminal of the frame buffer 19, As a result, the color data in the address “0, 0” of the sprite buffer A is written to the address “X, Y” of the frame buffer 19.

  Thereafter, the control unit 41 outputs the synchronization signal S at regular intervals. When the first synchronization signal S is output, the X increment circuit 42 adds 1 / K = 0.25 to the data “0” in the internal register, and the integer part “ 0 "is output. As a result, “0, 0” is output to the address terminal of the sprite buffer A. On the other hand, when the synchronization signal S is supplied to the X increment circuit 43, the output of the X increment circuit 43 becomes “1”, and therefore “X + 1, Y” is supplied to the address terminal of the frame buffer 19. As a result, the color data in the address “0, 0” of the sprite buffer A is written to the address “X + 1, Y” of the frame buffer 19. That is, the same color data as the address “X, Y” is written to the address “X + 1, Y” of the frame buffer 19.

  Thereafter, when the second and third synchronization signals S are sequentially output from the control unit 41, the addresses “X + 2, Y”, “X + 3, Y” of the frame buffer 19 are sequentially assigned to the addresses “X”. The same color data as “X, Y” is written. Next, when the fourth synchronization signal S is output from the control unit 41, the data “1” is output from the X increment circuit 42, whereby the color data in the address “1, 0” of the sprite buffer A is output. Are read out and output to the frame buffer 19. At this time, “4” is output from the X increment circuit 43, whereby the color data in the address “1, 0” of the sprite buffer A is written to the address “X + 4, Y” of the frame buffer 19.

  Thereafter, color data is sequentially written in the frame buffer 19 in the same manner. When the output of the X increment circuit 43 reaches the character size a, the pulse signal C1 is output from the comparator 46 and supplied to the reset terminals of the X increment circuits 42 and 43 and the input terminals of the Y increment circuits 44 and 45. . As a result, the X increment circuits 42 and 43 are reset and the output becomes “0”. Further, the data in the register of the Y increment circuit 45 becomes “0.25”, and therefore the output of the Y increment circuit 45 continues to be “0”. Further, the output of the Y increment circuit 44 becomes “1”. As a result, the color data in the address “0, 0” of the sprite buffer A is written into the address “X, Y + 1” of the frame buffer 19.

  Thereafter, each time the synchronization signal S is output, the frame buffer 19 is written, and every time the signal C1 is output from the comparator 46, the data in the register in the Y increment circuit 45 becomes “0.5”, “0”. .75 ". When the data in the register in the Y increment circuit 45 reaches “1”, the color data in the row where the Y address of the frame buffer A is “1” is read and written in the frame buffer 19. When the output of the Y increment circuit 44 reaches the character size b, the pulse signal C2 is output from the comparator 47 and supplied to the control unit 41. The control unit 41 receives this pulse signal C 2, detects the end of the enlarged drawing, and outputs an end notification to the controller 17.

  In the above description, the case of enlarging to 4 times (K = 4) is taken as an example, but the circuit of FIG. 1 can also be used for reducing an image. For example, when reducing to ¼, K = 1/4. Therefore, every time the X increment circuit 42 and the Y increment circuit 45 receive a pulse signal, the data “1 / K” is stored in the internal register. = 4 "is added and output.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings, but the specific configuration is not limited to these embodiments, and includes design changes and the like within a scope not departing from the gist of the present invention. It is. For example, although the rasterizer is included in the drawing engine 18 in the present embodiment, a function independent of the drawing engine 18 may be used.

It is a block diagram which shows the structure of the rasterizer by one Embodiment of this invention. It is a figure showing the expansion process of an image. 1 is a block diagram illustrating a configuration of an image drawing apparatus according to an embodiment of the present invention. It is a flowchart which shows schematic operation | movement of the embodiment. It is a structure figure of the sprite attribute table 22 in the same embodiment. It is a figure for demonstrating the conventional image expansion process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Character ROM, 12 ... FIFO memory, 13 ... Decompression engine, 14 ... Sprite color palette, 15 ... Flip-flop, 16 ... Sprite YUV decoder, 17 ... Controller, 18 ... Drawing engine, 19 ... Frame buffer, 20 ... CPU interface Block 21. SRAM interface block 22 Sprite attribute table 23 Display interface block 41 Control unit 42 X increment circuit 43 X increment circuit 44 Y increment circuit 45 Y increment circuit 46 , 47: Comparator, A (B): Sprite buffer, 48, 49: Adder circuit, A: Original image, B: Image enlarged by K times

Claims (2)

In the image drawing apparatus that enlarges / reduces the original image data in the first storage means to K times (K is a positive real number) and writes it in the second storage means,
First signal output means for outputting a write signal;
Second signal output means for outputting a row end signal each time writing of row data is completed;
A first X address generating means for generating an X address that sequentially increases by 1 / K each time the write signal is received, and outputting the integer part as a first X address;
First Y address generating means for generating a Y address that sequentially increases by 1 / K each time the row end signal is received, and outputting the integer part as a first Y address;
Second X address generation means for generating and outputting a second X address that is incremented by one each time the write signal is received;
Second Y address generation means for generating and outputting a second Y address that is incremented by 1 each time the row end signal is received;
The original image data is read from the first storage means by the first X address and the first Y address, and the original image data is read by the second X address and the second Y address. An image drawing apparatus, wherein the image is drawn in the second storage means. The second X address generation means includes a counting means for up-counting the write signal and a first addition circuit for adding the X coordinate of the image display position to the output of the counting means. The Y address generation means comprises: counting means for up-counting the row end signal; and a second addition circuit for adding the Y coordinate of the image display position to the output of the counting means. 2. The image drawing apparatus according to 1.

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