JP2006005372A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory device including a plurality of stack gate type memory cells that can shorten a time required for simultaneous erasing operation by eliminating writing operation before erasing and also shorten a time required for rewriting data. <P>SOLUTION: In erasing, electrons are simultaneously injected into floating gates 1005 from sources 1003 of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from the floating gate 1005 of a selected memory cell to a drain 1002. Thus, the threshold voltage of the selected memory cell is reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an electrically programmable and erasable nonvolatile semiconductor memory device (hereinafter referred to as a flash memory) including a stack gate type memory cell.

  First, the general definition of erase and program will be described. Erasing means changing the threshold voltages of a plurality of memory cells to a predetermined state at once. Programming means changing the threshold voltage of a selected memory cell to another predetermined state. Data “1” is made to correspond to the erased memory cell, and data “0” is made to correspond to the programmed memory cell.

(1) Cross-sectional structure of memory cell (FIGS. 128 and 129)
FIG. 128 shows a cross-sectional structure of a general stack gate type memory cell (memory transistor) used in a conventional flash memory. Two N + type impurity regions are formed on the main surface of the P− type semiconductor substrate 1001 with a predetermined interval. One impurity region constitutes the drain 1002 and the other impurity region constitutes the source 1003. On the region of the semiconductor substrate 1001 between the drain 1002 and the source 1003, an insulating film 1004 (about 100 cm) made of an extremely thin oxide film or the like is formed. A floating gate 1005 is formed on the insulating film 1004, and a control gate 1006 is further formed thereon via an insulating film. Thus, the memory cell has a double gate structure. The P − type semiconductor substrate 1001 may be replaced with a P − well.

  In a flash memory, information (data) is stored in a memory cell depending on whether electrons are injected into the floating gate 1005 or emitted from the floating gate 1005.

  In the state where electrons are injected into the floating gate 1005, the threshold voltage of the memory cell viewed from the control gate 1006 is high. As shown in FIG. 129, the drain 1002 and the source are not supplied unless the control gate voltage becomes Vg0 or higher. No current flows between 1003. This is because the positive voltage is canceled by the negative charge of the electrons accumulated in the floating gate 1005. This state is called a program state. In this case, data “0” is stored in the memory cell. Since the electrons accumulated in the floating gate 1005 are not permanently erased as they are, the stored data is also retained semipermanently.

  In the state where electrons are emitted from the floating gate 1005, the threshold voltage of the memory cell viewed from the control gate 1006 is low. As shown in FIG. 129, when the control gate voltage becomes Vg1 or more, the drain 1002 and the source A current flows between 1003. This state is called an erased state. In this case, data “1” is stored in the memory cell.

  By detecting these two states, data stored in the memory cell can be read.

(2) Program and erase of memory cell (FIG. 130)
FIG. 130A shows the voltage application conditions at the time of programming the memory cell, and FIG. 130B shows the voltage application conditions at the time of erasing the memory cell.

  At the time of programming, a write voltage Vw (usually about 6V) is applied to the drain 1002, a high voltage Vpp (usually about 12V) is applied to the control gate 1006, and the source 1003 is grounded. Accordingly, hot electrons due to avalanche breakdown are generated in the vicinity of the drain 1002, or channel hot electrons having high energy are generated in a channel formed in a region between the drain 1002 and the source 1003. Hot electrons accelerated by the high voltage of the control gate 1006 jump over the energy barrier by the insulating film 1004 and are injected into the floating gate 1005 from the vicinity of the drain. As a result, the threshold voltage of the memory cell increases.

  At the time of erasing, the drain 1002 is set in a floating state, a high voltage Vpp is applied to the source 1003, and the control gate 1006 is grounded. Accordingly, a high voltage is generated in the thin insulating film 1004, and electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

  Thus, at the time of programming, electrons are injected into the floating gate 1005 by hot electrons. Therefore, as shown in FIG. 130, a P + -type impurity region 1002a is provided along the drain 1002 so that a higher electric field is generated in the channel direction or the substrate direction.

  At the time of erasing, electrons are emitted from the floating gate 1005 to the source 1003 by a tunnel phenomenon. Therefore, only an electric field between the floating gate 1005 and the source 1003 is necessary at the time of erasing. The electric field in the channel direction or the substrate direction is preferably small so that no leakage current occurs. Therefore, an N − -type impurity region 1003a is provided along the source 1003 in order to weaken the electric field in the channel direction or the substrate direction.

(3) Overall configuration of flash memory (FIGS. 131 and 132)
FIG. 131 is a block diagram showing the overall configuration of a conventional flash memory.

  Memory array 1010 includes a plurality of bit lines, a plurality of word lines crossing the plurality of bit lines, and a plurality of memory cells provided at intersections thereof.

  In FIG. 131, four memory cells M00, M01, M10, and M11 arranged in two rows and two columns are shown for ease of explanation. The drains of the memory cells M00 and M01 are connected to the bit line BL0, and the drains of the memory cells M10 and M11 are connected to the bit line BL1. The control gates of the memory cells M00 and M10 are connected to the word line WL0, and the control gates of the memory cells M01 and M11 are connected to the word line WL1. Sources of the memory cells M00, M01, M10, and M11 are connected to the source line SL.

  Address buffer 1020 receives an externally applied address signal AD, provides an X address signal to X decoder 1030, and a Y address signal to Y decoder 1040. The X decoder 1030 selects one of the plurality of word lines WL0 and WL1 in response to the X address signal. The Y decoder 1040 generates selection signals Y0 and Y1 for selecting any of the plurality of bit lines in response to the Y address signal.

  Y gate 1050 includes Y gate transistors YG0 and YG1 corresponding to bit lines BL0 and BL1. Y gate transistors YG0 and YG1 connect bit lines BL0 and BL1 to sense amplifier 1060 and write circuit 1080 in response to selection signals Y0 and Y1, respectively.

  At the time of reading, sense amplifier 1060 detects data read on bit line BL0 or bit line BL1, and outputs the data to the outside via data input / output buffer 1070. During programming, externally applied data DA is applied to write circuit 1080 via data input / output buffer 1070, and write circuit 1080 applies a write voltage to bit lines BL0 and BL1 in accordance with the data.

  Vpp / Vcc switching circuit 1090 receives a high voltage (usually 12V) applied from the outside and a power supply voltage Vcc (usually 5V) applied from the outside, and supplies high voltage Vpp or Xpp to X decoder 1030, Y decoder 1040 and write circuit 1080. A power supply voltage Vcc is applied. A verify voltage generation circuit 1100 receives a power supply voltage Vcc supplied from the outside, and applies a predetermined verify voltage to a selected word line at the time of verify described later. Source control circuit 1110 applies high voltage Vpp to source line SL during erasing.

  The control signal buffer 1120 gives a control signal CT given from the outside to the control circuit 1130. The control circuit 1130 controls the operation of each circuit.

  As shown in FIG. 132, the X decoder 1030 includes a decoder circuit 1301 and a plurality of high voltage switches 1302 corresponding to the plurality of word lines WL. The decoder circuit 1301 decodes the X address signal XA and generates a selection signal for selecting any one of the plurality of word lines WL. Each high voltage switch 1302 applies the high voltage Vpp or the power supply voltage Vcc to the selected word line WL in response to the control signal SW supplied from the control circuit 1130.

This flash memory is formed on the chip CH.
(4) Flash memory operation (FIGS. 133 to 140)
(A) Program operation (FIG. 133)
FIG. 133 is a diagram illustrating voltage application conditions during a program operation. Here, for example, it is assumed that memory cell M00 is programmed. The control circuit 1130 is supplied with a control signal designating a program operation via the control signal buffer 1120. High voltage Vpp is externally applied to Vpp / Vcc switching circuit 1090. Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030 and Y decoder 1040.

  X decoder 1030 selects word line WL0 in response to the X address signal applied from address buffer 1020, and applies high voltage Vpp thereto.

  The Y decoder 1040 supplies a high voltage selection signal Y0 to the Y gate transistor YG0 in response to the Y address signal supplied from the address buffer 1020. Thereby, the Y gate transistor YG0 is turned on.

  The source control circuit 1110 applies 0 V to the source line SL. Write circuit 1080 is activated. Thereby, write voltage Vw is applied to bit line BL0.

  As a result, a voltage is applied to the memory cell M00 as shown in FIG. 130A, and the memory cell M00 is programmed.

(B) Erase operation (FIGS. 134 to 136)
The erase operation includes a pre-erase write operation and a batch erase operation.

(I) Write operation before erasure (FIG. 134)
Before erasing the memory cells at once, all the memory cells are programmed by the above method. In this way, the threshold voltage of all memory cells is increased. This is called a pre-erase write operation.

  The pre-erase write operation will be described with reference to the flowchart of FIG. First, it is determined whether or not the data in all the memory cells is “0” (step S51). If the data in all the memory cells is not “0”, the address designated by the address signal is set to address 0 (step S52). Then, the memory cell specified by the address signal is programmed by the program operation described above (step S53).

  Next, it is determined whether or not the address designated by the address signal is the last address (step S54). If the address is not the final address, the address is incremented by 1 (step S55), and the program operation is performed (step S53). This operation is continued until the address reaches the final address (steps S53, S54, S55). When the address reaches the final address, the pre-erase write operation is terminated.

(Ii) Batch erase operation (FIGS. 135 and 136)
Next, the batch erase operation will be described with reference to the flowchart of FIG. FIG. 136 shows voltage application conditions during batch erase.

  First, a control signal designating batch erase is given to the control circuit 1130 via the control signal buffer 1120. At the time of batch erasure, Vpp / Vcc switching circuit 1090 applies high voltage Vpp to source control circuit 1110. Source control circuit 1110 provides high voltage Vpp to source line SL (step S61).

  The X decoder 1030 grounds the word lines WL0 and WL1. The Y decoder 1040 supplies 0V selection signals Y0 and Y1 to the Y gate transistors YG0 and YG1, respectively. Thereby, the bit lines BL0 and BL1 are in a floating state.

  As a result, a voltage is applied to all the memory cells as shown in FIG. 130B, and the threshold voltages of all the memory cells are lowered.

  Only by applying a high voltage (erase voltage) once to the source line SL, it is difficult to lower the threshold voltages of all the memory cells below a predetermined value. Therefore, in general, a high voltage pulse is applied to the source line SL a plurality of times, and an erase verify operation is performed after each pulse is applied.

  First, after a high voltage pulse is applied to the source line SL (step S61), the source line SL is set to 0 V (step S62), and address 0 is selected (step S63). A predetermined verify voltage lower than the power supply voltage Vcc is applied to the selected word line by the verify voltage generating circuit 1100 (step S64). Thereby, the data of the selected memory cell is read out to the corresponding bit line and detected by sense amplifier 1060. Then, it is determined whether or not the data detected by the sense amplifier 1060 is “1” (step S65).

  If the data detected by the sense amplifier 1060 is “0”, steps S61 to S64 are repeated.

  If the data detected by the sense amplifier 1060 is “1”, it is determined whether or not the address specified by the address signal is the last address (step S66). If the address is not the final address, the address is incremented by 1 (step S67). In this way, the data of all the memory cells are read while incrementing the address by one. If the read data is “0”, a high voltage pulse is applied to the source line SL to erase the memory cell.

  In this manner, all the memory cells are gradually erased while monitoring the threshold voltage of the memory cells.

(C) Read operation (FIG. 137)
FIG. 137 shows voltage application conditions during the read operation. Here, it is assumed that data is read from memory cell M00.

  First, a control signal designating a reading operation is supplied to the control circuit 1130 via the control signal buffer 1120. X decoder 1030 selects word line WL0 in response to the X address signal applied from address buffer 1020, and applies power supply voltage Vcc thereto. At this time, the potential of the non-selected word line is kept at 0V.

  Y decoder 1040 turns on Y gate transistor YG0 in response to a Y address signal applied from address buffer 1020. Thereby, the bit line BL0 is connected to the sense amplifier 1060. At this time, 0 V is applied to the source line SL by the source control circuit 1110.

  As a result, when the threshold voltage of the memory cell M00 is low, the memory cell M00 is turned on. Thereby, current I flows through resistor R in sense amplifier 1060, and read voltage Vr on bit line BL0 is lowered. The read voltage Vr on the bit line BL0 is output as data “1” via the inverter INV2.

  When the threshold voltage of the memory cell M00 is high, the memory cell M00 is turned off. Thereby, the read voltage Vr on the bit line BL0 is increased. Read voltage Vr on bit line BL0 is output as data “0” via inverter INV2.

  When the voltage of the bit line at the time of reading becomes close to the power supply voltage Vcc, hot electrons are generated and the memory cell may be programmed. This is called soft light. In order to prevent this soft write, the read voltage Vr on the bit line is set to about 1 V by the N-channel transistor TR and the inverter INV1.

(D) Potential of each line in each operation (FIG. 138)
FIG. 138 shows word line, bit line, and source line potentials in the program operation, erase operation, and read operation. During programming and pre-erase writing, the high voltage Vpp is applied to the word line, the write voltage Vw is applied to the bit line, and 0 V is applied to the source line. At the time of batch erasing, high voltage Vpp is applied only to the source line, 0V is applied to the word line, and the bit line is in a floating state. At the time of reading, the power supply voltage Vcc is applied to the word line, the source line becomes 0V, and the read voltage Vr appears on the bit line.

(E) Reason why write operation before erasure is necessary (FIGS. 139 and 140)
Next, the reason why the pre-erase write operation is necessary at the time of erasing will be described with reference to FIGS. 139 and 140. FIG. FIG. 139 shows changes in the threshold voltage of the memory cell when the program operation and the batch erase operation are performed. FIG. 140 shows a change in the threshold voltage of the memory cell when the program operation, the pre-erase write operation, and the batch erase operation are performed.

  In the batch erase operation, as shown in FIG. 130B, the control gate 1006 of the memory cell becomes 0V, the drain 1002 enters a floating state, and the source 1003 is supplied with the high voltage Vpp. Under such a voltage application condition, a high voltage is generated between the source 1003 and the floating gate 1005, and electrons accumulated in the floating gate 1005 are extracted by the source 1003 due to the high voltage. As a result, the threshold voltage of the memory cell is lowered.

  However, if this erase operation is performed in a state where the threshold voltage is low (data “1”), the threshold voltage of the memory cell becomes negative as shown in FIG. This is called memory cell depletion. Due to the depletion of the memory cell, the following problems occur during reading.

  Here, in the read operation shown in FIG. 137, it is assumed that memory cell M00 is selected and memory cell M01 is depleted by batch erase. That is, the threshold voltage of the memory cell M01 is negative.

  In this case, the power supply voltage Vcc is applied to the word line WL0, but the potential of the word line WL1 remains 0V. If the memory cell M00 stores data “0”, the memory cell M00 is not turned on even if the potential of the word line WL0 becomes the power supply voltage Vcc. Therefore, no current is generated in the bit line BL0.

  However, if the threshold voltage of the memory cell M01 is negative, the memory cell M01 is turned on even if the potential of the word line WL1 is 0V. As a result, a current is generated in the bit line BL0. In this case, the sense amplifier 1060 determines that the data stored in the memory cell M00 is “1”.

  As described above, if the threshold voltage of at least one memory cell among the memory cells connected to the bit line is negative, even if the memory cell is in a non-selected state, a current is supplied to the bit line. It will flow. Therefore, the data stored in the selected memory cell cannot be read accurately.

  In order to solve such a problem, as shown in FIG. 140, a pre-erase write operation is performed before the batch erase operation. As a result, the threshold voltages of all the memory cells are once raised to a high state, and then a batch erase operation is performed. As a result, the voltage of the erased memory cell is unified to a positive value and a value lower than the power supply voltage Vcc. Thus, reliability is improved by the pre-erase write operation.

Hereinafter, the structure of the conventional flash memory will be described in more detail.
There is a flash memory as a memory device that can freely write data and is electrically erasable. An EEPROM composed of one transistor and capable of electrically erasing written information charges collectively, a so-called flash memory is disclosed in US Pat. No. 4,868,619, “An In-System Reprogrammable 32K × 8”. CMOS Flash Memory "by Virgil Niles Kynett et al. , IEEE Journal of Solid-State Circuits, vol. 23, no. 5, October 1988.

  FIG. 148 is a block diagram showing a general configuration of the flash memory. In the figure, the flash memory includes a memory cell matrix 1, an X address decoder 2, a Y gate 3, a Y address decoder 4, an address buffer 5, a write circuit 6, a sense amplifier 7 arranged in a matrix. The input / output buffer 8 and the control logic 9 are included.

  The memory cell matrix 1 has a plurality of memory transistors arranged in a matrix. An X address decoder 2 and a Y gate 3 are connected to select a row and a column of the memory cell matrix 1. The Y gate 3 is connected to a Y address decoder 4 for providing column selection information. Each of the X address decoder 2 and the Y address decoder 4 is connected to an address buffer 5 in which address information is temporarily stored.

  The Y gate 3 is connected to a write circuit 6 for performing a write operation at the time of data input and a sense amplifier 7 for determining “0” and “1” from a current value flowing at the time of data output. An input / output buffer 8 for temporarily storing input / output data is connected to each of the write circuit 6 and the sense amplifier 7. A control logic 9 for controlling the operation of the flash memory is connected to the address buffer 5 and the input / output buffer 8. The control logic 9 performs control based on the chip enable signal, the output enable signal, and the program signal.

  FIG. 149 is an equivalent circuit diagram showing a schematic configuration of memory cell matrix 1 shown in FIG. A flash memory having this memory cell matrix is called a NOR type. In the figure, a plurality of word lines WL1, WL2,..., WLi extending in the row direction and a plurality of bit lines BL1, BL2,. To do. Memory transistors Q11, Q12,..., Qij having floating gates are arranged at the intersections of the word lines and the bit lines. The drain of each memory transistor is connected to each bit line. The control gate of the memory transistor is connected to each word line. The source of the memory transistor is connected to each source line S1, S2,. The sources of the memory transistors belonging to the same row are connected to each other as shown in the figure.

  FIG. 150 is a partial cross-sectional view showing a cross-sectional structure of one memory transistor constituting the NOR flash memory as described above. FIG. 151 is a schematic plan view showing a planar arrangement of a NOR flash memory. 152 is a partial cross-sectional view taken along line AA in FIG. The structure of the NOR type flash memory will be described with reference to these drawings.

  Referring to FIGS. 150 and 152, an n-type impurity region, for example, drain region 11 and source region 12 are formed at an interval on the main surface of p-type impurity region 10 provided on the silicon substrate. Yes. In a region sandwiched between the drain region 11 and the source region 12, a control gate 13 and a floating gate 14 are formed so that a channel is formed. The floating gate 14 is formed on the p-type impurity region 10 with a thin gate oxide film 15 having a thickness of about 100 mm interposed therebetween. The control gate 13 is formed on the floating gate 14 with an interlayer insulating film 16 interposed so as to be electrically isolated from the floating gate 14. The floating gate 14 is made of polycrystalline silicon. The control gate 13 is composed of a polycrystalline silicon layer or a laminated film of a polycrystalline silicon layer and a refractory metal. The oxide film 17 is formed by depositing the surface of the polycrystalline silicon layer constituting the floating gate 14 and the control gate 13 by the CVD method. Further, a smooth coat film 21 (see FIG. 152) is formed so as to cover the floating gate 14 and the control gate 13.

  As shown in FIG. 151, the control gates 13 are formed as word lines so as to be connected to each other and extend in the horizontal direction (row direction). The bit line 18 is arranged so as to be orthogonal to the word line 13 and is electrically connected to each drain region 11 through the drain contact 20. As shown in FIG. 152, the bit line 18 is formed on the smooth coat film 21. As shown in FIG. 151, source region 12 extends along the direction in which word line 13 extends, and is formed in a region surrounded by word line 13 and field oxide film 19. The drain region 11 is also formed in a region surrounded by the word line 13 and the field oxide film 19.

  The operation of the NOR flash memory configured as described above will be described with reference to FIG.

  First, in the write operation, a voltage of about 5 V is applied to the drain region 11 and a voltage of about 10 V is applied to the control gate 13. The source region 12 and the p-type impurity region 10 are kept at the ground potential (OV). At this time, a current of several hundred μA flows through the channel of the memory transistor. Among the electrons flowing from the source to the drain, the electrons accelerated in the vicinity of the drain become electrons having high energy in the vicinity, so-called channel hot electrons. The electrons are injected into the floating gate 14 as indicated by the arrow 1 by the electric field generated by the voltage applied to the control gate 13. In this way, electrons are accumulated in the floating gate 14, and the threshold voltage Vth of the memory transistor becomes 8V, for example. This state is called a write state, “0”.

  Next, in the erase operation, a voltage of about 5V is applied to the source region 12, a voltage of about -10V is applied to the control gate 13, and the p-type impurity region 10 is held at the ground potential. Then, the drain region 11 is released. Due to the electric field generated by the voltage applied to the source region 12, as indicated by the arrow 2, electrons in the floating gate 14 pass through the thin gate oxide film 15 by the FN tunnel phenomenon. In this way, the electrons in the floating gate 14 are extracted, whereby the threshold voltage Vth of the memory transistor becomes 2V, for example. This state is called an erased state, “1”. Since the sources of the memory transistors are connected as shown in FIG. 149, all memories can be erased collectively by this erase operation.

  Further, in the read operation, a voltage of about 5 V is applied to the control gate 13 and a voltage of about 1 V is applied to the drain region 11. The source region 12 and the p-type impurity region 10 are held at the ground potential. At this time, “1” or “0” is determined depending on whether a current flows in the channel region of the memory transistor.

  That is, since Vth is 8V in the write state, no channel is formed and no current flows. On the other hand, since Vth is 2V in the erase state, a channel is formed and current flows.

  In the NOR type, electrons are injected into the floating gate 14 using channel hot electrons, and the write state is set to “0”. Since electron injection by channel hot electrons is inefficient, the NOR type has a problem that power consumption increases.

  Referring to FIG. 152, for example, when memory transistor 22a is selected and written, by applying a voltage of about 5V to drain region 11 and about 10V to control gate 13 as described above, the memory Writing is performed on floating gate 14 of transistor 22a.

  Next, when the memory transistor 22b is selected and written, the same voltage is applied to the drain region 11 and the control gate 13 in the memory transistor 22b. The memory transistor 22a and the memory transistor 22b share the drain region 11. Accordingly, in some cases, electrons injected into the floating gate 14 of the memory transistor 22a are pulled out to the drain region 11 by a tunnel phenomenon due to a voltage applied to the drain region 11 when writing to the memory transistor 22b. This phenomenon is called drain disturb phenomenon. Due to the drain disturb phenomenon, electrons are extracted from the floating gate of the memory transistor into which electrons have been injected, so that the memory transistor that should have been in the written state is in the erased state, causing malfunction of the flash memory.

  There is a NAND type to solve the problem of the NOR type. The NAND type flash memory is, for example, the NIKKE ELECTRONICS 1992.2.17 (no. 547) PP. 180-181. FIG. 153 is an equivalent circuit diagram of a part of the memory cell matrix of the NAND flash memory. In the select gate transistors 39a, 39b, and 39c, one impurity region is connected to the bit line, and the other impurity region is connected to the memory transistors 38a, 38b, and 38c.

  Eight memory transistors 38a arranged in the vertical direction are selected by the select gate transistor 39a, eight memory transistors 38b arranged in the vertical direction are selected by the select gate transistor 39b, and eight memory transistors 38b are arranged in the vertical direction by the select gate transistor 39c. The memory transistors 38c arranged side by side are selected. These memory transistors 38a, 38b, and 38c are grounded through select gate transistors 23a, 23b, and 23c, respectively.

  FIG. 154 is a cross-sectional view of a part of the memory cell matrix of the NAND flash memory. Impurity regions 27 are formed at intervals in the P-type impurity region 30 formed in the silicon substrate 26. A memory transistor 38 a including a floating gate 29 and a control gate 28 is formed between the impurity regions 27.

  FIG. 155 is a sectional view of the memory transistor 38a. Impurity regions 27 are formed in the p-type impurity region 30 formed on the silicon substrate with a space therebetween. A gate oxide film 35, a floating gate 29, an interlayer insulating film 36, and a control gate 28 are stacked on the p-type impurity region 30 between the impurity regions 27. The control gate 28 and the floating gate 29 are covered with an oxide film 37.

  The operation of the NAND flash memory will be described below with reference to FIGS. First, the writing operation will be described. For example, when writing to the memory transistor 38a having the word line W8, the select gate S2, the bit line B1, the source line and the p-type impurity region 30 of the select gate transistor are kept at the ground potential, and S1, B2 and B3 have about 10V. A voltage is applied, a voltage of about 20 V is applied to the word line W8, and the other word lines W1 to W7 are kept at the ground potential. Thereby, as shown by 1 in FIG. 155, in the memory transistor 38a having the word line W8 (control gate 28), electrons in the channel region are injected into the floating gate 29 by the channel FN. This is the write state “0”, and at this time, Vth is 3V.

  Next, the erase operation will be described. When erasing is performed, a voltage of 20 V is applied to the bit lines, S1, S2, and p-type impurity region 30, and the word lines W1 to W8 are kept at the ground potential. At this time, as indicated by 2 in FIG. 155, electrons are extracted from the floating gate 29 of the memory transistor 38a in the write state “0” to the channel region by the channel FN to be in the erase state “1”. Vth in the erase state “1” is −2V.

  Next, the reading operation will be described. For example, when the memory transistor 38a having the word line W8 is read, a voltage of about 1 V is applied to the bit line B1 to keep the source line and the substrate at the ground potential. Then, the word line W8 is kept at the ground potential, and a voltage of about 5V is applied to the word lines W1 to W7. Further, a predetermined voltage is applied to the selection gates S1 and S2 to turn on the selection gate transistor.

  Since the word line W8 is kept at the ground potential (0V), the memory transistor 38a is turned on when the memory transistor 38a having the word line W8 is in the erased state "1", and the memory transistor 38a is in the written state "0". The transistor 38a is turned off. Since the memory transistor 38a having the word lines W1 to W7 has a voltage of 5V applied to the word lines W1 to W7, the memory transistor 38a is turned on regardless of the write state "0" and the erase state "1".

  Therefore, when the memory transistor 38a having the word line W8 is in the erased state "1", referring to FIG. 154, the current passes through the channels formed by the word lines W1 to W8, passes through the bit lines, and sense amplifiers. Led to. In contrast, when the memory transistor 38a having the word line W8 is in the write state "0", no channel is formed by the word line W8, so that no current flows to the sense amplifier. When the sense amplifier senses a current, it is determined as an erase state “1”, and when it does not sense a current, it is determined as a write state “0”.

  Injecting electrons into the floating gate using the channel FN is more efficient than injecting electrons using channel hot electrons. Therefore, the NAND type can reduce power consumption compared to the NOR type.

  The NAND type uses the channel FN at the time of writing and does not apply a high voltage to the drain region of the memory transistor, so that the drain disturb phenomenon can be eliminated.

(1) Rewrite operation (Fig. 141)
When rewriting data stored in a memory cell in the above conventional flash memory, as shown in FIG. 141, a pre-erase write operation is performed (step S71), and a batch erase operation is performed (step S72). Thereafter, a program operation is performed (step S73).

  As the capacity of the flash memory increases, the time required for the pre-erase write operation becomes very long. For example, in a 1 Mbit flash memory, the time required to program the memory cells of all addresses is as long as 1 to 2 seconds.

  The long time required for the pre-erase write operation in this manner means that a long time is required for data rewriting. This is very inconvenient for the user.

(2) Depletion by over-erasure (Figs. 142 and 143)
As described above, at the time of erasing, the threshold voltage of the memory cells is unified to substantially the same value by performing the pre-erase write operation before the batch erase operation. However, in practice, there are always variations in the erase characteristics of a plurality of memory cells present in the erase unit.

  If this variation is very large as shown in FIG. 142, some memory cells are over-erased, and the over-erased memory cells are depleted.

  In such a depleted memory cell, a current flows even if its control gate is grounded. As a result, the data read from the memory cell connected to the same bit line as the depleted memory cell is disturbed by the depleted memory cell, and the data is always determined to be “1”.

  Such a problem does not exist in a memory cell having a structure as shown in FIG.

  In FIG. 143, N @ + -type impurity regions 1302, 1303 and 1310 are formed on the main surface of P @-type semiconductor substrate 1301 with a predetermined interval. A gate electrode 1304 is formed over a region between the impurity region 1302 and the impurity region 1303 through an insulating film made of an oxide film. Thereby, the selection transistor 1305 is configured.

  A floating gate 1307 is formed on the impurity region 1303 through a very thin oxide film 1306 of about 100 mm, and a control gate 1308 is formed thereabove via an insulating film. Thus, a memory transistor 1309 having a two-layer gate structure is formed.

  The selection transistor 1305 and the memory transistor 1309 form a 1-bit memory cell. Impurity region 1302 is connected to bit terminal B, and gate electrode 1304 is connected to word terminal W. Impurity region 1310 is connected to source terminal S. The control gate 1308 is connected to the control gate terminal CG.

  In the memory cell shown in FIG. 143, since the selection transistor 1305 is provided, the above-described problem does not occur even when the memory transistor 1309 is depleted.

  However, the memory cell of FIG. 143 has a more complicated structure and requires a larger area than the stacked gate type memory cell shown in FIG.

(3) Disturbance between sectors (Fig. 144)
In a conventional flash memory, a data rewrite unit can be subdivided by dividing a memory array into sectors. In this case, there is a problem that the memory cells in the selected sector affect the memory cells in the non-selected sector. This is called disturb.

  For example, as shown in FIG. 144, consider a case where a plurality of memory cells connected to word line WL0 are divided into sector SE1 and sector SE2. In this case, when programming the memory cell in the sector SE1, a high voltage is also applied to the control gate of the memory cell in the unselected sector SE2.

  Consider a case where a plurality of memory cells connected to the bit line BL0 are divided into a sector SE1 and a sector SE3. In this case, when programming the memory cell in the sector SE1, a high voltage is also applied to the drain of the memory cell in the non-selected sector SE3.

  In any case, even if a disturbance occurs several thousand times, the data can be sufficiently guaranteed. However, since there are a plurality of sectors on the same word line and the same bit line, if the number of rewrites of the memory cells in one sector is 10,000, the number of disturbances occurring in other sectors is as follows. .

Number of disturbs = (10000 times) × (number of sectors−1)
Thus, when there are a plurality of sectors, the number of disturbances occurring in a certain sector becomes enormous. In recent years, the required number of guaranteed sector rewrites is increasing, and disturb between different sectors is a serious problem.

(4) Power consumption When programming a conventional flash memory, electrons are injected into the floating gate by channel hot electrons. Therefore, a large channel current is required during programming. Therefore, power consumption during programming increases.

(5) Integration Level On the other hand, US Pat. No. 5,126,808 discloses a conventional flash memory having a main bit line and a sub bit line. In such a flash memory, electron injection by channel hot electrons is used for programming, and a large channel current flows. As a result, the following problems are also caused.

  FIG. 145 is a layout diagram on a semiconductor substrate of a conventional flash memory having a main bit line and a sub bit line. Referring to FIG. 145, main bit line MB and sub bit lines SB0 and SB1 are formed in parallel on the semiconductor substrate. Word lines VL0, WL1,... And select gate lines SGL0, SGL1 are formed in a direction perpendicular to these bit lines. A memory cell is formed at a position where each word line and sub-bit line intersect. For example, memory cells M11, M12,... Are formed at positions where the word lines WL0, WL1,. A select gate transistor SG ′ for sector selection is formed at a position where the main bit line MB and the select gate line SGL0 intersect. An N + diffusion layer 1405 is formed in the semiconductor substrate.

  In memory cells M11, M12,... Shown in FIG. 145, programming using channel hot electrons is performed as described above, so that a large channel current flows through sub bit line SB1. Therefore, since this large current flows through the select gate transistor SG ′ for sector selection, it is necessary to select a large channel width for the select gate transistor SG ′. This means that the select gate transistor SG ′ occupies a large area on the semiconductor substrate, and as a result, the degree of integration on the semiconductor substrate is lowered.

  In addition to this, in the flash memory shown in FIG. 145, the first and second aluminum wiring layers reduce the resistance of the main bit line MB and the sub bit lines SB0 and SB1, and the first and second aluminum wiring layers are connected to the sub bit lines SB0 and SB1. It is formed as a bit line MB. Therefore, the aluminum wiring layer cannot be used to reduce the resistance of the word lines WL0, WL1,... Formed by the polysilicon layer. As a result, a signal propagation in the word line is delayed and a high operation speed cannot be obtained.

  FIG. 146 is a structural diagram of a memory cell of a conventional flash memory. Referring to FIG. 146, two memory cells M00 and M10 are separated by an isolation oxide film 1402 formed on P well 1008. For example, when programming is performed on memory cell M10, a high voltage of 10V is applied to second aluminum interconnection layer 1006 constituting the control gate, while a voltage of 5V is applied to drain 1002 'of transistor M10. If the width Wb of the isolation oxide film 1402 is too narrow, the MOS transistor 1403 using the isolation oxide film 1402 as a gate oxide film exists equivalently. Presence of equivalent MOS transistor 1403 prevents a desired operation in memory cells M00 and M10. Therefore, in order to prevent the generation of this equivalent MOS transistor 1403, the width Wb of the isolation oxide film 1402 cannot be selected to a small value. This means that the degree of integration in the memory cell array is reduced.

  FIG. 147 is a circuit diagram showing the operation of the flash memory using a negative voltage. FIG. 147 (a) shows the voltage applied for programming, while FIG. 147 (b) shows the voltage applied for erasing.

  Referring to FIG. 147 (a), in order to inject electrons into the floating gate of memory cell M00, a voltage of 5V is applied to bit line BL0, while a negative voltage of −10V is applied to word line WL11. On the other hand, a voltage of 5V is applied to the unselected word line WL12. In other words, an X decoder not shown needs to output voltages of −10V and 5V.

  Referring to FIG. 147 (b), in order to erase the data stored in the selected sector SE1, a positive voltage of 10V is applied to the word lines WL11 and WL12, while the bit lines BL0 and BL1 have a high impedance. Brought to the state. On the other hand, a negative voltage of −8V is applied to the word lines WL21 and WL22 in the selector SE2 that is not selected. In other words, an X decoder not shown needs to output a positive voltage of 10V and a negative voltage of -8V.

  Therefore, an X decoder (not shown) needs to output an output voltage having a voltage difference of 15V in the program operation, while outputting an output voltage having a voltage difference of 18V in the erase operation. Therefore, since the voltage difference between the output voltages is large, it is difficult to form the X decoder in a smaller occupied area on the semiconductor substrate.

(6) External power supply During programming, it is necessary to apply a voltage of 5 V to 6 V to the drain of each memory cell. As described above, since channel hot electron programming requires a large channel current, it is very difficult to create this drain voltage by internal boosting using a single external power supply of 3V or 5V. Even if it is possible, a large number of bits cannot be programmed at the same time, and the programming time becomes enormous.

  However, the NAND type has a disadvantage that the read operation is slow because the read operation is performed by passing a current through eight memory transistors arranged in series.

  In addition, since a relatively high voltage of 20 V is used at the time of writing and erasing, there is a problem that high integration is difficult.

  An object of the present invention is to reduce the time required for the erase operation in the flash memory, thereby reducing the time required for the rewrite operation.

  Another object of the present invention is to prevent depletion due to over-erasure of a stacked gate type memory cell.

  Still another object of the present invention is to prevent disturbance when the memory array is divided into sectors.

Still another object of the present invention is to reduce power consumption during programming.
Still another object of the present invention is to provide a flash memory operable with a single external power source.

  Still another object of the present invention is a non-volatile semiconductor that can be operated with low power consumption, can reduce the drain disturb phenomenon, can increase the read operation speed, and can reduce the maximum voltage. It is to provide a storage device.

  In one aspect, a nonvolatile semiconductor memory device according to the present invention includes a source and a drain formed on the main surface of the semiconductor substrate at a predetermined interval, and a first on the main surface of the semiconductor substrate between the source and the drain. A memory substrate including a floating gate formed through an insulating film and a control gate formed through a second insulating film on the floating gate, and a semiconductor substrate so as to cover the sources and drains of the plurality of memory cells A plurality of wells formed on the main surface, and when erasing data of a plurality of memory cells, electrons are transferred between the wells and the floating gate through the first insulating film, and selected from the plurality of memory cells. When data is written to the memory cell, electrons are transferred between the drain and the floating gate through the first insulating film.

  In another aspect, the nonvolatile semiconductor memory device according to the present invention includes a semiconductor having a first conductivity type high concentration impurity region and a first conductivity type low concentration impurity region formed to cover the high concentration impurity region. A source and drain formed at a predetermined interval on the main surface of the substrate, a floating gate formed on the semiconductor substrate between the source and drain, and formed between the semiconductor substrate and the floating gate, from the semiconductor substrate to the floating gate A memory cell including an insulating film for injecting electrons by FN tunneling; a control gate formed through the insulating film on the floating gate; a word line connected to the control gate; and a bit line connected to the drain; Is provided.

  In still another aspect of the nonvolatile semiconductor memory device according to the present invention, the source and drain of the first conductivity type formed at a predetermined interval on the main surface of the semiconductor substrate, and the main substrate of the semiconductor substrate between the source and drain. A memory cell including a floating gate formed via a first insulating film on the surface, a control gate formed via a second insulating film on the floating gate, and a word line connected to the control gate A bit line connected to the drain via the first conductivity type MIS transistor, and a second conductivity type different from the first conductivity type formed on the main surface of the semiconductor substrate on which the memory cell and the MIS transistor are arranged. A well and a first conductivity type well formed to surround the second conductivity type well.

  According to one aspect of the present invention, since the electron movement of the floating gate is performed through the well and the drain, the degree of freedom of structure with respect to the source can be increased.

  According to another aspect of the present invention, electrons are injected from the semiconductor substrate into the floating gate by FN tunneling, so that the electric field between the high-concentration impurity region of the first conductivity type and the low-concentration impurity region is reduced in the source and drain. It can be made with a structure that can.

  According to still another aspect of the present invention, since the memory cell and the MIS transistor are formed in the second conductivity type well surrounded by the first conductivity type well, the memory cell and the MIS transistor are formed on the semiconductor substrate. It is possible to avoid being directly affected by potential.

  First, the relationship between the program and erase operations and the threshold voltage in the first to eleventh embodiments described below will be described in comparison with a conventional example.

  In the conventional example, as shown in FIG. 1B, the threshold voltage of the memory cell is increased by the program operation, and the threshold voltage of the memory cell is decreased by the erase operation. On the other hand, in the embodiment, as shown in FIG. 1A, the threshold voltage of the memory cell is lowered by the program operation, and the threshold voltage of the memory cell is raised by the erase operation.

  That is, in the conventional example, as shown in FIG. 2B, in the memory cell in the erased state, electrons are emitted from the floating gate, and the threshold voltage is low. In the memory cell in the programmed state, electrons are injected into the floating gate, and the threshold voltage is high.

  On the other hand, in the embodiment, as shown in FIG. 2A, in the memory cell in the erased state, electrons are injected into the floating gate, and the threshold voltage is high. In the memory cell in the programmed state, electrons are emitted from the floating gate, and the threshold voltage is low.

  The point that the erase state corresponds to data “1” and the program state corresponds to data “0” is the same in the embodiment and the conventional example.

  As described above, in the embodiment, the threshold voltage of each memory cell is increased by the erase operation. Therefore, as shown in FIG. The threshold voltage can be made higher than the power supply voltage Vcc.

  As shown in FIG. 4, even if the threshold voltages of a plurality of memory cells vary, some memory cells are not depleted by the batch erase operation.

(1) First embodiment (FIGS. 5 to 8)
(A) Overall configuration of flash memory (FIG. 5)
FIG. 5 is a block diagram showing the overall configuration of the flash memory according to the first embodiment. The entire configuration of the flash memory of FIG. 5 is the same as that of the conventional flash memory of FIG. 131 except that the voltage application conditions in each operation are different. The flash memory of FIG. 5 is also formed on the chip CH.

(B) Memory cell programming and erasure (FIG. 6)
FIG. 6A shows the voltage application conditions to the memory cell during programming. FIG. 6B shows the voltage application conditions to the memory cell at the time of erasing.

  At the time of programming, as shown in FIG. 6A, a high voltage Vpp (usually about 12V) is applied to the drain 1002, 0V is applied to the control gate 1006, and the source 1003 is brought into a floating state. Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

  At the time of erasing, as shown in FIG. 6B, 0V is applied to the drain 1002, a high voltage Vpp (usually about 12V) is applied to the control gate 1006, and a predetermined high voltage VSL (6V) is applied to the source 1003. Apply. Thereby, hot electrons or channel hot electrons are generated near the source 1003 due to avalanche breakdown. These hot electrons are accelerated by the high voltage Vpp of the control gate 1006 and are injected into the floating gate 1005 over the energy barrier by the insulating film 1004. As a result, the threshold voltage of the memory cell increases.

  Thus, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon during programming. Therefore, an N − -type impurity region 1002b is provided along the drain 1002 in order to weaken the electric field in the channel direction or the substrate direction.

  At the time of erasing, electrons are injected into the floating gate 1005 from the vicinity of the source 1003 by hot electrons. Therefore, a P + -type impurity region 1003b is provided along the source 1003 so that a higher electric field is generated in the channel direction or the substrate direction.

The P − well 1008 may be a P − type semiconductor substrate.
(C) Flash memory operation (FIG. 7)
Next, the batch erase operation, program operation and read operation of the flash memory will be described with reference to FIG. FIG. 7 shows some memory cells M11 to M13, M21 to M23, and M31 to M33 included in the memory array 1010.

(I) Batch erase operation ((a) of FIG. 7)
First, a control signal designating a batch erase operation is given to the control circuit 1130 via the control signal buffer 1120. High voltage Vpp is applied to Vpp / Vcc switching circuit 1090 from the outside.

  Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. The X decoder 1030 selects all the word lines WL to WL3 and applies a high voltage Vpp to them. The Y decoder 1040 turns on all the Y gate transistors included in the Y gate 1050. The write circuit 1080 applies 0 V to all the bit lines BL1 to BL3 via the Y gate 1050. Source control circuit 1110 applies a predetermined high voltage VSL (VSL <Vpp) to source line SL.

  In this way, a voltage is applied to all the memory cells M11 to M33 as shown in FIG. 6B. As a result, all the memory cells M11 to M33 are erased.

(Ii) Program operation ((b) of FIG. 7)
Here, it is assumed that the memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to the other memory cells.

  First, a control signal designating a program operation is supplied to the control circuit 1130 via the control signal buffer 1120. High voltage Vpp is applied to Vpp / Vcc switching circuit 1090 from the outside.

  The X decoder 1030 selects the word line WL2 in response to the X address signal supplied from the address buffer 1020, applies 0 V to the selected word line WL2, and supplies the power supply voltage Vcc to the unselected word lines WL1 and WL3. Apply.

  Vpp / Vcc switching circuit 1090 applies high voltage Vpp to write circuit 1080. Data is sequentially supplied from the outside to the writing circuit 1080 via the data input / output buffer 1070. At this time, the Y decoder 1040 sequentially turns on the Y gate transistors in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. Write circuit 1080 applies high voltage Vpp to bit line BL1 through Y gate 1050, and applies power supply voltage Vcc to bit lines BL2 and BL3. The source control circuit 1110 puts the source line SL in a floating state.

  In this way, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.

  (A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

  (B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

  (C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

  As a result, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed.

(Iii) Read operation ((c) of FIG. 7)
The read operation is almost the same as the operation described with reference to FIG. Here, it is assumed that data is read from memory cell MC12. First, a control signal designating a reading operation is supplied to the control circuit 1130 via the control signal buffer 1120.

  X decoder 1030 selects word line WL2 in response to the X address signal applied from address buffer 1020, and applies power supply voltage Vcc thereto. At this time, the other word lines WL1 and WL3 are kept at 0V. Y decoder 1040 turns on one Y gate transistor in Y gate 1050 in response to a Y address signal supplied from address buffer 1020. The source control circuit 1110 grounds the source line SL.

  As a result, the read voltage Vr appears on the bit line BL1. This read voltage Vr is detected and amplified by sense amplifier 1060 and output to the outside through data input / output buffer 1070.

(D) Rewrite operation (Fig. 8)
The data rewriting operation in the flash memory will be described with reference to the flowchart of FIG.

  First, it is determined whether or not data “1” is stored in all the memory cells (step S1). When data “1” is not stored in all the memory cells, a batch erase operation is performed (step S2). Thereafter, a program operation is performed (step S3). In this manner, data can be rewritten without performing the pre-write erase operation as in the conventional example.

(E) Modifications The non-selected bit lines BL2 and BL3 may be in a floating state during programming. At this time, the non-selected memory cell is in one of the following states.

  (A) The high voltage Vpp is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

  (B) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.

  (C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the source is in a floating state.

  Also in this case, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed by the tunnel phenomenon.

  The power supply voltage Vcc may be applied to the source line SL during programming. At this time, the high voltage Vpp is applied to the drain of the memory cell M12, 0V is applied to the control gate, and the power supply voltage Vcc is applied to the source. Other memory cells are in one of the following states.

  (A) A high voltage Vpp is applied to the drain, a power supply voltage Vcc is applied to the control gate, and a power supply voltage Vcc is applied to the source.

  (B) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.

  (C) The power supply voltage Vcc is applied to the drain, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.

  Also in this case, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed by the tunnel phenomenon.

  During programming, the unselected bit lines BL2 and BL3 may be in a floating state and the power supply voltage Vcc may be applied to the source line SL. At this time, the high voltage Vpp is applied to the drain of the memory cell M12, 0V is applied to the control gate, and the power supply voltage Vcc is applied to the source. Other memory cells are in any of the following states.

  (A) A high voltage Vpp is applied to the drain, a power supply voltage Vcc is applied to the control gate, and a power supply voltage Vcc is applied to the source.

  (B) The drain is in a floating state, 0 V is applied to the control gate, and the power supply voltage Vcc is applied to the source.

  (C) The drain is in a floating state, the power supply voltage Vcc is applied to the control gate, and the power supply voltage Vcc is applied to the source.

  Also in this case, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed by the tunnel phenomenon.

  Further, the verify operation may be performed after the batch erase operation. Further, by applying 0 V to the control gates of all the memory cells and applying the high voltage Vpp to the P-well (or P-type semiconductor substrate) before the batch erase operation, the control gates of all the memory cells The collective erasing operation may be performed while extracting electrons and then performing a verify operation. Thereby, the variation in threshold voltage of the memory cells erased at once can be further reduced.

(F) Effect of First Embodiment In the conventional flash memory, electrons are injected from the drain side into the floating gate. Therefore, if the potential of the bit line becomes high during the read operation, electrons may be injected from the drain into the selected memory cell, and soft write may occur.

  In contrast, in the flash memory of the first embodiment, electrons are injected from the source side into the floating gate. Therefore, soft write is unlikely to occur during the read operation.

  Note that the program operation may be performed while performing the verify operation. Thereby, the variation in the threshold voltage of the programmed memory cell can be reduced.

(2) Second embodiment (FIGS. 9 and 10)
The overall configuration of the flash memory according to the second embodiment is the same as the configuration shown in FIG.

(A) Memory cell program and erase (FIG. 9)
FIG. 9A shows voltage application conditions to the memory cell during programming. FIG. 9B shows voltage application conditions to the memory cell at the time of erasing. The voltage application conditions at the time of programming are the same as the voltage application conditions shown in FIG.

  At the time of erasing, as shown in FIG. 9B, 0 V is applied to the drain 1002, a high voltage Vpp (usually about 12 V) is applied to the control gate 1006, and 0 V is applied to the source 1003. As a result, a channel ch is formed in a region between the source 1003 and the drain 1002, and a high electric field is generated between the channel ch and the floating gate 1005. Electrons are injected from the channel ch into the floating gate 1005 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell increases.

  In this embodiment, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon during programming. Therefore, an N − -type impurity region 1002c is provided along the drain 1002 in order to weaken the electric field in the channel direction or the substrate direction.

  Note that an N − -type impurity region 1003c may be provided along the source 1003. As described above, when the N− type impurity regions 1002c and 1003c are provided on both the drain side and the source side, the number of manufacturing steps is reduced.

(B) Flash memory operation (FIG. 10)
Next, the batch erase operation, program operation, and read operation of the flash memory will be described with reference to FIG. The program operation and the read operation are the same as in the first embodiment. Therefore, the batch erase operation will be described below.

  First, a control signal designating a batch erase operation is given to the control circuit 1130 via the control signal buffer 1120. High voltage Vpp is applied to Vpp / Vcc switching circuit 1090 from the outside.

  Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. The X decoder 1030 selects all the word lines WL1 to WL3 and applies a high voltage Vpp to them. The Y decoder 1040 turns on all the Y gate transistors included in the Y gate 1050. The write circuit 1080 applies 0 V to all the bit lines BL1 to BL3 via the Y gate 1050. The source control circuit 1110 applies 0 V to the source line SL.

  In this way, a voltage is applied to all the memory cells M11 to M33 as shown in FIG. 9B. As a result, all the memory cells M11 to M33 are erased.

  Note that a negative voltage may be positively applied to the P-well (or P-type semiconductor substrate) during the batch erase operation.

  Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten without performing the pre-erase write operation as in the conventional example.

(3) Third embodiment (FIGS. 11 to 14)
FIG. 11 is a block diagram showing the overall configuration of the flash memory according to the third embodiment. The flash memory of FIG. 11 differs from the flash memory of FIG. 5 in the following points.

  A negative voltage control circuit 1140 that receives a negative voltage −Vee given from the outside and generates a predetermined negative voltage is further provided. Further, as shown in FIG. 12, the X decoder 1030 includes a plurality of potential control switches 1303 connected to the plurality of word lines WL instead of the plurality of high voltage switches 1302 (see FIG. 132). Each potential control switch 1303 applies high voltage Vpp or power supply voltage Vcc supplied from Vpp / Vcc switching circuit 1090 or negative voltage −Vee supplied from negative voltage control circuit 1140 to corresponding word line WL.

(B) Memory cell programming and erasure (FIG. 13)
FIG. 13A shows the voltage application conditions to the memory cells during programming. FIG. 13B shows the voltage application conditions to the memory cell at the time of erasing.

  At the time of programming, as shown in FIG. 13A, a power supply voltage Vcc (normally about 5V) is applied to the drain 1002, a negative voltage −Vee (−12V) is applied to the control gate 1006, and the source 1003 is in a floating state. To. Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

The voltage application conditions at the time of erasing are the same as the voltage application conditions shown in FIG.
Thus, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon during programming. Therefore, an N − -type impurity region 1002d is provided along the drain 1002 in order to weaken the electric field in the channel direction or the substrate direction.

  At the time of erasing, electrons are injected into the floating gate 1005 from the vicinity of the source 1003 by hot electrons. Therefore, a P + -type impurity region 1003d is provided along the source 1003 so that a higher electric field is generated in the channel direction or the substrate direction.

(C) Flash memory operation (FIG. 14)
Next, the batch erase operation, program operation and read operation of the flash memory will be described with reference to FIG. The batch erase operation and the read operation are the same as in the first embodiment. Therefore, the program operation will be described below.

  Here, it is assumed that the memory cell M12 is programmed. That is, data “0” is written to the memory cell M12, and data “1” is written to the other memory cells.

  First, a control signal designating a program operation is supplied to the control circuit 1130 via the control signal buffer 1120. The negative voltage control circuit 1140 is given a negative voltage -Vee from the outside.

  The X decoder 1030 selects the word line WL2 in response to the X address signal supplied from the address buffer 1020, applies the negative voltage −Vee from the negative voltage control circuit 1140 to the selected word line WL2, and selects the unselected 0V is applied to the word lines WL1 and WL3.

  Vpp / Vcc switching circuit 1090 supplies power supply voltage Vcc to write circuit 1080. Data is sequentially supplied from the outside to the writing circuit 1080 via the data input / output buffer 1070. At this time, the Y decoder 1040 sequentially turns on the Y gate transistors in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. Write circuit 1080 applies power supply voltage Vcc to bit line BL1 via Y gate 1050 and 0 V to bit lines BL2 and BL3. The source control circuit 1110 puts the source line SL in a floating state.

  In this way, a voltage is applied to the memory cell M12 as shown in FIG. At this time, the other memory cells are in one of the following states.

  (A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

  (B) 0 V is applied to the drain, negative voltage -Vee is applied to the control gate, and the source is in a floating state.

  (C) 0 V is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

(E) Modifications The non-selected bit lines BL2 and BL3 may be in a floating state during programming. At this time, the non-selected memory cell is in one of the following states.

  (A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and the source is in a floating state.

  (B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and the source is in a floating state.

  (C) The drain is in a floating state, 0 V is applied to the control gate, and the source is in a floating state.

  Also in this case, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed by the tunnel phenomenon.

  During programming, a non-selected bit line may be set in a floating state and 0 V may be applied to the source line SL. At this time, the power supply voltage Vcc is applied to the drain of the memory cell M12, the negative voltage -Vee is applied to the control gate, and 0 V is applied to the source. Other memory cells are in one of the following states.

  (A) The power supply voltage Vcc is applied to the drain, 0 V is applied to the control gate, and 0 V is applied to the source.

  (B) The drain is in a floating state, a negative voltage -Vee is applied to the control gate, and 0 V is applied to the source.

  (C) The drain is in a floating state, 0V is applied to the control gate, and 0V is applied to the source.

  Also in this case, a high electric field is generated only between the floating gate and drain of the memory cell M12, and only the memory cell M12 is programmed by the tunnel phenomenon.

  In the third embodiment, the batch erase operation may be performed in the same manner as the second embodiment shown in FIG. A voltage is applied to each memory cell as shown in FIG.

  In this case, since the injection of electrons into the floating gate and the emission of electrons from the floating gate are performed using the tunnel phenomenon, power consumption is reduced. Therefore, a high voltage and a negative voltage can be generated internally from a power supply voltage applied from the outside.

(4) Fourth embodiment (FIGS. 15 to 16)
The overall configuration of the flash memory according to the fourth embodiment is the same as the configuration shown in FIG. The voltage application conditions to the memory cells at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 6A and 6B. The fourth embodiment differs from the first embodiment only in the control method.

(A) Flash memory operation (FIG. 15)
Next, page batch erase operation, program operation and read operation of the flash memory will be described with reference to FIG. The program operation and read operation are the same as in the first embodiment. Therefore, the page batch erase operation will be described below.

  All memory cells connected to one word line are called a page. In the batch erase operation, batch erase is performed in units of pages. Here, a batch erase operation of pages corresponding to the word line WL2 will be described.

  First, a control signal designating a page batch erase operation is given to the control circuit 1130 via the control signal buffer 1120. High voltage Vpp is applied to Vpp / Vcc switching circuit 1090 from the outside.

  Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. The X decoder 1030 selects the word line WL2 in response to the X address signal supplied from the address buffer 1020, applies the high voltage Vpp to the selected word line WL2, and applies 0 V to the unselected word lines WL1 and WL3. Apply. The Y decoder 1040 turns on all the Y gate transistors included in the Y gate 1050. The write circuit 1080 applies 0 V to all the bit lines BL1 to BL3 via the Y gate 1050. Source control circuit 1110 applies a predetermined high voltage VSL (VSL <Vpp) to source line SL.

  In this manner, a voltage is applied to the memory cells M12, M22, and M32 connected to the word line WL2 as shown in FIG. 6B. As a result, the memory cells M12, M22, M32 are erased.

  In each memory cell connected to the unselected word lines WL1 and WL3, 0V is applied to the drain 1002, the high voltage VSL is applied to the source 1003, and 0V is applied to the control gate 1006. Therefore, there is little possibility that hot electrons are injected into the floating gate 1005 over the energy barrier formed by the insulating film 1004. Therefore, only the memory cells connected to the selected word line WL2 are erased at once.

  Thus, in the fourth embodiment, the batch erase operation is performed in units of pages, not in units of memory arrays.

(B) Rewrite operation (FIG. 16)
The data rewriting operation in the flash memory according to the fourth embodiment will be described with reference to the flowchart of FIG.

  First, it is determined whether or not data “1” is stored in all the memory cells (step S11). When data “1” is not stored in all the memory cells, a page batch erase operation is performed for the page to be rewritten (step S12). Thereafter, a program operation is performed (step S13).

  In this way, data can be rewritten in units of pages without performing the pre-write erase operation as in the conventional example.

(5) Fifth embodiment (FIG. 17)
The overall configuration of the flash memory according to the fifth embodiment is the same as the configuration shown in FIG. The voltage application conditions to the memory cell at the time of programming and erasing are the same as the voltage application conditions shown in FIGS. 9A and 9B. The fifth embodiment differs from the second embodiment only in the control method.

  The batch page erase operation, program operation and read operation of the flash memory according to the fifth embodiment will be described with reference to FIG. The program operation and the read operation are the same as in the second embodiment. Therefore, the page batch erase operation will be described below. Here, a batch erase operation of pages corresponding to the word line WL2 will be described.

  First, a control signal designating a page batch erase operation is given to the control circuit 1130 via the control signal buffer 1120. High voltage Vpp is applied to Vpp / Vcc switching circuit 1090 from the outside.

  Vpp / Vcc switching circuit 1090 applies high voltage Vpp to X decoder 1030. The X decoder 1030 selects the word line WL2 in response to the X address signal supplied from the address buffer 1020, applies the high voltage Vpp to the selected word line WL2, and applies it to the unselected word lines WL1 and WL3. Apply 0V. The Y decoder 1040 turns on all the Y gate transistors included in the Y gate 1050. The write circuit 1080 applies 0 V to all the bit lines BL1 to BL3 via the Y gate 1050. The source control circuit 1110 applies 0 V to the source line SL.

  In this way, a voltage is applied to the memory cells M12, M22, M32 connected to the word line WL2 as shown in FIG. 9B. As a result, the memory cells M12, M22, M32 are erased.

  In each memory cell connected to the unselected word lines WL1 and WL3, 0 V is applied to the drain 1002, the source 1003, and the control gate 1006. Therefore, a high electric field is not generated between the floating gate 1005 and the source 1003, and electrons are not injected into the floating gate 1005 due to a tunnel phenomenon. Therefore, only the memory cells connected to the selected word line are erased at once.

  As described above, also in the fifth embodiment, batch erasure can be performed in units of pages, not in units of memory arrays.

  Data rewriting is performed according to the procedure shown in FIG. Therefore, data can be rewritten in units of pages without performing the pre-erase write operation as in the conventional example.

(6) Sixth embodiment (FIGS. 18 to 33)
(A) Overall configuration of flash memory (FIGS. 18 and 19)
FIG. 18 is a block diagram showing the overall configuration of the flash memory according to the sixth embodiment. FIG. 19 is a circuit diagram showing a detailed configuration of the memory array and related parts.

  The flash memory of FIG. 18 differs from the conventional flash memory shown in FIG. 131 in the following points. Memory array 1010a is divided into a plurality of sectors. In the example of FIG. 18, the memory array 1010a is divided into sectors SE1 and SE2. Memory array 1010a includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively.

  Memory array 1010a is formed in P-well 1008. 131 is not provided, and high voltage generation circuits 1210 and 1220, negative voltage generation circuits 1230 and 1240, well potential generation circuit 1250 and select gate decoder 1260 are further provided. High voltage generation circuits 1210 and 1220 receive power supply voltage Vcc (for example, 5 V) from the outside and generate a high voltage (for example, 10 V). Negative voltage generation circuits 1230 and 1240 receive power supply voltage Vcc from the outside and generate a negative voltage (for example, −10 V). Well potential generating circuit 1250 applies a negative voltage (for example, -5 V) to P- well 1008 during erasing. Select gate decoder 1260 selectively activates select gates SG1 and SG2 in response to part of the address signal from address buffer 1020.

  Reference is now made to FIG. A plurality of main bit lines are arranged in memory array 1010a. FIG. 19 shows two main bit lines MB0 and MB1. Main bit lines MB0 and MB1 are connected to sense amplifier 1060 and write circuit 1080 via Y gate transistors YG0 and YG1, respectively.

  A plurality of sub bit lines are arranged corresponding to each main bit line. In the example of FIG. 19, two sub bit lines SB01 and SB02 are provided corresponding to the main bit line MB0, and two sub bit lines SB11 and SB12 are provided corresponding to the main bit line MB1.

  A plurality of word lines are arranged to cross the plurality of subbit lines. In the example of FIG. 19, the word lines WL0 and WL1 are arranged so as to cross the sub bit lines SB01 and SB11, and the word lines WL2 and WL3 are arranged so as to cross the sub bit lines SB02 and SB12.

  Memory cells M00 to M03 and M10 to M13 are provided at the intersections of the sub bit lines SB01, SB02, SB11, and SB12 and the word lines WL0 to WL3, respectively. Memory cells M00, M01, M10, and M11 are included in sector SE1, and memory cells M02, M03, M12, and M13 are included in sector SE2.

  The drain of each memory cell is connected to the corresponding subbit line, the control gate is connected to the corresponding word line, and the source is connected to the source line SL.

  Select gate SG1 includes select gate transistors SG01 and SG11, and select gate SG2 includes select gate transistors SG02 and SG12. Sub-bit lines SB01 and SB02 are connected to main bit line MB0 via select gate transistors SG01 and SG02, respectively, and sub-bit lines SB11 and SB12 are connected to main bit line MB1 via select gate transistors SG11 and SG12, respectively. . The select gate line SGL1 of the select gate decoder 1260 is connected to select gate transistors SG01 and SG11, and the select gate line SGL2 is connected to select gate transistors SG02 and SG12.

(B) Memory cell programming and erasure (FIG. 20)
FIG. 20A shows the voltage application conditions to the memory cells during programming. FIG. 20B shows voltage application conditions to the memory cell at the time of erasing.

  At the time of programming, as shown in FIG. 20A, a positive voltage (for example, 5V) is applied to the drain 1002, a negative voltage (for example, −10V) is applied to the control gate 1006, the source 1003 is brought into a floating state, and P -Apply 0V to the well 1008; Accordingly, a high electric field is generated between the floating gate 1005 and the drain 1002, and electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon. As a result, the threshold voltage of the memory cell decreases.

  At the time of erasing, as shown in FIG. 20B, the drain 1002 is set in a floating state, a high voltage (for example, 10V) is applied to the control gate 1006, the source 1003 is set in a floating state, and a negative voltage ( For example, -5V) is applied. As a result, a high voltage (15 V in this case) is applied between the control gate 1006 and the P − well 1008, and a high electric field is generated between the source 1003 and the floating gate 1005. As a result, electrons are injected from the source 1003 into the floating gate 1005 by the tunnel phenomenon, and the threshold voltage of the memory cell rises.

  Thus, electrons are emitted from the floating gate 1005 to the drain 1002 by a tunnel phenomenon during programming. Therefore, an N − -type impurity region 1002e is provided along the drain 1002 in order to weaken the electric field in the channel direction or the substrate direction.

  Note that an N − -type impurity region 1003e may be provided along the source 1003. As described above, when the N− type impurity regions 1002e and 1003e are provided on both the drain side and the source side, the number of manufacturing steps is reduced.

(C) Flash memory operation (FIG. 21)
Next, the sector batch erase operation, program operation and read operation of the flash memory will be described with reference to FIG.

(I) Sector Batch Erase Operation Here, it is assumed that the sector SE1 is batch erased. First, a control signal designating a sector batch erase operation is given to the control circuit 1130 via the control signal buffer 1120. Thereby, high voltage generation circuit 1220 and negative voltage generation circuit 1230 are activated.

  The high voltage generation circuit 1220 applies a high voltage (10 V) to the X decoder 1030. The X decoder 1030 applies a high voltage (10V) to the word lines WL0 and WL1 in the sector SE1, and applies 0V to the word lines WL2 and WL3 in the sector SE2. Negative voltage generation circuit 1230 applies a negative voltage to Y decoder 1040 and well potential generation circuit 1250. The Y decoder 1040 applies a negative voltage (−5V) to the Y gate transistors YG0 and YG1 in the Y gate 1050. Thereby, the main bit lines MB0 and MB1 are in a floating state. The source control circuit 10 places the source line SL in a floating state. The well potential generation circuit 1250 applies a negative voltage (−5 V) to the P − well 1008. The select gate decoder 1260 applies 0 V to the select gate lines SG1 and SG2.

  In this way, voltages are applied to the memory cells M00, M01, M10, and M11 in the sector SE1 as shown in FIG. As a result, all the memory cells in the sector SE1 are erased.

  At this time, in each memory cell in the unselected sector SE2, the voltage applied between the control gate and the P-well is 5V. Therefore, the tunnel phenomenon does not occur. Further, since this potential condition is substantially the same as the potential condition at the time of reading, there is almost no disturbance to data.

(Ii) Program operation ((b) of FIG. 21)
Here, it is assumed that memory cell M00 is programmed. That is, data “0” is written into the memory cell M00, and data “1” is written into the memory cell M10.

  First, a control signal designating a program operation is supplied to the control circuit 1130 via the control signal buffer 1120. Thereby, high voltage generating circuit 1210 and negative voltage generating circuit 1240 are activated.

  The negative voltage generation circuit 1240 gives a negative voltage to the X decoder 1030. The X decoder 1030 selects the word line WL0 in response to the X address signal supplied from the address buffer 1020, applies a negative voltage (−10V) to the selected word line WL0, and selects the unselected word lines WL1 to WL3. 0V is applied to.

  High voltage generation circuit 1210 applies a high voltage to Y decoder 1040, write circuit 1080, and select gate decoder 1260. First, data “0” is externally applied to the write circuit 1080 via the data input / output buffer 1070 and latched. Y decoder 1040 applies a high voltage (for example, 7V) to Y gate transistor YG0 in Y gate 1050 in response to a Y address signal applied from address buffer 1020, and applies 0V to Y gate transistor YG1. Thereby, the Y gate transistor YG0 is turned on.

  Write circuit 1080 applies a program voltage (5 V) corresponding to data “0” to main bit line MB0 via Y gate transistor YG0. The select gate decoder 1260 applies a high voltage (for example, (7V) to the select gate line SGL1 and 0V to the select gate line SGL2, so that the sub bit lines SB01 and SB11 are respectively connected to the main bit line MB0, The source control circuit 1110 brings the source line SL into a floating state, and the well potential generation circuit 1250 applies 0 V to the P− well 1008.

  In this way, a voltage is applied to the memory cell M00 as shown in FIG. As a result, the threshold voltage of the memory cell M00 decreases.

  After a predetermined time (for example, 1 ms), data “1” is externally applied to the write circuit 1080 via the data input / output buffer 1070 and latched. The Y decoder 1040 applies a high voltage (7V) to the Y gate transistor YG1 in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020, and applies 0V to the Y gate transistor YG0. Thereby, the Y gate transistor YG1 is turned on. Write circuit 1080 applies 0 V corresponding to data “1” to main bit line MB1 via Y gate transistor YG1. Therefore, the threshold voltage of the memory cell M10 is maintained high.

  A verify operation may be performed during the program operation. This verify operation will be described with reference to the flowchart of FIG.

  As described above, a negative voltage (−10V) is applied to the selected word line WL0, and a high voltage (7V) is applied to the selected select gate line SGL1 (step S21). Further, the source line SL is brought into a floating state (step S22), 5V is applied to the main bit line MB0 of data “0”, and 0V is applied to the main bit line MB1 of data “1” (step S23). Thereby, the threshold voltage of the memory cell M00 decreases. At this time, the threshold voltage of the memory cell M10 is kept high.

  After a predetermined time (for example, 1 msec) has elapsed, the verify operation is started by the control circuit 1130. Thereby, verify voltage generating circuit 1100 is activated. A verify voltage generation circuit 1100 supplies a verify voltage lower than the normal power supply voltage Vcc to the X decoder 1030. As a result, a verify voltage is applied to the selected word line WL0 (step S24). The source line SL is grounded by the source control circuit 1110 (step S25). Thereby, a reading operation is performed (step S26).

  When the threshold voltage of memory cell M00 is higher than the verify voltage, no current flows through main bit line MB0. Therefore, the sense amplifier 1060 detects data “1”. In this case, control circuit 1130 determines that the program is insufficient, and performs the program operation and the verify operation again (steps S27, S21 to S26).

  When the threshold voltage of memory cell M00 becomes lower than the verify voltage, a current flows through main bit line MB0. Therefore, the sense amplifier 1060 detects data “0”. In this case, the control circuit 1130 determines that the program is sufficient and ends the program operation for the memory cell M00.

  The X address signal applied to X decoder 1030 is sequentially incremented, and the program operation and the verify operation are sequentially performed on word lines WL1, WL2, and WL3 (steps S28 and S29).

(Iii) Read operation ((c) of FIG. 21)
Here, it is assumed that data is read from memory cell M00. First, a control signal designating a reading operation is supplied to the control circuit 1130 via the control signal buffer 1120.

  X decoder 1030 selects word line WL0 in response to an X address signal applied from address buffer 1020, and applies power supply voltage Vcc (5 V) thereto. At this time, the word lines WL1, WL2, WL3 are kept at 0V. The select gate decoder 1260 applies 5V to the select gate line SGL1, and applies 0V to the select gate line SGL2. The Y decoder 1040 turns on the Y gate transistor YG0 in the Y gate 1050 in response to the Y address signal supplied from the address buffer 1020. The source control circuit 1110 grounds the source line SL.

  Thereby, read voltage Vr appears on main bit line MBO. The read voltage Vr is detected by the sense amplifier 1060 and output to the outside through the data input / output buffer 1070.

(D) Cross-sectional structure of memory cell (FIG. 23)
FIG. 23 is a diagram showing a cross-sectional structure of a memory cell used in the flash memory of this embodiment. The structure shown in FIG. 23 is called a triple well structure.

  An N − well 1009 is formed in a predetermined region of the P − type semiconductor substrate 1001, and a P − well 1008 is formed in the N − well 1009. Two N + type impurity regions are formed in a predetermined region in the P- well 1008 with a predetermined interval. One of the N + -type impurity regions constitutes the drain 1002 and the other constitutes the source 1003. A floating gate 1005 is formed on a region between the source 1002 and the drain 1003 via an insulating film 1004 (about 100 mm) such as an extremely thin oxide film, and a control gate 1006 is further formed thereon via an insulating film. Is done. In this way, the memory cell MC is formed.

  CMOS circuit region 1300 includes an N channel transistor formed in the P − well and a P channel transistor formed in the N − well.

(E) High integration FIG. 24 is a structural diagram of two adjacent memory cells in the sixth embodiment. As shown in FIG. 24, two memory cells M00 and M10 are separated by an isolation oxide film 1400 formed on a P well 1008.

  In the program operation, a voltage of 5V is applied to the drain 1002 'of the selected memory cell M10, while a voltage of 0V is applied to the drain 1002 of the unselected memory cell M00. In addition to this, a negative voltage of −10 V is applied to the second aluminum wiring layer 1006 forming the control gate. Therefore, MOS transistor 1401 is equivalently present using isolation oxide film 1400 as a gate oxide film.

  The equivalent NMOS transistor 1401 receives a negative voltage of −10 V through the gate electrode. Therefore, this equivalent transistor 1401 cannot conduct in the above-described program operation, and therefore, the width Wa of the isolation oxide film 1400 can be selected to be smaller than the width Wb shown in FIG. Therefore, a higher degree of integration is obtained.

  FIG. 25 is a layout diagram of the memory cell array on the semiconductor substrate in the sixth embodiment. As already described, in the sixth embodiment, the program operation and the erase operation are performed using the tunnel phenomenon, so that the current flowing through the sub-bit line is extremely small. Therefore, the channel width of select gate transistors SG0 and SG1 for sector selection can be selected to a smaller value compared to the example shown in FIG. Therefore, a layout suitable for higher integration can be obtained.

  FIG. 26 is a circuit diagram showing voltages applied in the memory cell array of the sixth embodiment. FIG. 26 (a) shows the voltage applied in the program operation, while FIG. 26 (b) shows the voltage applied in the erase operation.

  As shown in FIG. 26A, in the program operation, an X decoder (not shown) outputs -10V and 0V output voltages. In other words, the X decoder outputs an output voltage having a voltage difference of 10V.

  On the other hand, as shown in FIG. 26B, the X decoder requires output voltages of 10V and 0V in the erase operation. In other words, the X decoder outputs an output voltage having a voltage difference of 10V.

  As can be seen by comparing the output voltage difference shown in FIG. 26 (ie, 10V) and the output voltage difference shown in FIG. 147 (ie, 15V and 18V), the output voltage difference of the X decoder in the sixth embodiment is reduced. Yes. This contributes to improving the integration degree of the X decoder. That is, in the sixth embodiment, since the output voltage difference of the X decoder becomes small, the X decoder can be formed in a smaller occupied area on the semiconductor substrate.

(F) High voltage generation circuit (FIGS. 27 and 28)
FIG. 27A shows an equivalent circuit of the high voltage generation circuit. The high voltage generation circuit includes a plurality of diodes D210 and a plurality of capacitances C210. A two-phase clock signal φ, / φ is applied to the capacitance C210. Thereby, a charge pump is configured.

  Each diode D210 is generally composed of an N-channel transistor as shown in FIG. The back gate of the N channel transistor is grounded.

  However, when the power supply voltage Vcc is low (for example, 3 V), it is difficult to obtain a high voltage due to the back gate effect. The back gate effect is that the threshold voltage increases when the back gate voltage decreases relative to the source voltage.

  Therefore, in this embodiment, the structure shown in FIG. 28 is used. A plurality of N− wells 1211 are formed in a P− type semiconductor substrate 1001, and P + type impurity regions 1212 and N + type impurity regions 1213 are formed in each N− well 1211. These P + type impurity region 1212 and N + type impurity region 1213 form a diode.

  According to this configuration, since each diode does not have a back gate, the back gate effect does not occur.

  However, in some cases, a parasitic transistor (bipolar transistor) as shown in FIG. 29 may exist in the high voltage generation circuit having the structure shown in FIG. Referring to FIG. 29, pnp type parasitic transistors 1411 and 1412 can be formed by P + type impurity region 1212, N − well 1211 and P − type semiconductor substrate 1001. Therefore, the presence of these parasitic transistors 1411, 1412,... Can equivalently form the circuit shown in FIG.

  30 is an equivalent circuit diagram of a circuit constituted by the parasitic transistors 1411, 1412,... Shown in FIG. As can be seen from FIG. 30, the cascaded parasitic transistors 1411, 1412,... Amplify some small leak current ILEAK and cause an excessive current In. That is, if the current amplification factor of each parasitic transistor 1411, 1412,... Is hfe, an excessive current In determined by the following equation flows.

I1 = (1 + hfe) · ILEAK
In = (1 + hfe) n · ILEAK
Therefore, in order to prevent an excessive current In from flowing in the high voltage generating circuit, the structure shown in FIG. 31 is proposed.

  FIG. 31 is a sectional view showing another structure of the high voltage generation circuit used in the flash memory according to the sixth embodiment. As shown in FIG. 31, the triple well structure is applied to the high voltage generation circuit. This prevents the presence of parasitic transistors 1411, 1412,... As shown in FIG. 29, and a stable boosting operation can be performed.

(G) Negative voltage generation circuit (FIGS. 32 and 33)
FIG. 32A shows an equivalent circuit of the negative voltage generation circuit. The negative voltage generation circuit includes a plurality of diodes D230 and a plurality of capacitances C230. A two-phase clock signal φ, / φ is applied to the capacitance C230. Thereby, a charge pump is configured.

  Each diode D230 is generally composed of a P-channel transistor as shown in FIG. The back gate of the P channel transistor is grounded.

  However, when the power supply voltage Vcc is low (for example, 3 V), it is difficult to obtain a low negative voltage due to the back gate effect.

  Therefore, in this embodiment, a triple well structure shown in FIG. 33 is used. An N− well 1231 is formed in a P− type semiconductor substrate 1001, a plurality of P− wells 1232 are formed in the N− well 1231, and an N + type impurity region 1233 and a P + type impurity region are formed in each P− well 1232. 1234 is formed. These N + type impurity region 1233 and P + type impurity region 1234 form a diode.

  According to this configuration, since each diode does not have a back gate, the back gate effect does not occur. Further, as shown in FIG. 23, since the memory cell is also formed in the N-well, the manufacturing process does not increase.

(7) Seventh embodiment (FIGS. 34 and 35)
FIG. 34 is a circuit diagram showing a detailed configuration of a memory array of a flash memory according to the seventh embodiment and parts related thereto. The entire configuration of the flash memory according to the embodiment of FIG. 7 is the same as the configuration shown in FIG.

  The seventh embodiment differs from the sixth embodiment in that capacitances C0 and C1 are connected to main bit lines MB0 and MB1 via transfer gate transistors TG0 and TG1, respectively. A well potential VB is applied to the capacitances C0 and C1. A control signal CG1 is supplied from the control circuit 1130 to the transfer gate transistors TG0 and TG1. The configuration of the other parts is the same as the configuration shown in FIG.

  Assuming that the program time for one memory cell is 1 ms, for example, the 2-bit configuration as shown in FIG. 34 requires 2 ms for programming. Actually, since the number of memory cells connected to one word line is several hundred to several thousand, it takes a long time to rewrite data. By providing a data latch for each main bit line, the memory cells connected to the plurality of bit lines may be programmed simultaneously. However, layout becomes difficult.

Therefore, as shown in the seventh embodiment, capacitances C0 and C1 are provided.
At the time of programming, the transfer gate transistors TG0 and TG1 are turned on in response to the control signal CG1. Further, the Y decoder 1040 switches the Y gate transistors YG0 and YG1 at a high speed, for example, at a cycle of several tens of microseconds in response to the Y address signal. At this time, data is sequentially applied to write circuit 1080 in accordance with the Y address signal. Thereby, the capacitances C0 and C1 are charged according to the data via the main bit lines MB0 and MB1. This operation is repeated for 1 ms.

  In general, since the current required for tunneling electrons from the floating gate is several nanoamperes or less, the current consumed for tunneling can be supplied by the charges accumulated in the capacitances C0 and C1.

  As shown in FIG. 35, for example, when the Y gate transistors YG0 and YG1 are switched every 250 μs, the program voltage is not applied to the main bit line MB0 for a period of 250 μs to 500 μs and a period of 750 μs to 1 ms. . However, during these periods, the voltage of the main bit line MB0 is held by the charges accumulated in the main bit line MB0 and the capacitance C0. Therefore, the time required to program the memory cells connected to the main bit lines MB0 and MB1 is 1 ms.

  Here, the voltage decrease amount ΔV during the period when the program voltage is not applied to the main bit line MB0 is determined by the value of the capacitance C0 and the switching frequency of the Y gate transistor. As the value of the capacitance C0 is larger or the switching frequency is larger, the decrease in the program voltage is suppressed, and the program is performed stably and at high speed.

  When the capacitances C0 and C1 are formed of MOS capacitors, it is preferable to connect the main bit lines MB0 and MB1 to the gates. This is because if the main bit lines MB0 and MB1 are connected to the diffusion layer of the MOS capacitor, the charged program voltage may be discharged in a short time due to, for example, junction leakage at a high temperature.

  The voltage application conditions during programming and erasing are the same as in the sixth embodiment. The sector batch erase operation and program operation are the same as in the sixth embodiment.

(8) Eighth Example (FIGS. 36 to 51)
(A) Overall configuration of flash memory (FIGS. 36 and 37)
FIG. 36 is a block diagram showing the overall configuration of the flash memory according to the eighth embodiment. FIG. 37 is a circuit diagram showing a detailed configuration of the memory array and related parts.

  The flash memory of FIG. 36 differs from the flash memory of the sixth embodiment shown in FIG. 18 in the following points. A source decoder 1270 is provided instead of the source control circuit 1110. Negative voltage generation circuit 1230 applies a negative voltage to select gate decoder 1260 and source decoder 1270 instead of Y decoder 1040.

  As shown in FIG. 37, the sources of the memory cells M00, M01, M10, and M11 in the sector SE1 are connected to the source line SL1, and the sources of the memory cells M02, M03, M12, and M13 in the sector SE2 are connected to the source line SL2. Connected. The output terminal of source decoder 1270 is connected to source lines SL1 and SL2.

  At the time of erasing, the source of each memory cell in the selected sector is in a floating state. When a leak path exists in the source, the source potential rises and the electric field between the source and the floating gate is reduced.

  Therefore, in order to stabilize the source potential at the time of erasing, capacitances C11 and C12 may be connected to the source lines SL1 and SL2 via transfer gate transistors TG11 and TG12, respectively.

  A well potential VB is applied to the capacitances C11 and C12. A control signal CG2 is supplied from the control circuit 1130 to the transfer gate transistors TG11 and TG12.

  At the time of erasing, the transfer gate transistors TG11 and TG12 are turned on in response to the control signal CG2. Thereby, the change in the source potential is reduced.

  Since the program operation and the read operation in the eighth embodiment are the same as those in the sixth embodiment, the sector batch erase operation will be described below.

  In the sixth embodiment, at the time of erasing, a voltage is applied as shown in FIG. However, if erasing is performed in a very short time (for example, several milliseconds), the formation of the inversion layer under the memory cell cannot follow the voltage application, and a depletion layer is formed under the memory cell. .

  In such a case, it is preferable that the voltage application condition to the memory cells in the selected sector is different from the voltage application condition to the memory cells in the non-selected sector.

  The voltage application conditions differ depending on whether the insulating film 1004 (tunnel insulating film) under the floating gate 1005 has no gate bird's beak or not. Here, the gate bird's beak means a state in which the peripheral portion of the lower surface of the floating gate 1005 is eroded by the tunnel insulating film under the floating gate 1005 at the time of manufacture, as indicated by gb in FIG. This increases the thickness of the tunnel insulating film below the peripheral edge of the floating gate 1005.

  First, voltage application conditions when the gate bird's beak is small or small will be described, and then voltage application conditions when the gate bird's beak is large will be described.

(B) When there is no gate bird's beak (FIGS. 38 to 42)
(I) Erase of memory cell (FIGS. 38 and 39)
38, Cg is a capacitance between the control gate 1006 and the floating gate 1005, Cf is a capacitance between the floating gate 1005 and the P-well 1008, Cb is a capacitance due to a depletion layer, Cd is a drain 1002 and a floating gate 1005 , Cs indicates a capacitance between the source 1003 and the floating gate 1005. Ct represents a combined capacity of the capacity Cf and the capacity Cb.

  Now, a positive voltage VCG is applied to the control gate 1006 and a negative voltage VB is applied to the P-well 1008. In this case, since the drain 1002 and the source 1003 are in a floating state, the drain voltage Vd and the source voltage Vs are almost negative voltages VB. If the potential of the floating gate 1005 at this time is VFG and the initial accumulated charge is 0, the following equation is established from the law of conservation of charge.

(VCG-VFG) .Cg = (VFG-VB). (Cs + Ct + Cd)
... (1)
When formula (1) is expanded, the following formula is obtained.

VFG = {VCG · Cg + (Cs + Ct + Cd) · VB} / (Cs + Ct
+ Cd + Cg) (2)
Further expanding equation (2) gives the following equation.

VFG = {VCG + (Cs + Ct + Cd) · VB / Cg} / {(Cs + Ct
+ Cd) / Cg + 1} (3)
Here, since Cs and Cd are smaller than Cg, they can be ignored. Therefore, Expression (3) becomes as follows.

VFG = (VCG + Ct · VB / Cg) / (Ct / Cg + 1) (4)
When the depletion layer spreads, the capacity Cb decreases and the capacity Ct also decreases. Therefore, the potential VFG of the floating gate 1005 approaches the potential VCG of the control gate 1006. However, the potentials of the drain 1002 and the source 1003 in the floating state are almost the same as the potential of the P − well 1008.

  In this case, the electric field E between the floating gate 1005 and the drain 1002 or the source 1003 is expressed by the following equation.

E = (VFG−VB) / TOX (5)
Here, VFG represents the potential of the floating gate 1005, VB represents the potential of the P-well 1008, and TOX represents the thickness of the tunnel insulating film.

  Since the potential VFG of the floating gate 1005 is increased, the electric field between the floating gate 1005 and the drain 1002 and the electric field between the floating gate 1005 and the source 1003 are increased. Therefore, the tunnel effect at the end of the drain 1002 or the source 1003 is improved. Therefore, the erase efficiency is improved.

  Such an effect is preferable in the selected sector, but not preferable in the non-selected sector.

  Therefore, the source 1003 of the memory cell in the selected sector is set in a floating state as shown in FIG. 39A, and the source 1003 of the memory cell in the non-selected sector is set in FIG. As shown in FIG. 5, the same potential as the potential of the P − well 1008 or a potential higher than the potential of the P − well 1008 is supplied.

  Thus, in the memory cell in the non-selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, the potential of the floating gate 1005 decreases due to capacitive coupling between the floating gate 1005 and the channel ch, and the electric field applied to the tunnel insulating film is relaxed. As a result, the data in the memory cells in the non-selected sector is stably protected.

(Ii) Flash memory sector batch erase operation (FIG. 40)
The sector batch erase operation of the flash memory when there is no gate bird's beak will be described with reference to FIG. Here, it is assumed that the sector SE1 is erased collectively.

  10V is applied to the word lines WL0 and WL1 in the sector SE1, and 0V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0V is applied to the select gate lines SGL1 and SGL2. -5V is applied to the P-well 1008. The source line SL1 is brought into a floating state, and −5V is applied to the source line SL2.

  As a result, the memory cells in the sector SE1 can be erased collectively while stably protecting the data in the memory cells in the sector SE2.

(Iii) Source decoder (FIGS. 41 and 42)
FIG. 41 is a diagram showing the configuration of the source decoder 1270 used when there is no gate bird's beak. FIG. 42 is a diagram showing voltages at various parts of the source decoder 1270 of FIG. FIG. 41 shows only a portion related to source line SL1. The configuration of the portion related to the source line SL2 is the same as the configuration shown in FIG. 41 except that the input signals applied to the input terminals AD0, AD1, and AD2 are different.

  The back gates of P-channel transistors P1, P2, and P3 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, N3, and N4 are connected to terminal VBB.

  At the time of erasing, 0V is applied to the terminal VDD, and a negative voltage (−5V) equal to the well potential is applied to the terminal VBB. Further, a negative voltage (−5 V) equal to the well potential or a negative voltage higher than the well potential is applied to the terminal VBB2.

  When the sector SE1 is selected, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Accordingly, the transistor N4 is turned off and the source line SL1 is in a floating state. When the sector SE1 is not selected, an input signal of −5V is applied to any one of the input terminals AD0 to AD2. Therefore, the transistor N4 is turned on, and −5V is applied to the source line SL1.

  During programming and reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, 0 V is applied to the terminal VBB, and 0 V is applied to the terminal VBB2.

  At the time of programming, an input signal of 5V is applied to all of the input terminals AD0 to AD2. Accordingly, the transistor N4 is turned off and the source line SL1 is in a floating state.

  At the time of reading, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N4 is turned on and 0 V is applied to the source line SL1.

(C) When there is a gate bird's beak (FIGS. 43 to 47)
(I) Erase of memory cell (FIGS. 43 and 44)
As shown in FIG. 43, when the gate bird's beak gb is large, the diffusion layer forming the drain 1002 and the source 1003 may not extend below the thin tunnel insulating film. In this case, a tunnel effect does not occur between the drain 1002 and the floating gate 1005 and between the source 1003 and the floating gate 1005. Therefore, erasing is performed by the tunnel effect between P @-well 1008 and floating gate 1005.

  The electric field E between the floating gate 1005 and the P-well 1008 is expressed by the following equation.

E = (VFG−VB) / (TOX + Id) (6)
Here, VFG represents the potential of the floating gate 1005, VB represents the potential of the P-well 1008, TOX represents the thickness of the tunnel insulating film, and Id represents the thickness of the depletion layer. As described above, when the drain 1002 and the source 1003 are in a floating state, the electric field is weakened by the depletion layer and the erasing efficiency is lowered.

  In such a case, a negative voltage (-5 V) equal to the potential of the P-well 1008 is applied to the source 1003 of the memory cell in the selected sector as shown in FIG. As shown in FIG. 44B, the source 1003 of the memory cell in the sector is set in a floating state.

  Accordingly, in the memory cell in the selected sector, a channel ch is formed between the source 1003 and the drain 1002, and the potential of the channel ch is supplied from the source 1003. Therefore, a sufficient electric field is applied to the tunnel insulating film between the channel ch and the floating gate 1005, and a tunnel phenomenon occurs between the channel ch and the floating gate 1005. As a result, the erase efficiency of the memory cells in the selected sector is improved.

  On the other hand, since the source 1003 of the memory cell in the unselected sector is in a floating state, a channel is not formed between the source 1003 and the drain 1002, and a depletion layer is formed below the memory cell. Therefore, the electric field between floating gate 1005 and P-well 1008 is relaxed.

(Ii) Flash memory sector batch erase operation (FIG. 45)
The sector batch erase operation of the flash memory when there is a gate bird's beak will be described with reference to FIG. Here, it is assumed that the sector SE1 is erased collectively.

  10V is applied to the word lines WL0 and WL1 in the sector SE1, and 0V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0V is applied to the select gate lines SGL1 and SGL2. -5V is applied to the P-well 1008. -5V is applied to the source line SL1, and the source line SL2 is brought into a floating state.

  As a result, the memory cells in the sector SE1 can be erased collectively while stably protecting the data in the memory cells in the sector SE2.

(Iii) Source decoder (FIGS. 46 and 47)
FIG. 46 is a diagram showing the configuration of the source decoder 1270 used when there is a gate bird's beak. FIG. 47 is a diagram showing voltages at various parts of the source decoder 1270 of FIG. FIG. 48 shows only a portion related to source line SL1. The configuration of the portion related to source line SL2 is the same as the configuration shown in FIG. 46 except that the input signals applied to input terminals AD0, AD1, and AD2 are different.

  The back gates of P-channel transistors P1, P2, P3, and P4 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, N3, N5, and N6 are connected to terminal VBB.

  At the time of erasing, 0V is applied to the terminal VDD, and a negative voltage (−5V) that is the same as the well potential is applied to the terminal VBB.

  When the sector SE1 is selected, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N6 is turned on, and −5V is applied to the source line SL1. When the sector SE1 is not selected, an input signal of −5V is applied to any one of the input terminals AD0 to AD2. Accordingly, the transistor N6 is turned off and the source line SL1 is in a floating state.

  During programming and reading, power supply voltage Vcc (5 V) is applied to terminal VDD, and 0 V is applied to terminal VBB.

  At the time of programming, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Accordingly, the transistor N6 is turned off and the source line SL1 is in a floating state.

  At the time of reading, a 5V input signal is applied to all of the input terminals AD0 to AD2. Therefore, the transistor N6 is turned on and 0 V is applied to the source line SL1.

(D) When the well potential is low (FIGS. 48 to 51)
(I) Erase of memory cell (FIG. 48)
In the above description, it has been assumed that the voltage applied to the P-well during erasing is -5V. Further, when the well potential is further lowered in order to improve the erasing efficiency, disturb in a non-selected sector becomes a problem.

  For example, when the gate bird's beak is large, as shown in FIG. 46, the negative voltage (−5V) of the terminal VBB which is the same as the well potential is applied to the source line of the selected sector. The source line is in a floating state.

  However, when the well potential is further lowered, the electric field between the floating gate and the P-well is increased in the memory cell in the non-selected sector. As a result, the data in the memory cells in the non-selected sector cannot be reliably protected.

  Therefore, a voltage higher than the well potential is applied to the source line of the unselected sector. For example, as shown in FIG. 48, the potential of the P-well 1008 is set to -10V. In this case, −10 V, which is the same as the well potential, is applied to the source 1003 of the memory cell in the selected sector, as shown in FIG. 48A, and the source 1003 of the memory cell in the unselected sector is applied. Applies -5V.

  Thereby, the potential difference between the channel and the control gate 1006 can be set to 5 V in the memory cells in the unselected sector.

(Ii) Flash memory sector batch erase operation (FIG. 49)
The sector batch erase operation of the flash memory when the well potential is low will be described with reference to FIG. Here, it is assumed that the sector SE1 is erased collectively.

  10V is applied to the word lines WL0 and WL1 in the sector SE1, and 0V is applied to the word lines WL2 and WL3 in the sector SE2. Further, 0V is applied to the select gate lines SGL1 and SGL2. −10V is applied to the P− well 1008. −10V is applied to the source line SL1, and −5V is applied to the source line SL2.

  As a result, the memory cells in the sector SE1 can be erased collectively while stably protecting the data in the memory cells in the sector SE2.

(Iii) Source decoder (FIGS. 50 and 51)
FIG. 50 is a diagram showing a configuration of a source decoder 1270 used when the well potential is low. FIG. 51 is a diagram showing voltages at various parts of the source decoder 1270 of FIG. FIG. 50 shows only a portion related to source line SL1. The configuration of the part related to source line SL2 is the same as the configuration shown in FIG. 50 except that the input signals applied to input terminals AD0, AD1, and AD2 are different.

  The back gates of P-channel transistors P1, P2, P3, and P5 are connected to terminal VDD, and the back gates of N-channel transistors N1, N2, and N3 are connected to terminal VBB.

  At the time of erasing, −5V is applied to the terminal VDD, and a negative voltage (−10V) that is the same as the well potential is applied to the terminal VBB. Further, 0V is applied to the control line CSL, and −10V is applied to the control line DSL.

  When the sector SE1 is selected, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Therefore, −10 V is applied to the source line SL1. When the sector SE1 is not selected, an input signal of −10V is applied to any one of the input terminals AD0 to AD2. Therefore, −5 V is applied to the source line SL1. Note that the potential of the source line at the time of non-selection can be freely selected by changing the potential applied to the terminal VDD at the time of erasing.

  During programming and reading, power supply voltage Vcc (5 V) is applied to terminal VDD, and 0 V is applied to terminal VBB.

  At the time of programming, 0V is applied to the control line CSL and 5V is applied to the control line DSL. Accordingly, the source line SL1 is in a floating state.

  At the time of reading, 5V is applied to the control line CSL and 0V is applied to the control line DSL. Further, an input signal of 5V is applied to all of the input terminals AD0 to AD2. Therefore, 0 V is applied to the source line SL1.

(9) Ninth embodiment (FIGS. 52 to 56)
(A) Overall configuration of flash memory (FIGS. 52 and 53)
FIG. 52 is a block diagram showing the overall configuration of the flash memory according to the ninth embodiment. FIG. 53 is a circuit diagram showing a detailed configuration of the memory array and related parts.

  The flash memory of FIG. 52 differs from the flash memory of the eighth embodiment shown in FIG. 36 in the following points. Source switches 1281 and 1282 are provided instead of the source decoder 1270. Negative voltage generating circuit 1230 applies a negative voltage to select gate decoder 1260.

  As shown in FIG. 53, the source switch 1281 receives the potential on the select gate line SGL1, and controls the potential of the source line SL1. The source switch 1282 receives the potential on the select gate line SGL2, and controls the potential of the source line SL2. The source switches 1281 and 1282 are controlled by a control signal CG3 from the control circuit 1130.

  Since the program operation and the read operation in the ninth embodiment are the same as those in the sixth embodiment, the erase operation will be described below.

(B) Flash memory sector batch erase operation (FIG. 54)
The sector batch erase operation of the flash memory according to the ninth embodiment will be described with reference to FIG. Here, it is assumed that collective erasure of sector SE1 is performed.

  As described in the eighth embodiment, −10 V is applied to the P − well 1008 in order to further improve the erase efficiency. 10V is applied to the word lines WL0 and WL1 in the sector SE1, and 0V is applied to the word lines WL2 and WL3 in the sector SE2. Further, -10V is applied to the select gate line SGL1, and -5V is applied to the select gate line SGL2. −10V is applied to the source line SL1 by the source switch 1281, and −5V is applied to the source line SL2 by the source switch 1282.

  As a result, the sector SE1 can be efficiently erased collectively without disturbing the sector SE2.

(C) Select gate decoder and source switch (FIGS. 55 and 56)
FIG. 55 is a circuit diagram showing configurations of a select gate decoder and a source switch used in the flash memory according to the ninth embodiment. FIG. 56 is a diagram showing voltages at respective parts of the select gate decoder and the source switch of FIG. FIG. 55 shows only a portion related to select gate line SGL1 of select gate decoder 1260 and source switch 1281 connected to source line SL1. The portion related to select gate line SGL2 of select gate decoder 1260 and the configuration of source switch 1282 are the same as the configuration shown in FIG. 55 except that the input signals applied to input terminals AD0, AD1, and AD2 are different. .

  The back gates of P channel transistors P21-P25 are connected to terminal VDD, and the back gates of N channel transistors N21-N28 are connected to terminal VBB. The control signal CG3 shown in FIG. 53 is given by the control lines ASL and BSL.

  At the time of erasing, 0V is applied to the terminal VDD and −10V is applied to the terminal VBB. -5V is applied to the terminal VBB2, and -10V is applied to the terminal VSG. 0V is applied to the control line ASL, and −10V is applied to the control line BSL.

  When the sector SE1 is selected, an input signal of 0V is applied to all of the input terminals AD0 to AD2. Therefore, the transistors N25 and P25 are turned on, and the potential (−10 V) of the terminal VSG is applied to the select gate line SGL1. Further, since the potential of the control line ASL is 0V, the transistor N27 is turned on, and the potential of the terminal VSG (−10V) is also applied to the source line SL1.

  When the sector SE1 is not selected, an input signal of −10V is applied to any one of the input terminals AD0 to AD2. Therefore, the transistor N26 is turned on, and the potential (−5V) of the terminal VBB2 is applied to the select gate line SGL1. Further, the potential (−5 V) of the terminal VBB2 is also applied to the source line SL1 through the transistor N27. Note that the potential of the source line of the unselected sector can be freely changed by changing the voltage applied to the terminal VBB2.

  In programming, the power supply voltage Vcc (7 V) is applied to the terminal VDD, and 0 V is applied to the terminals VBB and VBB2. 7v is applied to the terminal VSG, and 0V is applied to the control lines ASL and BSL.

  When the sector SE1 is selected, the transistors N25 and P25 are turned on, and the potential (7 V) of the terminal VSG is applied to the select gate line SGL1. At this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistors N27 and N28 are off, the source line SL1 is in a floating state.

  At the time of reading, the power supply voltage Vcc (5 V) is applied to the terminal VDD, and 0 V is applied to the terminals VBB and VBB2. 5V is applied to the terminal VSG. 0V is applied to the control line ASL, and 5V is applied to the control line BSL.

  When the sector SE1 is selected, the transistors N25 and P25 are turned on, and the potential (5 V) of the terminal VSG is applied to the select gate line SGL1. At this time, since the transistor N28 is on, the source line SL1 is grounded. When the sector SE1 is not selected, the transistor N26 is turned on, and the potential (0 V) of the terminal VBB2 is applied to the select gate line SGL1. Also at this time, since the transistor N28 is on, the source line SL1 is grounded.

  As described above, the well potential is applied to the source line of the selected sector and the potential higher than the well potential is applied to the source line of the unselected sector at the time of erasing without requiring the source decoder 1270 shown in FIG. Can be applied.

(10) Tenth embodiment (FIG. 57)
A feature of the flash memory according to the tenth embodiment is that a verify operation is not required at the time of programming. The configuration of the flash memory of the tenth embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erase operation and the read operation are the same as in the sixth to ninth embodiments.

  The program operation of the flash memory according to the tenth embodiment will be described with reference to the flowchart of FIG.

  First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S31). As a result, the selected select gate transistor is turned on. Then, the source line is brought into a floating state (step S32). The main bit line corresponding to the data “0” is precharged to 5V, and the main bit line corresponding to the data “1” is kept at 0V (step S33).

  Thereafter, the source line is grounded for a certain period (step S34). If the threshold voltage of the memory cell in the selected sector is higher than the verify level, the potential of the main bit line corresponding to data “0” is maintained at the precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data “0” is discharged through the memory cell.

  Thereafter, the source line is brought into a floating state (step S35), and a negative voltage is applied to the selected word line (step S36). Thereby, only the memory cells connected to the main bit line precharged to 5V are programmed.

  After repeating the above program cycle a specified number of times (step S37), the X address is incremented and the above program cycle is repeated for the next word line (steps S38 and S39). When the above program cycle is repeated for all the word lines in the selected sector, the program operation is completed (step S38).

  According to the above method, after the program voltage is applied to the main bit line, the program operation can be performed at high speed without performing the verify operation one by one.

  In order to stably maintain the precharge level, as shown in the second embodiment, a capacitance may be connected to the main bit line via a transfer gate transistor, and these transfer gate transistors may be turned on during programming. .

  The above method can be similarly applied to the flash memories of other embodiments.

(11) Eleventh embodiment (FIG. 58)
A feature of the flash memory according to the eleventh embodiment is that a verify operation is not required at the time of programming. The configuration of the flash memory of the eleventh embodiment is the same as the configuration of the flash memory of any of the sixth to ninth embodiments. The batch erase operation and the read operation are the same as in the sixth to ninth embodiments.

  The program operation of the flash memory according to the eleventh embodiment will be described with reference to FIG.

  First, the potential of the selected word line is set to the verify level, and a high voltage is applied to the selected select gate line (step S41). As a result, the selected select gate transistor is turned on. Then, the source line is brought into a floating state (step S42). The main bit line corresponding to data “0” is precharged to 5V, and the main bit line corresponding to data “1” is kept at 0V (step S43).

  Thereafter, the source line is grounded for a certain period (step S44). If the threshold voltage of the memory cell in the selected sector is higher than the verify level, the potential of the main bit line corresponding to data “0” is maintained at the precharge level. If the threshold voltage of the memory cell in the selected sector is lower than the verify level, the main bit line corresponding to data “0” is discharged through the memory cell.

  Thereafter, if the potentials of all the main bit lines are not 0 V (step S45), the source line is set in a floating state (step S46), and a negative voltage is applied to the selected word line (step S47). Thereby, only the memory cells connected to the main bit line precharged to 5V are programmed.

  The above program cycle is repeated until the potentials of all the bit lines become 0 V (step S45), then the X address is incremented and the above program cycle is repeated for the next word line (steps S48 and S49). When the above program cycle is performed for all the word lines in the selected sector, the program operation is finished (step S48).

  According to the above method, after the program voltage is applied to the main bit line, the program operation can be performed at high speed without performing the verify operation one by one, and the program operation can be automatically terminated.

The above method can be similarly applied to flash memories of other embodiments.
(12) Twelfth embodiment (FIGS. 59 to 64)
FIG. 59 is a block diagram showing the overall configuration of the flash memory according to the twelfth embodiment. In the flash memory shown in FIG. 59, the program operation and the erase operation are performed in a manner similar to that of the flash memory shown in FIG.

  Referring to FIG. 59, this flash memory is divided into predecoders 1451 to 1454, global decoder 1455, select gate decoder 1456, well potential control circuits 1457 and 1458, source line drivers 1459 and 1460, and sectors. Memory cell arrays 1461 and 1462, and local decoders 1463 and 1464 are included.

  FIG. 60 is a circuit diagram of the memory cell array and its peripheral circuits shown in FIG. In FIG. 60, detailed circuits for the global decoder 1455, the local decoder 1464, the memory cell array, the source line driver 1460, and the select gate decoder 1456 are shown. In FIG. 60, “2AL” indicates a wiring formed by the second aluminum wiring layer, and “2POL” indicates a wiring formed by the second polysilicon layer.

  Table 1 below shows voltages applied to the circuits shown in FIGS. 59 and 60 in the erase operation, program operation and read operation.

  In the twelfth embodiment, in addition to the various advantages already described, the following additional advantages are also obtained.

  FIG. 61 is a layout diagram on a semiconductor substrate showing a connection mode between word lines WL00 to WL07 and WL10 to WL17 shown in FIG. 60 and output lines WL0 to WL7 of local decoder 1464. Referring to FIG. 61, each of word lines WL00 to WL07 and WL10 to WL17 is formed of a second polysilicon layer. On the other hand, each output line of the local decoder 1464 is formed by the first aluminum wiring layer. Connection between each word line and the corresponding output signal line is made through a through hole. It is pointed out that the connection mode shown in FIG. 61 is also shown in the circuit diagram shown in FIG.

  By using the connection modes shown in FIGS. 60 and 61, the connection between the word line and the output line of the local decoder is simplified, and therefore the wiring density is reduced, and as a result, a high degree of integration is obtained.

  FIG. 62 is a cross-sectional structure diagram showing separation between two memory cells 1491 and 1492 shown in FIG. The memory cells 1491 and 1492 shown in FIG. 60 are placed at positions closest to the other sector in each sector. In order to separate these transistors 1491 and 1492, an isolation oxide film 1490 is formed in the semiconductor substrate as shown in FIG. The width Wc of the isolation oxide film 1490 necessary for isolating two adjacent transistors 1491 and 1492 is smaller than that in the case of using the field shield transistors 1495 and 1496 as shown in FIG. . That is, in the example shown in FIG. 63, a large width Wd is required only for forming the transistors 1495 and 1496 for isolation, but by using the isolation oxide film 1490, two transistors 1491 that are adjacent to each other with a smaller width Wc. And 1492 can be separated. Thereby, a higher integration degree can be obtained.

  FIG. 64 is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment. The word line voltage control circuit 1470 shown in FIG. 64 is omitted in FIG. 59 for simplification.

  64, word line voltage control circuit 1470 includes a VPP generator 1471, a VBB generator 1472, a voltage detector 1473, an inverter 1474, a VPP switching circuit 1475, a VPP switching circuit 1476, and a CMOS. Transmission gates 1477 and 1478.

  Predecoder 1452 includes a PMOS transistor 1481 and an NMOS transistor 1482 that constitute a CMOS transmission gate.

  In the word line voltage control circuit 1470 and the predecoder 1452 shown in FIG. 64, the voltages shown in Table 1 are applied to execute the erase operation, program operation and read operation.

  In general, in order to inspect the threshold voltage distribution of the memory cells of the flash memory, an external voltage VEW for testing is applied. As shown in FIG. 64, in the test mode operation, external voltage VEW is applied via CMOS transmission gate 1478 in word line voltage control circuit 1470 and CMOS transmission gate in predecoder 1452 (configured by transistors 1481 and 1482). This is applied to word lines WL00 to WL17 shown in FIG. Since the voltage path of the external voltage VEW is constituted only by the CMOS circuit, no voltage loss occurs due to the threshold voltage of the MOS transistor. In other words, the external voltage VEW changing in a wider range can be applied to the word line without changing the voltage level, and a desired test can be performed.

(13) Thirteenth Embodiment FIG. 65 is a schematic diagram of a thirteenth embodiment of a nonvolatile semiconductor memory device according to the present invention. The semiconductor substrate 80 is divided into a memory transistor region and a peripheral region. In the memory transistor region, memory transistors 87a, 87b, 87c, and 87d are formed with a space therebetween. Of the main surface of the semiconductor substrate 80, n-type source regions 84a and 84b and n-type drain regions 85a and 85b are formed in the memory transistor region with a space therebetween. The source region 84a becomes the source region of the memory transistors 87a and 87b, and the source region 84b becomes the source region of the memory transistors 87c and 87d.

  The drain region 85a becomes the drain region of the memory transistors 87b and 87c, and the drain region 85b becomes the drain region of the memory transistor 87d. Reference numeral 88 denotes a control gate, and 89 denotes a floating gate.

  A select gate transistor 86 having n-type source / drain regions 83a and 83b is formed in the memory transistor region on the main surface of the semiconductor substrate 80. The source / drain region 83b also serves as the drain region of the memory transistor 87a.

  A sub bit line 90 made of polycrystalline silicon is formed on the memory transistors 87a, 87b, 87c, 87d. Sub-bit line 90 is connected to source / drain region 83b. The branch line 91a branched from the subbit line 90 is connected to the drain region 85a, and the branch line 91b is connected to the drain region 85b. A main bit line 92 made of aluminum is formed on the sub bit line 90. The main bit line 92 is connected to the source / drain region 83a.

  A p well region 82 is formed in the semiconductor substrate 80 so as to surround the memory transistor region, and an n well region 81 is formed so as to surround the p well region 82. A MOS transistor 93 is formed in the peripheral region. A more detailed description of the nonvolatile semiconductor memory device according to the present invention will be given using the fourteenth embodiment.

(14) Fourteenth Embodiment FIG. 66A is a cross-sectional view of a part of a memory transistor portion of a fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. A p well region 210 is formed on the p type silicon substrate 201 with a space therebetween. On the p-well region 210, memory transistors 250 to 257, 261, 262 and select gate transistors 259, 260 are formed. In the p-well region 210, an n-type source region 223 and an n-type drain region 224 of each memory transistor are formed. Reference numeral 249 denotes an n-type impurity region.

  Each memory transistor and select gate transistor are covered with a silicon oxide film 247. The source region 223 is covered with a silicon oxide film 247. On the other hand, the drain region 224 and the impurity region 249 are not blocked by the silicon oxide film. Each memory transistor includes a floating gate 219 and a control gate 220.

  The drain regions 224 of the memory transistors 250 to 257 are electrically connected by one sub bit line 227a. The drain regions 224 of the memory transistors 261 and 262 are electrically connected by one sub bit line 227b. Impurity region 249 is electrically connected to connection conductive layer 248. A dummy gate transistor 258 having a dummy gate 242 is formed on the field oxide film 206. Details of the dummy gate transistor will be described later.

  An interlayer insulating film 245 is formed on the sub bit lines 227a and 227b, and a main bit line 233 is formed on the interlayer insulating film 245. The main bit line 233 is electrically connected to the connection conductive layer 248. An interlayer insulating film 246 is formed on the main bit line 233, and an aluminum wiring 238 is formed on the interlayer insulating film 246 with a space therebetween.

  On the other hand, an n well region 207 is formed in the silicon substrate 201 so as to cover the p well region 210.

  FIG. 66 (b) is an equivalent circuit diagram of the memory transistor shown in FIG. 66 (a). Each of the eight memory transistors has a drain region connected to the sub-bit line and a source region connected to the source line. The selection gate 1 conducts / cuts off the main bit line and the sub bit line. Word lines 1 to 8 are control gates.

  FIG. 67 is a cross-sectional structure diagram of a memory transistor of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention. A gate oxide film 213 is formed between the p well region 210 and the floating gate 219, and an ONO film 215 is formed between the floating gate 219 and the control gate 220.

  Next, the operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be explained with reference to FIGS. First, the erase operation will be described. The NOR type and NAND type described in the conventional example are in an erased state by extracting electrons, but in the fourteenth embodiment, they are in an erased state by injecting electrons. That is, when the memory transistors 250 to 257 are erased at once, the main bit line 233 is kept in a floating state and the select gate transistor 259 is turned OFF. As a result, the sub bit line 227a is also in a floating state. Then, a voltage of about −10 V is applied to the source line and p well region 210a. Then, a voltage of about 10 V is applied to the word lines 1 to 8. As a result, as shown in 2 of FIG. 67, electrons in the channel region are injected into the floating gate 219 by the channel FN phenomenon, which is one of the tunnel effects. This is the erased state “1”, and the value of Vth is about ˜6V.

  Next, the writing operation will be described. For example, when the memory transistor 257 is set to the write state “0”, the select gate transistor 259 is turned on and a voltage of about 5 V is applied to the main bit line 233. As a result, the voltage of the sub bit line 227a also becomes about 5V. Then, the p-well region 210a is kept at the ground potential, and the source line is set to OPEN. Further, a voltage of about −10 V is applied to the word line 8, and the word lines 1 to 7 are kept at the ground potential. As a result, as indicated by 1 in FIG. 67, electrons accumulated in the floating gate 219 of the memory transistor 257 are extracted to the drain region 224 by the drain FN phenomenon which is one of the tunnel effects. As a result, the memory transistor 257 is in the write state “0”, and at this time, the value of Vth becomes about 1V.

  Next, the reading operation will be described. For example, when the memory transistor 257 is read, the select gate transistor 259 is turned on and a voltage of about 1 V is applied to the main bit line 233. Then, the source line and p well region 210a are kept at the ground potential. Then, a voltage of about 3 to 5 V is applied to the word line 8 to bring the word lines 1 to 7 to the ground potential. At this time, when the memory transistor 257 is in the erased state “1”, no channel is formed and no current flows through the bit line. On the other hand, when the write state is “0”, a channel is formed and a current flows through the bit line. As a result, the write / erase state is determined.

  In the fourteenth embodiment, a negative voltage is applied to the p well region 210. Since there is an n-well region 207 around the p-well region 210, the p-well region 210 and the n-well region 207 are in a reverse bias state even when a negative voltage is applied, and a voltage is applied to the p-well region 210. However, no voltage is applied to the peripheral circuit formation region.

  In the erase operation, a negative voltage is applied to the p-well region and a positive voltage is applied to the word line, so that the maximum voltage value is reduced while the p-well region 210 and the control gate 220 are connected. The potential difference is made relatively large, and the channel FN effect can be caused.

  As shown in FIG. 66 (a), a sub bit line 227a is connected to each drain region 224 of the memory transistors 250-257. For this reason, a large amount of read current can be taken during the read operation, so that the read operation can be performed at a higher speed than the NAND type.

  Further, since the drain FN is used for the writing operation as shown in FIG. 67, the writing operation can be performed with a higher efficiency than the case of using channel hot electrons, thereby reducing the power consumption.

  Next, the planar arrangement state of the structure shown in FIG. FIG. 68 is a plan view up to the state where the control gate 220 is formed. The state of FIG. 68 cut along line AA shows the state up to the control gate 220 in FIG. The control gate 220, the selection gate 234, the dummy gate 242 and the source line 223a extend in the vertical direction. The source line 223a is obtained by connecting the source regions 223 shown in FIG. Field oxide films 206 and drain regions 224 are alternately formed. Note that the wiring layer (corresponding to the control gate of the memory transistor) on the selection gate 234 is not shown.

  FIG. 69 shows a state where sub-bit lines 227a and 227b are formed on FIG. The source line 223a is electrically connected to the wiring layer 241. The wiring layer 241 is formed simultaneously with the sub bit lines 227a and 227b.

  The selection gate 234 is electrically connected to the polypad 236. The poly pad 236 is also formed at the same time as the sub bit lines 227a and 227b. The contact between the sub bit lines 227a and 227b and the drain region 224 is not shown. Further, the contact between the connection conductive layer 248 and the impurity region 249 is not shown.

  FIG. 70 shows a state in which the main bit line 233 is formed on FIG. The main bit line 233 is electrically connected to the connection conductive layer 248. The aluminum electrodes 237a, 237b, 237c, and 237d are formed simultaneously with the main bit line 233. The aluminum electrode 237a is electrically connected to one poly pad 236, and the aluminum electrode 237b is electrically connected to the other poly pad 236. The aluminum electrode 237c is electrically connected to the wiring layer 241. The aluminum electrode 237d is electrically connected to the dummy gate 242.

  71 shows a state in which aluminum wirings 238a to 238g are formed on FIG. The aluminum wiring 238a is electrically connected to the aluminum electrode 237a, the aluminum wiring 238b is electrically connected to the aluminum electrode 237b, the aluminum wiring 238e is electrically connected to the aluminum electrode 237c, and the aluminum wirings 238f and 238g are aluminum electrodes. 237b is electrically connected.

  Next, first to seventh examples of the overall configuration and operation of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to Table 2.

  A memory cell matrix included in the nonvolatile semiconductor memory device is divided into a plurality of sectors as described below. Table 2 shows voltage application conditions to the memory cells (memory transistors) in the selected sector and the memory cells (memory transistors) in the non-selected sectors. In Table 2, Vd is a drain voltage, Vg is a control gate voltage, Vs is a source voltage, and Vbb is a well voltage.

<1> First Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 72 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the first example.

  Memory cell matrix 70 is divided into sectors SE1 and SE2. Memory cell matrix 70 includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively. Memory cell matrix 70 is formed in P well region 71.

  In the memory cell matrix 70, two main bit lines MB0 and MB1 are arranged. Main bit lines MB0 and MB1 are connected to sense amplifier 52 and write circuit 53 via Y gate transistors YG0 and YG1 in Y gate 72, respectively.

  Two sub bit lines SB01 and SB02 are provided corresponding to the main bit line MB0, and two sub bit lines SB11 and SB12 are provided corresponding to the main bit line MB1.

  Word lines WL0 and WL1 are arranged so as to cross sub-bit lines SB01 and SB11, and word lines WL2 and WL3 are arranged so as to cross sub-bit lines SB02 and SB12.

  Memory cells (memory transistors) M00 to M03 and M10 to M13 are provided at the intersections of the sub bit lines SB01, SB02, SB11, and SB12 and the word lines WL0 to WL3, respectively. Memory cells M00, M01, M10, and M11 are included in sector S1, and memory cells M02, M03, M12, and M13 are included in sector SE2.

  The drain of each memory cell is connected to the corresponding subbit line, the control gate is connected to the corresponding word line, and the source is connected to the source line SL.

  Select gate SG1 includes select gate transistors SG01 and SG11, and select gate SG2 includes select gate transistors SG02 and SG12. Sub-bit lines SB01 and SB02 are connected to main bit line MB0 via select gate transistors SG01 and SG02, respectively, and sub-bit lines SB11 and SB12 are connected to main bit line MB1 via select gate transistors SG11 and SG12, respectively. .

  Address buffer 58 receives an address signal given from the outside, gives an X address signal to X decoder 59, and gives a Y address signal to Y decoder 57. The X decoder 59 selects any one of the plurality of word lines WL0 to WL3 in response to the X address signal. Y decoder 57 generates a selection signal for selecting one of a plurality of main bit lines MB0 and MB1 in response to the Y address signal.

  Y gate transistors in Y gate 72 connect main bit lines MB0 and MB1 to sense amplifier 52 and write circuit 53 in response to a selection signal, respectively.

  At the time of reading, sense amplifier 52 detects data read on main bit line MB0 or main bit line MB1 and outputs the data to the outside via data input / output buffer 51.

  At the time of writing, externally applied data is applied to write circuit 53 via data input / output buffer 51, and write circuit 53 applies a program voltage to main bit lines MB0 and MB1 according to the data.

  High voltage generation circuits 54 and 55 receive power supply voltage Vcc (for example, 5 V) from the outside and generate a high voltage. Negative voltage generating circuit 56 receives power supply voltage Vcc from the outside and generates a negative voltage. Verify voltage generation circuit 60 receives power supply voltage Vcc applied from the outside, and applies a predetermined verify voltage to a selected word line at the time of verify. Well potential generating circuit 61 applies a negative voltage to p well region 71 during erasing. The source control circuit 62 applies a high voltage to the source line SL at the time of erasing. Select gate decoder 63 selectively activates select gates SG1 and SG2 in response to part of the address signal from address buffer 58.

  The write / erase control circuit 50 controls the operation of each circuit in response to a control signal given from the outside.

(B) Operation of Nonvolatile Semiconductor Memory Device Next, sector erase operation, write operation, and read operation of the nonvolatile semiconductor memory device will be described with reference to Table 1.

(I) Sector Erase Operation Here, it is assumed that the sector SE1 is erased collectively. First, a control signal designating the sector batch erase operation is given to the write / erase control circuit 50. Thereby, the high voltage generation circuit 55 and the negative voltage generation circuit 56 are activated.

  The high voltage generation circuit 55 applies a high voltage (10 V) to the X decoder 59. The X decoder 59 applies a high voltage (10V) to the word lines WL0 and WL1 of the sector SE1, and applies 0V to the word lines WL2 and WL3 of the sector SE2. Negative voltage generating circuit 56 applies a negative voltage to Y decoder 57 and well potential generating circuit 61. The Y decoder 57 applies a negative voltage to the Y gate transistors YG0 and YG1 in the Y gate 72. Thereby, the main bit lines MB0 and MB1 are in a floating state. The source control circuit 62 places the source line SL in a floating state. The well potential generation circuit 61 applies a negative voltage (−8 V) to the p well region 71. Select gate decoder 63 turns off select gates SG1 and SG2.

  In this way, voltages are applied to the memory cells in the selected sector SE1 and the memory cells in the non-selected sector SE2 as shown in (E1) of Table 2. As a result, all the memory cells in the sector SE1 are erased.

(Ii) Write Operation Here, it is assumed that the memory cell M00 is programmed. That is, data “0” is written into the memory cell M00, and the memory cell M10 holds data “1”.

  First, a control signal designating a program operation is given to the write / erase control circuit 50. Thereby, the high voltage generation circuit 54 and the negative voltage generation circuit 56 are activated.

  The negative voltage generation circuit 56 gives a negative voltage to the X decoder 59. The X decoder 59 selects the word line WL0 in response to the X address signal supplied from the address buffer 58, applies a negative voltage (−8V) to the selected word line WL0, and selects the unselected word lines WL1 to WL3. 0V is applied to.

  High voltage generation circuit 54 applies a high voltage to Y decoder 57, write circuit 53, and select gate decoder 63. First, data “0” is externally applied to the write circuit 53 via the data input / output buffer 51 and latched. The Y decoder 57 applies a high voltage to the Y gate transistor YG0 in the Y gate 72 in response to the Y address signal supplied from the address buffer 58, and applies 0 V to the Y gate transistor YG1. Thereby, the Y gate transistor YG0 is turned on.

  Write circuit 53 applies a program voltage (5 V) corresponding to data “0” to main bit line MB0 via Y gate transistor YG0. The select gate decoder 63 turns on the select gate SG1 and turns off the select gate SG2. Thereby, sub-bit lines SB01 and SB11 are connected to main bit lines MB0 and MB1, respectively. The source control circuit 62 places the source line SL in a floating state. Well potential generation circuit 61 applies 0 V to p well region 71.

  In this way, a voltage is applied to the memory cell M00 as shown in the left column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M00 decreases.

  After a predetermined time (for example, 1 ms), data “1” is externally applied to the write circuit 53 via the data input / output buffer 51 and latched. The Y decoder 57 applies a high voltage to the Y gate transistor YG1 in the Y gate 72 in response to the Y address signal supplied from the address buffer 58, and applies 0 V to the Y gate transistor YG0. Thereby, the Y gate transistor YG1 is turned on. Write circuit 53 applies 0 V corresponding to data “1” to main bit line MB1 via Y gate transistor YG1.

  In this way, a voltage is applied to the memory cell M10 as shown in the right column of (P1) in Table 2. As a result, the threshold voltage of the memory cell M10 is maintained high.

(Iii) Read Operation Here, it is assumed that data is read from memory cell M00. First, a control signal designating a read operation is applied to the write / erase control circuit 50.

  The X decoder 59 selects the word line WL0 in response to the X address signal supplied from the address buffer 58, and applies 3V thereto. At this time, the word lines WL1 to WL3 are kept at 0V. The select gate decoder 63 turns on the select gate SG1 and turns off the select gate SG2. Y decoder 57 turns on Y gate transistor YG 0 in Y gate 72 in response to a Y address signal applied from address buffer 58. The source control circuit 62 grounds the source line SL.

  In this way, a voltage is applied to the selected memory cell M00 as shown in the left column of (R1) in Table 2. Thereby, if the content of M00 is “1”, a read current flows through the main bit line MB0. This read current is detected by the sense amplifier 52 and output to the outside via the data input / output buffer 51. At this time, a voltage is applied to the unselected memory cells as shown in the right column of (R1) in Table 2.

<2> Second Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 73 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a second example.

  The non-volatile semiconductor memory device of FIG. 73 differs from the non-volatile semiconductor memory device of FIG. 72 in that the negative voltage generating circuit 56 applies a negative voltage to the source control circuit 62 during erasing.

The structure of other parts is the same as the structure shown in FIG.
(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and the read operation of the nonvolatile semiconductor memory device of the second example are the same as those of the first example. Also, the sector batch erase operation is different from the first example in that a negative voltage (−8 V) is applied to the source line SL by the source control circuit 62.

  At the time of batch erasing, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E2) in Table 2, and the memory cell in the unselected sector is applied to the right column of (E2) in Table 2. A voltage is applied as shown in FIG.

<3> Third Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 74 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the third example.

  The nonvolatile semiconductor memory device of the third example is different from the nonvolatile semiconductor memory device of the first example in the following points. A source decoder 102 is provided instead of the source control circuit 62. The negative voltage generation circuit 56 applies a negative voltage to the select gate decoder 63 and the source decoder 102 instead of the Y decoder 57.

  The sources of the memory cells M00, M01, M10, and M11 in the sector SE1 are connected to the source line SL1, and the sources of the memory cells M02, M03, M12, and M13 in the sector SE2 are connected to the source line SL2. The output terminal of the source decoder 102 is connected to the source lines SL1 and SL2.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the third example are the same as those of the first example. In the sector batch erase operation, the source decoder 102 places the source line corresponding to the selected sector in a floating state, and applies a negative voltage (−8 V) to the source line corresponding to the unselected sector. For example, at the time of batch erasing of the sector SE1, the source line SL1 is brought into a floating state, and −8V is applied to the source line SL2.

  In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E3) in Table 2, and the memory cells in the unselected sector are applied to the right of (E3) in Table 2. A voltage is applied as indicated in the column.

  As a result, the memory cells in the selected sector can be collectively erased while stably protecting the data in the memory cells in the non-selected sector.

<4> Fourth Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 75 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device according to a fourth example.

  The nonvolatile semiconductor memory device of the fourth example is different from the nonvolatile semiconductor memory device of the third example shown in FIG. 74 in the following points. Negative voltage generation circuit 56 applies a negative voltage only to well potential generation circuit 61 at the time of erasing, and does not apply a negative voltage to select gate decoder 63 and source decoder 102.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the fourth example are the same as those of the first example.

  During the batch erase operation, the source decoder 102 places the source line corresponding to the selected sector in a floating state, and applies 0 V to the source line corresponding to the non-selected sector. For example, at the time of collective erasure of sector SE1, source line SL1 is brought into a floating state, and 0 V is applied to source line SL2.

  In this way, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E4) in Table 2, and the memory cells in the non-selected sector are in accordance with (E4) in Table 2. A voltage is applied as shown in the right column.

  As a result, the memory cells in the selected sector can be collectively erased while stably protecting the data in the memory cells in the non-selected sector.

<5> Fifth Example (a) Overall Configuration of Nonvolatile Semiconductor Memory Device FIG. 76 is a block diagram showing the overall configuration of the nonvolatile semiconductor memory device according to the fifth example.

  The nonvolatile semiconductor memory device of the fifth example is different from the nonvolatile semiconductor memory device of the fourth example shown in FIG. 75 in the following points. Two negative voltage generation circuits 56a and 56b are provided. Negative voltage generation circuit 56 a applies a negative voltage to well potential generation circuit 61, select gate decoder 63 and source decoder 102. The negative voltage generation circuit 56 b gives a negative voltage to the X decoder 59. The structure of the other parts is the same as that shown in FIG.

(B) Operation of Nonvolatile Semiconductor Memory Device The write operation and read operation of the nonvolatile semiconductor memory device of the fifth example are the same as those of the first example.

  During the sector batch erase operation, the source decoder 102 places the source line corresponding to the selected sector in a floating state, and applies −4 V to the source line corresponding to the non-selected sector. For example, at the time of collective erasure of sector SE1, source line SL1 is brought into a floating state, and −4 V is applied to source line SL2.

  In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E5) in Table 2, and the memory cells in the unselected sector are in (E5) of Table 2. A voltage is applied as shown.

  As a result, the memory cells in the selected sector can be collectively erased while stably protecting the data in the memory cells in the non-selected sector.

<6> Sixth Example The overall configuration of the nonvolatile semiconductor memory device according to the sixth example is the same as the configuration shown in FIG. The write operation and read operation of the nonvolatile semiconductor memory device of the sixth example are the same as in the first example.

  During the batch erase operation, the source decoder 102 applies -8V to the source line corresponding to the selected sector, and applies 0V to the source line corresponding to the non-selected sector. For example, at the time of collective erasing of sector SE1, -8V is applied to source line SL1, and 0V is applied to source line SL2.

  In this way, the voltage is applied to the memory cells in the selected sector as shown in the left column of (E6) in Table 2, and the memory cells in the non-selected sector are in accordance with (E6) in Table 2. A voltage is applied as shown in the right column.

  As a result, the memory cells in the selected sector can be collectively erased while stably protecting the data in the memory cells in the non-selected sector.

<7> Seventh Example The overall configuration of the nonvolatile semiconductor memory device according to the seventh example is the same as the configuration shown in FIG. The write operation and read operation of the nonvolatile semiconductor memory device of the seventh example are the same as those of the first example.

  During the sector batch erase operation, the source decoder 102 applies -8V to the source line corresponding to the selected sector and -4V to the source line corresponding to the non-selected sector. For example, when sector SE1 is selected, -8V is applied to source line SL1, and -4V is applied to source line SL2.

  In this way, a voltage is applied to the memory cells in the selected sector as shown in the left column of (E7) in Table 2, and the memory cell in the unselected sector is applied to the right column of (E7) in Table 2. A voltage is applied as shown in FIG.

  As a result, the memory cells in the selected sector can be collectively erased while stably protecting the data in the memory cells in the non-selected sector.

<8> Advantages of each example In the first and second examples, the non-selected sector is disturbed to some extent from the substrate. However, the source decoder is not necessary and only one negative voltage generating circuit is required.

  In the third example, the disturbance that the non-selected sector receives from the substrate is small. Further, only one negative voltage generation circuit is required. Further, the junction breakdown voltage of the source at the time of erasing may be low. However, a source decoder is necessary.

  In the fourth and sixth examples, the disturbance that the unselected sector receives from the substrate is the smallest. Only one negative voltage generating circuit is required. However, a source decoder is required, and a source junction breakdown voltage of 8V is required.

  In the fifth and seventh examples, the disturbance that the non-selected sector receives from the substrate is slightly small, and the source junction breakdown voltage may be as small as ˜4V. However, a source decoder is necessary, and two negative voltage generation circuits are necessary.

  Next, a manufacturing method of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention shown in FIG. 66 (a) will be described with reference to FIGS. 77 to 95 are cross-sectional views showing the first to nineteenth steps in the method for manufacturing the nonvolatile semiconductor memory device having the above structure.

  First, referring to FIG. 77, underlying oxide film 202 having a thickness of about 300 mm is formed on the main surface of p-type silicon substrate 201. Then, a polycrystalline silicon film 203 having a thickness of about 500 mm is formed on the underlying oxide film 202 by using a CVD (Chemical Vapor Deposition) method. A silicon nitride film 204 of about 1000 mm is formed on the polycrystalline silicon film 203 by CVD or the like. Then, a resist 205 is formed on the silicon nitride film 204 so as to expose the element isolation region. By performing anisotropic etching using this resist 205 as a mask, the silicon nitride film 204 and the polycrystalline silicon film 203 on the element isolation region are etched.

  Thereafter, resist 205 is removed, and selective oxidation is performed using silicon nitride film 204 as a mask, thereby forming field oxide film 206 as shown in FIG. Then, the polycrystalline silicon film 203 and the silicon nitride film 204 are removed.

  Next, as shown in FIG. 79, phosphorus (P) is ion-implanted into the memory transistor region and a part of the peripheral circuit region under the conditions of 3.0 MeV and 2.0 × 10 13 cm −3. Then, impurity driving is performed for 1 hour at a temperature of 1000 ° C. Thereby, an n-well 207 is formed. Thereafter, as shown in FIG. 80, a resist 209 is formed so as to cover the memory cell formation region. Using this resist 209 as a mask, phosphorus (P) is 1.2 MeV, 1.0 × 10 13 cm −3. Ions are implanted under conditions, and phosphorus (P) is further implanted under conditions of 180 KeV and 3.5 × 10 12 cm −3. Thereby, an n-well (not shown) is formed in a part of the peripheral circuit region.

  Next, referring to FIG. 81, boron (B) is ion-implanted into the memory transistor region under the conditions of 700 KeV and 1.0 × 10 13 cm −3, and further boron under the conditions of 180 KeV and 3.5 × 10 12 cm −3. (B) is ion-implanted. Thereby, a p-well 210 is formed.

  Then, after the impurity implantation for controlling the threshold voltage of each memory transistor is performed, the entire surface of the main surface of the p-type silicon substrate 201 is subjected to a thermal oxidation process with reference to FIG. A thick gate insulating film 211 is formed. Then, a resist 212 is formed so as to cover a selection gate transistor (described later) formation region on the gate insulating film 211. Etching is performed by using the resist 212 as a mask to remove a portion of the gate insulating film 211 other than the selection gate transistor formation region.

  The resist 212 is removed, and a thermal oxidation process is performed again to form a gate insulating film 213 having a thickness of about 100 mm on the entire surface of the p-type silicon substrate 201. As a result, gate insulating films 211 and 213 having a film thickness of about 250 mm are formed in the select gate transistor formation region. Then, a first polycrystalline silicon film 214 is formed on the gate insulating films 211 and 213 to a thickness of about 1200 mm by using a CVD method or the like. Then, a resist 212a having a predetermined shape (in this case, a plurality of resist patterns are intermittently formed in a direction perpendicular to the paper surface) is deposited on the first polycrystalline silicon film thickness 214, and this resist 212a is deposited. Is used as a mask to etch the first polycrystalline silicon film 214.

  Thereafter, as shown in FIG. 84, a high-temperature oxide film having a thickness of about 100 mm is formed on the first polycrystalline silicon film 214 using the CVD method or the like, and the CVD method is formed on the high-temperature oxide film. A silicon nitride film is formed to a thickness of about 100 mm by using, for example, and a high-temperature oxide film having a thickness of about 150 mm is formed on the silicon nitride film using a CVD method. Thereby, an ONO film 215 is formed.

  Next, referring to FIG. 85, a polycrystalline silicon layer doped with impurities is formed on the above ONO film 215 by a CVD method to a thickness of about 1200 mm. Then, a tungsten silicide (WSi) layer is formed on the polycrystalline silicon layer by sputtering to a thickness of about 1200 mm. As a result, a conductive layer 216 serving as a control gate electrode is formed. A high-temperature oxide film 217 having a thickness of about 2000 mm is formed on the conductive layer 216 by CVD. Then, a resist 218 is formed on the high-temperature oxide film 217 located on the memory transistor region and the peripheral transistor formation region, and etching is performed using the resist 218 as a mask, thereby forming an electrode of a transistor used in the peripheral circuit. To do.

  Next, referring to FIG. 86, a resist 218a is intermittently formed on the high-temperature oxide film 217 in the lateral direction in FIG. Then, using this resist 218a as a mask, high temperature oxide film 217, conductive film 216, ONO film 215, and first polycrystalline silicon film 214 are etched. Thereby, floating gate electrode 219 and control gate electrode 220 are formed.

  Next, referring to FIG. 87 (a), a resist 221 is further applied onto the flash memory in the state shown in FIG. 86, and this resist 221 is patterned so as to expose a portion to be a source region of the memory transistor. To do. FIG. 87 (b) is a plan view showing a partial plan view of the flash memory in the state shown in FIG. 87 (a). And the cross section seen along the BB line in FIG. 87 (b) will be shown by FIG. 87 (a). The field oxide film 206 formed on the source region is removed by dry etching using the resist 221 patterned in this manner as a mask.

  Then, after removing the resists 218a and 211, a resist pattern 221a is formed so as to expose only the select gate transistor, as shown in FIG. Then, using this resist pattern 221a as a mask, phosphorus (P) is ion-implanted under the conditions of 60 KeV and 3.0 × 10 13 cm −3. Thereby, source / drain regions 223 and 224 of the select gate transistor are formed. Then, the resist 221a is removed.

  Thereafter, referring to FIG. 89, a resist pattern 221b is formed so as to cover the transistor to be the selection gate transistor and to expose other memory cells. Then, using this resist 221b as a mask, arsenic (As) is ion-implanted under the conditions of 35 KeV and 5.5 × 10 15 cm −3. As a result, the source / drain regions and the source line of the memory transistor are formed. Then, the resist 221b is removed.

  Next, referring to FIG. 90, a high temperature oxide film having a film thickness of about 2000 mm is formed in the memory transistor region by CVD. Then, the sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high temperature oxide film. Then, arsenic (As) is ion-implanted under the conditions of 35 KeV and 4.0 × 10 15 cm −3 using the sidewall 225 as a mask. Thereby, the source / drain regions of the peripheral transistors are formed.

  Thereafter, referring to FIG. 91, a silicon oxide film 226 made of a TEOS (Tetra ethyl ortho Silicate) film or the like is deposited in the memory transistor region. Then, the oxide film is sintered for about 30 minutes. Then, as shown in FIG. 92, sidewalls 225a are formed by anisotropically etching silicon oxide film 226. By forming the sidewall 225a, the source region in the memory cell is covered with the silicon oxide film.

  Next, referring to FIG. 93, a polycrystalline silicon layer having a thickness of about 2000 mm is formed by CVD or the like, and conductivity is imparted by introducing impurities into this polycrystalline silicon layer. A sub-bit line 227 is formed by applying a resist 228 having a predetermined shape on the polycrystalline silicon layer and patterning the resist 228 as a mask.

  Next, referring to FIG. 94, after removing the resist 228, a silicon oxide film 229 made of a TEOS film or the like is formed on the sub-bit line 227 using a CVD method. The thickness of this silicon oxide film 229 is about 1500 mm. A silicon nitride film 230 with a thickness of about 500 mm is formed on the silicon oxide film 229 by using a CVD method or the like. Then, a silicon oxide film 231 made of a BPTEOS film having a film thickness of about 10,000 mm is formed on the silicon nitride film 230 by using a CVD method or the like. Thereafter, reflow is performed by heat treatment at about 850 ° C., and the BPTEOS film is etched back by about 5,000 mm by HF or the like. Then, a resist 232 having a predetermined shape is deposited on the silicon oxide film 231, and the silicon oxide films 229 and 231 and the silicon nitride film 230 are etched using the resist 232 as a mask. As a result, a contact hole 233a for connecting the sub bit line 227 and the main bit line 233 formed in a later process is formed.

  Next, referring to FIG. 95, tungsten plug 233b is formed in contact hole 233a using the CVD method and the etch back method. Then, an aluminum alloy layer having a thickness of about 5000 mm is formed on the tungsten plug 233b and the silicon oxide film 231 by sputtering or the like. Then, a resist 232a having a predetermined shape is deposited on the aluminum alloy layer, and the main bit line 233 is formed by patterning the aluminum alloy layer using the resist 232a as a mask. Thereafter, resist 232a is removed, and an interlayer insulating layer is formed on the main bit line. Then, an aluminum wiring layer is further formed on the interlayer insulating layer through a through hole forming step. Thereby, the nonvolatile semiconductor device shown in FIG. 66A is formed.

  A method for manufacturing the select gate contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will now be described with reference to FIGS. 96 to 100 are views showing cross sections taken along line CC in FIG.

  First, referring to FIG. 96, up to high-temperature oxide film 217 is formed through the same steps as in the above-described embodiment. Speaking of the selection gate transistor, it is connected to an aluminum wiring layer 238 formed thereabove via a contact hole. Therefore, a contact hole is formed in the connection portion. This contact portion is shown in FIG. Referring to FIG. 97, after depositing high temperature oxide film 217 as described above, etching is performed to remove high temperature oxide film 217 and conductive film 216 in the contact portion. Thereby, a contact hole 251 is formed.

  Referring to FIG. 98, an oxide film made of a TEOS film or the like is formed on the entire surface by using the CVD method or the like, and then anisotropic etching is performed to leave silicon oxide film 235 on the side wall of contact hole 251. Let At this time, since the ONO film 215 on the first polycrystalline silicon film 214 is also etched when the silicon oxide film 235 serving as the sidewall is formed, the first polycrystalline silicon film 214 is exposed.

  Next, referring to FIG. 99, poly pad 236 made of polycrystalline silicon is formed in contact hole 251, and sub-bit line 227 is formed at the same time. Thereafter, as shown in FIG. 100, an interlayer insulating film 245 is formed on the poly pad 236 and the sub bit line 227. A contact hole 251a is formed in a portion of the interlayer insulating film 245 located on the poly pad 236, and an aluminum electrode 237 is formed in the contact hole 251a. At this time, the main bit line 233 is formed simultaneously with the formation of the aluminum electrode 237. Thus, by forming the polypad 236 in the contact portion of the select gate transistor, the aspect ratio in the contact portion can be reduced, and the margin of pattern superposition can be increased.

  After the main bit line 233 and the aluminum electrode 237 are formed as described above, the nonvolatile semiconductor memory device is formed through the same process as in the above embodiment.

  A method for manufacturing the source line contact portion of the fourteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will now be described with reference to FIGS. FIG. 101 is a plan view showing a part of the nonvolatile semiconductor memory device shown in FIG. First, referring to FIG. 101, source line 223a is formed in source line contact portion 239 to have a width W1 larger than width W2 of source line 223a other than the contact portion. On the other hand, reflecting this shape, the width of the drain region is as small as W4 in the portion sandwiched between the source line contact portions 239, and has a width of W3 larger than W4 in the other portions. Using this difference in width, in this embodiment, the contact hole formation in the source line contact portion 239 and the contact hole formation in the drain contact portion 240 are to be performed simultaneously.

  Details will be described below with reference to FIGS. FIG. 102I is a diagram illustrating a cross section viewed along line DD in FIG. FIG. 102 (II) is a view showing a cross section taken along line EE in FIG. The same applies to FIGS. 103 to 106.

  First, referring to FIG. 102, a floating gate electrode 219, an ONO film 215, a control gate electrode 220, and a high-temperature oxide film 217 in the memory transistor are formed through the same process as in the above embodiment. At this time, in FIG. (I), the interval between the source portions is wider than the interval between the drain portions, and in FIG. (II), the interval between the drain portions is wider than the interval between the source portions.

  In the memory transistor in such a state, as shown in FIG. 103, a sidewall 225 is formed by the same method as in the above embodiment. Then, an oxide film 226 is further deposited on the sidewall 225 as shown in FIG.

  Thereafter, referring to FIG. 105I, anisotropic etching is performed on oxide film 226 to form contact hole 239a in source line contact portion 239. At this time, since the width of the source portion is wider than the width of the drain portion, the source portion is more easily etched, and the contact hole 239a is formed in the source portion, but the contact hole is not formed in the drain portion.

  On the other hand, referring to FIG. 105 (II), in this case, since the drain portion is wider than the source portion, the contact hole is formed only in the drain portion in the same way as in the above case. 240a is formed. In this way, after contact holes 239a and 240a are formed simultaneously, as shown in FIG. 106, sub-bit line 227 and wiring layer 241 made of polycrystalline silicon or the like are formed on the memory transistor. .

  As described above, according to this embodiment, the source line contact portion 239 and the drain contact portion 240 are simultaneously formed by utilizing the difference in the width of the source line 223a and the difference in the width of the drain portion. Is possible. Further, since a mask for forming each contact hole is not required, the process can be simplified and the manufacturing cost can be reduced.

(15) Fifteenth Embodiment Next, a fifteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG. FIG. 107 (a) is a cross-sectional view of the nonvolatile semiconductor memory device after formation of the sub bit line 227 when no dummy memory transistor is formed, and FIG. 107 (b) is a case where a dummy memory transistor is formed, that is, a nonvolatile memory transistor. It is sectional drawing of 15th Example of an electroconductive semiconductor memory device. First, referring to FIG. 107A, one end of sub-bit line 227 is cut on select gate transistor 234 and the other end is cut on field oxide film 206. In such a case, there is a problem that the field oxide film 206 is reduced during contact etching or the like, and the isolation characteristics deteriorate.

  Therefore, in the fifteenth embodiment, a dummy memory transistor 242b is formed on the field oxide film 206. Thereby, it is possible to reduce the step in the sub bit line 227 without degrading the isolation breakdown voltage between elements. Thus, in the fifteenth embodiment, the dummy memory transistor 242b is formed on the field oxide film 206. However, as shown in FIG. 107B, the dummy memory transistor 242a is formed on the p-type silicon substrate 201. You may form directly. As a result, electrons can be injected between the dummy gate 242 and the p-type silicon substrate 201 using FN tunneling. As a result, a field shield effect can be provided. It is also possible to inject electrons into the dummy gate 242 by channel hot electrons using the sub bit line 227 sandwiching the dummy memory transistor 242a. Even in this case, the same field shield effect as in the above case can be expected.

(16) Sixteenth Embodiment Next, a sixteenth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIGS. FIG. 108 is a partial cross sectional view of the memory transistor portion of the nonvolatile semiconductor memory device according to the sixteenth embodiment of the invention. 109 is a cross-sectional view corresponding to a cross section taken along line FF in FIG. 69. 110 to 119 are cross-sectional views showing the tenth to nineteenth steps of the manufacturing process of the nonvolatile semiconductor memory device in this example.

  In each of the foregoing embodiments, the field oxide film 206 located on the source region is removed by etching, and in this state, arsenic (As) or the like is implanted into the source region to form the source line. However, in this case, the following problems can be considered. Immediately below the field oxide film 206, boron (B) or the like is implanted through the field oxide film 206 in advance in order to improve isolation characteristics between elements. Therefore, when arsenic (As) for source line formation is implanted after etching the field oxide film 206 as described above, boron (B) implanted through the field oxide film 206 and the source There will be a portion where arsenic (As) implanted for line formation overlaps. Thereby, in the overlapping portion, the carrier concentration is canceled out, and there is a problem that the source breakdown voltage is lowered.

  Therefore, in this embodiment, in order to form the source line, a wiring layer made of polycrystalline silicon or the like into which impurities are introduced so as to electrically connect the source regions is formed. Thereby, the wiring layer can be formed on the field oxide film 206, so that it is not necessary to remove the field oxide film 206 located on the source line formation region. As a result, the overlapping of the impurity regions as described above can be eliminated, and the source breakdown voltage can be prevented from being lowered.

  Hereinafter, the present embodiment will be described more specifically with reference to the drawings. First, referring to FIG. 108, a feature of the present embodiment is that a wiring layer 262 that electrically connects source regions 223 scattered in the word line direction is formed. Other structures are the same as those in the above embodiments. In this case, the wiring layer 262 is formed of polycrystalline silicon or the like.

  The wiring layer 262 connects the source regions 223 separated by the field oxide film 206 to each other. Therefore, as shown in FIG. 109, wiring layer 262 extends on source region 223 and field oxide film 206 sandwiched between source regions 223. In this manner, by providing the wiring layer 262, each source region 223 can be electrically connected, so that it is not necessary to remove a part of the field oxide film 206 by etching. Thereby, as described above, it is possible to prevent the source line breakdown voltage from being lowered.

  Next, a method for manufacturing a nonvolatile semiconductor memory device having the above structure will be described with reference to FIGS. First, referring to FIG. 110, high temperature oxide film 217, conductive film 216, ONO film 215, and first polycrystalline silicon film 214 are etched through the same process as in the second embodiment. Thereby, floating gate electrode 219 and control gate electrode 220 are formed. Then, the resist 218a is removed.

  Next, as shown in FIG. 111, a resist pattern 221a is formed so as to expose only the select gate transistor. Then, using this resist pattern 221a as a mask, phosphorus (P) is ion-implanted under the conditions of 60 KeV and 3.0 × 10 13 cm −2. Thereby, source / drain regions 223 and 224 of the select gate transistor are formed. Thereafter, the resist 221a is removed.

  Next, referring to FIG. 112, a resist pattern 221b is formed so as to cover the transistor to be the selection gate transistor and expose the other memory transistors. Then, using this resist pattern 221b as a mask, arsenic (As) is ion-implanted under the conditions of 35 KeV and 5.5 × 10 15 cm −2. Thereby, the source / drain regions of the memory transistor are formed. Thereafter, the resist 221b is removed.

  Next, referring to FIG. 113, a high temperature oxide film having a film thickness of about 2000 mm is formed in the memory transistor region by CVD. Then, the sidewall 225 is formed on the side wall of the select gate transistor or the side wall of the memory transistor by anisotropically etching the high temperature oxide film. Then, arsenic (As) is ion-implanted under the conditions of 35 KeV and 4.0 × 10 15 cm −2 using the sidewall 225 as a mask. Thus, the source / drain regions, the source region 223, and the drain region 224 of the peripheral transistor are formed.

  Next, referring to FIG. 114, a silicon oxide film 226 made of a TEOS (Tetra ethyl Ortho Silicate) film or the like is deposited in the memory transistor region. Then, the oxide film is sintered for about 30 minutes. Thereafter, a resist pattern 261 is formed so as to expose the silicon oxide film 226 located on the source region 223. Then, a part of the silicon oxide film 226 and the side wall 225 located on the source region 223 is etched using the resist pattern 261 as a mask. Thereby, as shown in FIG. 115, contact hole 268 is formed in a region located on source region 223. Then, the resist 261 is removed.

  Next, referring to FIG. 116, a polycrystalline silicon layer 262 is formed on the inner surface of contact hole 268 and on silicon oxide film 226 by CVD or the like. Then, an oxide film 263 is formed on the polycrystalline silicon layer 262 by using a CVD method or the like. Then, a resist pattern 264 is formed on the oxide film 263 located on the source region 223. At this time, the end portions of the resist pattern 264 are positioned on the end portions of the floating gate electrode 219 and the control gate electrode 220 located on the source side. Thereby, the distance between polycrystalline silicon layer 262 and sub-bit line 227 can be increased, and a desired breakdown voltage between polycrystalline silicon layer 262 and sub-bit line 227 can be ensured. Further, the breakdown voltage between the control gate electrode 220 and the polycrystalline silicon layer 262 can be set to a desired value.

  Then, as shown in FIG. 117, oxide film 263 and polycrystalline silicon layer 262 are etched using resist pattern 264 as a mask. As a result, a wiring layer 262 that electrically connects the source regions 223 scattered in the word line direction is formed.

  Next, referring to FIG. 118, after removing resist 264, oxide film 265 is formed on oxide films 226 and 263 by CVD or the like. Then, a resist pattern 266 is formed so as to expose the oxide film 265 located on the drain diffusion region 224. Then, using this resist pattern 266 as a mask, the oxide films 265 and 226 located on the drain region 224 are removed by etching. Thereby, a part of the drain region 224 is exposed.

  Then, referring to FIG. 119, after removing the resist 266, a polycrystalline silicon layer having a thickness of about 2000 mm is formed by CVD or the like, and impurities are introduced into this polycrystalline silicon layer. This provides conductivity. A sub-bit line 227 is formed by applying a resist 228 having a predetermined shape on the polycrystalline silicon layer and patterning the polycrystalline silicon layer using the resist 228 as a mask. Thereafter, a nonvolatile semiconductor memory device is formed through the same process as in the second embodiment.

(17) Seventeenth Embodiment Next, a seventeenth embodiment according to the present invention will be described with reference to FIGS. 120 to 125 and FIGS. 156 to 159. FIG. 120 is a partial cross-sectional view of the nonvolatile semiconductor memory device in the seventeenth embodiment according to the invention. 121 to 125 are views showing the first to fifth steps of the manufacturing process of the nonvolatile semiconductor memory device shown in FIG. FIG. 156 is a plan view showing a conventional structure of the nonvolatile semiconductor memory device in the seventeenth embodiment and a cross-sectional view taken along line BB in FIG. . FIG. 157 is a partial cross-sectional view for describing the write operation of the conventional nonvolatile semiconductor memory device shown in FIG. FIG. 158 is a partial cross-sectional view for describing an erasing operation of the nonvolatile semiconductor memory device shown in FIG. FIG. 159 is a partial cross-sectional view for illustrating problems in the conventional nonvolatile semiconductor memory device shown in FIG.

  First, the conventional structure of the nonvolatile semiconductor memory device according to the seventeenth embodiment of the present invention will be described with reference to FIGS. Referring to FIGS. 156 (a) and 156 (b), this type of nonvolatile semiconductor memory device is generally called a nonvolatile semiconductor memory device having a virtual ground array memory cell array (Virtual Ground Array). It is.

  Referring to FIG. 156 (b), n-type high-concentration impurity regions 302a, 302b, 302c, and 302d functioning as bit lines are formed on the main surface of p-type semiconductor substrate 301 at substantially parallel intervals. Has been. Floating gates 305 a, 305 b, and 305 are formed through an insulating film 304 on regions sandwiched between these high concentration impurity regions 302 a to 302 d. An insulating film 306 is formed so as to cover these floating gates 305a, 305b, and 305. A control gate 307 is formed on the surface of the insulating film 306. Referring to FIG. 156 (a), control gate 307 extends on a plurality of floating gates 305 and is substantially orthogonal to high concentration impurity regions 302a to 302d.

  Next, a conventional operation of the conventional nonvolatile semiconductor memory device having the above structure will be described with reference to FIGS. 157 and 158. First, the writing operation will be described. Referring to FIGS. 156 (a) and 157, description will be given of the case where writing is performed to floating gate 305b. When writing to the floating gate 305b, a voltage of about 12V is applied to the control gate 307 extending over the floating gate 305b, and a voltage of about 5V is applied to the high concentration impurity region 302b functioning as a bit line. Is done.

  At this time, the high concentration impurity region 302a is kept in a floating state. Impurity region 302c is held at the ground potential. Accordingly, a current flows from the high concentration impurity region 302b to the high concentration impurity region 302c. At this time, electrons are injected into the floating gate 305b. Thereby, writing to floating gate 305b is performed.

  Next, the erase operation will be described. When erasing information written in each floating gate 305, 305a, 305b, each control gate 307 is held at the ground potential, and a voltage of about 10 V is applied to each high-concentration impurity region 302a-302d. As a result, electrons are simultaneously extracted from the floating gates 305, 305a, and 305b, and the written information is erased. This is shown in FIG.

  When a non-volatile semiconductor memory device having the above-described configuration and having a conventional virtual ground configuration memory cell array is operated according to the present invention, the following problems are encountered. Will occur. The problem will be described with reference to FIG.

  When a conventional non-volatile semiconductor memory device having a memory cell array with a virtual ground configuration is operated according to the present invention, a problem occurs when the write operation according to the present invention is performed. . Referring to FIG. 159, for example, in order to write information to floating gate 305a by performing the writing operation according to the present invention, a voltage of about −8 V, for example, is applied to selected control gate 307. . At this time, a voltage of about 5 V is applied to the selected bit line, in this case, the high concentration impurity region 302b functioning as the bit line. The unselected bit lines, in this case, the high concentration impurity regions 302a, 302c, and 302d are held at the ground potential.

  Accordingly, as indicated by an arrow in FIG. 159, electrons are extracted from the floating gate 305a, and at the same time, electrons are extracted from the floating gate 305b adjacent to the floating gate 305a. This is because one end portion of the high concentration impurity region 302b partially overlaps the floating gate 305a and the other end portion partially overlaps the floating gate 305b.

  In this way, the high concentration impurity region 302b, the floating gate 305a, and the floating gate 305b are formed in a positional relationship such that they partially overlap, and in the overlapping portion, the floating gates 305a and 305b are caused by the FN phenomenon. The electrons will be pulled out from. That is, information is written in both floating gates 305a and 305b. As a result, a problem of causing a malfunction of the nonvolatile semiconductor memory device occurs.

  The nonvolatile semiconductor memory device in the present embodiment is devised to solve the above problems. Hereinafter, the structure and operation of the nonvolatile semiconductor memory device in this example will be described with reference to FIGS.

  Referring to FIG. 120, in the nonvolatile semiconductor memory device having the memory cell array of the virtual ground configuration in this embodiment, one end of high concentration impurity regions 302a, 302b, 302c, 302d functioning as bit lines is floating. It is located under the gate 305 and the other end is formed so as not to be located under the adjacent floating gate 305. The concentration of the high concentration impurity regions 302a, 302b, 302c, and 302d is preferably 1020 / cm3 or more.

  More specifically, referring to FIG. 120, one end of high-concentration impurity region 302b is located below floating gate 305a, but floating gate 305b adjacent to floating gate 305a does not overlap impurity region 302b. So that it is offset. Other structures are almost the same as the conventional structure shown in FIG. 156 (b).

  In this way, by forming the end portion of the high concentration impurity region 302b so as not to overlap with the adjacent floating gate 305b, for example, when performing the write operation according to the present invention on the floating gate 305a, the adjacent floating gate 305b. It is possible to avoid a situation in which electrons are extracted from 305b. This makes it possible to write information more reliably.

  Next, a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment having the structure shown in FIG. 120 will be described with reference to FIGS. First, referring to FIGS. 121A and 121B, an insulating film 304 having a thickness of about 100 mm is formed on the main surface of p-type semiconductor substrate 301. Then, a first polycrystalline silicon layer 305c having a thickness of about 1000 mm is deposited on the insulating film 304 by using a CVD method or the like.

  A resist 308 having a desired film thickness is applied on the first polycrystalline silicon 305c. The resist 308 is patterned into a predetermined shape. Using this patterned resist 308 as a mask, the first polycrystalline silicon layer 305c is patterned by etching.

  Next, referring to FIG. 122A, after patterning the first polycrystalline silicon layer 305c, using the resist 308 as a mask, an n-type impurity such as arsenic (As) is p-type semiconductor substrate. Ions are implanted into the main surface of 301. At this time, the impurity implantation angle is inclined by a predetermined angle θ. Thus, high-concentration impurity regions 302 a to 302 d are formed on the main surface of p-type semiconductor substrate 301 by shadowing effect by resist 308 so that only one of adjacent floating gates has its end portion partially overlapped. It becomes possible.

  The value of the tilt angle θ is preferably about 7 °. In this way, arsenic (As) is ion-implanted at an angle of θ with respect to the vertical direction, whereby one of the adjacent first polycrystalline silicon layers 305c patterned in accordance with the resist 308 is selected. High-concentration impurity regions 302a to 302d are formed which overlap with the first polycrystalline silicon layer 305c but are offset from the other first polycrystalline silicon layer 305c. A state of viewing this state in a plan view is shown in FIG. 122 (b).

  Next, referring to FIG. 123, after removing resist 308, oxide film 309 is formed so as to cover first polycrystalline silicon layer 305c by CVD or the like. Then, the oxide film 309 is buried between the first polycrystalline silicon layers 305c by etching back the oxide film 309.

  Next, referring to FIG. 124, an insulating film 306 is formed on oxide film 309 and first polycrystalline silicon layer 305c using the CVD method or the like. On the insulating film 306, a second polycrystalline silicon layer 307a having a predetermined thickness is deposited by CVD or the like. Thereafter, referring to FIG. 125A, a resist 310 is applied on the second polycrystalline silicon layer 307a, and this resist 310 is patterned into a predetermined shape. In this case, referring to FIG. 125B, the resist 310 is patterned in a direction substantially orthogonal to the high concentration impurity regions 302a to 302d. Etching using the resist 310 thus patterned as a mask forms a control gate 307, floating gates 305a, 305b, and 305, and an insulating film 306, as shown in FIG. Thereafter, the resist 310 is removed. Through the above steps, the nonvolatile semiconductor memory device shown in FIG. 120 is completed.

  Next, another aspect of the seventeenth embodiment shown in FIG. 120 will be described with reference to FIG. In the nonvolatile semiconductor memory device shown in FIG. 120, only high-concentration impurity regions 302a to 302d are formed. However, in this embodiment, n-type high-concentration impurity regions 302a to 302d involved in the write operation are formed by using the same method as that in the seventeenth embodiment, and the n-type low-concentration impurity region is further formed. 303 is formed. By providing the low concentration impurity region 303 in this manner, it is possible to improve the operation characteristics of the nonvolatile semiconductor memory device. The low concentration impurity region 303 is formed by ion-implanting n-type impurities such as arsenic (As) into the main surface of the semiconductor substrate 301 at the same implantation angle as in the conventional example.

  As an example of the implantation conditions, arsenic (As) in an amount of 10 11 / cm 2 or more is implanted to form the low concentration impurity region 303. As a result, the concentration of the low concentration impurity region 303 to be formed has a concentration of 10 16 / cm 3 or more. At this time, when the high concentration impurity regions 302a to 302d are formed, the amount of arsenic (As) implanted is preferably 10 15 / cm 2 or more. As a result, the concentration of the high concentration impurity regions 302a to 302d becomes 1020 / cm3 or more.

  The present invention will now be summarized with reference to FIG. FIG. 127 is a schematic diagram showing an essential configuration of the nonvolatile semiconductor memory device according to the present invention. Referring to FIG. 127, impurity regions 402a and 402b are formed on the main surface of semiconductor substrate 401 at intervals. An insulating film 403 is formed on the channel region 409 between the impurity regions 402a and 402b. A floating gate 404 is formed on the insulating film 403. This floating gate 404 serves as an electron storage means. A word line 406 is formed on the floating gate 404 via an insulating film 405. An interlayer insulating film 407 is formed on the word line 406, and a bit line 408 is formed on the interlayer insulating film 407. The bit line 408 is electrically connected to the impurity region 402a through a contact hole 410 provided in the interlayer insulating film 407.

  In the nonvolatile semiconductor memory device having the above configuration, a characteristic operation according to the present invention is performed. First, in the characteristic operation of the nonvolatile semiconductor memory device according to the present invention, the initial state is the erased state. That is, the state in which electrons are accumulated in the floating gate 404 is an erased state (initial state). As a method for accumulating electrons in the floating gate 404, first, the bit line 408 is held in a floating state, and a voltage of about −10 V, for example, is applied to the semiconductor substrate 401. At this time, a voltage of about 10 V is applied to the word line 406. As a result, electrons can be injected into the floating gate 404 by the FN phenomenon (channel FN) over the entire surface of the channel region 409. At this time, the threshold voltage Vth (E) of the memory transistor in the erased state is higher than the voltage VRead applied to the word line 406 during reading.

  As described above, after the erase state is first set, information is written by extracting electrons from a predetermined memory transistor. At the time of writing, a voltage of about 5 V is applied to the bit line 408. At this time, the semiconductor substrate 401 is kept at the ground potential. Then, a voltage of about −10 V is applied to the word line 406. As a result, electrons are extracted from the floating gate 404. At this time, extraction of electrons is performed by the FN phenomenon in the overlapping portion between the floating gate 404 and the impurity region 402a. As a result, the threshold voltage Vth (p) of the memory transistor after writing becomes a value smaller than the voltage VRead applied to the word line 406 at the time of reading.

  As described above, in the operation of the nonvolatile semiconductor memory device according to the present invention, the state in which electrons are injected into the memory transistor is the erased state, and electrons are emitted from a predetermined memory transistor among all the memory transistors. Information is written by pulling out. In each of the above embodiments, the case where the present invention is applied to a nonvolatile semiconductor memory device has been described. However, the present invention can also be applied to semiconductor memory devices other than nonvolatile semiconductor memory devices.

It is a figure which shows the relationship between the program and erasing operation | movement in 1st-11th Example, and a threshold voltage compared with a prior art example. It is a figure which shows the erase state and program state in the 1st-11th Example compared with a prior art example. It is a figure which shows the threshold voltage at the time of the batch erase in the 1st-11th Example. It is a figure which shows the change of the threshold voltage by the batch erase operation in the 1st-11th Example. 1 is a block diagram showing an overall configuration of a flash memory according to a first embodiment. FIG. It is a figure which shows the voltage application conditions to the memory cell at the time of the program in the 1st Example, and the erase. It is a figure which shows the voltage application conditions at the time of the collective erase operation in 1st Example, a program operation, and a read-out operation. It is a flowchart for demonstrating the rewriting operation | movement in a 1st Example. It is a figure which shows the voltage application conditions to the memory cell at the time of the program in the 2nd Example, and the erase. It is a figure which shows the voltage application conditions at the time of the batch erase operation in 2nd Example, a program operation, and a read-out operation. It is a block diagram which shows the whole structure of the flash memory by a 3rd Example. FIG. 12 is a block diagram showing a configuration of an X decoder included in the flash memory of FIG. 11. It is a figure which shows the voltage application conditions to the memory cell at the time of the program in the 3rd Example, and the erase. It is a figure which shows the voltage application conditions at the time of the batch erase operation in 3rd Example, a program operation, and a read-out operation. It is a figure which shows the voltage application conditions at the time of page batch erasing operation in 4th Example, program operation, and read-out operation. It is a flowchart for demonstrating the rewriting operation | movement in a 4th Example. It is a figure which shows the voltage application conditions at the time of page collective erasing operation in 5th Example, program operation, and read-out operation. It is a block diagram which shows the whole structure of the flash memory by a 6th Example. FIG. 19 is a circuit diagram showing a detailed configuration of a memory array and related parts included in the flash memory of FIG. 18. It is a figure which shows the voltage application conditions to the memory cell at the time of the program in the 6th Example, and the erase. It is a figure which shows the voltage application conditions at the time of the sector batch erase operation in the 6th Example, a program operation, and a read-out operation. It is a flowchart for demonstrating the program operation | movement and verify operation | movement in a 6th Example. It is sectional drawing which shows the structure of the memory cell used for the flash memory by the 6th Example. FIG. 10 is a structural diagram of two adjacent memory cells in a sixth embodiment. It is a layout diagram of the memory cell array in the sixth embodiment. FIG. 7 is a circuit diagram showing voltages applied in the memory cell array of the embodiment of FIG. 6. It is a circuit diagram which shows the equivalent circuit of a high voltage generation circuit. It is sectional drawing which shows the structure of a part of high voltage generation circuit used for the flash memory by a 6th Example. It is sectional drawing for demonstrating that a parasitic transistor exists in the structure shown in FIG. FIG. 30 is an equivalent circuit diagram of a circuit configured by the parasitic transistor shown in FIG. 29. It is sectional drawing which shows another structure of the high voltage generation circuit used for the flash memory by the 6th Example. It is a circuit diagram which shows the equivalent circuit of a negative voltage generation circuit. It is sectional drawing which shows the structure of a part of negative voltage generation circuit used for the flash memory by a 6th Example. It is a circuit diagram which shows the detailed structure of the memory array contained in the flash memory by 7th Example, and the part relevant to it. It is a figure which shows the change of the voltage of the main bit line at the time of the program in a 7th Example. It is a block diagram which shows the structure of the whole flash memory by an 8th Example. FIG. 37 is a circuit diagram showing a detailed configuration of a memory array and related parts included in the flash memory of FIG. 36; It is a figure for demonstrating the state of the memory cell at the time of erasing in case there is no gate bird's beak. It is a figure which shows the voltage application conditions to the memory cell of the selection sector at the time of erasure | erasing in case there is no gate bird's beak, and the memory cell of a non-selection sector. It is a figure which shows the voltage application conditions at the time of the sector batch erase operation in case there is no gate bird's beak. It is a circuit diagram which shows the structure of the source decoder used when there is no gate bird's beak. It is a figure which shows the voltage of each part of the source decoder of FIG. It is a figure for demonstrating the state of the memory cell at the time of erasure | erasing in case there exists a gate bird's beak. It is a figure which shows the voltage application conditions to the memory cell of the selection sector at the time of erasure | erasing in case there exists a gate bird's beak and the memory cell of a non-selection sector. It is a figure which shows the voltage application conditions at the time of the sector batch erase operation in case there is a gate bird's beak. It is a circuit diagram which shows the structure of the source decoder used when there exists a gate bird's beak. FIG. 47 is a diagram illustrating voltages at various parts of the source decoder in FIG. 46. It is a figure which shows the voltage application conditions to the memory cell of the selection sector at the time of erasure | elimination when a well electric potential is low, and the memory cell of a non-selection sector. It is a figure which shows the voltage application condition at the time of sector collective erasure | elimination operation | movement when a well electric potential is low. It is a circuit diagram which shows the structure of the source decoder used when a well electric potential is low. It is a figure which shows the voltage of each part of the source decoder of FIG. It is a block diagram which shows the structure of the whole flash memory by a 9th Example. FIG. 53 is a circuit diagram showing a detailed configuration of a memory array and related parts included in the flash memory of FIG. 52. It is a figure which shows the voltage application conditions at the time of the sector batch erase operation in a 9th Example. FIG. 53 is a circuit diagram showing a configuration of a select gate decoder and a source switch included in the flash memory of FIG. 52. FIG. 56 is a diagram showing voltages of respective parts of the select gate decoder and the source switch of FIG. 55. It is a flowchart for demonstrating the program operation | movement in the flash memory by a 10th Example. It is a flowchart for demonstrating the program operation | movement in the flash memory by 11th Example. It is a block diagram which shows the structure of the whole flash memory by a 12th Example. FIG. 60 is a circuit diagram of the memory cell array and its peripheral circuits shown in FIG. 59. FIG. 61 is a layout diagram on a semiconductor substrate showing a connection mode between a word line shown in FIG. 60 and an output line of a local decoder. FIG. 61 is a cross-sectional structure diagram showing separation between two memory cells 1491 and 1492 shown in FIG. 60. FIG. 61 is a cross-sectional structure diagram in the case where isolation between two memory cells 1491 and 1492 shown in FIG. 60 is performed by a field shield transistor. It is a circuit diagram of a word line voltage control circuit and a predecoder used in the twelfth embodiment. It is a partial cross-sectional view of a memory transistor portion of a thirteenth embodiment of a nonvolatile semiconductor memory device according to the present invention. (A) is a partial cross-sectional view of a memory transistor portion of a fourteenth embodiment of a nonvolatile semiconductor memory device according to the present invention, and (b) is an equivalent circuit diagram thereof. It is sectional structure drawing of the memory transistor of 14th Example of the non-volatile semiconductor memory device according to this invention. FIG. 66 is a plan view up to a state where a control gate having the structure shown in FIG. FIG. 66 is a plan view showing a state where sub-bit lines having the structure shown in FIG. FIG. 66 is a plan view up to the state where the main bit line having the structure shown in FIG. FIG. 66 is a plan view up to a state where aluminum wiring having the structure shown in FIG. It is a block diagram which shows the 1st example of the whole structure of 14th Example of the non-volatile semiconductor memory device according to this invention. It is a block diagram which shows the 2nd example of the whole structure of 14th Example of the non-volatile semiconductor memory device according to this invention. It is a block diagram which shows the 3rd example of the whole structure of 14th Example of the non-volatile semiconductor memory device according to this invention. It is a block diagram which shows the 4th example of the whole structure of 14th Example of the non-volatile semiconductor memory device according to this invention. It is a block diagram which shows the 5th example of the whole structure of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 1st process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 3rd process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 5th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 6th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 7th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 8th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 9th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 10th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 11th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 12th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 13th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 14th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 15th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 16th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 17th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 18th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 19th process of the manufacturing method of the memory transistor part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 1st process of the manufacturing method of the select gate contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the select gate contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 3rd process of the manufacturing method of the select gate contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the select gate contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 5th process of the manufacturing method of the select gate contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is a top view of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 1st process of the manufacturing method of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 3rd process of the manufacturing method of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 5th process of the manufacturing method of the source line contact part of 14th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing of the memory transistor part of 15th Example of the non-volatile semiconductor memory device according to this invention. It is a cross-sectional view of a part of a memory transistor portion of a sixteenth embodiment of a nonvolatile semiconductor memory device according to the present invention. It is a figure which shows the cross section corresponding to the cross section seen along the FF line in FIG. It is sectional drawing which shows the 10th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 11th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 12th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 13th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 14th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 15th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 16th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 17th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 18th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is sectional drawing which shows the 19th process of the manufacturing method of the memory transistor part of 16th Example of the non-volatile semiconductor memory device according to this invention. It is a fragmentary sectional view showing a seventeenth embodiment of a nonvolatile semiconductor memory device according to the present invention. (A) is a fragmentary sectional view showing the 1st process of the manufacturing method of the memory transistor part of the 17th Example of the nonvolatile semiconductor memory device according to this invention. (B) is a plan view in this case. (A) is a fragmentary sectional view showing the 2nd process of the manufacturing method of the memory transistor part of the 17th Example of the non-volatile semiconductor memory device according to this invention. (B) is a plan view in this case. It is a fragmentary sectional view which shows the 3rd process of the manufacturing method of the memory transistor part of the 17th Example of the non-volatile semiconductor memory device according to this invention. It is a fragmentary sectional view which shows the 4th process of the manufacturing method of the memory transistor part of 17th Example of the non-volatile semiconductor memory device according to this invention. (A) is a fragmentary sectional view showing the 5th process of the manufacturing method of the memory transistor part of 17th Example of the nonvolatile semiconductor memory device according to this invention. (B) is a plan view in this case. It is a fragmentary sectional view which shows the other aspect of the 17th Example of the non-volatile semiconductor memory device according to this invention. It is a schematic diagram for explaining a characteristic operation of the nonvolatile semiconductor memory device according to the present invention. It is sectional drawing which shows the structure of the stack gate type memory cell used for the conventional flash memory. It is a figure which shows the relationship between program and erase | elimination operation | movement and threshold voltage in the conventional flash memory. It is a figure which shows the voltage application conditions to the memory cell at the time of the program in the conventional flash memory, and the erase. It is a block diagram which shows the whole structure of the conventional flash memory. FIG. 132 is a block diagram showing a configuration of an X decoder included in the flash memory of FIG. 131. It is a figure which shows the voltage application conditions at the time of program operation in the conventional flash memory. 6 is a flowchart for explaining a pre-erase write operation in a conventional flash memory. 10 is a flowchart for explaining a batch erase operation in a conventional flash memory. It is a figure which shows the voltage application conditions at the time of the batch erase operation | movement in the conventional flash memory. It is a figure which shows the voltage application conditions at the time of read-out operation in the conventional flash memory. It is a figure which shows the voltage of each line at the time of the program operation | movement in the conventional flash memory, the erase operation, and the read-out operation. It is a figure which shows the threshold voltage at the time of performing batch erase operation | movement, without performing the write operation before erase in the conventional flash memory. It is a figure which shows the threshold voltage at the time of performing batch erase operation after performing write operation before erase in the conventional flash memory. It is a flowchart for demonstrating the rewriting operation | movement in the conventional flash memory. It is a figure which shows the change of the threshold voltage at the time of performing batch erase operation in the conventional flash memory. It is sectional drawing which shows the structure of the memory cell containing a selection transistor. It is a figure for demonstrating the disturbance at the time of a sector division. FIG. 6 is a layout diagram of a memory cell array of a conventional flash memory having a main bit line and a sub bit line. It is a structural diagram of a memory cell of a conventional flash memory. It is a circuit diagram which shows the voltage given in the memory cell array of the conventional flash memory. 1 is a block diagram showing a general configuration of a flash memory. 3 is an equivalent circuit diagram showing a schematic configuration of a NOR type memory cell matrix. FIG. FIG. 3 is a cross-sectional structure diagram of a NOR type memory transistor. It is a schematic plan view showing a NOR type planar arrangement. It is a fragmentary sectional view which follows the AA line of FIG. 2 is an equivalent circuit diagram of a part of a memory cell matrix of a NAND flash memory. FIG. 2 is a cross-sectional view of a part of a memory cell matrix of a NAND flash memory. FIG. 1 is a cross-sectional structure diagram of a memory transistor of a NAND flash memory. (A) is a top view which shows schematic structure of the non-volatile semiconductor memory device which has a memory cell array of the conventional virtual ground structure. (B) is sectional drawing seen along the BB line in (a). FIG. 156 is a diagram for explaining a conventional writing operation of the nonvolatile semiconductor memory device shown in FIG. 156. FIG. 156 is a diagram for explaining a conventional erase operation of the nonvolatile semiconductor memory device shown in FIG. 156. FIG. 156 is a diagram for explaining a problem in the case where the conventional nonvolatile semiconductor memory device shown in FIG. 156 is operated according to the present invention.

Explanation of symbols

80 Semiconductor substrate 81 n well region 82 p well region 83a, b source / drain region 84a, b source region 85a, b drain region 86 select gate transistor 87a, b, c, d memory transistor 88 control gate 89 floating gate 90 subbit Line 91a, b Branch line 92 Main bit line 93 MOS transistor 1001 P-type semiconductor substrate 1002 Drain 1003 Source 1004 Insulating film 1005 Floating gate 1006 Control gate 1008 P-well 1010, 10a Memory array 1020 Address buffer 1030 X decoder 1040 Y decoder 1050 Y gate 1060 Sense amplifier 1070 Data input / output buffer 1080 Write circuit 1090 Vpp / Vcc off Circuit 100 Verify voltage generation circuit 1110 Source control circuit 1120 Control signal buffer 1130 Control circuit 1140 Negative voltage control circuit 1210, 1220 High voltage generation circuit 1230, 1240 Negative voltage generation circuit 1250 Well potential generation circuit 1260 Select gate decoder 1270 Source decoder 1281, 1282 Source switch BL1, BL2, BL3 Bit lines WL0, WL1, WL2, WL3 Word lines M11, M12, M13, M21, M22, M23, M31, M32, M33
Memory cell SL source line SE1, SE2 Sector MB0, MB1 Main bit line SB01, SB02, SB11, SB12 Sub bit line SL1, SL2 Source line SGL1, SGL2 Select gate line .

Claims (3)

A source and a drain formed at a predetermined interval on the main surface of the semiconductor substrate;
A floating gate formed between the source and the drain via a first insulating film on the main surface of the semiconductor substrate; and a control gate formed via a second insulating film on the floating gate; A memory cell including:
A well formed on the main surface of the semiconductor substrate so as to cover the source and drain of the plurality of memory cells,
When erasing data of the plurality of memory cells, electrons are transferred between the well and the floating gate through the first insulating film,
A nonvolatile semiconductor memory device in which electrons are transferred between the drain and the floating gate through the first insulating film when data is written to a selected memory cell among the plurality of memory cells. A source formed at a predetermined interval on a main surface of a semiconductor substrate having a first conductivity type high concentration impurity region and the first conductivity type low concentration impurity region formed so as to cover the high concentration impurity region; Drain,
A floating gate formed on the semiconductor substrate between the source and the drain;
An insulating film formed between the semiconductor substrate and the floating gate and injecting electrons from the semiconductor substrate to the floating gate by FN tunneling;
A memory cell including a control gate formed through an insulating film on the floating gate;
A word line connected to the control gate;
A non-volatile semiconductor memory device comprising a bit line connected to the drain. A source and drain of a first conductivity type formed at a predetermined interval on the main surface of the semiconductor substrate, and a floating formed between the source and drain via a first insulating film on the main surface of the semiconductor substrate A memory cell including a gate and a control gate formed through a second insulating film on the floating gate;
A word line connected to the control gate;
A bit line connected to the drain via a MIS transistor of a first conductivity type;
A well of a second conductivity type different from the first conductivity type formed on the main surface of the semiconductor substrate on which the memory cell and the MIS transistor are disposed;
A non-volatile semiconductor memory device comprising: a first conductivity type well formed to surround the second conductivity type well.

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