JP2001015615A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent erroneous writing to a nonselected memory cell when data '1' is written to a selected memory cell by reducing the actual threshold voltage. SOLUTION: The nonvolatile semiconductor storage device comprises bit lines BL1 and BL2, a source line SL, and a plurality of serially connected nonvolatile transistors each having a floating gate and a control gate. The device also includes NAND memory cells Mi, j each inserted between the corresponding one of the lines BL1 and BL2 and the line SL, selecting gates S1, 1 and S1, 2 each connected between the corresponding NAND memory cell and the corresponding one of the lines BL1 and BL2, selecting gates S2, 1 and S2, 2 each connected between the corresponding NAND memory cell and the line SL, and resistors R inserted on the way along paths each formed of the NAND memory cells and selecting gates arranged between the corresponding one of the lines BL1 and BL2 and the line SL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile transistor having a stacked gate structure including a floating gate and a control gate. In particular, a plurality of nonvolatile transistors are connected in series to form a NAND memory cell. The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile semiconductor memory (EEPROM) which can be electrically rewritten and which can be highly integrated.
, N in which a plurality of nonvolatile transistors are connected in series
An AND type EEPROM is known. One cell transistor has a stack gate structure in which a floating gate and a control gate are stacked on a semiconductor substrate via an insulating film. A plurality of cell transistors are connected in series so that adjacent ones share a source / drain, and this is connected as a unit to a bit line to form a NAND.
A type memory cell is configured. Such NAND type memory cells are arranged in a matrix to form a memory cell array.

[0005] NANDs arranged in the column direction of a memory cell array
The drain on one side of the memory cell is connected to a bit line (data line) via one or two or more select gates.
The other end is similarly connected to a common source line serving as a source line (reference potential wiring) via one or more select gates. The control gate and the select gate of the cell transistor extend in the row direction of the memory cell array, and are commonly connected as a control gate line (word line) and a select gate line, respectively.

FIG. 11 is a plan view showing a part of a conventional NAND type EEPROM in which a plurality of nonvolatile transistors are connected in series to form a NAND type memory cell array. In the vertical direction (column direction) in the figure, a plurality of bit lines BLj (this example illustrates a case where j = 1 to 3)
Are extended so as to be parallel to each other. Further, a source line SL is arranged to extend in the left-right direction (row direction) in the drawing. Then, the plurality of bit lines BL
A plurality of memory cells Mi, j (in this example, i = in this example) composed of nonvolatile transistors connected in series between j and the source line SL via a bit line contact BC and a source line contact SC, respectively. 1 to 16 and j = 1 to 3) are inserted.

Each of the memory cells Mi, j comprises a floating gate (a hatched area in the figure) for storing signal charges and a control gate for controlling the amount of signal charges in the floating gate. It has a stacked gate structure, and floating gates are separated from adjacent bit lines. The control gate of each of the memory cells Mi, j is integrally formed as a plurality of word lines WLi (i = 1 to 16) arranged so as to intersect with each of the bit lines BLj. One memory cell Mi, j is connected to each word line WLi for each bit line BLj.

In order to selectively control data write and read operations for these memory cell groups, N
Two select gates Sk, j (k = 1, 2; j = 1 to 3) formed of switching transistors are connected to both ends of the plurality of memory cells Mi, j connected in an AND type.
That is, the plurality of memory cells M are in contact with the bit line contact BC and the source line contact SC, respectively.
Two select gates Sk, j are arranged at both ends of i, j. The plurality of memory cells Mi, j and the two select gates Sk, j are formed in an element region extending in the bit line direction such that adjacent ones share a source / drain diffusion layer. .

The switching control of each of the selection gates Sk, j is performed by two selection gate lines SG1, SG2. It is to be noted that not only one select gate is necessarily arranged on each of the bit line side and the source line side, but also
In some cases, a plurality of select gates may be arranged in series.

FIG. 12 is a cross-sectional view when a plurality of NAND type memory cells Mi, j and two select gates Sk, j are cut along the line AA parallel to the bit line direction in FIG. FIG. The plurality of memory cells Mi, j and the two select gates Sk, j are connected to a silicon substrate (P well).
The semiconductor device has an N-type diffusion region formed as a source / drain region 12. On the substrate between each pair of source / drain regions 12, a floating gate 14 made of, for example, amorphous silicon is formed via a first gate insulating film 13 made of a thin silicon oxide film. Further, a control gate 16 composed of, for example, two layers of amorphous silicon and tungsten is formed on the floating gate 14 via a second gate insulating film 15. In the two selection gates Sk, j, the floating gate 14 and the control gate 16 are electrically connected.

An interlayer insulating film 18 is formed on the entire surface, and is electrically connected to a pair of source / drain regions 12 located at both ends of the NAND type memory cell in the interlayer insulating film 18. The formed bit line contact BC and source line contact SC are formed. Further, the bit line BL1 is connected to the bit line contact BC.

FIG. 13 is a sectional view showing a case where a plurality of memory cells Mi, j in FIG. 11 are cut along the line BB parallel to the word line direction. Note that, in FIG. 13, the same reference numerals are given to portions corresponding to FIG. 11 and FIG. The plurality of memory cells Mi, j are stored in STI (Shallow
They are separated from each other by an element isolation region 19 using a Trench Isolation technique.

Here, the floating gate 14 of each memory cell Mi, j is set in a floating state, and electrons are tunnel-injected from the N-type channel region into the floating gate 14 through the first gate insulating film 13. The writing of the memory cell is performed. At this time, a control voltage for controlling writing is applied to the control gate 16.

FIG. 14 shows the NAND type EEP shown in FIG.
FIG. 3 is an equivalent circuit diagram of a ROM.

Incidentally, the NAND type EEP as described above
In order to write data to a ROM, a self-boost writing method capable of writing at a lower voltage has been proposed and put to practical use. If this self-boost writing method is used, all transistors in a peripheral circuit such as a column decoder connected to a bit line can be operated using a Vcc system power supply voltage, for example, 3.3 V, so that the peripheral circuit is occupied. The area can be reduced,
The advantage that the chip area can be reduced is obtained.

FIG. 15A is a cross-sectional view showing one extracted memory cell, and FIG. 15B shows a voltage as shown in FIG. 15A applied to each part of the memory cell at the time of self-boost writing. It is a figure showing an equivalent circuit at the time of addition. FIG.
In the equivalent circuit of (b), the capacitance C1 is the sum of the parasitic capacitance existing between the channel region of the memory cell and the floating gate 14 and the parasitic capacitance existing between the floating gate 14 and the control gate 16. , The capacitance C2 is the sum of the parasitic capacitances existing between the substrate 11 and the source / drain regions 12, VCG is the control gate voltage, Vsub is the voltage applied to the substrate, and Vch is the voltage ( Channel voltage).

Next, a conventional self-boost write operation will be described with reference to a waveform diagram of FIG. here,
An example of binary data writing in which “1” or “0” data is written in one memory cell will be described.

Now, in FIG. 14, for example, the word line W
L1 and the selected word line WL1 and bit line BL
1, the memory cells M1, circled by a solid circle located at the intersection with
When "0" data is written in 1 (hereinafter, referred to as cell A), unselected memory cells M2,2 (hereinafter, cell B) encircled by a broken line located at the intersection of word line WL1 and bit line BL2. ), The word line WL2 and the bit line B
The problem of erroneous writing occurring in the non-selected memory cell M2,1 (hereinafter, referred to as cell C) surrounded by a dashed-line circle located at the intersection with L1 will be described. Note that the above two non-selected memory cells are shown only as examples, and the same problem as that of the cell B is caused by the problem that all cells located at the intersection of the selected word line WL1 with the “1” write bit line other than the bit line BL2. The same problem as the cell C also occurs in all the memory cells located at the intersections of the bit line BL1 and the unselected word lines. In addition,
In “1” writing, the erased state of the memory cell (state in which “0” writing is not performed) is maintained as it is.

Normally, when writing data to a plurality of memory cells, writing is performed sequentially from a cell far from the bit line to a cell near the bit line. In the case of random writing, cell writing is performed in an arbitrary order.

In the self-boost write operation, FIG.
As shown in (2), the voltage VSG2 of the selection gate line SG2 on the source line side is set to 0 V, and the selection gates S2,1, S2,2 are cut off.

Next, the voltage VBL1 of the bit line BL1 of the NAND memory cell to which the cell A to which "0" data is written is connected to 0V, and the NAND type memory to which the cell B to which "1" data is written is connected. Bit line B of the memory cell
The voltage VBL2 of L2 is connected to the select gate line SG1 on the drain side.
Voltage VSG1 is equal to or higher than the voltage VSG1, or is set to the voltage VBL2 such that the drain-side select gates S1, 2 are sufficiently cut off even if the voltage has a value lower than the voltage. . As a result, the drain-side selection gate S1,1 is turned on, and S1,2 is cut off, and writing is selected in each bit line BL1, BL2.

In this state, a transfer voltage Vpass (for example, 10 V) having a value that turns on the memory cell is applied to all the non-selected word lines WL2 to WL16 other than the selected word line in the selected block, and the selected word line is turned on. WL1 has a write pulse Vpp (for example, 20 V) higher than the transfer voltage Vpass.
give. As a result, all of the selected word lines WL1 to WL to which the transfer voltage Vpass and the write pulse Vpp have been applied.
All the memory cells connected to No. 16 are turned on, and a voltage of 0 V is transferred to each channel region of the NAND type memory cell connected to the bit line BL1 for writing “0”.

The bit line BL for writing "1"
2, the channel region of the NAND memory cell connected to the select gate S from the voltage VBL2 of the bit line BL2.
An initial voltage obtained by subtracting the threshold voltages 1 and 2 becomes floating while being transferred from the selection gates S1 and S2. At this time, 0 V or a voltage of a certain positive value for sufficiently cutting off the source-side select gates S2,1, S2,2 is applied to the source line SL.

As described above, since the write pulse voltage Vpp higher than the transfer voltage Vpass is applied to the selected word line WL1, "0" data is applied to the cell A connected to the bit line BL1 to which 0 V is applied. Is written.
That is, the capacitance C in the equivalent circuit shown in FIG.
1, the floating gate of cell A becomes 0
A voltage higher than V is set, whereby a tunnel current flows between the floating gate and the channel region, and electrons are injected from the channel region into the floating gate. Therefore,
The threshold voltage of the memory cell to which "0" has been written changes in the positive direction.

At this time, in the channel region of the cell B connected to the same selected word line WL1 as the cell A and to the bit line BL2 where "1" write is performed, the select gates S1, 2 are cut off. So it is floating. Then, in order to prevent “0” writing from being performed on the cell B, its channel voltage must be sufficiently high. That is, the channel voltage Vch must be set so that the change in the threshold voltage of the cell B due to the write pulse voltage Vpp is within an allowable range. In cell B, the smaller the difference between the write pulse voltage Vpp and the channel voltage Vch, the smaller the change in threshold voltage.

Therefore, the voltages VWL2 to VWL2 of the non-selected word lines
The transfer voltage Vpass of a value lower than the write pulse voltage Vpp is applied to VWL16 as described above, and each channel voltage Vch of the non-selected memory cells is increased from the initial voltage to a higher voltage by capacitive coupling. I have to.
Each channel voltage Vch increases as the value of the transfer voltage Vpass increases, so that the change in the threshold voltage of the cell B decreases as the value of the transfer voltage Vpass increases.

On the other hand, among the memory cells connected to the bit line BL1 to which 0 V is applied, the transfer voltage Vpass is also applied to the control gate of an unselected memory cell, for example, the cell C. Therefore, the change in the threshold voltage of the cell C is different from that of the cell B, and becomes larger as the value of the transfer voltage Vpass becomes larger.

As described above, when "0" data is written to the selected cell A, the non-selected cell B connected to the same word line as the selected memory cell and the non-selected cell B connected to a different word line from the selected memory cell are connected. Since the threshold voltages of the non-selected cells C change in the opposite directions with respect to the magnitude of the transfer voltage Vpass applied to each word line, the threshold values of the cells B and C are taken into consideration. The optimum value of the transfer voltage Vpass is determined so that both changes in the value voltage are small.

As described above, after the channel region of each memory cell connected to the bit line BL2 to which "1" data is applied is brought into a floating state, the voltage VWL2 of the word lines WL2 to WL16 is set. ~ VWL
If 16 is set to Vpass, the bit line BL2 and the word line WL2
WL16, the channel region and the source / drain region of the memory cell connected to each of the intersections have the transfer voltage V
The voltage is boosted (booted) by capacitive coupling corresponding to the rise to the pass.

The boosting operation at this time will be described with reference to FIG. Now, the state where the substrate is set to 0V (Vsu
b = 0 V), and when a voltage VCG (word line voltage) is applied to the control gate, the voltage VCG is applied to the channel region of the memory cell.
A voltage is generated in which CG is divided by the capacitors C1 and C2. This channel voltage Vch is expressed as follows.

Vch = {C1 / (C1 + C2)} VCG... 1 Here, C1 / (C1 + C2) is called a boot ratio.

When the transfer voltage Vpass is given as the voltage VCG, and the booted channel voltage Vch is a positive value, the floating gate of the unselected memory cell connected to the selected memory cell and the common word line is connected to the floating gate. Charge (electron) injection can be prevented.

Normally, the transfer voltage Vpass and the write pulse voltage Vpp are set to reduce the distribution of the threshold voltage of the selected memory cell to which "0" data is written and to avoid erroneous writing in the unselected memory cell. , Respectively the initial voltage,
The step voltage, the final voltage, the voltage pulse width and the like are applied using a step-up method that is optimized. In the case of the waveform diagram of FIG. 16, the initial voltage and the final voltage of the transfer voltage Vpass and the write pulse voltage Vpp are set to the same 0V.

On the other hand, the data written in the memory cells is erased by using either a batch erasing method for simultaneously erasing all the memory cells of the NAND type memory cells or a block erasing method for erasing data in byte units. Done.

That is, in the case of batch erasing, all word lines are set to 0 V, unselected bit lines and source lines are set in a floating state, and a high voltage, for example, a voltage of 20 V is applied to the silicon substrate (P well). As a result, the electrons accumulated in the floating gates of all the memory cells are released to the substrate, and the threshold voltage changes in the negative direction.

In the case of block erasure, all word lines in the selected block are set to 0 V, a high voltage, for example, 18 V is applied to the word lines of the non-selected blocks, and the non-selected bit lines and source lines are in a floating state. Then, a high voltage, for example, a voltage of 20 V is applied to the silicon substrate (P well).

Data is read from a word line to which a selected gate line and a non-selected memory cell are connected.
For example, 3.3 V is applied to turn on the selected gate and unselected memory cells, and 0 V is applied to the word line connected to the selected memory cell. At this time, the change of the bit line voltage due to the current flowing through the bit line is sensed by a sense amplifier (not shown), so that the data of “1” and “0” is determined.

[0036]

By the way, the NAND type E in the above-mentioned conventional self-boost writing method is used.
In EPROM, the structure and manufacturing process of a memory cell,
There are the following inconveniences related to the voltage applied to the channel region of the memory cell connected to the unselected bit line.

That is, as described with reference to the waveform diagram of FIG. 16, the channel region and the source / drain region of the memory cell connected to the bit line to which "1" data is written are brought into a floating state at the time of data writing. .
Thereafter, the voltage of the selected word line is set to Vpp, the voltage of the unselected word line is set to Vpass, and the channel voltage of the unselected memory cells in the floating state is booted to Vch.
At this time, the relationship between the channel voltage Vch and the voltage of each section is expressed by the following equation.

Vch = VSG−VSGth (Vchinit) + Cr1 (Vpass−Vpassth−Vchinit) + Cr2 (Vpp−Vpassth−Vchinit) − {Tpw / 16 (Cins + Cch)} × I 2 In the above two equations, VSG is This corresponds to VSG1 in FIG. 16, and is supplied with, for example, a power supply voltage Vcc. Also, V
SGth (Vchinit) is the threshold voltage of the select gate S1,2 on the drain side when the channel voltage is Vchinit;
Is the boot ratio of the channel of the memory cell to which the transfer voltage Vpass is applied, Cr2 is the boot ratio of the channel of the memory cell to which the write pulse voltage Vpp is applied, and Vpassth is the memory to which the transfer voltage Vpass is applied when the channel voltage is Vchinit. The voltage required for the cell to turn on, T
pw is the pulse width of the write pulse voltage Vpp, and Cins
Is the capacitance per memory cell, Cch is the capacitance of the depletion layer extending below the channel region, and I is the leakage current flowing from the channel region to the well or adjacent bit line.

As shown in the waveform diagram of FIG. 16, the write pulse voltage Vpp is applied as the voltage VWL1 of the selected word line, and the transfer voltage Vpass is applied as the voltages VWL2 to VWL16 of the unselected word lines. The channel voltage of the non-selected memory cell is booted to Vch, and erroneous writing can be prevented.

Here, the impurity concentration profile in the select gate and the memory cell and the silicon substrate (P well) for forming them, and the impurity concentration profile such as channel ion implantation introduced into the channel region of the select gate and the memory cell. , And the source of the select gate or memory cell /
Depending on various process conditions such as the impurity concentration profile of the drain region, the initial voltage Vchinit transferred from the bit line to the channel region decreases, the depletion layer capacitance below the channel region and other terminals to which 0V is applied and the channel region. The channel boot ratio (Cr1,
As a result, a sufficiently high channel voltage may not be obtained, and the threshold voltage of the memory cell connected to the non-selected bit line may change to cause erroneous writing.

The transfer voltage V for such erroneous writing
The relationship between the pass and the threshold voltage of the cell B in FIG. 14 for writing "1" data is shown in the characteristic diagram of FIG. In addition,
The vertical axis in the figure indicates the threshold voltage of the memory cell,
Vth0 is the threshold voltage of “0” data, Vth1 is the threshold voltage of “1” data, and the threshold voltage indicated by the dashed line in the drawing is the threshold voltage of “1” data and “0” data. It corresponds to the border.

If a write operation to the cell A is performed in a region where the voltage Vpass (or the write pulse voltage Vpp) is low, the channel voltage cannot be sufficiently increased in the cell B, and "0" as shown by a solid line. Writing is performed, and erroneous writing occurs in cell B. However, if the voltage Vpass (or the write pulse voltage Vpp) is made sufficiently high, the channel voltage of the cell B booted by the voltage Vpass (Vpp) becomes high, so that erroneous writing is avoided.

On the other hand, as for the cell C in FIG. 14, a voltage of 0 V is transferred to the channel region as described above.
By increasing the voltage Vpass applied to the control gate, FIG.
As shown by the broken line in FIG. 7, the threshold voltage increases, and erroneous writing occurs.

Therefore, in order to prevent erroneous writing in all the non-selected memory cells, the voltage Vpass (Vpp) is set so that both the solid line and the broken line in FIG. 17 are located below the dashed line.
You have to choose.

The change in the threshold voltage depends on the gate length of the memory cell, the wing width, the thickness of the tunnel oxide film (first gate insulating film 13 in FIGS. 12 and 13), the interpoly insulating film ( There is a tendency that the thickness of the second gate insulating film 15) in FIGS.
In particular, this is more likely to occur as the number of bits in the write selection block increases.

Furthermore, if the leakage current between the floating channel region or the source / drain region and the well or between the adjacent bit lines is large, the change in the threshold voltage is further increased. In addition, variations in the characteristics of the selection gate that transfers the bit line voltage to the channel region also have a significant effect. The change in the threshold voltage due to such erroneous writing tends to increase further as the miniaturization of elements progresses and the influence of the short channel effect cannot be ignored.

As described above, conventionally, there is a problem that the characteristics of the memory cell and the selection gate cause erroneous writing to the non-selected memory cell depending on the structure and the manufacturing process of the memory cell.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of reliably preventing erroneous writing to an unselected memory cell. is there.

[0049]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a plurality of serially connected nonvolatile transistors each having a bit line, a source line, and a floating gate and a control gate. A NAND memory cell inserted between the bit line and the source line; a first select gate connected between the NAND memory cell and the bit line; A second select gate connected between the second select gate and the source line;
The NAND type memory cell between the bit line and the source line, and a resistor inserted in the middle of a path formed by a first select gate and a second select gate.

Further, in the nonvolatile semiconductor memory device according to the first aspect, the resistor is provided at a source end and a drain end which are in contact with a channel region of each of the plurality of nonvolatile transistors.

Further, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, the resistor is provided at a source end and a drain end that are in contact with a channel region of each of the plurality of nonvolatile transistors. They have different impurity concentrations.

Further, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, the resistor is provided at a source end and a drain end which are in contact with a channel region of each of the plurality of nonvolatile transistors. No impurities have been introduced.

Further, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, the resistor is connected to the bit line and the first line.
And a diffusion region having an impurity concentration different from that of the source / drain diffusion region of the first selection gate.

Further, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, the resistor may be connected to the source line and the second line.
And a diffusion region having a different impurity concentration from the source / drain diffusion region of the second selection gate.

The nonvolatile semiconductor memory device according to the second invention is
A plurality of serially connected non-volatile transistors each having a bit line, a source line, and a floating gate and a control gate. When data is read, a first voltage is supplied to a selected control gate, and a non-selected Are supplied with a second voltage having a value higher than the first voltage, respectively, and a NAND memory cell inserted between the bit line and the source line, the NAND memory cell and the bit A first selection gate connected between the NAND-type memory cell and the source line, the third selection gate being connected to the third memory cell and being supplied with a third voltage higher than the first voltage and lower than the second voltage when reading data; And a second selection gate to which the third voltage is supplied when data is read.

[0056]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings with reference to the embodiments.

FIG. 1 shows a nonvolatile semiconductor memory device according to a first embodiment of the present invention.
It is a top view which extracts and shows a part of PROM. In the vertical direction (column direction) in the figure, a plurality of bit lines BLj (in this example, the case where j = 1 to 3 are illustrated) are extended so as to be parallel to each other. Further, a source line SL is arranged to extend in the left-right direction (row direction) in the drawing. A plurality of memory cells Mi, which are composed of nonvolatile transistors connected in series, are connected between the plurality of bit lines BLj and the source line SL via a bit line contact BC and a source line contact SC, respectively. j
(This example illustrates a case where i = 1 to 16 and j = 1 to 3).

Each of the memory cells Mi, j includes a floating gate for storing signal charges (a shaded area in the figure) and a control gate for controlling the amount of signal charges in the floating gate. It has a stacked gate structure, and floating gates are separated from adjacent bit lines. The control gate of each of the memory cells Mi, j is integrally formed as a plurality of word lines WLi (i = 1 to 16) arranged so as to intersect with each of the bit lines BLj. One memory cell Mi, j is connected to each word line WLi for each bit line BLj.

In order to selectively control data write and read operations for these memory cell groups, N
Two select gates Sk, j (k = 1, 2; j = 1 to 3) formed of switching transistors are connected to both ends of the plurality of memory cells Mi, j connected in an AND type.
That is, the plurality of memory cells M are in contact with the bit line contact BC and the source line contact SC, respectively.
Two select gates Sk, j are arranged at both ends of i, j. The plurality of memory cells Mi, j and the two select gates Sk, j are formed in an element region extending in the bit line direction such that adjacent ones share a source / drain diffusion layer. .

The switching control of each selection gate Sk, j is performed by two selection gate lines SG1 and SG2. It is to be noted that not only one select gate is necessarily arranged on each of the bit line side and the source line side, but also
In some cases, a plurality of select gates may be arranged in series.

In the case of this embodiment, no source / drain impurities are introduced into the source end and the drain end of each memory cell Mi, j which are in contact with the channel region. / Drain regions, each of which has a high resistance region UD sufficiently higher than the drain region. Similarly, no source / drain impurities are introduced into the source end and the drain end of each select gate Sk, j which are in contact with the channel region, and the resistance is made sufficiently higher than the source / drain regions. High resistance regions UD are provided.

FIG. 2 shows three memory cells M in FIG.
FIG. 3 shows a cross-sectional view when i and j are cut along the line AA parallel to the bit line direction. The dimensions in the drawings do not necessarily reflect actual dimensions. The three memory cells Mi, j have N-type diffusion regions formed in a P-type silicon substrate (P well) 11 as source / drain regions 12. On the substrate between each pair of source / drain regions 12, a floating gate 14 made of, for example, amorphous silicon is formed via a first gate insulating film 13 made of a thin silicon oxide film. Further, a control gate 16 made of, for example, two layers of amorphous silicon and tungsten is provided on the floating gate 14 through a second gate insulating film 15 having a thickness larger than that of the first gate insulating film 13. Are formed.

A sidewall insulating film 17 is formed around the stacked gate including the floating gate 14 and the control gate 16.
Are deposited at a uniform thickness. And the above source /
The drain region 12 is filled with, for example, 5 × 10 ¹² (cm ² ) of N-type ions with respect to the substrate 11 by an ion implantation method using the stacked gate with the side wall insulating film 17 formed therearound as a mask. It is formed by introducing a dose and then performing diffusion.

Here, since the side wall insulating film 17 is formed on the stacked gate, source / drain impurities are respectively introduced into the source end and the drain end in contact with the channel region of each memory cell Mi, j. A region not formed is formed, and this region becomes the high resistance region UD.

In FIG. 1, a cross-sectional view of a plurality of memory cells Mi, j cut along the line BB parallel to the word line direction is the same as that of FIG. .

Here, the floating gate 14 of each memory cell Mi, j is brought into a floating state, and electrons are tunnel-injected from the N-type channel region into the floating gate 13 through the first gate insulating film 13 to thereby store the memory. Cell writing is performed. At this time, a control voltage for controlling writing is applied to the control gate.

FIG. 3 shows the NAND type EEPROM shown in FIG.
It is an equivalent circuit diagram of M. This equivalent circuit differs from the equivalent circuit of the conventional EEPROM shown in FIG. 14 in that the high resistance region UD is provided on the source / drain region side of a plurality of memory cells Mi, j and select gates Sk, j. High resistances R are inserted in series.

Next, for example, a word line WL1 is selected, and "0" data is stored in a memory cell M1,1 (cell A) surrounded by a solid line located at the intersection of the selected word line WL1 and the bit line BL1. The operation for writing will be described. In addition,
The unselected memory cells M2,2 surrounded by a broken line circle located at the intersection of the word line WL1 and the bit line BL2 are referred to as a cell B, and are surrounded by a broken line located at the intersection of the word line WL2 and the bit line BL1. The unselected memory cell M2,1 is referred to as a cell C.

Here, an example of binary data writing in which "1" or "0" data is written into one memory cell as in the prior art will be described. However, in the case of writing multi-level data, normally, “1” data is “0” data (threshold voltage is negative), and “0” data is “1”, “2”,
The data may be replaced with “3” data (threshold voltages are positive and each data is separated into a certain threshold voltage range). Even a multi-valued memory having no such threshold distribution can operate similarly if the threshold voltages are separated into a plurality.

The operation will be described with reference to FIG.
The description will be made with reference to the waveform chart of FIG.

First, the voltage VSG2 of the selection gate line SG2 on the source line side is set to 0 V, and the selection gates S2,1, S2,2 are cut off.

Next, the voltage VBL1 of the bit line BL1 of the NAND memory cell to which the cell A to which "0" data is to be written is connected is set to 0 V, and the NAND type memory to which the cell B to which "1" data is to be written is connected. Bit line B of the memory cell
The voltage VBL2 of L2 is connected to the select gate line SG1 on the drain side.
Voltage VSG1 is equal to or higher than the voltage VSG1, or is set to the voltage VBL2 such that the drain-side select gates S1, 2 are sufficiently cut off even if the voltage has a value lower than the voltage. . As a result, the drain-side selection gate S1,1 is turned on, and S1,2 is cut off, and writing is selected in each bit line BL1, BL2.

In this state, a transfer voltage Vpass (for example, 10 V) having a value that turns on the memory cell is applied to all the non-selected word lines WL2 to WL16 other than the selected word line in the selected block, and the selected word line is turned on. WL1 has a write pulse Vpp (for example, 20 V) higher than the transfer voltage Vpass.
give. As a result, all of the selected word lines WL1 to WL to which the transfer voltage Vpass and the write pulse Vpp have been applied.
All the memory cells connected to No. 16 are turned on, and a voltage of 0 V is transferred to each channel region of the NAND type memory cell connected to the bit line BL1 for writing “0”.

The bit line BL for writing "1"
2, the channel region of the NAND memory cell connected to the select gate S from the voltage VBL2 of the bit line BL2.
A certain initial voltage, which is obtained by subtracting the threshold voltages of 1, 2 from the selection gate S1, 2, becomes floating. At this time, 0 V or a voltage of a certain positive value for sufficiently cutting off the source-side select gates S2,1, S2,2 is applied to the source line SL.

Here, in order to prevent "0" writing from being performed on the cell B, the channel voltage of the cell B must be sufficiently increased. That is, it is necessary to set the channel voltage Vch of the cell B so that the change in the threshold voltage of the cell B due to the write pulse voltage Vpp is within an allowable range. In the cell B, the write pulse voltage Vpp applied to the control gate and the channel voltage ch
Is smaller, the change in the threshold voltage is smaller.

In the EEPROM according to this embodiment,
A plurality of memory cells MM are provided between a bit line and a source line.
Since each high resistance R is inserted in series with each source / drain region of i and j, the cell current flowing through the cell B is limited by the presence of these high resistances R.

FIG. 4A shows the cell current (logIcell) with respect to the control gate voltage (Vg) of each memory cell MMi, j.
FIG. 4 is a characteristic diagram showing a change in the characteristic. Normally, NAND type EEP
In the ROM, the value of the cell current flowing through the memory cell when reading "0" data is about 0.5 .mu.A. In the EEPROM according to this embodiment, the current flowing through the cell is determined by the presence of the high resistance R, so that the cell current is saturated at about 0.5 μA. On the other hand, in the conventional cell, when the value of the control gate voltage becomes large, 0.5 μA
Go beyond.

Normally, as shown in FIG. 4A, the threshold value (current definition) for reading “0” data is higher than the threshold value for strong inversion (strong inversion threshold value). Here, when the present invention is compared with the prior art, the high resistance R
Is present, the threshold value of "0" data is larger in the present invention than in the related art, even if the strong inversion threshold value is the same. In FIG. 4A, point a is the threshold value of "0" data of the conventional cell, and point b is "0" of the present invention.
This is the data threshold.

Next, for example, as shown in FIG.
The threshold value of the “0” data (the value of the control gate voltage Vg when a cell current of 0.5 μA flows) is adjusted to 1 V.
Consider a so-called verify operation. Note that FIG.
FIG. 4B is obtained by shifting the characteristics of the present invention to the left in the drawing so that the positions of the points a and b coincide in FIG. 4A.

As shown in FIG. 4B, the strong inversion threshold value of the cell of the present invention is smaller than that of the conventional cell even if the same threshold value at the time of reading "0" of 1 V is provided.

Incidentally, erroneous writing at the time of writing "1" data largely depends on the value of Vpassth in the above two equations. In the present invention, as described above, the strong inversion threshold value is smaller than that of the related art, and as a result, the value of Vpassth is substantially reduced, so that the channel voltage Vch can be increased. That is, the threshold voltage at the time of data reading can be high and the threshold voltage at the time of writing can be low, so that erroneous writing as in the related art can be significantly improved.

FIG. 5 is a characteristic diagram showing the relationship between the transfer voltage Vpass (or the write pulse voltage Vpp) and the threshold voltage of the memory cell for writing "1" data. As in FIG. 17, the vertical axis in the figure indicates the threshold voltage of the memory cell, Vth0 is the threshold voltage of "0" data, and Vth1 is the threshold voltage of "1" data. The threshold voltage indicated by a dashed line in the drawing corresponds to the boundary between “1” data and “0” data.

As described above, since the threshold voltage at the time of data writing can be lowered, even if the writing operation to the selected memory cell is performed in a region where the control gate voltage is low, the same word line as that of the selected memory cell is used. The channel voltage can be sufficiently increased in the non-selected memory cell connected to the memory cell, and "0" writing is performed as shown by the solid line, thereby preventing erroneous writing in the non-selected memory cell (cell B). be able to.

FIG. 6 is a plan view showing a part of a NAND type EEPROM according to the second embodiment of the present invention.

The EEPR of the first embodiment shown in FIG.
In the OM, no source / drain impurities are introduced into the source end and the drain end contacting the channel region of each memory cell Mi, j and the source end and the drain end contacting the channel region of each select gate Sk, j. By providing the high resistance region UD, the high resistance R is dispersedly formed.

However, in this embodiment, each bit line contact BC and each selection gate S1,1, S1,2, S1,3 are selected.
By forming a high-resistance region HR with a low impurity concentration (a region with fine dots in the figure) in a part of the N-type source / drain region between the... As shown, each bit line contact BC and each select gate S
A high resistance R is formed between 1,1, S1,2, S1,3,.

FIG. 8A is a graph showing the relationship between the drain voltage (Vd) and the cell current (Iceell) of each memory cell in the second embodiment in comparison with the prior art and the present invention. FIG. In the case of the present invention, since the voltage drop occurs in the high resistance R, the slope becomes gentler than in the related art. This inclination is determined by the resistance value in the high resistance region HR in FIG. 6, and the resistance value is further determined by the concentration of the impurity introduced into the high resistance region HR.
Generally, for example, 5 ×
An impurity (for example, phosphorus) is introduced at a dose of about 10 ¹³ (cm ² ), but the impurity is introduced into the high resistance region HR at a dose of about 5 × 10 ¹² (cm ² ), which is one digit lower than that. be introduced. This dose is determined, for example, as follows.

FIG. 8B is a characteristic diagram showing the relationship between the control gate voltage (Vg) and the cell current (logIceell) in each memory cell. In the high current region, the resistance component is dominant, and the value of the high resistance R is set to Ice when Vg changes by 1V.
ell is set to a value that changes by two digits, for example.

Also in this embodiment, since the threshold voltage at the time of data writing can be lowered, even if the writing operation to the selected memory cell is performed in a region where the control gate voltage is low, the selected memory cell In an unselected memory cell connected to the same word line as above, the channel voltage can be sufficiently increased, and erroneous writing in the unselected memory cell can be prevented.

In this embodiment, a part of the N-type source / drain region between each bit line contact BC and each select gate S1,1, S1,2, S1,3. By forming the high resistance region HR having a low
As shown in the equivalent circuit diagram of FIG.
, A high resistance R is formed between each of the selection gates S1,1, S1,2, S1,3,..., And each of the source line contacts SC and each of the selection gates S2,1, S2,2, S2,3. Are formed in a part of the N-type source / drain regions between the source line contacts SC and the select gates S2,1, S2,2, S2,3. High resistance R between
May be formed.

FIG. 9 is a sectional view showing a part of a NAND type EEPROM according to the third embodiment of the present invention.

The EEPR of the first embodiment shown in FIG.
In the OM, by providing the high resistance region UD, the high resistance R
Had formed. However, in this embodiment, the high resistance R is formed by making the height (contact length) of the conductive material forming the bit line contact BC higher than in the prior art.

That is, FIG. 9A shows a conventional EEPRO.
FIG. 4 is a cross-sectional view showing an extracted portion of an M bit line contact BC. A bit line contact portion 21 made of, for example, phosphorus-doped amorphous silicon is connected to a source / drain region 12. The height (contact length) of the bit line contact portion 21 is, for example, 1 μm.

On the other hand, FIG. 9B shows the third embodiment of the present invention.
FIG. 13 is a cross-sectional view extracting and showing a portion of a bit line contact BC of the EEPROM according to the embodiment. In this case, the height (contact length) of the bit line contact portion 21 is set to, for example, 2 μm, which is twice the conventional height.

As described above, by making the height (contact length) of the bit line contact portion 21 higher than in the prior art, a plurality of N lines are formed between the bit line BL and the source line SL.
A high resistance is substantially inserted in the middle of the path formed by the AND type memory cell and the two select gates.

Also in this embodiment, since the threshold voltage at the time of data writing can be lowered, even if the writing operation to the selected memory cell is performed in the region where the control gate voltage is low, the selected memory cell In a non-selected memory cell connected to the same word line as above, the channel voltage can be sufficiently increased, and erroneous writing in the non-selected memory cell can be prevented.

Next, a fourth embodiment of the present invention will be described.

In each of the first to third embodiments, a high resistance is inserted between the bit line and the source line to prevent erroneous writing in an unselected memory cell. Was.

On the other hand, in the fourth embodiment,
By setting the gate voltage of the selection gate lower than the voltage of the control gate of the memory cell, the same effect as in the case where a high resistance is formed can be obtained.

That is, FIG. 10A shows a conventional EEPR
It is an equivalent circuit diagram at the time of data reading in OM. As shown, the control gate (word line) of the selected memory cell
Is applied to the control gate of the other unselected memory cells and the power supply voltage of 3.3 V is applied to the gates (selection gate lines) of the two selection gates.

On the other hand, FIG. 10B is an equivalent circuit diagram at the time of data reading in the EEPROM in the case of the present invention, wherein 0 V is applied to the control gate (word line) of the selected memory cell, and A power supply voltage of 3.3 V is applied to the control gates of the non-selected memory cells. Further, a voltage lower than 3.3 V, for example, 2. 5 is applied.

As described above, by applying a voltage lower than the voltage applied to the control gate of the non-selected memory cell to the selection gate, the cell current decreases as in the case where the high resistance is inserted, and Thus, the difference between the threshold value at the time of reading “0” data and the strong inversion threshold value can be increased.

[0103]

As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory device capable of reliably preventing erroneous writing to unselected memory cells.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a NAND type EEPROM of the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the NAND-type EEPROM shown in FIG.

FIG. 4 is a characteristic diagram showing a change in cell current with respect to a control gate voltage of each memory cell in FIG. 1;

FIG. 5 is a characteristic diagram showing a relationship between a transfer voltage Vpass (or a write pulse voltage Vpp) and a threshold voltage of a memory cell in which “1” data is written.

FIG. 6 shows a NAND type E according to a second embodiment of the present invention;
FIG. 2 is a plan view of an EPROM.

FIG. 7 is an equivalent circuit diagram of the NAND-type EEPROM shown in FIG. 6;

FIG. 8 is a characteristic diagram showing the relationship between the drain voltage and the cell current in each memory cell in the second embodiment in comparison with the conventional and the present invention, and the control gate in each memory cell in the second embodiment; FIG. 4 is a characteristic diagram showing a relationship between voltage and cell current.

FIG. 9 shows a NAND type E according to a third embodiment of the present invention.
Sectional drawing which shows EPROM compared with the conventional.

FIG. 10 is an equivalent circuit diagram showing a NAND-type EEPROM according to a fourth embodiment of the present invention in comparison with the related art.

FIG. 11 is a plan view of a conventional NAND EEPROM.

FIG. 12 is a sectional view taken along the line AA in FIG. 11;

FIG. 13 is a sectional view taken along the line BB in FIG. 11;

FIG. 14 shows the conventional NAND type EEPROM shown in FIG.
FIG.

15 is a sectional view of one memory cell in FIG. 11 and an equivalent circuit diagram thereof.

FIG. 16 is a waveform diagram for explaining a self-boost write operation in the conventional NAND type EEPROM of FIG. 11 and the NAND type EEPROM of the present invention.

FIG. 17 shows transfer voltage Vpass and “1” related to erroneous writing.
FIG. 15 is a characteristic diagram showing the relationship between the threshold voltage of the cell B in FIG. 14 where data is written.

[Explanation of symbols]

 BLj: Bit line, SL: Source line, BC: Bit line contact, SC: Source line contact, Mi, j: Memory cell, WLi: Word line, Sk, j: Select gate, SG1, SG2: Select gate line, UD ... High resistance region, R: High resistance, HR: High resistance region 11: P-type silicon substrate (P well), 12: Source / drain region, 13: First gate insulating film, 14: Floating gate, 15 ... Second gate insulating film, 16: control gate, 17: sidewall insulating film, 21: bit line contact portion.

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5B025 AA01 AC01 AE08 5F001 AA01 AB08 AB09 AD05 AD12 AD18 AD41 AD53 AE02 AF06 5F083 EP02 EP23 EP33 EP34 EP61 EP76 ER03 ER09 ER21 GA15 LA12 LA16 LA20 NA01

Claims (7)

[Claims] 1. A NAND type transistor comprising: a bit line; a source line; and a plurality of serially connected non-volatile transistors each having a floating gate and a control gate, and inserted between the bit line and the source line. A memory cell; a first select gate connected between the NAND type memory cell and the bit line; a second select gate connected between the NAND type memory cell and the source line; A nonvolatile memory comprising a NAND memory cell between the bit line and the source line, and a resistor inserted in the middle of a path formed by a first select gate and a second select gate. Semiconductor storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said resistor is provided at a source end and a drain end that are in contact with a channel region of each of said plurality of nonvolatile transistors. 3. The semiconductor device according to claim 1, wherein the resistor is provided at a source end and a drain end in contact with a channel region of each of the plurality of nonvolatile transistors, and has a different impurity concentration from the source / drain. 2. The nonvolatile semiconductor memory device according to 1. 4. The semiconductor device according to claim 1, wherein the resistance is provided at a source end and a drain end which are in contact with a channel region of each of the plurality of nonvolatile transistors, and each of the resistances is not doped with a source / drain impurity. Item 2. The nonvolatile semiconductor memory device according to item 1. 5. The resistor is provided between the bit line and the first selection gate, and is formed of a diffusion region having an impurity concentration different from that of a source / drain diffusion region of the first selection gate. The nonvolatile semiconductor memory device according to claim 1, wherein: 6. The resistor is provided between the source line and the second selection gate, and includes a diffusion region having an impurity concentration different from that of a source / drain diffusion region of the second selection gate. The nonvolatile semiconductor memory device according to claim 1, wherein: 7. A nonvolatile memory device comprising: a plurality of nonvolatile transistors connected in series having a bit line, a source line, and a floating gate and a control gate, and a first voltage is applied to a selected control gate when data is read. A second memory cell that is supplied to the non-selected control gates and that is supplied with a second voltage higher than the first voltage, and that is inserted between the bit line and the source line; A first selection gate connected between a memory cell and the bit line, to which a third voltage higher than the first voltage and lower than the second voltage is supplied when data is read; And a second selection gate connected between the first and second source lines and supplied with the third voltage at the time of reading data.