JP2005311564A - Jitter generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a jitter generation circuit that does not require an analog circuit, reduces circuit size, and can reduce power consumption. <P>SOLUTION: The jitter generation circuit comprises signal wiring P1 to which a clock signal, where a jitter component is added, is transmitted; an input buffer 10 provided at the input side of the signal wiring P1; an output buffer 30 provided at the output side of the signal wiring P1; signal wiring P2 closely arranged to the signal wiring P1; and a jitter generation signal output section 20 for inputting a jitter generation signal in synchronization with the clock signal inputted to the signal wiring P1 to the signal wiring P2. As the jitter generation signal, for example a pseudo random bit string signal is used. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a jitter generation circuit that fluctuates the rising and falling timings of a clock signal or a data signal.

  In recent years, cases where a giga-band high-speed interface circuit is mounted on an LSI are rapidly increasing. Along with this, testing for jitter that has not been considered as important in interface circuits at relatively low data transmission rates has become indispensable. These interface circuits are mainly serial transmissions including a serializer / deserializer (SERDES) circuit. The jitter of a reference clock signal used for this and the recovery clock signal of a CDR (clock recovery) system are It is a very important factor that determines the accuracy of transmission.

  In addition, jitter tolerance measurement (Jitter Tolerance) is used to test how accurately a receiver circuit that receives a data stream can receive the jitter of the reference clock signal and the jitter included in the data stream. . In this test, it is necessary to apply a known jitter amount as external jitter to the interface circuit unit in the receiving circuit, and it is essential that the applied jitter amount can be arbitrarily controlled. In general, in a receiving circuit adopting the CDR method, this test is equivalent to testing the accuracy of the PLL clock signal. However, in practice, it is necessary to consider the overall jitter tolerance from the transmission circuit to the reception circuit. Therefore, when adding jitter to the data stream, it is necessary to add jitter to the reference clock signal of the transmission circuit.

As a jitter generation device that adds jitter to a clock signal, a configuration including a variable delay circuit that delays the clock signal is known (see, for example, Patent Document 1). In this jitter generator, the fluctuation of the sine wave is given to the change timing of the clock signal by comparing the offset voltage of the sine wave and the output voltage of the ramp generator.
JP-A-6-104708 (page 3-4, FIG. 1-3)

  Incidentally, since the jitter generator disclosed in Patent Document 1 described above is configured by an analog circuit such as an oscillator, a ramp generator, or a voltage comparator that generates a sine wave offset voltage, the circuit scale is increased and consumption is increased. There was a problem that there was a lot of electric power. Further, since it is generally used to operate a clock signal or a logical LSI, there is a problem that it is not preferable to mix a jitter generation device constituted by an analog circuit in the logical LSI. For example, when a digital circuit and an analog circuit are mixed in an LSI, the manufacturing process becomes complicated, resulting in an increase in manufacturing cost and an analog circuit becoming a noise source for the digital circuit.

  The present invention was created in view of the above points, and an object thereof is to provide a jitter generation circuit that does not require an analog circuit and can reduce the circuit scale and power consumption. It is in.

  In order to solve the above-described problem, the jitter generation circuit of the present invention is provided on the input side of the first signal wiring for transmitting the first signal to which the jitter component is added and the first signal wiring. An input buffer, an output buffer provided on the output side of the first signal wiring, a second signal wiring disposed close to the first signal wiring, and a first signal input to the first signal wiring. A jitter generation signal output unit that inputs a second signal synchronized with the first signal to the second signal wiring as a jitter generation signal. The second signal wiring is arranged close to the first signal wiring for transmitting the first signal to which the jitter component is to be added, and the first signal voltage is changed in accordance with the timing at which the voltage level of the first signal changes. By changing the voltage level of the jitter generation signal input to the second signal wiring, interference noise can be superimposed on the first signal wiring using interference between the signal wirings. Since this interference noise occurs at the timing when the voltage level of the jitter generation signal changes, by using the jitter generation signal synchronized with the first signal, the interference of the first signal transmitted over the first signal wiring Interference noise can be superimposed in accordance with the rising or falling timing, and jitter can be added to the first signal. In particular, when a jitter generation signal synchronized with the first signal is input to the signal wiring P2, an analog circuit is not necessary, so that the circuit scale of the entire jitter generation circuit can be reduced. In addition, since only a digital jitter generation signal is generated and input to the signal wiring P2, it is possible to significantly reduce electric power generated compared to the case of using an analog circuit such as an oscillator.

  In addition, it is desirable that the jitter generation signal described above has a part of rising and falling timing coincident with the first signal. This makes it possible to easily generate interference noise that coincides with the rise or fall timing of the first signal. By superimposing this interference noise on the first signal itself, jitter of the first signal can be reduced. Addition can be performed easily and reliably.

  In addition, the plurality of second signal wirings described above are arranged in close proximity to the first signal wiring, and the jitter generation signal output unit inputs a jitter generation signal to each of the plurality of second signal wirings. It is desirable to do. As a result, interference noise corresponding to each of the plurality of second signal lines can be generated on the first signal line, so that the jitter added to the first signal is increased and the variable range is widened. can do.

  In addition, it is desirable that a jitter generation signal whose rising and falling timings coincide with each other is input to each of the plurality of second signal wirings. By making the generation timing of interference noise corresponding to each of the plurality of second signal wirings coincide, particularly large jitter can be added.

  In addition, it is desirable that a jitter generation signal having different rising and falling timings is input to each of the plurality of second signal wirings. Thereby, since the generation timing of the interference noise corresponding to each of the plurality of second signal wirings can be shifted, the randomness of jitter added as a combination of these interference noises can be improved, and the first signal It becomes possible to add complex jitter to the above.

  Further, it is desirable that the one second signal wiring described above has a wiring length different from that of the other second signal wiring. Accordingly, it is possible to vary the magnitude of interference noise generated corresponding to each of the plurality of second signal wirings, and complex jitter can be added as a combination of these.

  Further, it is desirable that the first signal wiring and the second signal wiring described above are surrounded by a grounded ground layer. As a result, it is possible to prevent a signal from wrapping from each signal wiring to other wirings and various signals from other wiring to each signal wiring.

  The jitter generation signal output unit described above includes a jitter generation signal generation unit that generates a jitter generation signal, and the rising and falling timings of the jitter generation signal generated by the jitter generation signal generation unit. It is desirable to provide a synchronization establishment unit that synchronizes with the falling edge. This makes it easy to generate a jitter generation signal synchronized with the first signal and input it to the second signal wiring.

  The jitter generation signal output unit described above selects a jitter generation signal generation unit that generates a jitter generation signal and a plurality of second signal wirings that are input destinations of the jitter generation signal generated by the jitter generation signal generation unit. It is desirable to include a selection unit and a synchronization establishment unit that synchronizes the rise and fall timings of the jitter generation signal selected by the selection unit with the rise and fall of the first signal. This makes it easy to generate a jitter generation signal synchronized with the first signal and input it to the second signal wiring, and selectively select the second signal wiring that is the input destination of the jitter generation signal. It becomes possible to set.

  In addition, it is desirable to further include a timing adjustment unit that adjusts the timing of signals input to the first and second signal wirings described above. As a result, it is possible to adjust the difference in signal propagation time between the circuits provided in the preceding stage of the first and second signal wirings. Therefore, the first signal input to these signal wirings and the jitter generation signal can be adjusted. It is easy to make the respective rises or rise timings coincide with each other.

  Further, the synchronization establishment unit described above is preferably a flip-flop that takes in and outputs a jitter generation signal in synchronization with the rising or falling timing of the first signal. This makes it possible to force the rise and fall timings of the jitter generation signal to coincide with the rise and fall timings of the first timing.

  The jitter generation signal described above is preferably a random bit string signal whose logic level changes randomly. This makes it possible to add a random jitter amount to the first signal.

  The jitter generation signal generator described above extracts a plurality of cascaded flip-flops and a plurality of specific outputs from the plurality of flip-flops, and inputs their exclusive ORs to the specific flip-flop. It is desirable to provide a logic circuit that Thereby, a random bit string can be generated with a simple configuration.

  The jitter generation signal generator described above extracts a plurality of cascaded flip-flops and a plurality of specific outputs from the plurality of flip-flops, and inputs their exclusive ORs to the specific flip-flop. It is desirable that a jitter generation signal input to each of the plurality of second signal wirings is taken out from different positions of the plurality of flip-flops. As a result, it is possible to simultaneously input a random bit string whose contents are shifted to each of the plurality of second signal wirings, and it is possible to increase randomness and add complicated jitter.

  The jitter generation signal generator described above preferably includes a plurality of flip-flops connected in a ring shape, and presets the content held by at least one flip-flop. This makes it possible to add jitter that changes periodically with a simple configuration.

  Further, it is desirable to further include a variable capacitance element connected to the output terminal of the jitter generation signal generator described above. By adding a variable capacitance element and changing its capacitance, it is possible to adjust the magnitude of jitter added to the first signal when transmitted through the first signal wiring. .

  It is desirable to further include an amplitude setting unit that variably sets the amplitude of the jitter generation signal input from the jitter generation signal generation unit described above to the second signal wiring. By adding an amplitude setting unit to vary the amplitude of the jitter generation signal, it is possible to adjust the magnitude of the jitter added to the first signal when transmitted through the first signal wiring. Become.

  In addition, it is desirable that the first and second signal wirings, the input buffer, the output buffer, and the jitter generation signal output unit described above are included in the same large-scale integrated circuit. As a result, it is not necessary to prepare a jitter generation circuit as a separate part, and therefore it is easy to reduce costs by reducing the number of parts. In addition, a BIST (built-in self test) circuit using a jitter generation circuit can be easily realized.

  Hereinafter, a jitter generation circuit according to an embodiment to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 1 is an explanatory diagram of the basic principle of the jitter generation circuit of the present invention. As shown in FIG. 1, the jitter generation circuit of the present invention includes an input buffer 10 connected to an input terminal IN, a jitter generation signal output unit 20 connected to a control terminal S, and an output terminal of the input buffer 10. One end is connected to the signal wiring P1 to which the end is connected, the output terminal of the jitter generation signal output unit 20, and the other end of the signal wiring P1 is connected to the signal wiring P2 disposed in the vicinity of the signal wiring P1. The output buffer 30 and the output buffer 40 connected to the other end of the signal wiring P2 and terminating the other end of the signal wiring P2 are configured. Each of the input buffer 10 and the output buffers 30 and 40 is constituted by, for example, a CMOS inverter circuit. Since the output buffer 40 is a termination circuit for passing a signal through the signal wiring P2 similarly to the signal wiring P1, it is not always necessary to use a CMOS inverter circuit as in the output buffer 30, and an AND circuit. Alternatively, other circuits may be used. The signal wiring P1 corresponds to the first signal wiring, and the signal wiring P2 corresponds to the second signal wiring.

  FIG. 2 is a diagram showing an equivalent circuit of the two signal wirings P1 and P2 arranged close to each other. In each of the signal wirings P1 and P2, when the frequency of the input pulse signal is increased, the inductance component L cannot be ignored in addition to the resistance component R. Further, a mutual conductance component G and a capacitance component C appear between these two signal wirings P1 and P2. Thus, a distributed constant circuit having a resistance component R, an inductance component L, a mutual conductance component G, and a capacitance component C is constituted by the two signal wirings P1 and P2.

  FIG. 3 is a diagram showing signal waveforms input to and output from the two signal wirings P1 and P2 shown in FIG. “A clock signal (input)” in FIG. 3A is a signal waveform input from the input buffer 10 to the signal line P1, and for example, a clock signal that rises and falls at a predetermined cycle is input to the signal line P1. The case is shown. Further, the “jitter generation signal” in FIG. 3B is a signal waveform input from the jitter generation signal output unit 20 to the signal wiring P2. “Interference noise” in FIG. 3C is a noise waveform on the signal line P1 determined by a combination of a clock signal input to the signal line P1 and a jitter generation signal input to the signal line P2. The “clock signal (output)” in FIG. 3D is an output waveform of the signal wiring P1 when the interference noise generated on the signal wiring P1 is superimposed on the clock signal input to the signal wiring P1. .

  A clock signal that is alternately switched between a high level and a low level at a predetermined cycle is input from the input buffer 10 to the signal wiring P1 (FIG. 3A). In addition, a jitter generation signal whose rising and falling timings coincide with each other is input from the jitter generation signal output unit 20 to the signal wiring P2. For example, a random bit string signal whose logic level changes at random is used for this jitter generation signal (FIG. 3B). When the rising and falling timings of the clock signal input to the signal wiring P1 coincide with the rising and falling timings of the jitter generation signal input to the signal wiring P2, interference noise is generated on the signal wiring P1 (FIG. 3). (C)). In this embodiment, since a random bit string signal is used as the jitter generation signal, the rise and fall of the jitter generation signal combined with the rise and fall of the clock signal are indefinite and change randomly. The interval and polarity of the interference noise generated on P1 are also random. Since interference noise is superimposed on the clock signal input from the input buffer 10 on the signal wiring P1, a clock signal having fluctuation (jitter) at the rising and falling timings with respect to the input clock signal. Is output (FIG. 3D).

  FIG. 4 is a diagram showing the distribution of each cycle of the clock signal output from the signal wiring P1. In FIG. 4, the horizontal axis indicates the rising or falling interval of each cycle of the clock signal, and the vertical axis indicates the frequency. When the jitter generation signal is a random bit string, a jitter component corresponding to the content appears. Therefore, the interval for each period of rising or falling is a predetermined value (clock when there is no jitter component) as shown in FIG. A statistical distribution centering on a value corresponding to the period of the signal).

  As described above, in the jitter generation circuit according to the present invention, the clock signal to be jitter-added is input to the signal wiring P1, and the jitter generation signal composed of a random bit string with respect to the signal wiring P2 arranged close to the signal wiring P1. Is input, it is possible to add jitter according to the contents of the random bit string to the clock signal propagating through the signal wiring P1. In particular, when a jitter generation signal composed of a random bit string is generated and input to the signal wiring P2, an analog circuit is unnecessary, so that the circuit scale of the entire jitter generation circuit can be reduced. In addition, since only a digital jitter generation signal is generated and input to the signal wiring P2, it is possible to significantly reduce electric power generated compared to the case of using an analog circuit such as an oscillator.

  Next, a specific example (embodiment) when an actual jitter generation circuit is configured based on the principle of the present invention described above will be described.

[First Embodiment]
FIG. 5 is a diagram illustrating a configuration of the jitter generation circuit according to the first embodiment. As shown in FIG. 5, the jitter generation circuit of this embodiment includes three signal wirings P1, P2, and P3 arranged close to each other, and an input buffer 10 connected to the input side and the output side of the signal wiring P1, respectively. The timing adjustment unit 12 and the output buffer 30, the jitter generation signal output unit 20 provided on the input side of the signal wirings P2 and P3, and the output buffers 400 and 402 provided on the output side of the signal wirings P2 and P3, respectively. It is comprised including. The two signal wirings P2 and P3 are adjacently arranged at equal intervals on both sides of the signal wiring P1.

  The input buffer 10 is composed of a CMOS inverter circuit, and inverts the logic level of the input clock signal and outputs it. The timing adjustment unit 12 is for performing time adjustment for making the input timing of the clock signal from the input buffer 10 to the signal wiring P1 coincide with the input timing of the edge generation signal to the signal wirings P2 and P3. It is configured by an inverter circuit. In this embodiment, the timing of signal input to the three signal wirings P1, P2, and P3 is adjusted by providing the timing adjustment unit 12 including one CMOS inverter circuit in the previous stage of the input buffer 10. When the adjustment time is long, the number of cascaded CMOS inverter circuits constituting the timing adjustment unit 12 may be increased, or another circuit may be used. Further, depending on the input timing of each signal input to the three signal wirings P1, P2, and P3, the signal wirings P2 and P3 are provided on the input side of the signal wiring P1 instead of or in parallel with the timing adjustment unit 12. A timing adjustment unit may be provided on the input side.

  The output buffer 30 is connected to the output end side of the signal wiring P1, and outputs a signal obtained by performing waveform shaping on the clock signal output from the signal wiring P1. The output buffer 400 terminates the output end of the signal wiring P2. The output buffer 402 terminates the output end of the signal wiring P3.

  The jitter generation signal output unit 20 outputs a jitter generation signal toward each of the two signal wirings P2 and P3 arranged in proximity to the signal wiring P1 through which the clock signal is transmitted. For this purpose, the jitter generation signal output unit 20 includes a clock generation unit 100, a random bit string generation unit 110, a jitter generation signal path control unit 120, and output buffers 130 and 132.

  The clock generation unit 100 generates a clock signal having a predetermined frequency to be jittered. The clock signal generated by the clock generation unit 100 is input to the signal wiring P1 via the timing adjustment unit 12 and the input buffer 10. Note that the clock generation unit 100 is not necessarily included in the jitter generation signal output unit 20. For example, a reference clock signal input from the outside may be used instead of the clock signal generated by the clock generator 100. In this specification, a case where jitter is added to a clock signal will be described as an example. However, a signal to which jitter is added is not limited to a clock signal, and other signals having non-periodic rising and falling edges. Jitter may be added to this signal.

  The random bit string generation unit 110 is configured by, for example, a linear feedback shift register (LFSR) circuit, and generates a pseudo random bit string signal. FIG. 6 is a diagram illustrating a configuration of the random bit string generation unit 110. As shown in FIG. 6, the random bit string generation unit 110 includes N flip-flops 114-1 to 114 -N connected in cascade, and a specific plurality of them, for example, i-th and N-th flip-flops. And an exclusive OR circuit 112 as a logic circuit that obtains an exclusive OR of the outputs of 114-i and 114-N and inputs it to a specific (for example, first stage) flip-flop 114. Each of the flip-flops 114-1 to 114 -N captures, holds, and outputs the input data in synchronization with the clock signal output from the clock generation unit 100. The number N of stages of the flip-flops 114-1 to 114-N is set to 23 or 31, for example. In this manner, by combining the shift register including the N flip-flops 114-1 to 114 -N and the exclusive OR circuit 112, a pseudo random bit string signal can be easily generated. Note that the random bit string generation unit 110 only needs to be able to generate a pseudo-random bit string signal, and thus is not limited to the configuration illustrated in FIG. 6, and other configurations may be employed.

  The jitter generation signal path control unit 120 sets the output path of the jitter generation signal based on the control signal. There are four possible output paths for the jitter generation signal: when the signal path P2 is selected, when the signal path P3 is selected, when both are selected, and when neither is selected.

  FIG. 7 is a diagram illustrating a configuration of the jitter generation signal path control unit 120. As shown in FIG. 7, the jitter generation signal path control unit 120 includes a decoder 122, AND circuits 124 and 125, and flip-flops 126 and 127. The decoder 122 individually outputs a 1-bit selection signal for specifying the signal wirings P1 and P2 that are output destinations of the jitter generation signal to the two AND circuits 124 and 125 based on the input control signal. To do. One selection signal is input to one input terminal of the AND circuit 124, and the other selection signal is input to one input terminal of the AND circuit 125. In one AND circuit 124, the pseudo random bit string signal output from the random bit string generator 110 is input to the other input terminal, and the selection signal input from the decoder 122 is at a high level (“1”). This pseudo random bit string signal is output. Similarly, in the other AND circuit 125, the pseudo random bit string signal output from the random bit string generator 110 is input to the other input terminal, and this pseudo signal is input when the selection signal input from the decoder 122 is at a high level. A random bit string signal is output. Therefore, when only one of the two selection signals output from the decoder 122 is at a high level, a pseudo random bit string signal is output only from an AND circuit to which the high level selection signal is input. Further, when both of the two selection signals output from the decoder 122 are at a high level, pseudo random bit string signals are output from both of the two AND circuits 124 and 125. In addition, when both of the two selection signals output from the decoder 122 are at a low level, neither of the two AND circuits 124 and 125 outputs a pseudo random bit string signal. The decoder 122 and the two AND circuits 124 and 125 described above constitute a selection unit.

  One flip-flop 126 captures and outputs a signal output from one AND circuit 124 in synchronization with the clock signal output from the clock generator 100. A signal output from the flip-flop 126 is input to the signal line P2 via the output buffer 130. Similarly, the other flip-flop 127 takes in and outputs the signal output from the other AND circuit 125 in synchronization with the clock signal output from the clock generation unit 100. The signal output from the flip-flop 127 is input to the signal line P3 through the output buffer 132. These two flip-flops 126 and 127 constitute a synchronization establishing unit.

  Incidentally, in the jitter generation circuit shown in FIG. 5, two signal wirings P2 and P3 are arranged close to each other on both sides of the signal wiring P1 through which the clock signal is inputted / outputted, but these two signal wirings P2 and P3 are arranged. Focusing only on either of these, the relationship between the signal wiring P2 and the signal wiring P1 in the basic configuration shown in FIG. 1 is the same. Therefore, when the rise timing of the clock signal and the rise or fall timing of the jitter generation signal match, or when the fall timing of the clock signal and the rise or fall timing of the jitter generation signal match, Corresponding interference noise is generated on the signal wiring P1, and a clock signal with jitter added is output from the signal wiring P1. Further, when a jitter generation signal composed of the same pseudo-random bit string is input to both of the two signal wirings P2 and P3, the level of interference noise becomes large (almost twice), and therefore output from the signal wiring P1. The amount of jitter added to the clock signal to be generated also increases.

  As described above, the two signal wirings P2 and P3 are arranged close to the signal wiring P1 to which the clock signal is inputted / outputted, and the jitter generation signal is inputted to each of the signal wirings P2 and P3, so that the clock signal is converted into the clock signal. On the other hand, jitter can be added. In addition, the magnitude of jitter added to the clock signal can be changed by switching the number of signal wirings to which the jitter generation signal is input. Moreover, in such a jitter generation circuit for adding jitter, an analog circuit such as an oscillator is not used, so that the circuit scale can be reduced and the power consumption can be reduced, and a large-scale integrated circuit (BIST circuit) By including it in the LSI together with other constituent circuits, an on-chip jitter adding circuit with a very small circuit scale can be realized. In addition, since a jitter generation signal synchronized with a clock signal to be jitter-added is used, it is possible to add jitter having a high frequency (for example, a gigahertz band) close to the clock signal.

[Second Embodiment]
FIG. 8 is a diagram illustrating the configuration of the jitter generation circuit according to the second embodiment. As shown in FIG. 8, the jitter generation circuit of this embodiment is connected to nine signal wirings P1, P2A to P2D, and P3A to P3D arranged close to each other, and to the input side and output side of the signal wiring P1, respectively. The input buffer 10 and the output buffer 30, the jitter generation signal output unit 20A provided on the input side of the signal wirings P2A to P2D, P3A to P3D, and the output side of the signal wirings P2A to P2D and P3A to P3D Output buffers 400A to 400D, 402A to 402D. Four signal wirings P2A to P2D are arranged close to one side across the signal wiring P1, and four signal wirings P3A to P3D are arranged close to the other side.

  The jitter generation signal output unit 20A outputs a jitter generation signal toward each of the eight signal wirings P2A to P2D and P3A to P3D that are arranged close to the signal wiring P1 through which the clock signal is transmitted. For this purpose, the jitter generation signal output unit 20A includes a jitter generation signal path control unit 120A and output buffers 130A to 130D and 132A to 132D. Except for these configurations, the configuration is the same as that of the jitter generation signal output unit 20 shown in FIG. 5 (the clock generation unit 100 and the random bit string generation unit 110), and these configurations are omitted in FIG. ing.

  The jitter generation signal path control unit 120A sets the output path of the jitter generation signal based on the control signal. FIG. 9 is a diagram illustrating a configuration of the jitter generation signal path control unit 120A. As shown in FIG. 9, the jitter generation signal path control unit 120A includes a decoder 122A, AND circuits 124A to 124D, 125A to 125D, and flip-flops 126A to 126D, 127A to 127D. The decoder 122A outputs eight AND circuits 124A to 124D, 125A to a 1-bit selection signal for specifying the signal wirings P2A to P2D and P3A to P3D that are output destinations of the jitter generation signal based on the input control signal. Output individually for each of 125D. Each of the eight AND circuits 124A to 124D and 125A to 125D performs basically the same operation as the two AND circuits 124 and 125 included in the jitter generation signal path control unit 120 illustrated in FIG. When a selection signal input to one input terminal is at a high level, a pseudo random bit string signal input to the other is output. The decoder 122A and the eight AND circuits 124A to 124D and 125A to 125D constitute a selection unit.

  Each of flip-flops 126 </ b> A to 126 </ b> D and 127 </ b> A to 127 </ b> D takes in and outputs a signal output from each AND circuit provided in the preceding stage in synchronization with the clock signal output from clock generation unit 100. Each flip-flop and each of the eight signal wirings P2A to P2D and P3A to P3D have a one-to-one correspondence, and signals output from the flip-flops are output from the output buffers 130A to 130D and 132A to 132D, respectively. Are input to the corresponding signal wirings. The eight flip-flops 126A to 126D and 127A to 127D constitute a synchronization establishing unit.

  In this way, a total of eight signal lines P21,..., P2N, P31,..., P3N are arranged on each side of the signal line P1, and a jitter generation signal is selectively input to these signal lines. By doing so, the variable amount of jitter added to the clock signal can be widened.

  By the way, as shown in FIG. 5, when two signal wirings P2 and P3 are arranged close to each other on both sides of the signal wiring P1, each of these two signal wirings P2 and P3 and the signal wiring P1 are arranged. The degree of interference between the signal wirings and the signal wiring P1 is increased when other signal wirings are arranged close to each other as shown in FIG. The degree decreases in inverse proportion to the square of the distance. Therefore, even when the same jitter generation signal is input, if the distance from the signal wiring P1 is input to a different signal wiring, interference noise of a different voltage level is generated, and the jitter generation signal is input. By switching the signal wiring, it is possible to increase the resolution added to the clock signal.

[Third Embodiment]
In the above-described first and second embodiments, the same jitter generation signal is input to each signal wiring arranged on both sides of the signal wiring P1, but at least a part of the signal wiring has a different content from the others. A jitter generation signal may be input.

  FIG. 10 is a diagram showing a modification of the jitter generation signal path control unit that inputs a jitter generation signal having different contents to each signal wiring arranged close to the signal wiring P1 through which the clock signal is input and output. The jitter generation signal path control unit 120B illustrated in FIG. 10 includes a decoder 122A, AND circuits 124A to 124D, 125A to 125D, and flip-flops 128A to 128H. The jitter generation signal path control unit 120B can be replaced with the jitter generation signal path control unit 120A shown in FIG. 8, and the jitter generation signal is input to each of the output buffers 130A to 130D and 132A to 132D arranged in the subsequent stage. To do.

  The decoder 122A outputs eight AND circuits 124A to 124D, 125A to a 1-bit selection signal for specifying the signal wirings P2A to P2D and P3A to P3D that are output destinations of the jitter generation signal based on the input control signal. Output individually to one input terminal of 125D. The eight flip-flops 128A to 128H are connected in cascade, and a pseudo random bit string signal is input to the first flip-flop 128A. Each flip-flop holds and outputs input data in synchronization with a clock signal output from the clock generation unit 100. Each of the flip-flops 128A to 128H has a one-to-one correspondence with each of the eight AND circuits 124D, 124C, 124B, 124A, 125A, 125B, 125C, and 125D, and is output from each flip-flop. Data (pseudo random bit string signal) is input to the other input terminal of the corresponding AND circuit. Each AND circuit outputs a pseudo random bit string signal input to the other input terminal when the selection signal input to one input terminal from the decoder 122A is at a high level. By changing the extraction position of the pseudo random bit string signal corresponding to each AND circuit, the contents of the pseudo random bit string signal simultaneously input to each AND circuit can be made different. When the jitter generation signal path control unit 120B shown in FIG. 10 is used, pseudo random bit string signals are separately extracted from different positions of a plurality of flip-flops constituting the random bit string generation unit 110 shown in FIG. become. As a result, the randomness of the interference noise generated on the signal wiring P1 can be increased, and complex jitter can be added to the clock signal.

[Fourth Embodiment]
FIG. 11 is a diagram illustrating a configuration of a jitter generation circuit according to the fourth embodiment. The jitter generation circuit shown in FIG. 11 differs from the jitter generation circuit shown in FIG. 1 in that a variable capacitance element 60 is added between the output terminal of the jitter generation signal output unit 20 and the ground. The configuration is the same. As described above, FIG. 1 shows a configuration for explaining the basic principle of the jitter generation circuit. However, in the jitter generation circuit of each embodiment shown in FIGS. When the same modification is performed, the variable capacitance elements are individually (not necessarily all, but may be a part) individually for the input terminals of the signal wirings P2, P2A to P2D, P3, and P3A to P3D. 60 may be connected.

  When the variable capacitance element 60 is connected to the output terminal of the jitter generation signal output unit 20, when the jitter generation signal output from the jitter generation signal output unit 20 rises from L level to H level, or from H level to L level. At the time of falling, since the charging and discharging operation determined by the time constant determined by the output resistance of the input buffer provided in the output stage in the jitter generation signal output unit 20 and the capacitance of the variable capacitance element 60 is involved, these rising waveforms In addition, a delay occurs in the falling waveform, and a so-called waveform waveform appears. This degree is determined by the size of the time constant, that is, the capacitance of the variable capacitance element 60.

  By the way, the degree of interference with the clock signal transmitted through the signal wiring P1, that is, the magnitude of the interference noise appearing on the signal wiring P1, is as long as the rise and fall of the jitter generation signal input to the signal wiring P2 is steep. The larger the value, the smaller the jitter generation signal when the falling edge or falling edge becomes gentle. Therefore, by adding the variable capacitance element 60 and changing the capacitance thereof, it is possible to adjust the magnitude of jitter added to the clock signal when transmitted via the signal wiring P1.

[Fifth Embodiment]
FIG. 12 is a diagram illustrating the configuration of the jitter generation circuit according to the fifth embodiment. The jitter generation circuit shown in FIG. 12 is different from the jitter generation circuit shown in FIG. 1 in that a variable amplitude driver circuit 70 is inserted between the jitter generation signal output unit 20 and the signal wiring P2. The configuration is the same. The variable amplitude driver circuit 70 operates as an amplitude setting unit.

  The variable amplitude driver circuit 70 is a driver circuit capable of variably setting the amplitude level according to a control signal, and includes a current source 71, FETs 72, 73, 74, and a resistor 75. As the resistor 75, for example, an ON resistance of an FET may be used. The current source 71 can set a current value according to the control signal, and supplies a current between the source and the drain to the FET 72. The drain and gate of the FET 72 and the gate of the FET 73 are connected in common, and the two FETs 72 and 73 constitute a current mirror circuit. A FET 74 whose on / off state is controlled by a jitter generation signal is connected to the drain side of the FET 73, and the drain of the FET 74 is connected to the power supply VDD via a resistor 75. When the current value supplied to the FET 72 by the current source 71 changes according to the control signal, the current flowing between the sources and drains of the FETs 73 and 74 also changes, so the value of the voltage across the resistor 75 also changes. The amplitude of the signal output from the variable amplitude driver circuit 70 is changed.

  By the way, the degree of interference with the clock signal transmitted through the signal line P1, that is, the magnitude of interference noise appearing on the signal line P1, increases as the amplitude of the jitter generation signal input to the signal line P2 increases. If the amplitude of becomes smaller, it becomes smaller accordingly. Therefore, by adding the variable amplitude driver circuit 70 to vary the amplitude of the jitter generation signal, it is possible to adjust the magnitude of the jitter added to the clock signal when transmitted through the signal wiring P1. Become.

  Since the variable amplitude driver circuit 70 described above inverts the logic of the input jitter generation signal and outputs the inverted signal, for example, the logic level of the pseudo random bit string signal output from the random bit string generator 110 shown in FIG. When an attempt is made to input to the signal wiring P2 or the like without change, an inverter circuit is added before the variable amplitude driver circuit 70, or the output buffer 20 provided at the output stage of the jitter generation signal output unit is replaced with a CMOS inverter circuit. It is necessary to devise such as configuring with. Alternatively, as shown in FIG. 13, when a differential variable amplitude driver circuit 70A is used, a jitter generation signal can be input to the signal wiring P2 without inversion of logic. In addition, when there is a shift in timing from when the pseudo random bit string signal is output from the random bit string generator 110 to the input to the signal wiring P2 or the like with this change, a time corresponding to this shift is set. It is necessary to readjust in the variable delay circuit 12A for timing adjustment.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, in the above-described embodiment, the pseudo random bit string signal generated by the random bit string generator 110 is used as the jitter generation signal. However, a jitter generation signal generated with a simpler configuration may be used.

  FIG. 14 is a diagram illustrating a modification of the jitter generation signal output unit. 14 includes a clock generation unit 100, a decoder 122A, eight flip-flops 129A to 129H, eight AND circuits 124A to 124D, 125A to 125D, eight output buffers 130A to 130D, It is comprised including 134A-134D. In this jitter generation signal output unit, eight flip-flops 129A to 129H connected in a ring shape are used instead of the random bit string generation unit 110. For example, the flip-flop 129A is preset at a predetermined timing and the output signal becomes H level. Therefore, thereafter, each of the flip-flops 129A to 129H sequentially outputs an H level signal at a rate of once every eight periods of the input clock signal. The signals periodically changing to H level output from the flip-flops 129A to 129H are input to the buffers 130A to 130D and 134A to 134D connected to the subsequent stage through AND circuits corresponding to one-to-one. Is done. In the example shown in FIG. 14, the four buffers 130A to 130D output the input signal without inverting the logic, and the other four buffers 134A to 134D invert the input signal logic. Output. This complicates the combination of jitter generation signals input to each of the eight signal wirings P2A to P2D and P3A to P3D from the jitter generation signal output unit. Therefore, the random generation is random as in the case of using a pseudo-random bit string signal. High-quality jitter can be added to the clock signal. In addition, the configuration of the jitter generation signal output unit can be simplified as compared with the case where the random bit string generation unit 110 is used.

  Further, in each of the above-described embodiments, the lengths of the plurality of signal wirings P2, P3 and the like arranged close to the signal wiring P1 are the same. However, these wiring lengths may be different. FIG. 15 is a diagram illustrating a modified example of the jitter generation circuit in which the length of the signal wiring is changed. The jitter generation circuit shown in FIG. 15 differs from the jitter generation circuit shown in FIG. 5 in that the signal generation line P4 has a shorter wiring length than the signal wiring P2, and other configurations are common. . The resistance component R, inductance component L, mutual conductance component G, and capacitance component C included in the equivalent circuit shown in FIG. 2 vary depending on the positional relationship between the two signal wirings, and these two signal wirings face each other. It changes in proportion to the length. Therefore, by shortening the length of one signal wiring P4 arranged adjacent to the signal wiring P1, the level of interference noise generated corresponding to one signal wiring P4 can be reduced. Thus, by making the lengths of the two signal wirings P4 and P3 different, it becomes possible to add various combinations of complex jitter to the clock signal.

  In addition, in the description of each embodiment described above, the peripheral structure of each signal wiring is not particularly described. However, in order to control the level of jitter added to the clock signal, or from each signal wiring to other wiring, etc. In order to prevent noise emission and the like, it is desirable to surround these signal wirings with a ground layer and shield them.

  FIG. 16 is a diagram showing a specific example of the shield structure using the ground layer, and shows a cross-sectional structure corresponding to the three signal wirings P1, P2, and P3 shown in FIG. As shown in FIG. 16, the three signal wirings P1, P2, P3 arranged in parallel to each other are composed of ground layers G1, G2 arranged on both side surfaces thereof and ground layers G3, G4 as upper and lower layers. being surrounded. These ground layers G1 to G4 are connected to each other by a VIA hole (V). In this way, by surrounding the signal wirings P1, P2, and P3 arranged close to each other with the ground layers G1 to G4, the signal wiring from the signal wirings P1, P2, and P3 to other wirings, It is possible to prevent various signals from wrapping around from the wiring to the signal wiring P1.

  FIG. 17 is a diagram showing a configuration when the jitter generation circuit of each of the above-described embodiments is incorporated in a semiconductor test apparatus. The semiconductor test apparatus shown in FIG. 17 includes a RATE generation unit 900, a test pattern generation unit 910, a timing generation circuit 930, a jitter generation circuit 940, a waveform shaping unit 950, and an expected value comparison unit 960. Various tests are performed on the device under test). The RATE generation unit 900 generates a RATE signal having a predetermined period for setting a basic period for performing a test. The test pattern generation unit 910 generates pattern data to be input to each input pin of the DUT. The timing generation circuit 930 generates various timing edges included in the basic period based on the RATE signal output from the RATE generation unit 900. The jitter generation circuit 940 has the configuration shown in FIGS. 5 and 8 and the like, and adds jitter to the signal by passing the signal input from the timing generation circuit 930 through the signal wiring P1. It should be noted that during a normal test operation in which no jitter is added, a jitter generation signal may not be input from the jitter generation signal output unit 20 or the like to each signal wiring P2 or the like. The waveform shaping unit 950 performs waveform control of a signal input to each input pin of the DUT based on the timing edge output from the timing generation circuit 930 corresponding to the pattern data output from the test pattern generation unit 910. The expected value comparison unit 960 compares the data output from each output pin of the DUT with the expected value data for each output pin output from the test pattern generation unit 910. In the semiconductor test apparatus having such a configuration, the timing generation circuit 930 and the jitter generation circuit 940 are formed as the timing generation LSI 920 on the same semiconductor substrate. As described above, the jitter generation circuit 940 can be formed as a part of the LSI together with the timing generation circuit 930 as another circuit, and the clock signal and other input data to which the jitter is added by the jitter generation circuit 940. Can be input to the DUT to test whether this DUT operates normally.

It is explanatory drawing of the basic principle of the jitter generator circuit of this invention. It is a figure which shows the equivalent circuit of two signal wiring P1, P2 arrange | positioned mutually close. It is a figure which shows the signal waveform input / output to two signal wiring P1, P2 shown in FIG. It is a figure which shows distribution of each period of the clock signal output from signal wiring P1. It is a figure which shows the structure of the jitter generation circuit of 1st Embodiment. It is a figure which shows the structure of a random bit stream generation part. It is a figure which shows the structure of a jitter production | generation signal path | route control part. It is a figure which shows the structure of the jitter generation circuit of 2nd Embodiment. It is a figure which shows the structure of the jitter generation signal path | route control part shown in FIG. It is a figure which shows the structure of the jitter generation signal path | route control part contained in the jitter generation circuit of 3rd Embodiment. It is a figure which shows the structure of the jitter generation circuit of 4th Embodiment. It is a figure which shows the structure of the jitter generator circuit of 5th Embodiment. It is a figure which shows the modification of the variable amplitude driver circuit contained in the jitter generation circuit of 5th Embodiment. It is a figure which shows the modification of a jitter generation signal output part. It is a figure which shows the modification of the jitter generation circuit which changed the length of signal wiring. It is a figure which shows the specific example of the shield structure using a ground layer. It is a figure which shows the structure of the semiconductor test apparatus incorporating the jitter generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Input buffer 12 Timing adjustment part 20 Jitter generation signal output part 30, 40, 130, 132, 400, 402 Output buffer 100 Clock generation part 110 Random bit sequence generation part 120 Jitter generation signal path control part P1, P2, P3 Signal wiring

Claims (18)

A first signal wiring for transmitting a first signal to which a jitter component is added;
An input buffer provided on the input side of the first signal wiring;
An output buffer provided on the output side of the first signal wiring;
A second signal wiring disposed close to the first signal wiring;
A jitter generation signal output unit configured to input a second signal synchronized with the first signal input to the first signal wiring to the second signal wiring as a jitter generation signal;
A jitter generation circuit comprising: In claim 1,
The jitter generation circuit according to claim 1, wherein a timing of a part of rising and falling of the first generation signal coincides with that of the first signal. In claim 1 or 2,
A plurality of the second signal wirings are disposed in proximity to the first signal wirings;
The jitter generation signal output unit inputs the jitter generation signal to each of a plurality of the second signal wirings. In claim 3,
The jitter generation circuit, wherein the jitter generation signals whose rising and falling timings coincide with each other are input to each of the plurality of second signal wirings. In claim 3,
The jitter generation circuit, wherein the jitter generation signals having different rising and falling timings are input to each of the plurality of second signal wirings. In any one of Claims 3-5,
A jitter generation circuit, wherein one of the second signal wirings has a wiring length different from that of the other second signal wirings. In any one of Claims 1-6,
A jitter generation circuit, wherein the first signal wiring and the second signal wiring are surrounded by a grounded ground layer. In any one of Claims 1-7,
The jitter generation signal output unit includes:
A jitter generation signal generator for generating the jitter generation signal;
A synchronization establishment unit that synchronizes the rise and fall timings of the jitter generation signal generated by the jitter generation signal generation unit with the rise and fall of the first signal;
A jitter generation circuit comprising: In any one of Claims 3-6,
The jitter generation signal output unit includes:
A jitter generation signal generator for generating the jitter generation signal;
A selection unit that selects a plurality of the second signal wirings that are input destinations of the jitter generation signal generated by the jitter generation signal generation unit;
A synchronization establishment unit that synchronizes the rise and fall timings of the jitter generation signal selected by the selection unit with the rise and fall of the first signal;
A jitter generation circuit comprising: In claim 9,
A jitter generation circuit, further comprising a timing adjustment unit that adjusts a timing of a signal input to each of the first and second signal wirings. In claim 9 or 10,
The jitter generation circuit, wherein the synchronization establishment unit is a flip-flop that takes in and outputs the jitter generation signal in synchronization with the rising or falling timing of the first signal. In any one of Claims 8-11,
The jitter generation circuit, wherein the jitter generation signal is a random bit string signal whose logic level changes at random. In claim 12,
The jitter generation signal generation unit extracts a plurality of cascaded flip-flops and a specific plurality of outputs from the plurality of flip-flops, and inputs their exclusive ORs to the specific flip-flop. A jitter generation circuit comprising a logic circuit. In any one of Claims 9-11,
The jitter generation signal generation unit extracts a plurality of cascaded flip-flops and a specific plurality of outputs from the plurality of flip-flops, and inputs their exclusive ORs to the specific flip-flop. A jitter generation circuit comprising: a logic circuit; and extracting the jitter generation signal input to each of the plurality of second signal wirings from different positions of the plurality of flip-flops. In any one of Claims 8-11,
The jitter generation circuit includes a plurality of flip-flops connected in a ring shape, and presets the contents held in at least one of the flip-flops. In any one of Claims 8-15,
A jitter generation circuit, further comprising: a variable capacitance element connected to an output terminal of the jitter generation signal generation unit. In any one of Claims 8-16,
A jitter generation circuit, further comprising: an amplitude setting unit that variably sets the amplitude of the jitter generation signal input from the jitter generation signal generation unit to the second signal wiring. In any one of Claims 1-17,
A jitter generation circuit comprising the first and second signal lines, the input buffer, the output buffer, and the jitter generation signal output unit in the same large-scale integrated circuit.

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