CN107271890B - A kind of jittered device of train pulse part failing edge - Google Patents
A kind of jittered device of train pulse part failing edge Download PDFInfo
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- CN107271890B CN107271890B CN201710446127.XA CN201710446127A CN107271890B CN 107271890 B CN107271890 B CN 107271890B CN 201710446127 A CN201710446127 A CN 201710446127A CN 107271890 B CN107271890 B CN 107271890B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
- G01R31/31709—Jitter measurements; Jitter generators
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Abstract
The invention discloses a kind of jittered devices of train pulse part failing edge, list entries pulse is passed through to the gate-control signal interception after synchronizing, obtain needing the part without loading shake except the partial-sum gate control signal that failing edge loads shake, for needing the partial sequence impulse waveform for loading shake to be decomposed into rising edge signal and failing edge signal, delay timing control, which is converted, by shake is loaded into rising edge, rising edge signal makes train pulse carry out Shi Lagao in rising edge as trigger clock and failing edge signal as reset signal, it is dragged down when failing edge comes, Waveform composition after realization is jittered to the failing edge of the partial sequence pulse signal, obtain the jittered train pulse signal of complete part failing edge.
Description
Technical field
The invention belongs to digital test techniques fields, more specifically, are related to a kind of train pulse part failing edge and add
The device trembled.
Background technique
In recent years, under the background of electronic technology fast development, digitizer also continues to develop therewith, and logical
The fields such as letter, navigation show its unique and property in short supply.From the point of view of present case, the development of digitizer is along with half
The development of conductor device towards integrated with intelligentized direction evolution, and shows high-precision, high integration, multi-functional
Property, the development characteristic of man-machine interaction, programmability.Meanwhile the development of semiconductor technology and integrated technology has also pushed number
The innovation of change technology, the development of digitizing technique largely reflect the development of Current electronic industry.
Train pulse signal generator has great research meaning in many fields as a kind of typical digitizer
Justice.Firstly, especially carrying out relevant functional test, noise to high-frequency circuit, high-speed digital facilities etc. in traditional test field
Tolerance test, the test of signal jitter tolerance when corresponding test, generally require to provide that chattering frequency is adjustable, trembles for tested test system
The dynamic adjustable spectrum component of size variable duty ratio pulse signal abundant, generally requires functional mode test signal abundant and goes
Carry out analysis test, identify its corresponding situation, operating status etc., or fault diagnosis is carried out to it, often want band limits it is wide,
Transmission power is big, signal source with high accuracy services for it.
Shake refers to the offset that train pulse signal instantaneous variation important in a short time occurs relative to ideal position.It trembles
It is dynamic to be divided into Random jitter (RJ) and deterministic jitter (DJ), and deterministic jitter can be divided into periodic jitter
(PJ), three kinds of data dependent jitter (DDJ) and duty cycle dither (DCD).
Randomized jitter Producing reason is very complicated, is difficult to eliminate.Device inside thermal noise, the random vibration of crystal, universe
Ray etc. is likely to cause randomized jitter.Randomized jitter meets Gaussian Profile, is theoretically non-boundary, only to be tested
Time long enough, randomized jitter are also infinitely great.Deterministic jitter is not Gaussian Profile, is usually to have limit, it is can
It repeats predictable.Reflection, crosstalk, switching noise, power supply disturbance, EMI of signal etc. can generate Random jitter.
It is over the years peak-to-peak value shake (Peak-to-peak Jitter) come the most common method for quantifying shake
With rms jitter (Root-Mean-Square Jitter).Since clock system is the very crucial a part of digital display circuit,
The success or failure for directly determining data transmission and reception, are the aortas of whole system, therefore the shake of clock has been a concern.
High-speed serial data Standard General requires the overall shake of (such as 10e-12) in specific bit error rate, inherently shakes, is random
The indexs such as shake cannot be excessive；And clock signal is usually that chip handbook provides requirement.
In digital display circuit, shake will cause the increase of error rate of system, in order to make digital display circuit have the case where shake
Under, still ensure that the index of system, then shaking should just limit within limits, here it is so-called jitter tolerations.
Therefore in order to measure the jitter toleration of digital display circuit, it is necessary to simulate polymorphic type digital dither signal or clock jitter, controllably tremble
Dynamic amplitude etc., the maximum jitter range allowed in the case where guaranteeing the index of system.And current open source information at home
In have no on train pulse signal load shake come to being devices under the technology tested.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of jittered dresses of train pulse part failing edge
It sets, provides periodic part failing edge dither signal to be devices under, in the controllable situation of jitter range, complete tested
The test of equipment.
For achieving the above object, the jittered device of a kind of train pulse part of the invention failing edge, which is characterized in that
Include:
Delay compensating circuit 1, for receiving sequence pulse signal DIN, and to train pulse signal DINDelay compensation is carried out,
Make the failing edge of synchronous circuit output signal prior to train pulse signal DINArriving signal intercepts circuit；
Synchronous circuit, for receiving sequence pulse signal DINAnd gate-control signal, complete gate-control signal and train pulse signal
Synchronization, obtain the intercept signal for intercepting train pulse；
Signal intercepts circuit 1 and signal intercepts circuit 2, receives the sequence after 1 delay compensation of delay compensating circuit respectively
Column pulse signal and intercept signal intercept the train pulse signal after delay compensation by intercept signal, obtain outdoors
Signal and Men Nei signal；Signal intercepts circuit 2 and signal in door is fanned out into two-way, be respectively fed to rising edge detection circuit and under
Drop is along detection circuit；
Rising edge detection circuit and failing edge detection circuit, for extracting the rising edge information and failing edge letter of signal in door
Breath obtains narrow rising edge signal and the failing edge signal that narrows；
Address control unit is loaded to after clock signal and gate enable signal progress delay disposal as shake data
Signal is sent to delay circuit for data are shaken for controlling shake data storage circuitry；
Data storage circuitry is shaken, under the control of shake data load signal, shake data storage circuitry will be carried
The shake data of inherent delay are sent to delay control circuit；
Head delay circuit, for receiving the rising edge signal that narrows, and carries out controllable delay, realizes the failing edge signal that narrows
Negative shake under different jitter amplitudes, is then forwarded to along combiner circuit；
Delay control circuit, for receiving narrow failing edge signal and shake data, and in shake data load control letter
Number control under, will shake data be loaded into the failing edge signal that narrows, be then forwarded to along combiner circuit；
Along combiner circuit, the signal that head delay circuit and delay control circuit are sent is synthesized, is obtained comprising rising
Along the jittered signal of the failing edge of information and failing edge information；
Delay compensating circuit 2, for receiving signal outdoors, and on the door, external signal carries out delay compensation, make outdoors signal with
The total delay of the jittered signal of failing edge is identical, is re-fed into data synthesis circuit；
Signal outdoors after the jittered signal of failing edge and delay compensation is carried out exclusive or synthesis, obtained by data synthesis circuit
The jittered train pulse signal of part failing edge.
Goal of the invention of the invention is achieved in that
A kind of jittered device of train pulse part of the invention failing edge, passes through the gate after synchronizing for list entries pulse
Signal interception obtains needing the part without loading shake except the partial-sum gate control signal that failing edge loads shake.It is right
In needing the partial sequence impulse waveform for loading shake to be decomposed into rising edge signal and failing edge signal, delay is converted by shake
Timing controlled is loaded into rising edge, and rising edge signal makes sequence as reset signal as trigger clock and failing edge signal
Pulse carrys out Shi Lagao in rising edge, drags down when failing edge comes, after realization is jittered to the failing edge of the partial sequence pulse signal
Waveform composition.Wherein, failing edge time delay under the action of programmable delay line, since the numerical value of time delay is PLC technology,
Therefore with control data variation at the time of failing edge arrives, by the failing edge for the train pulse signal that rising edge and failing edge synthesize
Just produce shake.Finally by data synthesis circuit by the partial sequence pulse for being loaded with shake and the part for not loading shake
Train pulse synthesizes to obtain the jittered train pulse signal of complete part failing edge.
Meanwhile a kind of jittered device of of the invention train pulse part failing edge also has the advantages that
(1), it by using programmable delay line and trigger pulse synthetic technology, realizes and adds on independent failing edge
Carry programmable jitter；
(2), the shake loaded can be controlled to obtain any type of shake, including sinusoidal jitter, triangle dither, height by data
This shake etc.；
(3), the jittered device of train pulse can load shake after signal source generates data content, the process of load without
External synchronization clock is needed, to signal source equipment without Compulsory Feature, only needs the input of signal source end and the control data of shake i.e.
Dither controller can be integrated into equipment, maximum feature is without redesigning signal source end.
(4), edge trembling is converted into the control of delay timing, obtains train pulse failing edge using high-resolution delay line
The high-accuracy control of shake is, it can be achieved that jitter resolution is better than 1ps.
Detailed description of the invention
Fig. 1 is a kind of jittered device principle block diagram of train pulse part of the invention failing edge；
Fig. 2 is the dotted box portion i.e. circuit diagram of the jittered device of train pulse part failing edge in Fig. 1；
Fig. 3 is the shake data load timing diagram of the jittered device of the failing edge of train pulse part shown in Fig. 2；
Fig. 4 is the timing waveform of the jittered device of the failing edge of train pulse part shown in Fig. 2.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is a kind of jittered device principle block diagram of train pulse part of the invention failing edge.
In the present embodiment, as shown in Figure 1, a kind of jittered device of train pulse part failing edge of the invention, comprising: prolong
Slow compensation circuit 1 and delay compensating circuit 2, synchronous circuit, signal interception circuit 1 and signal interception circuit 2, rising edge detection electricity
Road and failing edge detection circuit, address control unit, shake data storage circuitry, delay circuit, head delay control circuit, edge synthesis
Circuit and data synthesis circuit；
Each submodule is described in detail below:
Delay compensating circuit 1, for receiving sequence pulse signal DIN, and to train pulse signal DINDelay compensation is carried out,
Make the failing edge train pulse data-signal D of synchronous circuit output signalINArriving signal intercepts circuit；
Synchronous circuit, for receiving sequence pulse signal DINAnd gate-control signal, complete gate-control signal and train pulse signal
Synchronization, obtain the intercept signal for data intercept；
Signal intercepts circuit 1 and signal intercepts circuit 2, receives the sequence after 1 delay compensation of delay compensating circuit respectively
Column pulse signal and intercept signal intercept the train pulse signal after delay compensation by intercept signal, obtain outdoors
Signal and Men Nei signal；Signal intercepts circuit 2 and signal in door is fanned out into two-way, be respectively fed to rising edge detection circuit and under
Drop is along detection circuit；
Rising edge detection circuit and failing edge detection circuit, for extracting the rising edge information and failing edge letter of signal in door
Breath obtains narrow rising edge signal and the failing edge signal that narrows；
Address control unit is loaded to after clock signal and gate enable signal progress delay disposal as shake data
Signal is sent to delay circuit for data are shaken for controlling shake data storage circuitry；
Data storage circuitry is shaken, under the control of shake data load signal, shake data storage circuitry will be carried
The shake data of inherent delay are sent to delay control circuit；
Head delay circuit, for receiving the rising edge signal that narrows, and carries out controllable delay, realizes the failing edge signal that narrows
Negative shake under different jitter amplitudes, is then forwarded to along combiner circuit；
Delay control circuit, for receiving narrow failing edge signal and shake data, and in shake data load control letter
Number control under, will shake data be loaded into the failing edge signal that narrows, be then forwarded to along combiner circuit；
Along combiner circuit, the signal that head delay circuit and delay control circuit are sent is synthesized, is obtained comprising rising
Along the jittered signal of the failing edge of information and failing edge information；
Delay compensating circuit 2, for receiving signal outdoors, and on the door, external signal carries out delay compensation, make outdoors signal with
The total delay of the jittered signal of failing edge is identical, is re-fed into data synthesis circuit；
Signal outdoors after the jittered signal of failing edge and delay compensation is carried out exclusive or synthesis, obtained by data synthesis circuit
The jittered train pulse signal of part failing edge.
Fig. 2 is the dotted box portion i.e. circuit diagram of the jittered device of train pulse part failing edge in Fig. 1.
As shown in Fig. 2, in the present embodiment, the time delay t2 of address control unit and the time delay t5 for shaking data storage circuitry
The sum of be less than the clock cycle half T/2.It can guarantee in this way in the jitter sequences pulse signal of delay circuit in shake data
It arrives before loading signal, realizes the load of shake data.
In the present embodiment, signal interception circuit includes one and door, defeated when with two fan-in of door according to being all " 1 "
It is out " 1 ", output end is " 0 " as long as having an input terminal to be " 0 ".It is achieved that the interception function of signal.
Rising edge detection circuit selects a d type flip flop, and the D of d type flip flop terminates high level, and clock end connects rising edge letter
Number；When rising edge arrives, the output of the end d type flip flop Q becomes high level, and the reset signal as d type flip flop from low level, makes
D type flip flop output resets, and becomes low level from high level, and the end d type flip flop Q exports the rising edge signal that narrows.
Failing edge detection circuit selects a d type flip flop, and the D of d type flip flop terminates high level, and clock terminates failing edge letter
Number；When failing edge arrives, the output of the end d type flip flop Q becomes low level, and the reset signal as d type flip flop from high level, makes
D type flip flop output resets, and becomes high level from low level, and the end d type flip flop Q exports the failing edge signal that narrows.
Fig. 3 is the shake data load timing diagram of the jittered device of the failing edge of train pulse part shown in Fig. 2.
As shown in figure 3, in the present embodiment, shaking data DJITTERIt arrives in shake data load signal LOAD rising edge
When load, shake data load signal LOAD and clock signal clk have the time delay of t3, DJITTERIt is produced according to address generator
Raw address AD DRESS reads from shake data storage and obtains.All shake data load process are all in trigger signal
It is carried out within the scope of GATE_EN high level.When GATE_EN signal is low, shake data address controller stops generating address, protects
Stay GATE_EN be it is high when the last one address date, while shake data stop output, GATE_EN next time be it is high when
Then address when a upper GATE_EN is low continues to output shake data, ensures that shake data can have in this way
It is loaded on failing edge to effect.
Fig. 4 is the timing waveform of the jittered device of the failing edge of train pulse part shown in Fig. 2.
As shown in figure 4, in the present embodiment, being loaded with the train pulse signal D of shake in failing edgeOUTIt is trembled with not loading
There is the delay T generated by fixed delay line between dynamic train pulse signalDELAY.Shake size (Trj1 ... Trj3) does not exceed
By the pulsewidth of the rising edge and failing edge that narrow.
As shown in figure 4, GATE signal is Men Youxiao when being high level, the data input signal within the scope of high level all can
It is intercepted out, the signal for intercepting out is D after rising edge load shakeP1, it is D in signal outdoorsP2, finally by DP1
And DP2The jittered output signal D of failing edge in gate-control signal is synthesized by data synthesis circuitOUT。
It should be noted that in the present invention using train pulse waveform along decomposition and along synthetic method, by adjusting respectively
The precision for going out current moment to the rising edge and failing edge of train pulse waveform is completed in the delay of the delay and failing edge that save rising edge
Control converts the shake of waveform failing edge to the timing controlled of failing edge.Delay circuit, which can not only choose numerical control and may be programmed, to be prolonged
Slow line, can also choose the high-precision controllable delay line of analog level control, and shakes data and then complete shake number by DAC chip
According to the simulation of high-precision controllable delay line that control to analog level of digital-to-analogue conversion control.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (5)
1. a kind of jittered device of train pulse part failing edge characterized by comprising
First delay compensating circuit, for receiving sequence pulse signal DIN, and to train pulse signal DINDelay compensation is carried out, is made
The failing edge of synchronous circuit output signal is prior to train pulse signal DINArriving signal intercepts circuit；
Synchronous circuit, for receiving sequence pulse signal DINAnd gate-control signal, completion gate-control signal are same with train pulse signal
Step, obtains the intercept signal for intercepting train pulse；
First interception circuit and the second interception circuit, receive the train pulse after the first delay compensating circuit delay compensation
Signal and intercept signal intercept the train pulse signal after delay compensation by intercept signal, obtain outdoors signal and
Signal in door；Signal in door is fanned out into two-way by the second interception circuit, is respectively fed to rising edge detection circuit and failing edge inspection
Slowdown monitoring circuit；
Rising edge detection circuit and failing edge detection circuit, for extracting the rising edge information and failing edge information of signal in door,
Obtain narrow rising edge signal and the failing edge signal that narrows；
Address control unit loads letter as shake data to after clock signal and gate enable signal progress delay disposal
Number, delay circuit is sent to by data are shaken for controlling shake data storage circuitry；
Data storage circuitry is shaken, under the control of shake data load signal, it is intrinsic that shake data storage circuitry will be carried
The shake data of delay are sent to delay control circuit；
Head delay circuit, for receiving the rising edge signal that narrows, and carries out controllable delay, realizes the difference for the failing edge signal that narrows
Negative shake under jitter amplitude, is then forwarded to along combiner circuit；
Delay control circuit, for receiving narrow failing edge signal and shake data, and in shake data load control signal
Under control, shake data are loaded into the failing edge signal that narrows, are then forwarded to along combiner circuit；
Along combiner circuit, the signal that head delay circuit and delay control circuit are sent is synthesized, obtains believing comprising rising edge
The jittered signal of failing edge of breath and failing edge information；
Second delay compensating circuit, for receiving signal outdoors, and on the door, external signal carries out delay compensation, make outdoors signal under
Drop is identical along the total delay of jittered signal, is re-fed into data synthesis circuit；
Signal outdoors after the jittered signal of failing edge and delay compensation is carried out exclusive or synthesis, obtains part by data synthesis circuit
The jittered train pulse signal of failing edge.
2. a kind of jittered device of train pulse part failing edge according to claim 1, which is characterized in that the address
The time delay of controller and the sum of the intrinsic time delay of the shake data storage circuitry are less than the half of clock cycle.
3. a kind of jittered device of train pulse part failing edge according to claim 1, which is characterized in that described is upper
It rises and selects a d type flip flop along detection circuit, the D of d type flip flop terminates high level, and clock end connects rising edge signal；Work as rising edge
When arrival, the end Q of d type flip flop, which is exported from low level, becomes high level, and the reset signal as d type flip flop, keeps d type flip flop defeated
It resets out, and low level is become from high level, the end d type flip flop Q exports the rising edge signal that narrows.
4. a kind of jittered device of train pulse part failing edge according to claim 1, which is characterized in that under described
Drop selects a d type flip flop along detection circuit, and the D of d type flip flop terminates high level, and clock terminates failing edge signal；Work as failing edge
When arrival, the output of the end d type flip flop Q becomes low level, and the reset signal as d type flip flop from high level, exports d type flip flop
It resets, and high level is become from low level, the end d type flip flop Q exports the failing edge signal that narrows.
5. a kind of jittered device of train pulse part failing edge according to claim 1, which is characterized in that described prolongs
Slow control circuit chooses the high-precision controllable delay line of numerical control programmable delay line or analog level control.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710446127.XA CN107271890B (en) | 2017-06-14 | 2017-06-14 | A kind of jittered device of train pulse part failing edge |
| US15/729,298 US10156603B1 (en) | 2017-06-14 | 2017-10-10 | Apparatus for adding jitters to the edges of a pulse sequence |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710446127.XA CN107271890B (en) | 2017-06-14 | 2017-06-14 | A kind of jittered device of train pulse part failing edge |
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| CN107271890A CN107271890A (en) | 2017-10-20 |
| CN107271890B true CN107271890B (en) | 2019-07-12 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109142820B (en) * | 2018-09-26 | 2021-07-13 | 深圳市鼎阳科技股份有限公司 | Pulse wave generating device |
| CN110995249B (en) * | 2019-12-18 | 2023-05-30 | 电子科技大学 | Clock jitter generating device |
| CN113640656B (en) * | 2021-07-30 | 2024-04-09 | 深圳速跃芯仪科技有限公司 | Digital test pattern generation method based on time delay |
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