JP2005101120A - Compound semiconductor wafer and its cleavage method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor wafer wherein a cleavage plane is formed with high yield, in a wafer in which an orientation flat or an index flat is formed by the cleavage surface, and also to provide its cleavage method. <P>SOLUTION: The rough-surface finish 7 is processed in one side 3 of the wafer 1 with different roughness in the front surface from that in the back surface, at a previous process of the cleavage process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a compound semiconductor wafer that can be easily cleaved and a cleavage method thereof.

  GaAs wafers are widely used as substrates for light receiving, light emitting elements, high frequency elements and the like. Ions are directly implanted into these GaAs wafers with an ion implantation apparatus, or an epitaxial layer (film) is formed on the wafer surface to produce a semiconductor element.

  As for the size of a GaAs wafer used as a substrate of a light emitting element such as a semiconductor laser or an LED, there are many diameters of φ2 inch (50 mm) and φ3 inch (76 mm).

  Such a GaAs wafer is obtained by cylindrically grinding a GaAs single crystal with a predetermined diameter, slicing with a predetermined thickness, chamfering a peripheral portion with a chamfering machine, aligning the wafer thickness by lapping, and etching with an etching solution, Manufactured by applying a back surface of a wafer to a ceramic plate, applying it to a plate board with the front side down and a polishing cloth of a polisher, and polishing it onto a mirror surface while dropping the polishing liquid from above.

  Among these manufacturing processes, the process of processing the shape of the periphery of the wafer is a chamfering process. In the chamfering process, the periphery of the sliced wafer is chamfered with a rotating grindstone and processed to a desired diameter, and the orientation flat or index flat for identifying the orientation or front and back of the wafer on the periphery is called respectively. Machining a straight part. One of the purposes of chamfering the outer peripheral portion is to prevent the wafer from being cracked or partially damaged during wafer transport in the processing steps after chamfering or in the process of manufacturing elements.

  1 and FIG. 3 according to the embodiment of the present invention will be described in detail. In a general wafer end grinding machine (chamfering machine), a sliced pre-chamfered wafer 1 (see the dotted line in FIG. 1). Is vacuum-adsorbed on the processing table, and the wafer outer peripheral portion 20 is chamfered by applying the wafer 10 itself to a grindstone 30 rotating at a high speed as shown in FIG. The grindstone 30 has a grinding groove 31 composed of a tapered portion 32 and an R (R) portion 35. The upper surface of the wafer outer peripheral portion 20 is applied to the upper tapered portion (upper grinding surface 33) of the grinding groove 31, and the lower surface is applied to the lower tapered portion (lower grinding surface 34) of the grinding groove 31. Thus, the chamfered portion 21 is chamfered to form a tapered portion 22 that follows the ground surface as shown in FIG.

  On the other hand, in FIG. 1A, reference numeral 9 denotes a linear portion of an orientation or index flat for identifying the orientation or front / back of the wafer. In a compound semiconductor wafer used as a substrate for a semiconductor laser, such orientation or index flat is used. 19 may be formed by a cleaved surface without chamfering.

  A single crystal is grown so as to have a certain crystal direction, and a wafer surface produced by slicing and polishing the single crystal also has a certain direction. In most cases, the wafer surface of a semiconductor wafer such as a GaAs wafer is inclined in a (100) direction, an equivalent direction, or an angle from this direction (such a wafer is called an off-wafer, an off-substrate, etc.). .

  Taking the (100) wafer as an example, the position of the orientation flat to be processed is one of the four directions (0-1-1), (01-1), (011), and (0-11). In many cases, the index flat is processed in one of the 90 ° and 270 ° directions. These orientation flats and index flats are often chamfered in the same way as other peripheral parts, but the orientation part is not chamfered in <100> wafers or off-wafers that are used as substrates for semiconductor laser diodes. In most cases, it is formed with a cleavage plane.

  This is due to the following reasons.

  In a semiconductor laser diode (hereinafter referred to as LD), an optical waveguide constituting a resonator is formed in a semiconductor crystal. The optical waveguide has an elongated shape with a width of several μm and a length of several hundreds of μm, and reflecting mirrors are formed at both ends of the LD chip. In many cases, the longitudinal direction of the waveguide is formed in a direction perpendicular to the orientation flat (OF: <011> plane). This reflecting mirror is automatically formed by “cleavage” unique to the III-V compound semiconductor process. To set the light reflectance of the reflector to a predetermined value with good yield, it is necessary to make the optical waveguide and the reflector completely vertical (90 degrees). Orientation flat (OF) settings are typically used.

  When a laser diode is manufactured in this way, an epitaxial layer or the like is formed on a wafer, and a chip is cut out by cleavage perpendicular to the orientation flat and the index flat. If the flat is formed with a cleavage plane, there is theoretically no deviation from the <011> direction, and the chip cannot be cut out well as described above.

  Conventionally, in the case of a wafer whose orientation flat or index flat is a cleavage plane, the cleavage plane is formed by drawing a few millimeters of a scribing line with a diamond pen at the location to be cleaved on the outer periphery of the wafer and holding this part by hand. The wafer is cut by concentrating the force on the part, or formed by using a dedicated cutting machine.

  When forming such a cleavage plane, if the wafer cannot be broken well, a minute step is formed on the cleavage plane, or the cracked surface becomes a curved surface, which is not an ideal <110> plane. End up.

Although it is not a technique to break the wafer as described above as a conventional technique, it is known that cleavage is generated by applying a heat treatment such as periodic thermal cycle or rapid cooling after scratching the semiconductor wafer (for example, , See Patent Document 1). This is because a compound semiconductor layer for infrared detection element formation is scratched on a semiconductor wafer in which a compound semiconductor layer for infrared detection element formation is epitaxially grown on a single crystal semiconductor substrate, and the single crystal semiconductor substrate and the infrared detection element formation thereon are formed. This is a technique for causing cleavage only in the compound semiconductor layer for forming an infrared detection element by strain based on the difference in thermal expansion coefficient from the compound semiconductor layer for use.
JP-A-8-130297

  However, the technique of Patent Document 1 causes cleavage only in the compound semiconductor layer for forming the infrared detection element due to strain based on the difference in thermal expansion coefficient between the single crystal semiconductor substrate and the compound semiconductor layer for forming the infrared detection element thereon. Therefore, the method cannot be applied to cleaving the entire wafer in the stacking direction of the epitaxial growth layer, that is, dividing the wafer well and forming the orientation flat or the index flat by the cleavage plane.

  As described above, in the case of a wafer in which an orientation flat or index flat is formed with a cleavage plane, the cleavage plane is formed by drawing a scribing line with a diamond pen at the location to be cleaved on the outer periphery of the wafer with a few mm (scribe line). Formation of traces), holding this part by hand and concentrating the force on this part to cut the wafer, or using a dedicated cutting machine. That is, a scribe line is formed on the surface of the wafer, and the semiconductor wafer is cleaved by applying a force to the semiconductor wafer from the side of the scribe line surface.

  When forming such a cleavage plane, if the wafer cannot be broken well, a minute step is formed on the cleavage plane, or the cracked surface becomes a curved surface, which is not an ideal <110> plane. Such a wafer cannot be used as a product for the following reasons. That is, in order to manufacture a laser diode, as described in the background art, cleavage is performed so that it is perpendicular to the orientation flat, but there are steps on the cleavage surface or a curved surface. This is because it becomes difficult to cleave vertically.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a compound semiconductor wafer capable of forming a cleavage plane with a high yield in a wafer in which an orientation flat or an index flat is formed by a cleavage plane, and a cleavage method thereof. There is to do.

  In order to achieve the above object, the present invention is configured as follows.

  The compound semiconductor wafer according to the invention of claim 1 is a compound semiconductor wafer obtained by cutting a compound semiconductor crystal, wherein an orientation flat or an index flat for identifying the orientation of the wafer is formed on a cleavage plane of the crystal. In the compound semiconductor wafer, a roughening process for differentiating the surface roughness between the front surface and the back surface is performed on one side of the wafer in a step before the processing step of cleaving.

  According to a second aspect of the present invention, in the compound semiconductor wafer according to the first aspect, the roughening treatment is performed by etching using an etching solution.

  A third aspect of the present invention is the compound semiconductor wafer according to the first aspect, wherein the roughening treatment is performed by lapping.

  A method for cleaving a compound semiconductor wafer according to a fourth aspect of the present invention comprises forming a scribe line on a surface subjected to the roughening treatment of the wafer according to the first, second, or third aspect. The semiconductor wafer is cleaved by applying a force to the semiconductor wafer from the side.

  In the first, second, or third invention, the present invention can be applied regardless of whether the wafer material is GaAs, InP, InSb, InAs, or GaP.

<Key points of the invention>
In the manufacturing process of a wafer in which the orientation flat is formed by a cleavage plane, or a wafer in which the index flat is formed by a cleavage plane, before the process of forming the cleavage plane, the opposite side of the surface where the marking line for cleavage is inserted Etching or lapping the surface of the surface to add a process intended to make the surface where the marking line is inserted rougher than the surface where the marking line is not included. Therefore, it is important to provide a method for manufacturing a wafer in which an orientation flat or an index flat is formed by a cleavage plane with a high yield and a wafer obtained thereby.

  As a factor for facilitating the cleaving work, it is conceivable that the surface on which the marking line is inserted is rougher than the surface on which the marking line is not inserted.

  Processing damage occurs on the surface of the wafer when it is sliced from the ingot to the wafer. This damage causes warpage of the wafer. Since the roughness of the wafer surface after slicing is the same on both sides, the degree of warpage is also the same. However, when the roughness of one surface is increased, it is estimated that a difference occurs in the degree of warpage between the two surfaces. In the cleaving work, since the cleaving is performed from the surface side where the needle is inserted, it is considered that the warpage will be larger if the degree of roughness of this surface is increased, so that the cleaving will proceed easily.

  According to the present invention, in the compound semiconductor wafer in which the orientation or index flat is formed by the cleavage plane, the surface roughness of the front surface and the back surface is made different by roughening one surface of the wafer. The balance of the degree of warpage is lost, and a force is generated on the wafer so that the surface subjected to the roughening process becomes a convex side (force in a direction in which warpage occurs). Therefore, a scribe line is formed on the roughened surface of the wafer, and when the semiconductor wafer is cleaved by applying a force to the semiconductor wafer from the side of the scribe line forming surface, the cleavage surface is increased. It becomes possible to form in the yield.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

  FIG. 1 shows an orientation flat 8 for cleaving a crystal orientation of a compound semiconductor wafer (wafer 1 before chamfering) obtained by cutting a compound semiconductor crystal such as GaAs, InP, InSb, InAs, or GaP. A semiconductor wafer 10 is shown in which a wafer outer peripheral portion 20 is formed by chamfering and grinding the periphery into a circle (chamfered portion 21) as shown in FIG. A characteristic feature of this semiconductor wafer 10 is that a roughening process 7 for making the surface roughness of the front surface 3 and the back surface 5 different is performed on one surface 3 of the wafer in a step before the processing step of cleaving. It is a point that has been. A surface 3 (referred to as a “front surface” for convenience of explanation) on which the surface of the wafer is subjected to the roughening treatment 7 is a surface (scribe surface forming surface) that will be a side on which a scribe line will be formed later. The semiconductor wafer is cleaved by applying a force to the semiconductor wafer from the forming surface (front surface 3) side.

  The semiconductor wafer 10 is manufactured through the following series of manufacturing processes. That is, after the outer periphery of the single crystal ingot manufactured by the single crystal pulling method is performed, slicing is performed with an inner peripheral saw or a wire saw to obtain the slice wafer 1 (slicing step A).

  Next, a roughening process 7 is performed on one surface (front surface) 3 of the slice wafer 1 to make the surface roughness different from that of the back surface 5. The roughening process 7 of the wafer is performed by etching using an etching solution or by lapping (roughening step B).

  Next, for example, an orientation flat (OF) 8 for positioning in the crystal direction is formed on the slice wafer 1 using the cleavage plane of the crystal. That is, by using a diamond pen and scratching and scribing the wafer, a scribing mark is formed on the front surface 3 subjected to the roughening treatment of the wafer, and the semiconductor wafer 1 is formed on the side of the scribing mark forming surface. On the other hand, by applying a force, the crystal of the semiconductor wafer 1 is cleaved from the scribe line, and the cleaved surface is used as the OF portion (scribing step C).

  At this time, the front surface 3 of the wafer 1 has been subjected to a roughening treatment, and the surface roughness of the front surface and the back surface is different, so that the wafer 1 has a roughened surface. A force that tends to be on the convex side (a force that causes warping) is born. This force acts in the direction of assisting cleavage in the operation of cleaving the semiconductor wafer. Therefore, when a scribe line is formed on the front surface 3 subjected to the roughening treatment 7 of the wafer and a force is applied to the semiconductor wafer 1 from the side of the scribe line forming surface, the semiconductor wafer 1 can be easily formed. And is cleaved accurately.

  Next, the chamfering process D is entered, the wafer outer peripheral portion 20 is ground into a circle while leaving the cleaved surface 9 of the wafer, and further, the wafer outer peripheral portion 20 excluding the cleaved portion (portion of the orientation flat 8), To be precise, chamfering is performed on the ridgeline between the wafer outer peripheral portion 20 and the front and back surfaces of the wafer by beveling with a grinding wheel (chamfering step D).

  In this way, the wafer outer peripheral portion 20 excluding the cleaved surface 9 of the wafer is ground into a circle, and the wafer outer peripheral portion 20 is chamfered by beveling (chamfering step D), and then uniform thickness is obtained by double-sided lapping. Finish to have parallelism, flatness and some surface roughness (double-sided lapping process E).

  The wrapped wafer obtained as described above is subjected to etching with acid or alkali to remove the processing strain and remove the processing damage layer (etching process), and then mirror finished by mechanochemical polishing (single side) Primary mirror polishing process, single-sided mirror polishing process).

  In order to confirm the effect of the present invention, the compound semiconductor wafers of Example 1 and Comparative Example 2 were prototyped as follows, and the two were compared.

<Example 1>
(100) About 100 GaAs wafers having a thickness of 600 μm and a diameter of 78 mm, one side of the (100) GaAs wafer is adsorbed on an adsorption pad, and the opposite side is adsorbed with ammonia water, hydrogen peroxide water, and pure water at 1.5. The sample was immersed in an etching solution prepared by mixing at a volume ratio of 1: 5.5, and etched by 5 μm while rocking.

  After etching, 10 wafers were randomly selected from these wafers, and the roughness between the adsorbed surface and the non-adsorbed etched surface was measured. The roughness of the adsorbed surface was an average value of 10 sheets, Ra = 0.5 μm, and the roughness of the etched surface without adsorption was an average value of 10 sheets, Ra = 0.2 μm.

  These 1000 wafers were cleaved from this place by putting a needle into the surface that was not etched and concentrating the force manually on the place where the needle was put. This cleaved surface was chamfered so as to have an orientation flat, and a wafer having a diameter of 76 mm and an orientation flat length of 22 mm was produced.

  With respect to all the wafers, the deviation angle of the orientation flat from the <011> direction was measured using an X-ray diffraction method. A histogram of the measurement results of the deviation angle is shown in FIG.

<Comparative Example 1>
Of 1000 (100) GaAs wafers having a thickness of 600 μm and a sliced diameter of 78 mm, 10 sliced GaAs wafers were randomly selected from these wafers, and the roughness of both sides was measured. The roughness of one surface was an average value of 10 sheets, Ra = 0.5 μm, and the roughness of the other surface was an average value of 10 sheets, Ra = 0.5 μm.

  These 1000 wafers were cleaved from this place by putting a needle into the surface in the same direction as in Example 1 and manually concentrating the force on the place where the needle was put. This cleaved surface was chamfered so as to have an orientation flat, and a wafer having a diameter of 76 mm and an orientation flat length of 22 mm was produced.

  For all the wafers, the angle of deviation of the orientation flat from the <011> direction was measured using X-ray diffraction. A histogram of the measurement results of the deviation angle is shown in FIG.

  From the results of Example 1 and Comparative Example 1 described above, when processing a wafer having an orientation flat formed on a cleavage plane, before performing the processing, the opposite side of the surface into which the needle for cleaving is inserted is processed. It can be seen that the cleaved surface can be processed with a high yield by adding a process for making the surface roughness smaller than the surface roughness of the needle.

<Other embodiments>
In Example 1, the roughening treatment was performed by etching, but instead of etching, the surface on the opposite side of the surface into which the needle for cleaving work was placed was made rougher than the surface into which the needle was inserted. Even when the cleaving operation was carried out after reducing the size, the same effect as in Example 1 was obtained.

  In the case of the above embodiment, the cleavage plane of the orientation flat or index flat is formed by drawing a scribing line with a diamond pen at the location to be cleaved on the outer periphery of the wafer by several mm (formation of scribing marks). Although the wafer was cut by concentrating the force on this part, a dedicated cutting machine or the like can also be used.

  FIG. 2 shows a cleavage method called a three-point bending method. This is formed by arranging a plurality of scribe streaks 2 on one end edge of the surface of the semiconductor wafer 1 (the scribe streaks 2 are provided at the boundary position of the element forming region of the semiconductor wafer 1). A pair of fulcrum members 4a and 4b are arranged parallel to the scribe line 2 with the scribe line 2 sandwiched between them, and the scribe line is formed on the back surface 5 opposite to the scribe line forming surface 3. Similarly, the fulcrum member 6 is arranged in parallel to the scribe line 2 at the position opposite to the scribe line 2, and the cleavage stress is concentrated on the scribe line 2 by applying the fulcrum forces P2, P1, and F1 from these fulcrum members. Then, the semiconductor wafer 1 is cleaved from the position of the scribe mark 2 on the ZOY plane.

  In any case, the cleavage method of the present invention is an operation for forming a scribe line on the surface of the wafer and cleaving the semiconductor wafer by applying a force to the semiconductor wafer from the side of the scribe line formation surface. Can be applied.

The state after forming the orientation flat by cleavage of the compound semiconductor wafer of this invention is shown, (a) is a top view, (b) is sectional drawing. It is a figure which shows the wafer cleaving method by a three-point bending method. It is the figure which showed the mode when chamfering a wafer outer peripheral part. It is the figure which showed frequency distribution of the shift | offset | difference angle from the <011> direction of the surface orientation of the orientation flat of 100 wafers produced by Example 1 of this invention. It is the figure which showed frequency distribution of the shift | offset | difference angle from the <011> direction of the surface orientation of the orientation flat of 100 wafers produced by the comparative example 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Scribe mark 3 Front side (Roughening surface: Scribe mark formation surface)
5 Back side (back side opposite to scribe line formation side)
7 Roughening treatment 8 Orientation flat 9 Cleaved surface 10 Wafer 20 Wafer peripheral portion 21 Chamfered portion 22 Tapered portion

Claims (4)

A compound semiconductor wafer obtained by cutting a compound semiconductor crystal, wherein the orientation flat or index flat for identifying the orientation of the wafer is formed on the cleavage plane of the crystal,
A compound semiconductor wafer, wherein a roughening process is performed on one surface of a wafer to make the surface roughness different between a front surface and a back surface in a step prior to a cleaving process. The compound semiconductor wafer according to claim 1,
A compound semiconductor wafer, wherein the roughening treatment is performed by etching with an etchant. The compound semiconductor wafer according to claim 1,
A compound semiconductor wafer, wherein the roughening treatment is performed by lapping.   4. A scribe line is formed on the surface of the wafer subjected to the roughening treatment according to claim 1, 2 or 3, and the semiconductor wafer is cleaved by applying a force to the semiconductor wafer from the side of the scribe line surface. A method for cleaving a compound semiconductor wafer.

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