TWI807347B - Semiconductor substrate and fabrication method of semiconductor device - Google Patents

Abstract

A semiconductor substrate includes a silicon carbide wafer having a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface. There is a first inclined surface and/or a first curved surface between the first surface and the side surface. There is a second inclined surface and/or a second curved surface between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

Description

Semiconductor substrate and method for manufacturing semiconductor device

The present invention relates to a semiconductor substrate, and in particular to a semiconductor substrate including a silicon carbide wafer and a method for manufacturing a semiconductor device.

In the semiconductor industry, a wafer manufacturing method includes forming an ingot first, and then slicing the ingot to obtain wafers. Crystal anchors are manufactured, for example, in a high-temperature environment. In some anchor manufacturing processes, the seed crystal is placed in a high-temperature furnace, the seed crystal contacts gaseous or liquid raw materials, and semiconductor materials are formed on the surface of the seed crystal until an anchor with a desired size is obtained. Crystal anchors can have different crystalline structures depending on the manufacturing method and raw materials.

After the growth of the anchor is completed, the anchor is cooled down to room temperature by furnace cooling or other means. After the crystal anchor cools down, use a cutting machine to remove the poorly shaped head and tail ends of the anchor, and then use a grinding wheel to grind the anchor to a desired size (for example, 3 inches to 12 inches). In the manufacturing process of some anchors, a flat edge or V-shaped groove is ground on the edge of the anchor. This flat edge or V-groove is suitable as a marker of the crystallographic orientation of the anchor. Then the wafer is sliced to obtain multiple wafers (Wafers). In some cases, the corners of the wafers are prone to cracking due to collisions.

The invention provides a semiconductor substrate, which can solve the problem of corner cracking of silicon carbide wafers after grinding.

The invention provides a method for manufacturing a semiconductor device, which can solve the problem of corner cracking of a silicon carbide wafer after grinding.

At least one embodiment of the present invention provides a semiconductor substrate. The semiconductor base includes a silicon carbide wafer, which has a first surface, a second surface parallel to the first surface, and side surfaces perpendicular to the first surface and the second surface. A first inclined surface and/or a first arc surface are included between the first surface and the side surface. A second inclined surface and/or a second arc surface are included between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

At least one embodiment of the present invention provides a method of manufacturing a semiconductor device, including: providing a silicon carbide wafer; and processing an edge of the silicon carbide wafer. After processing, the silicon carbide wafer includes a first surface, a second surface parallel to the first surface, and side surfaces perpendicular to the first surface and the second surface. A first inclined surface and/or a first arc surface are included between the first surface and the side surface. A second inclined surface and/or a second arc surface are included between the second surface and the side surface. In the first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface.

1A to 1H are schematic diagrams of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

Please refer to FIG. 1A , which is a perspective view of the cutting process of the crystal anchor 100 . The anchor 100 is cut with a cutting tool 200 . The cutting tool 200 includes a fixing device 210 , a roller 220 and a cutting wire 230 . The fixing device 210 is used for fixing the crystal anchor 100 . The cutting wire 230 includes a steel wire and abrasive grains (such as diamond grains) on the steel wire. The dicing wire 230 is wound on the roller 220 to define a plurality of cutting segments, and the dicing wire 230 is used to cut the peg 100 repeatedly, so as to cut the peg 100 into tens to hundreds of wafers. In this embodiment, the anchor 100 is cut with a diamond wire, but the invention is not limited thereto. In other embodiments, the anchor 100 is cut by a knife, laser, water jet or other methods.

In this embodiment, the material of the anchor 100 includes silicon carbide. After dicing, the anchor 100 forms a plurality of silicon carbide wafers.

1B to 1H are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1B , a silicon carbide wafer 110 is provided. In this embodiment, the silicon carbide wafer 110 includes a first surface 112 , a second surface 114 parallel to the first surface 112 , and a side surface 116 perpendicular to the first surface 112 and the second surface 114 before processing. In some embodiments, before processing the silicon carbide wafer 110, the first surface 112 is connected to the side 116, and the angle between the first surface 112 and the side 116 is approximately a right angle, and the second surface 114 is connected to the side 116, and the angle between the second surface 114 and the side 116 is approximately a right angle.

Edge 116 of silicon carbide wafer 110 is machined. For example, the edge of the silicon carbide wafer 110 is ground by the grinding head 300 . The grinding head 300 includes a first protruding portion 310 and a second protruding portion 320 . The first protruding portion 310 is used for processing the edge of the upper side of the silicon carbide wafer 110 , that is, the portion of the side surface 116 close to the second surface 114 . The second protruding portion 320 is used for processing the edge of the lower side of the silicon carbide wafer 110 , that is, the portion of the side surface 116 close to the first surface 112 . The shape of the first protrusion 310 is different from the shape of the second protrusion 320 . In this embodiment, the first protruding portion 310 is more protruding than the second protruding portion 320 in the direction toward the SiC wafer 110 . Therefore, when the SiC wafer 110 is rotated to grind the edge of the SiC wafer 110 , the second protruding portion 320 removes more SiC wafer 110 than the first protruding portion 310 .

Referring to FIG. 1C , the silicon carbide wafer 110 includes a first surface 112 a , a second surface 114 a parallel to the first surface 112 a and a side surface 116 a perpendicular to the first surface 112 a and the second surface 114 a after processing. A first inclined surface and/or a first arc surface are included between the first surface 112a and the side surface 116a. In this embodiment, a first arc surface 113 is included between the first surface 112a and the side surface 116a. A second inclined surface and/or a second arc surface are included between the second surface 114a and the side surface 116a. In this embodiment, a second arc surface 115 is included between the second surface 114a and the side surface 116a.

In the first direction D1 parallel to the first surface 112a, the distance A1 between the first surface 112a and the side surface 116a is greater than the distance A2 between the second surface 114a and the side surface 116a. In the second direction D2 parallel to the side surface 116a, the distance B1 between the first surface 112a and the side surface 116a is greater than the distance B2 between the second surface 114a and the side surface 116a. The first direction D1 is perpendicular to the second direction D2. In some embodiments, A1:B1 is 150:80 to 250:160, and A2:B2 is 60:40 to 80:60. In this embodiment, the distance A1 is greater than the distance A2, and the area of the second surface 114a is greater than the area of the first surface 112a. In some embodiments, the distance A1 is 150 microns to 250 microns, the distance B1 is 80 microns to 160 microns, the distance A2 is 60 microns to 80 microns, and the distance B2 is 40 microns to 60 microns.

In some embodiments, before or after processing the edge 116 of the silicon carbide wafer 110 , a physical polishing process and/or a chemical-mechanical polishing process (Chemical-Mechanical Polishing) is performed on the silicon carbide wafer 110 . In the chemical mechanical polishing process, the surface (eg, the first surface and/or the second surface) of the silicon carbide wafer 110 is polished with a corrosive polishing liquid and abrasive materials together with a polishing pad. The corrosive polishing liquid in the chemical mechanical polishing process can chemically react with the wafer surface, transforming the uneven part of the wafer surface into a material with less hardness, so that the abrasive can more easily remove the uneven part of the wafer surface. In some examples, after the chemical mechanical polishing process, the silicon carbide wafer 110 is annealed, so that atoms inside the silicon carbide wafer 110 can be arranged more orderly, thereby reducing crystal defects inside the wafer.

Referring to FIG. 1D , an epitaxial layer 120 is formed on the second surface 114 a. In some embodiments, the first surface 112a is a carbon surface, and the second surface 114a is a silicon surface. Therefore, forming the epitaxial layer 120 on the second surface 114a can obtain better epitaxial quality. In this embodiment, the epitaxial layer 120 is formed on the second arc surface 115 and extends from the second arc surface 115 to the center of the second surface 114a. With the arrangement of the second curved surface 115 , the epitaxial layer 120 will not be formed on the edge with a right angle or an acute angle, thereby reducing the generation of cracks in the epitaxial layer 120 due to local stress concentration at the edge at a right angle or an acute angle.

Referring to FIG. 1E , a plurality of semiconductor elements 130 are formed on or in the epitaxial layer 120 . In FIG. 1E , the semiconductor device 130 is located above the upper surface of the epitaxial layer 120 , but the invention is not limited thereto. In other embodiments, the semiconductor device 130 is embedded in the epitaxial layer 120 . The method of forming the semiconductor device 130 includes, for example, ion implantation, lithography etching, chemical vapor deposition, material vapor deposition, atomic layer deposition or other processes.

Referring to FIG. 1E and FIG. 1F , a grinding process is performed on the first surface 112 a to reduce the thickness of the silicon carbide wafer 110 . The first surface 112 a is ground to obtain the third surface 118 , and the angle α between the third surface 118 and the edge of the SiC wafer 110 a is a right angle or an obtuse angle. For example, if the first surface 112a is ground until the first arc surface 113 is completely removed, then the angle between the third surface 118 and the side surface 116a is a right angle. If the grinding is not performed until the first arc surface 113 is completely removed, the angle between the obtained third surface 118 and the remaining first arc surface 113 is an obtuse angle.

If the distance A2 is increased so that the distance A2 is equal to or greater than the distance A1, the side surface 116a is easily removed completely after grinding, so that the third surface 118 obtained after grinding is connected to the first arc surface 115, and an acute angle is formed, which will cause the edge of the silicon carbide wafer 110 to be easily broken, as shown in FIG. 2 . Therefore, the distance A1 being greater than the distance A2 can make the SiC wafer 110 less likely to break after performing the grinding process on the first surface 112a, thereby improving the process yield. In addition, the larger the distance A1, the smaller the area of the first surface 112a, and the smaller the area of the first surface 112a, the easier the grinding process of the first surface 112a is.

In some embodiments, the thickness T of the silicon carbide wafer 110 before the grinding process is about 250 microns to 500 microns, and the thickness T' of the silicon carbide wafer 110 after the grinding process is about 50 microns to 150 microns, but the invention is not limited thereto. The thickness of the silicon carbide wafer 110 can be adjusted according to actual needs.

Referring to FIG. 1G , multiple conductive layers 144 , 148 and multiple insulating layers 142 , 146 are formed on the semiconductor device 120 . The conductive layers 144 , 148 and the insulating layers 142 , 146 constitute a redistribution layer (Redistribution Layer) 140 , and are electrically connected to the semiconductor device 120 .

In some embodiments, an encapsulation material (not shown) is formed on the redistribution layer 140 to protect the redistribution layer 140 and the semiconductor device 120 , but the invention is not limited thereto.

Referring to FIG. 1H , the silicon carbide wafer 110 and the redistribution layer 140 are cut to obtain a plurality of wafers 10 . The wafer 10 includes a silicon carbide substrate 110a, an epitaxial layer 120a, a semiconductor device 130 and a redistribution layer 140a. In some embodiments, wafer 10 also includes encapsulation material.

Based on the above, before grinding the first surface 112a, the distance A1 is greater than the distance A2 to make the SiC wafer 110 less likely to break after performing the grinding process on the first surface 112a, thereby improving the process yield.

FIG. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. It must be noted here that the embodiment in FIG. 3 follows the component numbers and part of the content of the embodiment in FIG. 1A to FIG. 1H , where the same or similar numbers are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The difference between the silicon carbide wafer 110a in FIG. 3 and the silicon carbide wafer 110 in FIG. 1C is that: the silicon carbide wafer 110a includes a first slope 113A between the first surface 112a and the side surface 116a, and a second slope 115A between the second surface 114a and the side surface 116a.

Referring to FIG. 3 , the first inclined surface 113A connects the first surface 112 a and the side surface 116 a, and the fillet angle between the first inclined surface 113A and the first surface 112 a is β1. The second inclined surface 115A connects the second surface 114a and the side surface 116a, and the fillet angle between the second inclined surface 115A and the second surface 116a is β2, and β1 is greater than β2. In some embodiments, β1 is 130r (µm) to 200r (µm), and β2 is 100r (µm) to 140r (µm). The rounding angle between the first slope 113A and the side surface 116a is γ1, the rounding angle between the second slope 115A and the side surface 116a is γ2, and γ2 is greater than γ1. In some embodiments, γ1 is 110° to 130° and γ2 is 105° to 125°.

Based on the above, before grinding the first surface 112a, the distance A1 is greater than the distance A2 to make the SiC wafer 110 less likely to break after performing the grinding process on the first surface 112a, thereby improving the process yield.

FIG. 4 is a schematic cross-sectional view of a wafer according to an embodiment of the invention. It must be noted here that the embodiment in FIG. 4 follows the component numbers and partial content of the embodiment in FIG. 3 , wherein the same or similar numbers are used to denote the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and details are not repeated here.

The difference between the silicon carbide wafer 110b in FIG. 4 and the silicon carbide wafer 110a in FIG. 3 is that the silicon carbide wafer 110b includes a first slope 113A and a third slope 113B between the first surface 112a and the side surface 116a.

In this embodiment, the angle of the fillet between the first slope 113A and the third slope 113B is δ1. Since the first surface 112a and the side surface 116a include the first slope 113A and the third slope 113B, the angle γ1 of the fillet between the third slope 113B and the side 116a and the angle β1 of the fillet between the first surface 112a and the side 116a can be increased, thereby further reducing the cracking of the silicon carbide wafer 110b when grinding the first surface 112a.

10: Wafer 100: crystal anchor 110, 110a, 110b: silicon carbide wafer 112, 112a: the first side 113: The first arc surface 113A: first bevel 113B: the third slope 114, 114a: the second side 115: Second arc surface 115A: Second slope 116, 116a: side 118: The third side 120: epitaxial layer 130: Semiconductor components 140:Redistribution layer 142, 146: insulating layer 144, 148: conductive layer 200: cutting tools 210: Fixtures 220: roller 230: cutting line 300: grinding head 310: first protrusion 320: second protrusion A1, A2, B1, B2: Distance D1: the first direction D2: Second direction Thickness: T, T' α: included angle β1, β2, γ1, γ2, δ1: angle

1A to 1H are schematic diagrams of a manufacturing method of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of a wafer according to an embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a wafer according to an embodiment of the invention.

110:Silicon carbide wafer

112a: first side

113: The first arc surface

114a: second side

115: Second arc surface

116a: side

A1, A2, B1, B2: Distance

D1: the first direction

D2: Second direction

Claims (15)

A semiconductor substrate, comprising: a silicon carbide wafer, having a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface, wherein in a first direction parallel to the first surface, a distance A1 between the first surface and the side surface is greater than a distance A2 between the second surface and the side surface, wherein: a first slope is included between the first surface and the side surface, and a second slope is included between the second surface and the side surface, wherein the first slope and the second slope are separated by the side surface, wherein The first slope connects the first surface and the side surface, and the angle of the fillet between the first slope and the first surface is β1, wherein the second slope connects the second surface and the side surface, and the angle of the fillet between the second slope and the second surface is β2, and β1 is greater than β2. The semiconductor substrate as claimed in claim 1, wherein in a second direction parallel to the side surface, a distance B1 between the first surface and the side surface is greater than a distance B2 between the second surface and the side surface. The semiconductor substrate according to claim 2, wherein the ratio of A1:B1 is 150:80 to 250:160. The semiconductor substrate according to claim 2, wherein the ratio of A2:B2 is 60:40 to 80:60. The semiconductor substrate according to claim 1, wherein β1 is 130r (μm) to 200r (μm), and β2 is 100r (μm) to 140r (μm). The semiconductor substrate as claimed in claim 1, wherein the first surface is a carbon surface, and the second surface is a silicon surface. The semiconductor substrate according to claim 1, further comprising: an epitaxial layer formed on the second surface. The semiconductor substrate as claimed in claim 1, wherein the area of the second surface is larger than the area of the first surface. A method of manufacturing a semiconductor device, comprising: providing a silicon carbide wafer; and processing the edge of the silicon carbide wafer, wherein the silicon carbide wafer includes a first surface after processing, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface, wherein in a first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface, wherein: the first surface and the side surface include a first slope, and the second surface and the second surface The side surface includes the second slope, wherein the first slope and the second slope are separated by the side, wherein the first slope connects the first surface and the side surface, and the angle of the fillet between the first slope and the first surface is β1, wherein the second slope connects the second surface and the side surface, and the angle of the fillet between the second slope and the second surface is β2, and β1 is greater than β2. The method for manufacturing a semiconductor device as claimed in claim 9, further comprising: forming an epitaxial layer on the second surface; forming a plurality of semiconductor elements on or in the epitaxial layer; performing a grinding process on the first surface to reduce the thickness of the silicon carbide wafer; forming multiple conductive layers and multiple insulating layers on the semiconductor elements; and cutting the silicon carbide wafer. The method for manufacturing a semiconductor device according to claim 9, wherein the first surface is ground to obtain a third surface, and the angle between the third surface and the edge of the silicon carbide wafer is a right angle or an obtuse angle. The method for manufacturing a semiconductor device as claimed in claim 9, wherein the thickness of the silicon carbide wafer is about 250 microns to 500 microns before a grinding process, and the thickness of the silicon carbide wafer is about 50 microns to 150 microns after the grinding process. The method for manufacturing a semiconductor device according to claim 9, wherein the method for processing the edge of the silicon carbide wafer includes: grinding the edge of the silicon carbide wafer with a grinding head, wherein the grinding head includes a first protrusion and a second protrusion, the first protrusion is used for processing the edge of the upper side of the silicon carbide wafer, and the second protrusion is used for processing the edge of the lower side of the silicon carbide wafer, the shape of the first protrusion is different from the shape of the second protrusion. A semiconductor substrate, comprising: a silicon carbide wafer, having a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface, wherein a first slope is included between the first surface and the side surface, and a second slope is included between the second surface and the side surface, wherein in a first direction parallel to the first surface, the distance A1 between the first surface and the side surface is greater than the distance A2 between the second surface and the side surface, wherein the first slope connects the first slope One side and the side surface, and the angle of the fillet between the first slope and the first surface is β1, wherein the second slope connects the second surface and the side surface, and the angle of the fillet between the second slope and the second surface is β2, and β1 is greater than β2; and an epitaxial layer is formed on the second surface and the second slope. A semiconductor substrate, comprising: a silicon carbide wafer, having a first surface, a second surface parallel to the first surface, and a side surface perpendicular to the first surface and the second surface, wherein a first slope is included between the first surface and the side surface, and a second slope is included between the second surface and the side surface, wherein in a first direction parallel to the first surface, a distance A1 between the first surface and the side surface is greater than a distance A2 between the second surface and the side surface, wherein the first slope connects the first surface and the side surface, and the first slope The angle of the fillet between the first surface and the first surface is β1, wherein the second slope connects the second surface and the side surface, and the angle of the fillet between the second slope and the second surface is β2, and β1 is greater than β2; and an epitaxial layer is conformal to the second surface and the second slope.

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