JP2005159080A - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP2005159080A JP2005159080A JP2003396918A JP2003396918A JP2005159080A JP 2005159080 A JP2005159080 A JP 2005159080A JP 2003396918 A JP2003396918 A JP 2003396918A JP 2003396918 A JP2003396918 A JP 2003396918A JP 2005159080 A JP2005159080 A JP 2005159080A
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- JP
- Japan
- Prior art keywords
- differential
- line
- conductor
- signal
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Structure Of Printed Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
【解決手段】 配線基板1は、絶縁基板2に互いに平行に形成された一対の信号貫通導体9a,9bから成る差動貫通導体9と、絶縁基体2の主面または内層に互いに平行に形成されるとともに信号貫通導体9a,9bに一端が電気的に接続された一対の線路導体8a,8bから成る差動線路8とを具備し、差動貫通導体9の間隔が差動線路8の間隔よりも大きく、差動貫通導体9の信号貫通導体9a,9bと差動線路8の線路導体8a,8bとは、線路導体8a,8bと90°を超える角度をなす接続線路部12を介して接続されている。
【選択図】 図2
Description
2・・・絶縁基板
2a〜2f・・・絶縁層
3・・・信号配線群
4・・・接地導体層
5・・・半導体素子
6・・・導体バンプ
7・・・電極パッド
8・・・差動線路
8a,8b・・・線路導体
9・・・差動貫通導体
9a,9b・・・信号貫通導体
10・・・接地貫通導体
12・・・接続線路部
13・・・差動線路と接続線路部との成す角度
Claims (2)
- 絶縁基板に互いに平行に形成された一対の信号貫通導体から成る差動貫通導体と、前記絶縁基体の主面または内層に互いに平行に形成されるとともに前記信号貫通導体に一端が電気的に接続された一対の線路導体から成る差動線路とを具備しており、前記差動貫通導体の間隔が前記差動線路の間隔よりも大きく、前記差動貫通導体の前記信号貫通導体と前記差動線路の前記線路導体とは、前記線路導体と90°を超える角度をなす接続線路部を介して接続されていることを特徴とする配線基板。
- 前記接続線路部は、その長さが使用周波数帯域の上限周波数の波長の1/4以下であることを特徴とする請求項1記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003396918A JP4340131B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003396918A JP4340131B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008236594A Division JP2008311682A (ja) | 2008-09-16 | 2008-09-16 | 配線基板 |
JP2008236802A Division JP2009004809A (ja) | 2008-09-16 | 2008-09-16 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005159080A true JP2005159080A (ja) | 2005-06-16 |
JP4340131B2 JP4340131B2 (ja) | 2009-10-07 |
Family
ID=34722217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003396918A Expired - Fee Related JP4340131B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4340131B2 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007142307A (ja) * | 2005-11-22 | 2007-06-07 | Hitachi Ltd | 高速差動信号用多層基板、通信装置およびデータ記憶装置 |
JP2008109094A (ja) * | 2006-09-29 | 2008-05-08 | Sanyo Electric Co Ltd | 素子搭載用基板および半導体モジュール |
JP2008311682A (ja) * | 2008-09-16 | 2008-12-25 | Kyocera Corp | 配線基板 |
US7609130B2 (en) | 2006-08-21 | 2009-10-27 | Murata Manufacturing Co., Ltd. | High-frequency module including connection terminals arranged at a small pitch |
CN114173470A (zh) * | 2021-10-29 | 2022-03-11 | 广东浪潮智慧计算技术有限公司 | 一种差分走线排布结构 |
-
2003
- 2003-11-27 JP JP2003396918A patent/JP4340131B2/ja not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007142307A (ja) * | 2005-11-22 | 2007-06-07 | Hitachi Ltd | 高速差動信号用多層基板、通信装置およびデータ記憶装置 |
US7609130B2 (en) | 2006-08-21 | 2009-10-27 | Murata Manufacturing Co., Ltd. | High-frequency module including connection terminals arranged at a small pitch |
USRE43957E1 (en) | 2006-08-21 | 2013-02-05 | Murata Manufacturing Co., Ltd. | High-frequency module including connection terminals arranged at a small pitch |
JP2008109094A (ja) * | 2006-09-29 | 2008-05-08 | Sanyo Electric Co Ltd | 素子搭載用基板および半導体モジュール |
JP2008311682A (ja) * | 2008-09-16 | 2008-12-25 | Kyocera Corp | 配線基板 |
CN114173470A (zh) * | 2021-10-29 | 2022-03-11 | 广东浪潮智慧计算技术有限公司 | 一种差分走线排布结构 |
CN114173470B (zh) * | 2021-10-29 | 2024-02-09 | 广东浪潮智慧计算技术有限公司 | 一种差分走线排布结构 |
Also Published As
Publication number | Publication date |
---|---|
JP4340131B2 (ja) | 2009-10-07 |
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