JP2005039320A - Semiconductor element and high frequency power amplifying apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain downsizing and cost reduction of a semiconductor element. <P>SOLUTION: In the semiconductor element including: a semiconductor substrate; and transistors formed on the semiconductor substrate and for configuring first-stage and next-stage amplifiers of first and second amplifier systems, part of the region of the semiconductor substrate includes: first, second, and third transistors configuring the first-stage amplifier of the first amplifier system and the next-stage amplifier of the second amplifier system; and a switch element for selecting two prescribed transistors among the three transistors on the basis of a received switching signal. By switching the switch element, the first-stage amplifier of the first amplifier system is configured with the second and third transistors or the next-stage amplifier of the second amplifier system is configured with the first and second transistors. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element and a high-frequency power amplifying apparatus incorporating the semiconductor element, and relates to a technique that is effective when applied to, for example, a high-frequency power amplifying apparatus (high-frequency power amplifying module) incorporated in a cellular mobile phone.
[0002]
[Prior art]
As a cellular phone, a product capable of supporting a plurality of communication systems having different wavelength ranges (bands) and communication modes is known (for example, see Patent Document 1).
[0003]
Also, in a wireless communication system such as cellular communication, a caller's mobile phone (mobile terminal) is connected to a base station in the vicinity of the telephone network, and then sequentially connected to a single base station or a plurality of base stations. This is a system in which the mobile terminal of the target person is called and then a call with the target person can be made. At this time, the base station amplifies and transfers the received signal. Such amplification is performed by a mobile phone base station transmission amplifier (high frequency power amplifier for base station). The transmission amplifier has a structure in which MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistors) which are one of MIS (Metal Insulator Semiconductor) type transistors are connected in multiple stages.
[0004]
The silicon high-frequency MOSFET incorporated in the base station high-frequency power amplifying device has a higher operating voltage and a higher drain breakdown voltage than the high-frequency power amplifying device incorporated in the mobile phone. Also, operation at a frequency exceeding 1 GHz is required. As such a base station silicon high frequency power amplifier (high frequency power transistor), LDMOS (Laterally Diffused MOS) having advantages such as simplification of a bias circuit and high power gain is used (for example, Non-Patent Document 1). ).
[0005]
[Patent Document 1]
Japanese Patent Laying-Open No. 2001-7657 (sixth, FIG. 1)
[Non-Patent Document 1]
Microwave Workshop Digest (MWE '99 Microwave Workshop Digest (pages 283-288, Fig. 2 and Fig. 3))
[0006]
[Problems to be solved by the invention]
With advanced information communication, mobile phones are becoming more multifunctional. For this reason, the high-frequency power amplifying device (high-frequency power amplifying module) incorporated in the mobile phone is also multifunctional following the above. In particular, in a high-frequency power amplifying apparatus having a plurality of communication modes (including communication bands), the number of assembly parts is increased as compared with a single communication mode product, the apparatus is increased in size, and the product cost is increased.
[0007]
In view of this, the present inventors have studied the miniaturization of a semiconductor element (semiconductor chip) incorporating a field effect transistor in order to miniaturize the high-frequency power amplifier.
[0008]
15 to 17 are diagrams relating to a high-frequency power amplifier (high-frequency power amplifier module) studied prior to the present invention. 15 is a schematic block diagram showing a circuit configuration of the high-frequency power amplifier, FIG. 16 is a schematic layout diagram showing electronic components mounted on the module substrate in the high-frequency power amplifier, and FIG. 17 is a high-frequency power amplifier. It is a typical top view of the semiconductor element built in.
[0009]
A high-frequency power amplifier (hereinafter referred to as “reviewed high-frequency power amplifier”) 80 studied prior to the present invention is a dual-band type high-frequency power amplifier module. As shown in the circuit diagram of FIG. This is a high-frequency power amplifying apparatus equipped with a GSM (Global System for Mobile Communications) system and a DCS (Digital Communication System) system as a second amplification system.
[0010]
In the high frequency power amplifying apparatus 80, in the GSM amplification system, three stages (first stage, next stage, last stage) of amplifiers (amplification stages) 81, 82, 83 are arranged in series between the input terminal PinG and the output terminal PoutG. In the DCS amplification system, the amplifiers (amplification stages) 84, 85, 86 in three stages (first stage, next stage, and final stage) are connected in cascade between the input terminal PinD and the output terminal PoutD. It has become.
[0011]
The first-stage and next-stage amplifiers of GSM and DCS are incorporated in a single semiconductor device 90. The GSM final stage amplifier 83 is incorporated in the semiconductor element 91, and the DCS final stage amplifier 86 is incorporated in the semiconductor element 92 (see FIGS. 15 and 16).
[0012]
Each amplifier is composed of, for example, an LDMOS which is one of field effect transistors. FIG. 17 is a schematic plan view showing a semiconductor element 90 in which amplifiers 81, 82, 84, and 85 are incorporated. LDMOS regions 93 to 96 are arranged at each corner (near each vertex) of the rectangular semiconductor element 90. For example, an LDMOS (not shown) that forms the GSM first stage amplifier 81 is located in the LDMOS region 93 in the lower left corner, and an LDMOS (not shown) that forms the GSM next stage amplifier 82 is located in the LDMOS region 94 in the upper left corner. An LDMOS (not shown) that forms the DCS first stage amplifier 84 is located in the LDMOS region 95 in the lower corner, and an LDMOS (not shown) that forms the DCS next stage amplifier 85 is located in the LDMOS region 96 in the upper right corner. Further, a control IC 97 is formed in the central portion of the semiconductor element 90, and matching circuits 98 and 99 are formed between the control IC 97 and the LDMOS regions 93 and 94.
[0013]
In the GSM and DCS amplification systems, various circuits are connected to each amplifier (amplification stage). For example, an input matching circuit is formed on the input side of the transistor, an output matching circuit is formed on the output side, and a bias circuit is connected to the gate electrode. As shown in FIG. 16, in the examination high-frequency power amplifying apparatus, on the main surface of the module substrate 100, a number of electronic components that are not denoted by reference numerals but are indicated by rectangles are mounted. The electronic component is a passive component such as a chip resistor, a chip capacitor, or a chip inductor. The matching circuits, bias circuits, and the like are configured including these electronic components.
[0014]
On the other hand, in the field effect transistor, for example, efficiency, characteristics such as output and threshold, current capacity, and the like are determined by selecting a gate length Lg and a gate width Wg. In this case, in the high frequency power amplifying apparatus under consideration, for example, the gate width Wg is 6 mm for the first stage amplifier 81, 16 mm for the next stage amplifier 82, and 56 mm for the last stage (output stage) amplifier 83 in GSM. In the DCS, the first stage amplifier 84 is 2 mm, the next stage amplifier 85 is 6 mm, and the final stage (output stage) amplifier 86 is 24 mm.
[0015]
The gate width of the DCS first-stage amplifier 84 is the narrowest at 2 mm. The gate width of the DCS next-stage amplifier 85 is 6 mm, which is three times the gate width of the DCS first-stage amplifier 84. In GSM, the gate width of the first stage amplifier 81 is 6 mm, which is three times the gate width of the first stage amplifier 84 of the DCS, and the gate width of the next stage amplifier 82 is 16 mm, which is eight times the gate width of the first stage amplifier 84 of the DCS. It is. The gate width of the DCS next-stage amplifier 85 and the gate width of the GSM first-stage amplifier 81 are 6 mm having the same dimensions.
[0016]
Therefore, the present inventor has noticed that, by sharing a transistor having the same gate width in GSM and DCS, the semiconductor device can be miniaturized by reducing the number of transistors. I did it.
[0017]
In addition, the present inventor, for example, arranges a plurality of single FET patterns in which three source / drain / gate electrodes extend in parallel, and a part or all of the plurality of single FET patterns are switched elements. Since the transistors having desired gate widths can be formed by selecting each of the above, it has been realized that the semiconductor element can be miniaturized by reducing the formation area of the transistor which is an active element.
[0018]
In addition, the present inventor, for example, arranges a plurality of single FET patterns in which three source / drain / gate electrodes extend in parallel, and a part or all of the plurality of single FET patterns are switched elements. The present invention made it possible to form GSM or DCS transistors each having a desired gate width.
[0019]
An object of the present invention is to reduce the size and cost of a semiconductor element (high frequency power amplifying element).
[0020]
Another object of the present invention is to reduce the size and cost of a high-frequency power amplifier.
[0021]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0022]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0023]
(1) The semiconductor element of the present invention is
A semiconductor substrate;
A semiconductor element having transistors formed on the semiconductor substrate and constituting a first amplifier and a second amplifier of a first amplification system and a second amplification system,
In a partial region of the semiconductor substrate,
First, second and third transistors constituting the first amplifier of the first amplification system and the next amplifier of the second amplification system;
A switching element that selects two predetermined transistors from the three transistors according to an input switching signal;
By switching the switch element, the first transistor of the first amplification system is configured by the second transistor and the third transistor, or the second amplification system is configured by the first transistor and the second transistor. The next-stage amplifier is configured.
[0024]
(2) The high frequency power amplifier of the present invention is
A first and second amplification systems are formed on a module substrate, and each amplification system is a high-frequency power amplification device having transistors constituting the first stage, the next stage, and the last stage,
One of the semiconductor elements mounted on the module substrate has a transistor constituting the first stage amplifier and the second stage amplifier of the first amplification system and the second amplification system,
In a partial region of the semiconductor substrate of the semiconductor element having transistors constituting the first stage amplifier and the second stage amplifier of the first amplification system and the second amplification system,
First, second and third transistors constituting the first amplifier of the first amplification system and the next amplifier of the second amplification system;
A switching element that selects two predetermined transistors from the three transistors according to an input switching signal;
By switching the switch element, the first transistor of the first amplification system is configured by the second transistor and the third transistor, or the second amplification system is configured by the first transistor and the second transistor. The next-stage amplifier is configured.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
[0026]
(Embodiment 1)
In the first embodiment, an example in which the present invention is applied to a semiconductor element (semiconductor chip) incorporating a plurality of amplification systems and a high-frequency power amplification apparatus (high-frequency power amplification module) incorporating this semiconductor element will be described. For example, a dual-type semiconductor element incorporating a GSM amplification system and a DCS amplification system and a high-frequency power amplification apparatus incorporating this semiconductor element will be described.
[0027]
1 to 10 are diagrams relating to a high-frequency power amplifying apparatus according to an embodiment (Embodiment 1) of the present invention. FIG. 1 is a schematic block diagram showing a circuit configuration of a high-frequency power amplifier, and FIG. 2 is a schematic plan view in which a part of the high-frequency power amplifier is cut out.
[0028]
The high-frequency power amplifier (high-frequency power amplifier module) 1 has a flat rectangular structure in appearance as shown in FIG. In the high-frequency power amplifying apparatus 1, a flat rectangular body package 4 is configured by a plate-like module substrate (wiring substrate) 2 and a cap 3 that is attached to one surface side (main surface side) of the module substrate 2. It has a structure. The cap 3 is made of metal and resin mold which play an electromagnetic shielding effect.
[0029]
On the main surface (upper surface) of the module substrate 2, as shown in FIG. 2, electronic components such as active components and passive components are mounted to form a high frequency power amplifier 1. As shown in FIG. 1, the high frequency power amplifying apparatus 1 incorporates GSM and DCS amplification systems. Each amplification system has a three-stage amplification configuration of a first stage amplifier, a next stage amplifier, and a final stage (output stage) amplifier.
[0030]
That is, as shown in FIG. 1, in the GSM, the high-frequency power amplifying apparatus 1 includes a second amplifier (AMP2) as a first-stage amplifier, a second-stage amplifier, and a final-stage amplifier between an input terminal PinG and an output terminal PoutG. The third amplifier (AMP3) and the fourth amplifier (AMP4) are connected in cascade. In the DCS, a first amplifier (AMP1), a second amplifier (AMP2), and a fifth amplifier (AMP5) are provided as an initial stage amplifier, a next stage amplifier, and a final stage amplifier between an input terminal PinD and an output terminal PoutD. ) Are connected in cascade. Each amplifier (AMP) is composed of a field effect transistor. In the first embodiment, an LDMOS is used as a transistor.
[0031]
The transistors constituting AMP4 and AMP5 are incorporated in separate semiconductor elements (semiconductor chips). In FIG. 2, the transistor constituting the AMP 4 is incorporated in a semiconductor element (semiconductor chip) 6, and the transistor constituting the AMP 5 is incorporated in a semiconductor element (semiconductor chip) 7. The transistors constituting AMP1, AMP2, and AMP3 are incorporated in a semiconductor element (semiconductor chip) 5.
[0032]
As shown in FIG. 1, AMP1 to AMP3 are AMP2 in the case of a GSM amplification system by four switch elements (SW1 to SW4) controlled by a switching control unit 8 that is separate from the high frequency power amplifier 1. , AMP3 are selected, and in the case of a DCS amplification system, AMP1 and AMP2 are selected. The gate widths Wg of AMP1 to AMP5 are different from each other, and the next stage is larger than the first stage, and the final stage is larger than the next stage. For example, to give one example, the gate width Wg of the transistor constituting AMP1 is 2 mm, the gate width Wg of the transistor constituting AMP2 is 6 mm, the gate width Wg of the transistor constituting AMP3 is 16 mm, and the transistor constituting AMP4 The gate width Wg of the transistor constituting the AMP5 is 56 mm. The switch element is also formed of a transistor, that is, an LDMOS. The gate width Wg of the transistors constituting each switch element is also the gate width Wg adapted to the transistors constituting each AMP. That is, the gate width Wg of the transistors constituting SW1 and SW3 is 2 mm corresponding to the gate width Wg of the transistors constituting AMP1. The gate width Wg of the transistors constituting SW2 and SW4 is 6 mm corresponding to the gate width Wg of the transistors constituting AMP2.
[0033]
In FIG. 2, semiconductor elements 5, 6 and 7 are mounted on the main surface of the module substrate 2. A predetermined electronic component is mounted around these semiconductor elements 5, 6, and 7. The semiconductor elements 5, 6 and 7 are electronic parts and active elements, but many passive parts indicated by a number of rectangles are mounted around the active elements, although not denoted by reference numerals. The passive component is a surface mount type passive component such as a chip resistor, a chip capacitor, or a chip inductor. These passive components constitute an input matching circuit, an output matching circuit, a gate bias circuit, and the like in each transistor to form a three-stage amplification system. In FIG. 2, electrodes (not shown) around the semiconductor elements 5, 6, and 7 are electrically connected to the wire connecting portions of the module substrate 2 (not shown) by conductive wires 9. In the plan view of the semiconductor element, electrode pads for connecting wires are omitted.
[0034]
Although not shown, external electrode terminals are provided from the peripheral surface to the bottom surface of the module substrate 2. The high-frequency power amplifying apparatus 1 has a surface mounting structure, and when mounted on a mounting board, the external electrode terminal is overlaid on a land (foot) provided on the main surface of the mounting board, and a previously supplied solder or the like is joined. By reflowing the material, the high frequency power amplifying apparatus 1 can be connected (mounted) to the mounting substrate.
[0035]
FIG. 3 is a schematic plan view of a rectangular semiconductor element. As shown in FIG. 3, a control IC 15 is provided in the center portion shown by hatching. The upper left corner and right upper and lower corners (near each vertex) of the semiconductor element 5 having a quadrangular shape are LDMOS regions 16 to 18. The LDMOS regions 16 to 18 are dotted regions in FIG. The three LDMOSs in the LDMOS region form the first stage amplifier and the next stage amplifier for GSM and DCS. For example, the first stage amplifier (DCS1st) for DCS is formed in the LDMOS region 16 in the lower right corner, the next stage amplifier (GSM2nd) for GSM is formed in the LDMOS region 17 in the upper left corner, and the LDMOS region 18 in the upper right corner is formed. A GSM first stage amplifier (GSM1st) and a DCS next stage amplifier (DCS2nd) are formed.
[0036]
FIG. 4 is a schematic diagram showing a layout of the active region A, gate electrode pad (G), and drain electrode pad (D) of the LDMOS formed in the LDMOS regions 16 to 18 of FIG. In the LDMOS region 16 in the lower right corner, an active region A of the DCS 1st, a gate electrode pad (G) located on one end side of this region, and a drain electrode pad (D) located on the other end side are located.
[0037]
In the LDMOS region 17 in the upper left corner, an active region A of GSM2nd, a gate electrode pad (G) located on one end side of this region, and two drain electrode pads (D) located on the other end side are located. ing. In order to increase the output of GSM2nd, the active area A is wider than that of DCS1st and has two.
[0038]
The LDMOS region 18 in the upper right corner includes an active region A of GSM1st and DCS2nd, two gate electrode pads (G) located on one end side of this region, and two drain electrode pads (G) located on the other end side ( D) is located. The LDMOS in the LDMOS region 18 is switched in mode by a switch circuit (SW). That is, when GSM amplification is performed by this switch circuit (SW), a predetermined gate electrode pad (G) and drain electrode pad (D) are selected to constitute GSM1st, and when DCS amplification is performed. A predetermined gate electrode pad (G) and drain electrode pad (D) are selected to form DCS2nd. A matching circuit 20 is disposed between the control IC 15 and the LDMOS region 17 and the LDMOS region 18.
[0039]
In the first embodiment, the LDMOS region is arranged at three corners of the rectangular semiconductor element 5, and at one corner, two types of amplifiers (amplification stages) can be selected by selection by a switch circuit. As shown in FIG. 17, the semiconductor element can be downsized as compared with the structure arranged at the four corners. For example, when the semiconductor element shown in FIG. 17 is 2.5 mm long and 2.25 mm wide, the semiconductor element 5 of Embodiment 1 is as small as 2.25 mm long and 2.25 mm wide. Further, even if it is not miniaturized, it is possible to add a further control IC element to the vacant space to achieve high functionality.
[0040]
FIG. 5 is a schematic cross-sectional view showing active elements and passive elements formed in the semiconductor element 5. For convenience of explanation, in this figure, from left to right, LDMOS, resistor (R), protection diode, PMOS, PN diode, and NMOS are shown. By combining these elements, the semiconductor element 5 shown in FIGS. 3 and 4 is formed. 5, the arrow a region is a field effect transistor (FET) portion, and the arrow b region is a control IC portion.
[0041]
The semiconductor element 5 is P-type (p ⁺ Type of semiconductor substrate 30 made of silicon (Si) on the main surface (upper surface) of the P-type epitaxial layer 31 formed on the main surface (upper surface) of the desired conductivity type (n-type, p-type) semiconductor region (including well region: PW, NW) are provided to form the predetermined element. In the epitaxial layer 31, an isolation region 33 is provided at a necessary portion for forming each element, and a predetermined region is an electrically isolated and independent region. Further, since the source of the FET is GND, a punching layer 32 is provided to connect to the GND on the back surface, and the GND region is electrically provided. The capacitance and resistance are formed using a dielectric (insulator) or a conductive layer provided on the semiconductor substrate. The surface of the semiconductor element 5 is covered with an insulating film 35 formed in a plurality of layers, and a back electrode (not shown) is formed on the back surface. Although not shown, a part of the final passivation film which is the outermost layer of the insulating film 35 is removed, and the surface of the conductor layer is exposed at the opening due to this removal. The exposed portion of the conductor layer becomes the electrode pad described above. The thickness of the semiconductor substrate 30 of the semiconductor element 5 is as thin as 280 μm, for example.
[0042]
The description of the structure of each element in the semiconductor element 5 is omitted, but the LDMOS will be described with reference to FIGS. FIG. 6 is a schematic plan view showing a part of the electrode pattern of the LDMOS 37, and FIG. 7 is a schematic cross-sectional view of the part along the line AA in FIG.
[0043]
As shown in FIG. 6, one drain electrode 41 is elongated from the rectangular drain electrode pad 40. A square gate electrode pad 42 is located on the distal end side of the drain electrode 41. One gate electrode 43 extends from the gate electrode pad 42 toward the drain electrode 41, and the gate electrode 43 is bifurcated. The two branched electrode portions sandwich the drain electrode 41 and extend in parallel along the drain electrode 41. A source electrode 44 extends in parallel with the gate electrode 43 outside the gate electrode 43. The source electrode 44, the drain electrode 41, and the gate electrode 43 extend in parallel with each other at a length c. FIG. 6 is a unit FET pattern schematically showing the basic portion of the LDMOS. In this pattern, the distance (width) d from the outer end of one source electrode 44 to the outer end of the other source electrode 44 is, for example, 12.8 μm. The length c is 41 μm. The gate width Wg in this unit FET pattern is twice the length c, that is, 82 μm. In this case, the areas of the source electrode, the drain electrode, and the gate electrode, which are called the FET area in a narrow sense. The FET area in the narrow sense is about 524.8 μm ² It becomes.
[0044]
The LDMOS has a cross section as shown in FIG. As shown in FIG. 7, a P-type epitaxial layer 51 is provided on the main surface of a semiconductor substrate 50 made of a low-resistance P-type silicon substrate (P-sub). P-type P well regions (PW) 52 and 53 are provided in the surface layer portion of the epitaxial layer 51 so as to be separated from each other by a predetermined distance. This layer acts as a punch-through stopper layer.
[0045]
A surface layer portion of the epitaxial layer 51 between the pair of P well regions 52 and 53 is an N-type drain offset region 54. An N-type drain region 55 is provided in an N-type drain offset region 54 portion between the pair of P-well regions 52 and 53. The bottom of the drain region 55 passes through the N-type drain offset region 54 and extends to a mid-depth of the epitaxial layer 51.
[0046]
On the other hand, outside the pair of P well regions 52, 53, P reaches the intermediate depth of the semiconductor substrate 50 so as to surround the P well regions 52, 53, etc. ⁺ A mold region 56 is provided and this P ⁺ P is exposed on the mold region 56. ⁺ A P-type contact region 57 of the type is provided. Further, an N-type source region 58 is provided in the surface layer portion of the pair of P-well regions 52 and 53 at a predetermined distance from the end of the N-type drain offset region 54.
[0047]
A well region portion between the N-type drain offset region 54 and the source region 58 becomes a channel layer. A gate electrode 43 is formed on the channel layer via a gate insulating film (oxide film) 59.
[0048]
A predetermined number of insulating films 60 are formed on the main surface side of the semiconductor substrate 50. The predetermined insulating film is provided with a contact hole, and a conductor is formed in a predetermined pattern on the predetermined insulating film. The conductor is filled in a predetermined contact hole. As a result, as shown in FIG. 7, the gate electrode 43, the drain electrode 41, the source electrode 44, and the source wiring 61 are formed. The P-type contact region 57 and the source region 58 are electrically connected by the source electrode 44 and the source wiring 61. Accordingly, the source region 58 is electrically connected to the semiconductor substrate 50 and is electrically connected to a back electrode (not shown) formed on the back surface of the semiconductor substrate 50. The source region extends P so as to penetrate the epitaxial layer 51 vertically. ⁺ Since it is electrically guided to the back electrode on the back surface of the semiconductor substrate 50 by the mold region 56, the parasitic resistance component (ON resistance) is reduced, and it is difficult to oscillate when used in a high frequency range. The drain region 55 is electrically connected to the drain electrode 41. Thus, the LDMOS is a lateral diffusion type field effect transistor.
[0049]
Next, an area of a transistor having a predetermined gate width Wg, a switch element (transistor), and the like will be described. FIG. 8 shows an example in which a plurality of unit FET patterns shown in FIG. 6 are arranged in parallel, the gate width of the unit FET pattern is also increased, and the gate width Wg of the transistor is 6 mm (hereinafter referred to as a Wg 6 mm transistor). . The length e of the unit FET pattern in FIG. 8 is six times the length c of the unit FET pattern in FIG. 6, that is, 246 μm. The Wg 6 mm transistor has a configuration in which twelve long unit FET patterns are arranged in parallel. The gate width Wg of the Wg 6 mm transistor is about 6 mm (more precisely, 5.904 mm). In this case, the FET area in the narrow sense is about 37785.6 μm. ² become.
[0050]
FIG. 9 shows the FET patterns of SW1 and SW2 shown in FIG. 1, and has a pattern configuration in which four unit FET patterns shown in FIG. 6 are arranged in parallel. This is a switch element (hereinafter referred to as a switch element for Wg 2 mm) that switches the current path of AMP1 in which the gate width Wg is 2 mm. The FET area in the narrow sense of the switch element for Wg 2 mm is four times as large as the unit FET pattern shown in FIG. ² become.
[0051]
FIG. 10 shows the FET patterns of SW3 and SW4 shown in FIG. 1, and has a pattern configuration in which 12 unit FET patterns shown in FIG. 6 are arranged in parallel. This is a switch element (hereinafter referred to as a switch element for Wg 6 mm) that switches the current path of AMP2 in which the gate width Wg is 6 mm. The FET area in the narrow sense of the switch element for Wg 6 mm is 12 times as large as the unit FET pattern shown in FIG. 6, that is, about 6297.6 μm. ² become.
[0052]
When the first and second stage transistors of GSM and DCS are formed separately, that is, the first stage transistor of GSM and the next stage transistor of DCS having a gate width Wg of 6 mm are provided in a single semiconductor element (semiconductor chip). In this case, the FET area in the narrow sense of the two transistors is one area of the Wg 6 mm transistor is 37785.6 μm. ² Therefore, 75571.2 μm ² It becomes.
[0053]
On the other hand, in the case of the first embodiment, one Wg 6 mm transistor (area 37785.6 μm). ² ) And two Wg 2 mm switch elements (area 2099.2 μm) ² ) And two Wg 6 mm switch elements (area 6297.6 μm) ² ), The total area is 54579.2 μm. ² In the case of the structure of the first embodiment, about 21000 μm ² Can be reduced. As a result, the area of the semiconductor chip can be reduced, or the element formation area can be increased accordingly.
[0054]
The first embodiment has the following effects.
(1) In a semiconductor element having transistors constituting first-stage amplifier and second-stage amplifier of first amplification system and second amplification system, first and first transistors provided in partial regions of a semiconductor substrate forming the semiconductor element By switching the switching element from the second and third transistors, the first transistor of the first amplification system is configured by the second transistor and the third transistor, or the second amplification system is configured by the first transistor and the second transistor. Therefore, one transistor can be omitted, and a reduction in the size of the semiconductor element can be achieved.
[0055]
Specifically, the semiconductor device of the present invention includes a first amplifier (AMP1) having a gate width Wg of 2 mm, a second amplifier (AMP2) having a gate width Wg of 6 mm, and a third amplifier having a gate width Wg of 16 mm. (AMP3) and first to fourth switch elements (SW1 to SW4) for selecting two amplifiers from these three amplifiers, and AMP2 and AMP3 are selected by the selection operation of the switch elements. Are selected to form the first and second stage amplifiers of the first amplification system (GSM), and the first and second stages of the second amplification system (DCS) are selected by selecting AMP1 and AMP2 by the switching operation of the switch elements. A stage amplifier is formed. That is, the transistor constituting the AMP2 is configured to be used in any amplification system. The structure in which one transistor constituting the AMP2 and four switch elements are incorporated in the semiconductor element as in the first embodiment is compared with the case where two transistors constituting the AMP2 are formed in the semiconductor element. The area can be reduced.
[0056]
(2) Therefore, from the above (1), the semiconductor element can be miniaturized. In this case, it is possible to reduce the size of the high-frequency power amplifying apparatus incorporating this semiconductor element.
[0057]
(3) Therefore, from the above (1), the transistor formation area can be reduced, so that more elements can be formed in the vacant region, and the output can be increased or other functions can be added.
[0058]
(4) Since the semiconductor element is formed by cutting a single semiconductor substrate (wafer) vertically and horizontally, downsizing of the semiconductor element increases the number of semiconductor elements obtained from one semiconductor substrate. The cost of the element can be reduced. Therefore, the high-frequency power amplifying apparatus incorporating such a miniaturized semiconductor element can also be miniaturized and can be reduced in cost.
[0059]
(Embodiment 2)
11 to 14 are diagrams related to a high-frequency power amplifying apparatus according to another embodiment (Embodiment 2) of the present invention.
[0060]
FIG. 11 is a schematic diagram showing an arrangement state of each amplification stage in a semiconductor element incorporated in the high-frequency power amplifier, FIG. 12 is a schematic block diagram showing a circuit configuration of the high-frequency power amplifier, and FIG. 13 is a semiconductor according to the second embodiment. FIG. 14 is a schematic cross-sectional view taken along the line BB in FIG. 13. FIG. 14 is a schematic plan view showing an electrode pattern of an NMOS switch element incorporated in the element.
[0061]
In the second embodiment, in the semiconductor element 5 of the first embodiment, a transistor capable of obtaining DCS1st and GSM2nd by an on / off operation of a switch element is arranged in the upper left corner of the semiconductor element 5. As a result, the semiconductor element can be further reduced (shrinked).
[0062]
FIG. 12 shows a circuit configuration of a transistor (LDMOS) that selectively forms DCS1st and GSM2nd. That is, in the case of the first embodiment, DCS1st and GSM2nd are formed separately, but in the present embodiment 12, the transistors constituting DCS1st or GSM2nd are formed by selectively using the transistors of the pattern of FIG. Is. Accordingly, since the transistor having the pattern shown in FIG. 12 includes the switch element, at least the area of the portion where the switch element is formed is increased, but the area of the Wg 2 mm transistor constituting the DCS 1st becomes unnecessary.
[0063]
In the present embodiment, as shown in FIG. 12, n FET patterns 65 having a gate width Wg of 1 mm are arranged, and a transistor for DCS1st having a Wg of 2 mm by an on / off operation of the switch element group, or a Wg of 16 mm This constitutes a GSM2nd transistor. That is, 16 FET patterns 65 are arranged in parallel to form two groups of 2 and 14. The group consisting of 2 constitutes a Wg 2 mm transistor, and the group consisting of 14 constitutes a Wg 14 mm transistor. Therefore, if both groups are selected, a Wg 16 mm transistor can be obtained, and if only two groups are selected, a Wg 2 mm transistor can be obtained.
[0064]
In the second embodiment, the two groups are connected to the drain electrode pad 40 and the gate electrode pad 42, respectively. In FIG. 12, one drain electrode pad 40 is shown for DCS and two are shown for GSM, and one gate electrode pad 42 is shown for both DCS and GSM. The aforementioned wire 9 is connected to the drain electrode pad 40 and the gate electrode pad 42.
[0065]
In addition, the wiring portion connecting the two groups and each electrode pad has a predetermined wiring pattern and is connected to the switch elements (SW11 to SW16). Switching of the DCS amplification system is possible. SW11, SW12, SW13 are arranged on the drain electrode pad side, and SW14, SW15, SW16 are arranged on the gate electrode pad side. As shown in FIG. 12, these SW11 to SW16 are controlled by a switching control unit 66 that is separate from the high-frequency power amplifier.
[0066]
Since SW11 to SW13 arranged on the drain electrode pad side have a large amount of current, a switch element for Wg 2 mm is used as in the case of the first embodiment. On the other hand, since SW14 to SW16 arranged on the gate electrode pad side have a small amount of current, a Wg 82 μm switch element (LDMOS) having a gate width Wg of 82 μm or an NMOS switch having a gate width Wg of 10 μm. Elements are used.
[0067]
The NMOS switch element has a structure shown in FIGS. FIG. 13 is a schematic plan view showing an electrode pattern of the NMOS switch element, and FIG. 14 is a schematic cross-sectional view taken along the line BB of FIG.
[0068]
The NMOS switch element 68 has a P-type epitaxial layer 70 formed on the main surface. ⁺ It is formed on the basis of a type silicon semiconductor substrate 69. A P-type well region (PW) 71 is provided in the surface layer portion of the epitaxial layer 70. A gate insulating film 72 is formed in the center of the P-type well region 71, and a gate electrode 73 is formed on the gate insulating film 72. In addition, n is sandwiched between the gate insulating film 73 and the region. ⁺ A mold region is formed. These n ⁺ The mold region is located in the P-type well region 71. These n ⁺ One of the mold regions is a source region 74 and the other is a drain region 75. Each n ⁺ A source electrode 76 and a drain electrode 77 are formed on the mold region. As shown in FIG. 12, a plurality of thick insulating films (LOCOS) 78 and a plurality of insulating films (not shown) are formed on the surface of the NMOS switch element 68 and cover the gate electrode 73, the source electrode 76, and the drain electrode 77. These gate electrode 73, source electrode 76, and drain electrode 77 are connected by a conductor layer (wiring) formed between insulating films so as to have a circuit configuration as shown in FIG.
[0069]
FIG. 13 is a schematic diagram showing the dimensional relationship of the NMOS switch element 68. When the length in the gate length direction is k and the length in the gate width direction is j, when the gate width Wg is 10 μm, k = 10.6 μm and j = 14.6 μm, and the area of the NMOS switch element 68 is Approx. 154.8 μm ² It becomes.
[0070]
Next, in the configuration shown in FIG. 12, SW11 to SW13 on the drain electrode pad side use Wg 2 mm switch elements as in the first embodiment, and SW14 to SW16 on the gate electrode pad side change to (1) Wg 82 μm. The area reduction (shrink) will be described separately for the case where the switch element is used and (2) the case where the NMOS switch element is used. That is, in the case of the twelfth embodiment, DCS1st (Wg 2 mm transistor) and GSM2nd (Wg 16 mm transistor) are formed by the transistors having the configuration shown in FIG. Since the number of switch elements (SW11 to SW16) increases, the area increases.
[0071]
The area of the Wg 2 mm transistor is 12595.2 μm ² It becomes. Therefore, (1) In the case of (1) above, the area of the switch element is the area of three switch elements for Wg 2 mm, 6297.6 μm. ² (2099.2 × 3) and the area of three Wg 82 μm switch elements, 1574.4 μm ² 7872 μm which is the sum of (524.8 × 3) ² become. Therefore, shrink is 12595.2 μm. ² To 7872 μm ² Minus 4723.2 μm ² It becomes.
[0072]
In the case of (2) above, the area of the switch element is the area of three switch elements for Wg 2 mm, 6297.6 μm. ² (2099.2 × 3) and the area of three NMOS switch elements, 464.4 μm ² 6762 μm which is the sum of (154.8 × 3) ² become. Therefore, shrink is 12595.2 μm. ² To 6762 μm ² Minus 5833.2 μm ² It becomes.
[0073]
Thus, even if the switch element is selected, in any case, 4723.2 μm ² Or 5833.2 μm ² And the area can be reduced. Although each numerical value is a calculation using rough numbers, the chip area can be surely reduced. Further, when the area is not reduced, the area portion becomes an element formable region, so that an element portion or a new element can be further added.
[0074]
Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Nor. That is, in the present embodiment, an example in which a MOSFET is used as a transistor has been described. However, the present embodiment can be similarly applied to a GaAs-MES (Metal-Semiconductor) FET, a HEMT (High Electron Mobility Transistor), a Si-GeFET, and the like. Similar effects can be obtained.
[0075]
Further, although the dual band system has been described in the embodiment, it can be similarly applied to a multi-mode communication system and a multi-band multi-mode communication system, and similar effects can be obtained.
[0076]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0077]
(1) The semiconductor element (high frequency power amplifying element) can be reduced in size and cost.
[0078]
(2) The high frequency power amplifier can be reduced in size and cost.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a circuit configuration of a high-frequency power amplifier device according to an embodiment (Embodiment 1) of the present invention.
FIG. 2 is a schematic plan view in which a part of the high-frequency power amplifier is cut away.
FIG. 3 is a schematic plan view of the semiconductor element according to the first embodiment incorporated in the high-frequency power amplifier.
FIG. 4 is a schematic diagram showing an arrangement state of each amplification stage in a semiconductor element incorporated in the high-frequency power amplifier.
FIG. 5 is a cross-sectional view schematically showing active elements and passive elements incorporated in the semiconductor element.
6 is a schematic plan view showing a single electrode pattern of an LDMOS incorporated in the semiconductor element of Embodiment 1. FIG.
7 is a schematic cross-sectional view taken along line AA in FIG.
FIG. 8 is a schematic plan view showing a comb-like electrode pattern in the LDMOS.
FIG. 9 is a schematic plan view showing an electrode pattern of a switch element having a first gate width in the semiconductor element of the first embodiment.
10 is a schematic plan view showing an electrode pattern of a switch element having a second gate width in the semiconductor element of Embodiment 1. FIG.
FIG. 11 is a schematic diagram showing an arrangement state of each amplification stage in a semiconductor device according to another embodiment (Embodiment 2) of the present invention.
FIG. 12 is a schematic block diagram showing a circuit configuration of a high-frequency power amplifier device according to another embodiment (Embodiment 2) of the present invention.
FIG. 13 is a schematic plan view showing an electrode pattern of an NMOS switch element incorporated in a semiconductor element according to the second embodiment.
14 is a schematic cross-sectional view taken along line BB in FIG.
FIG. 15 is a schematic block diagram showing a circuit configuration of a high-frequency power amplification device studied prior to the present invention.
FIG. 16 is a schematic layout diagram showing electronic components mounted on a module substrate in the high-frequency power amplifying apparatus examined prior to the present invention.
FIG. 17 is a schematic plan view of a semiconductor element incorporated in a high-frequency power amplifying apparatus examined prior to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... High frequency power amplification apparatus (high frequency power amplification module), 2 ... Module substrate, 3 ... Cap, 4 ... Package, 5-7 ... Semiconductor element (semiconductor chip), 8 ... Switching control part, 9 ... Wire, 15 ... Control IC ... 16-18 ... LDMOS region, 20 ... matching circuit, 30 ... semiconductor substrate, 31 ... epitaxial layer, 32 ... punching layer, 33 ... isolation region, 35 ... insulating film, 40 ... drain electrode pad, 41 ... Drain electrode, 42 ... Gate electrode pad, 43 ... Gate electrode, 44 ... Source electrode, 50 ... Semiconductor substrate, 51 ... Epitaxial layer, 52,53 ... P well region (PW), 54 ... N-type drain offset region, 55 ... Drain region 56 ... P ⁺ Type region 57 ... P-type contact region 58 ... Source region 59 ... Gate insulating film (oxide film) 60 ... Insulating film 61 ... Source wiring 65 ... FET pattern 66 ... Switch control unit 68 ... NMOS switch Element 69 ... Silicon semiconductor substrate 70 ... Epitaxial layer 71 ... Well region (PW) 72 ... Gate insulating film 73 ... Gate electrode 74 ... Source region 75 ... Drain region 76 ... Source electrode 77 ... Drain Electrode 78 ... Thick insulating film (LOCOS), 80 ... High frequency power amplifier, 81-86 ... Amplifier (amplification stage), 90-92 ... Semiconductor element, 93-96 ... LDMOS region, 97 ... Control IC, 98, 99 ... Matching circuit, 100 ... module substrate.

Claims (5)

A semiconductor substrate;
A semiconductor element having transistors formed on the semiconductor substrate and constituting a first amplifier and a second amplifier of a first amplification system and a second amplification system,
In a partial region of the semiconductor substrate,
First, second and third transistors constituting the first amplifier of the first amplification system and the next amplifier of the second amplification system;
A switching element that selects two predetermined transistors from the three transistors according to an input switching signal;
By switching the switch element, the first transistor of the first amplification system is configured by the second transistor and the third transistor, or the second amplification system is configured by the first transistor and the second transistor. A semiconductor device comprising a next-stage amplifier. A first switch element connected between an input terminal of the first amplification system and the second transistor;
A second switch element connected between the second transistor and the third transistor connected to the final amplifier of the first amplification system;
A first switch connected to the input terminal of the second amplification system and a third switch element connected between the second transistor;
2. The semiconductor device according to claim 1, further comprising a fourth switch element connected between the second transistor and a final-stage amplifier of the second amplification system. Each of the transistors and the switch elements is a field effect transistor,
The gate widths of the first transistor and the first and third switch elements are the first gate width,
The gate width of the second transistor and the second and fourth switch elements is a second gate width wider than the first gate width,
The third transistor has a third gate width that is wider than the second gate width,
The semiconductor element according to claim 2, wherein a gate width of the third transistor is a third gate width wider than the second gate width. A semiconductor substrate;
A semiconductor element having transistors formed on the semiconductor substrate and constituting a first amplifier and a second amplifier of a first amplification system and a second amplification system,
A plurality of single FETs formed in a partial region of the semiconductor substrate;
A switch element for selecting a part or all of the plurality of single FETs formed in a partial region of the semiconductor substrate;
By switching the switch element, a part of the plurality of single FETs constitutes the first stage amplifier of the one amplification system, or all of the plurality of single FETs forms the second stage amplifier of the other amplification system. The semiconductor element characterized by the above-mentioned. A first and second amplification systems are formed on a module substrate, and each amplification system is a high-frequency power amplification device having transistors constituting the first stage, the next stage, and the last stage,
One of the semiconductor elements mounted on the module substrate has a transistor constituting the first stage amplifier and the second stage amplifier of the first amplification system and the second amplification system,
In a partial region of the semiconductor substrate of the semiconductor element having transistors constituting the first stage amplifier and the second stage amplifier of the first amplification system and the second amplification system,
First, second and third transistors constituting the first amplifier of the first amplification system and the next amplifier of the second amplification system;
A switching element that selects two predetermined transistors from the three transistors according to an input switching signal;
By switching the switch element, the first transistor of the first amplification system is configured by the second transistor and the third transistor, or the second amplification system is configured by the first transistor and the second transistor. A high-frequency power amplifying apparatus comprising:

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