JP2004274039A - Bilateral device, manufacturing method thereof, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a bilateral device with a high withstand voltage and low on-voltage, and a manufacturing method thereof. <P>SOLUTION: An n-type extended drain region 4 is formed on each trench bottom 3a, and a p-type offset region 5 is formed in each divided semiconductor region, then a first n-type source region 9 and a second n-type source region 10 are formed on the surface of the p-type offset region 5, thereby decreasing each planar distance between the first n-type source region 9 and the second n-type source region 10 for higher cell density. Higher withstand voltage is achieved by maintaining the withstand voltage along each trench. Making the voltage of each gate electrode 7 higher than that of each first n-type source electrode 11 and that of each second n-type source electrode 12, a channel is formed on each trench sidewall, thereby realizing a bilateral LMOSFET (lateral metal oxide semiconductor field effect transistor) with high withstand voltage and low on-voltage, in which a current flows bilaterally. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a power integrated circuit (power IC) having a bidirectional element and a method of manufacturing the same.

2. Description of the Related Art In a power supply device such as a battery, both charging a battery and discharging a battery (supplying a current to a load) are controlled to prevent overcharging and overdischarging of the battery. Therefore, a bidirectional semiconductor switch capable of turning on / off an AC signal or AC power is required. As the bidirectional semiconductor switch, a composite bidirectional element in which unidirectional semiconductor elements are connected in antiparallel is used. .
In addition, a power supply device is miniaturized by using a power IC in which the composite type bidirectional element and a control IC for controlling the same are integrated on the same semiconductor substrate.
Also, a single bidirectional element has been developed, and as one example, a bidirectional lateral insulated gate transistor (LIGBT) has been proposed (for example, see Non-Patent Document 1). Next, the structure and operation of the bidirectional LIGBT will be described.

FIG. 30 is a cross-sectional view of a main part of the bidirectional LIGBT. In the bidirectional LIGBT, two p ⁺ well regions 504 and 505 are formed on the surface side of the n semiconductor layer 503, and n ⁺ emitter regions 506 and 507 are formed in the p ⁺ well regions 504 and 505. The p ⁺ well regions 504 and 505 are formed so as to be exposed on the surface of the n semiconductor layer 503 and are separated by a predetermined distance (drift distance) so as to maintain a predetermined breakdown voltage. Further, n ⁺ emitter regions 506 and 507 are also formed to be exposed on the surface of n semiconductor layer 503 (the surfaces of p ⁺ well regions 504 and 505).
An insulated gate type gate electrode made of polysilicon or the like is formed on the portion of the p ⁺ well regions 504 and 505 located between the two n ⁺ emitter regions 506 and 507 via gate insulating films 508 and 509. 510 and 511 are formed. Further, emitter electrodes 512 and 513 are formed so as to extend over the p ⁺ well regions 504 and 505 and the n ⁺ emitter regions 506 and 507. In this structure, by controlling the voltage applied to the gate electrodes 510 and 511, the on / off of the main current flowing bidirectionally between the emitter electrodes 512 and 513 can be controlled.

FIG. 31 is a diagram showing output characteristics of the bidirectional LIGBT of FIG. Since the main current does not start flowing until the rising voltage (0.6 V) due to the built-in potential of the pn junction is exceeded, the on-voltage is high and the on-loss increases in a small current region.
In order to improve this, there is a single bidirectional MOSFET in which a bidirectional element is formed by a MOSFET whose voltage becomes zero V at the rise (for example, see Patent Document 1). The contents will be described.
FIG. 32 is a cross-sectional view of a main part of a conventional bidirectional MOSFET. Here, a bidirectional LDMOSFET (Lateral Double-Diffused MOSFET) is exemplified. As in the above example, the semiconductor device has an SOI structure, and an n semiconductor layer 103 is formed on a semiconductor substrate 101 with an insulating layer 102 interposed therebetween. On the surface side of the n semiconductor layer 103, two n ⁺⁺ drain regions 104 and 105 are formed, and ap ⁺ well region 106 is formed between the two n ⁺⁺ drain regions 104 and 105. The p ⁺ well region 106 is formed to a depth reaching the insulating layer 102, and divides the n semiconductor substrate 103 into two regions. Further, two n ⁺⁺ source regions 107 and 108 are formed in the p ⁺ well region 106, and a p ⁺⁺ base contact 109 region is formed between the two n ⁺⁺ source regions 107 and 108. . The n ⁺⁺ drain regions 104 and 105 and the p ⁺ well region 106 are exposed on the surface of the n semiconductor substrate 103, and the n ⁺⁺ source regions 107 and 108 and the p ⁺⁺ base contact region 109 are exposed on the surface of the p ⁺ well region 106. Exposure to On the p ⁺ well region 106, insulated gate type gate electrodes 112 and 113 are formed via gate insulating films 110 and 111, and both gate electrodes 112 and 113 are commonly connected. Drain electrodes 114 and 115 are connected to the n ⁺⁺ drain regions 104 and 105, respectively. Further, the source electrode 117 is connected so as to extend over the n ⁺⁺ source regions 107 and 108 and the p ⁺⁺ base contact region 109.

To turn on the above-described bidirectional LDMOSFET, a voltage is applied between the gate electrodes 112 and 113 and the source electrode 117 so that the gate electrodes 112 and 113 have a positive potential. At this time, a channel is formed immediately below the gate insulating films 110 and 111 in the p ⁺ well region 106. Here, assuming that a voltage is applied between the drain electrodes 114 and 115 so that the potential of the drain electrode 114 becomes high, the drain electrode 114 → the n ⁺⁺ drain region 104 → the n semiconductor layer 103 → the gate electrode 112 The corresponding channel → the n ⁺⁺ source region 107 → the source electrode 117 → the n ⁺⁺ source region 108 → the channel corresponding to the gate electrode 113 → the n semiconductor layer 103 → the n ⁺⁺ drain region 105 → the electron current in the route of the drain electrode 115 Flows. At this time, the current is dominated by the electron current (that is, it is monopolar), and there is no junction in the current path, so that no offset component occurs even at a low potential. That is, the linearity is good even in the minute current region. When the polarity of the voltage applied to the drain electrodes 114 and 115 is reversed, the direction of the current is reversed, but the operation is the same. As a result, as shown in FIG. 33, an alternating current can flow, and an operation with good linearity can be expected even in a minute current region.

On the other hand, to turn off the above-described bidirectional LDMOSFET, the gate electrodes 112 and 113 and the source electrode 117 are short-circuited. As a result, the channel formed immediately below the gate insulating films 110 and 111 in the p ⁺ well region 106 disappears, the electron current stops flowing, and the p ⁺ well region 106 is turned off. In the off state, no current flows regardless of whether a positive or negative voltage is applied between the drain electrodes 114 and 115. That is, it is turned off with respect to the AC voltage. Here, the breakdown voltage is equal to the breakdown voltage of one side portion of the bidirectional LDMOSFET.
AC power can be turned on and off with a single chip using the above-described bidirectional LDMOSFET, and when conducting, the linearity of the voltage-current characteristics is good even in a small current region, so that it can be used for turning on and off the signal current. Becomes possible. In addition, since the gate electrodes 112 and 113 are commonly connected and the number of the source electrodes 117 is one, only one drive circuit for supplying a control signal to the gate is required and control is easy.

As described above, since the main current flows through the channel without passing through the pn junction, the main current is basically the same as the current flowing through the resistor. Is reduced, and the on-loss can be reduced.
JP-A-11-224950 ISPSD (International Symposium on Power Semiconductor Devices and ICs) 1997, pp. 37-40)

However, in the bidirectional LDMOSFET of FIG. 32, the breakdown voltage is maintained by the breakdown voltage of one MOSFET of the bidirectional LDMOSFET. In order to maintain the forward / reverse breakdown voltage, the breakdown voltage is required for both MOSFETs, and the occupied area is doubled. As a result, the area occupied by the drain regions increases. Also, because of the planar structure, it is difficult to miniaturize the cells constituting the bidirectional LDMOSFET, and it is therefore difficult to improve the on-voltage.
An object of the present invention is to solve the above-mentioned problems and to provide a high-breakdown-voltage semiconductor device capable of increasing a cell density of a bidirectional element and reducing an on-voltage, and a method of manufacturing the same.

  In order to achieve the above object, first and second divided semiconductor regions formed by dividing a surface layer of the semiconductor region by a trench formed in a first conductivity type semiconductor region; A first conductive type first region formed on the bottom surface or the bottom surface and the side wall; and a second conductive type contacting the trench side wall and the first region formed on the first and second divided semiconductor regions, respectively. Second and third regions, a fourth region of the first conductivity type formed in contact with a side wall of the trench and in contact with the second region, in the first divided semiconductor region, and in the second divided region. A fifth region of a first conductivity type formed in contact with a side wall of the trench in contact with the semiconductor region, and a fifth region of the first conductivity type formed in contact with the third region; Through the first insulating film over the fourth region A first control electrode formed, a second control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fifth region via a second insulating film, The semiconductor device includes a first main electrode formed on the fourth region and a second main electrode formed on the fifth region.

Further, a sixth region having a lower impurity concentration than the first region may be provided between the first region and the second region, and between the first region and the third region.
Further, it is preferable that the first control electrode and the second control electrode are electrically connected.
Further, it is preferable that the first control electrode and the second control electrode are electrically insulated.
Further, it is preferable that the semiconductor region is a region formed in a surface layer of a semiconductor substrate of the second conductivity type.
It is preferable that a plurality of the first and second divided semiconductor regions are provided.
Further, it is preferable that the first divided semiconductor region and the second divided semiconductor region are formed adjacent to each other.
Further, it is preferable that a plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider between different divided regions than between the same divided regions.

Further, the first and second main electrodes may be electrically connected to the second and third regions, respectively.
Further, it is preferable that a conductor reaching the first region via an interlayer insulating film is provided inside the control electrode.
The semiconductor device may further include a seventh region of a second conductivity type formed on the bottom surface of the trench, in contact with the second and third regions, and in contact with the conductor.
Further, it is preferable that the bidirectional element and a control circuit for controlling the bidirectional element are formed on the same semiconductor substrate.
Forming a second conductivity type diffusion region in a surface layer of the first conductivity type semiconductor region; forming a trench from the surface of the diffusion region; and forming first and second divided semiconductors surrounded by the trench. Forming a region, forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the bottom of the trench, and forming the semiconductor region and the first region in the first divided semiconductor region. Forming a fourth region of the first conductivity type so as to be in contact with a side wall of the trench from a surface layer of a second region surrounded by the region and the trench; and forming the semiconductor region in the second divided semiconductor region. Forming a fifth region of a first conductivity type so as to contact a side wall of the trench from a surface layer of a third region surrounded by the first region and the trench; and forming a fifth region of the first divided semiconductor region. Trench side Forming a first control electrode through an insulating film from the first region to the fourth region; and forming the first control electrode on the trench sidewall of the second divided semiconductor region from the first region to the fifth region. Forming a second control electrode over an area through an insulating film, forming a first main electrode on the fourth area, and forming a second main electrode on the fifth area; And a manufacturing method including:

The manufacturing method may be such that the trench is formed so as to reach the semiconductor region, and the first region is formed inside the semiconductor region.
The manufacturing method may be such that the trench is formed so as to reach the semiconductor region, and the first region is formed so as to be connected to the second and third regions.
Forming a trench from the surface of the semiconductor region of the first conductivity type, forming first and second divided semiconductor regions surrounded by the trench; and diffusing a second conductivity type in a surface layer of the semiconductor region. Forming a region, forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the bottom of the trench, and forming the semiconductor region and the first region in the first divided semiconductor region. Forming a fourth region of the first conductivity type so as to be in contact with a side wall of the trench from a surface layer of a second region surrounded by the region and the trench; and forming the semiconductor region in the second divided semiconductor region. Forming a fifth region of a first conductivity type from a surface layer of a third region surrounded by the first region and the trench so as to be in contact with a sidewall of the trench; and forming a fifth region of the first divided semiconductor region. Trench Forming a first control electrode on a wall via an insulating film from the first region to the fourth region; and forming the first control electrode on the trench side wall of the second divided semiconductor region from the first region. Forming a second control electrode through an insulating film over five regions, forming a first main electrode on the fourth region, and forming a second main electrode on the fifth region And a manufacturing method including:

In addition, the manufacturing method may include a step of forming an interlayer insulating film between the first control electrode and the second control electrode.
It is preferable that the manufacturing method includes a step of forming an opening reaching the first region in the interlayer insulating film, and a step of filling the opening with a conductor.
The manufacturing method may include a step of forming a sixth region of the second conductivity type on the bottom surface of the trench, adjacent to the first region and in contact with the second and third regions.
Further, it is preferable to adopt a manufacturing method of forming a plurality of the first and second divided semiconductor regions.
In addition, the trench between the first divided semiconductor region and the second divided semiconductor region is defined as a first trench, between the first divided semiconductor regions, and between the second divided semiconductor regions. In the case where the trench is a second trench, the manufacturing method may be such that the width of the first trench is formed wider than the width of the second trench.

According to the present invention, a trench is formed in a semiconductor substrate, a gate electrode is formed on a side wall of the trench, a drain region is formed below a bottom surface of the trench, an insulating film is formed on the drain region, and the trench is surrounded by the trench. By forming the first and second source regions in the formed semiconductor region, it is possible to achieve a high withstand voltage and a low on-voltage of the bidirectional element.
In addition, the first and second source regions and the contact region are formed in the semiconductor region surrounded by the trench, and the first and second source electrodes are formed thereon, so that the safe operation region of the bidirectional element can be widened. can do.
Also, a trench is formed in a semiconductor substrate, a gate electrode is formed on a side wall of the trench, a source region is formed under the trench bottom, an insulating film is formed on the source region, and a semiconductor surrounded by the trench is formed. By forming the first and second drain regions in the region, it is possible to achieve a high withstand voltage and a low on-voltage of the bidirectional element.

  Further, by forming a source region and a base pickup region below the bottom of the trench and forming a metal electrode thereon, a safe operation region of the bidirectional element can be widened.

  In the following description, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type, but this may be reversed.

1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a plan view of a main part, and FIG. 1B is an enlarged view of a portion A in FIG. FIG. 3C is a cross-sectional view of a main part taken along line XX of FIG. Here, a bidirectional LMOSFET (bidirectional lateral MOSFET) will be described as an example. The structure of this bidirectional LMOSFET is similar to a TLPM (trench lateral power MOSFET) structure.
An n-well region 2 is formed in a p-type semiconductor substrate 1, a trench 3 is formed in the n-well region 2, an n-drain region 4 is formed below the trench bottom surface 3a, and a p-offset region is formed in a surface layer of the n-well region 2. 5 is formed.
A gate insulating film 6 is formed on the inner wall of the trench 3, and a gate electrode 7 is formed on the trench side wall 3b via the gate insulating film. First n source region 9 and second n source region 10 are selectively formed on the surface of p offset region 5 surrounded by trench 3 so as to be in contact with trench 3. The first n source regions 9 and the second n source regions 10 are formed alternately with the trench 3 interposed therebetween. The gate electrode 7 and the inside of the trench 3 are filled with an interlayer insulating film 8 and flattened. After an interlayer insulating film 8a is formed on the entire surface, a contact hole is opened in the interlayer insulating film, and a first source electrode 11 and a second source electrode 12 are formed on the first n source region 9 and the second n source region 10, respectively. Form. The first source electrodes 11 are connected to each other and the second source electrodes 12 are connected to each other via a first source wiring 13 and a second source wiring 14. The gate electrode 7 is connected to a gate pad (not shown) via a gate wiring.

As described above, since the n-drain region 4 is formed at the bottom of the trench, the electric field is relaxed and a high withstand voltage of about 30 V can be secured.
Further, as described above, by forming the gate electrode 7 and the n-drain region 4 at the bottom of the trench 3, the withstand voltage is maintained along the trench 3, so that the first n-source region 9 and the second n-source The interval on the surface of the region 10 can be reduced, and the cell can be miniaturized. As a result, the ON voltage can be reduced.
By using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. Further, the n-extended n-drain regions 4 formed at the bottom of the trench are formed apart from each other, but may be formed so that the respective n-drain regions 4 are in contact with each other.

Further, a configuration as shown in FIG. 2 may be used. FIG. 2A shows a configuration in which the n-well region 2 also serves as the n-drain region 4 in FIG. 1C. FIGS. 2A and 2B show a configuration in the case where the semiconductor substrate is an n-type, and FIG. 2B shows a configuration in which the semiconductor substrate 1 also serves as the n-drain region 4 in FIG. 1C. In FIG. 3C, the n-drain region 4 in FIG. 3B is further formed.
Further, in FIG. 1C, the gate electrode 7 is formed in the trench 3 so as to be divided into right and left, but may be one as shown in FIG.
FIG. 3 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of the bidirectional LDMOSFET 50 will be described. By applying a high voltage to the second source terminal S2 with respect to the first source terminal S1 and applying a voltage higher than the second source terminal S2 to the gate terminal G, the first and second n source regions 9 in FIG. A channel is formed on the side surface of the p offset region 5 sandwiched between the drain region 10 and the n drain region 4, and a current flows from the second source terminal S2 to the first source terminal S1. By applying a high voltage to the first source terminal S1 with respect to the second source terminal S2 and applying a voltage higher than the first source terminal S1 to the gate terminal G, the first and second n source regions 9, 10 and n A channel is formed on the side surface of the p-offset region 5 sandwiched between the drain regions 4, and a current flows from the first source terminal S1 to the second source terminal S2. As described above, a bidirectional LMOSFET capable of flowing a current in both directions is obtained.

  On the other hand, by setting the gate terminal G to the potential of the lower potential side terminal of the first and second source terminals S1 and S2 or to the ground potential, the channel formed in the p offset region 5 is extinguished. The bidirectional LMOSFET can be in a blocking state.

4A and 4B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention. FIG. 4A is a plan view of a main part corresponding to FIG. 1B, and FIG. It is principal part sectional drawing cut | disconnected by XX of FIG. The difference from FIG. 1 is that p contact regions 15 and 16 surrounded by first and second n source regions 9 and 10 are formed in the surface layer of the p offset region 5, and the p contact regions 15 and 16 are formed on the first n source region 9 and the second n source region. 10 and the p contacts 15 and 16 are formed. The operation is the same as that described with reference to FIG.
By forming the p-contact regions 15 and 16 as described above, the potential of the p-offset region 5 is stabilized, and the safe operation region of the bidirectional LMOSFET is widened. Others are the same as the first embodiment.
The bidirectional LMOSFET has a built-in parasitic diode due to the formation of the p contact regions 15 and 16, and also has an operation mode as a bidirectional IGBT. Therefore, even when the gate voltage (the voltage of the gate electrode 7) is lower than the voltage of the source electrode on the high potential side, the main current can flow between the first source electrode 11 and the second source electrode 12.

5A and 5B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention. FIG. 5A is a plan view of a main part, and FIG. 5B is an enlarged view of a portion B in FIG. FIG. 3C is a cross-sectional view of a main part taken along line XX of FIG. Here, a bidirectional LMOSFET will be described as an example.
An n well region 2 is formed in a p semiconductor substrate 1, a trench 33 is formed in the n well region 2, an n source region 34 is formed below the trench bottom surface 33a, and a p offset region is formed in a surface layer of the n well region 2. 35 is formed.
A gate insulating film 36 is formed on the inner wall of the trench 33, and a gate electrode 37 is formed on the trench side wall 33b via the gate insulating film 36. A first n drain region 39 and a second n drain region 40 are formed on the surface of the p offset region 35 surrounded by the trench 33 so as to be in contact with the trench 33. The first n drain regions 39 and the second n drain regions 40 are formed alternately with the trench 33 interposed therebetween. The gate electrode 37 and the inside of the trench 33 are filled with an interlayer insulating film 38 and flattened. A contact hole is opened in the interlayer insulating film 38, a first drain electrode 41 and a second drain electrode 42 are formed on the first n drain region 39 and the second n drain region 40, respectively. And the pickup electrode 45 is filled. This pickup electrode 45 has an effect of setting the same potential when the n source region is formed by dividing the source region into a plurality of parts, and can be set at a predetermined potential by applying a control voltage. For example, a ground potential can be applied when the device is off to prevent a current from flowing between D1 and D2. The first drain electrodes 41 and the second drain electrodes 42 are connected by a first drain wiring 43 and a second drain wiring 44, respectively. The gate electrode 37 is connected to a gate pad (not shown) via a gate wiring.

Since the n source region 34 is formed at the bottom of the trench and is covered with the interlayer insulating film 38, the electric field is relaxed and a high withstand voltage of about 30 V can be secured.
Further, as described above, by forming the gate electrode 37 and the p-offset region 35 in the trench, the breakdown voltage is maintained along the trench side wall 33b, so that the first n-drain region 39 and the second n-drain The interval on the surface of the region 40 can be reduced, and the cell can be miniaturized. As a result, the ON voltage can be reduced.
By using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. Although the n source regions 34 formed at the bottom of the trench are formed apart from each other, they may be formed so that the respective n drain regions 34 are in contact with each other.

  FIG. 6 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of the bidirectional LMOSFET 60 will be described. By applying a high voltage to the second drain terminal D2 with respect to the first drain terminal D1 and applying a voltage higher than the first drain terminal D1 to the gate terminal G, the first and second n drain regions 39 shown in FIG. , 40 and a channel is formed on the side surface of p offset region 35 interposed between n source regions 34, and current flows from second drain terminal D2 to first drain terminal D1. By applying a high voltage to the first drain terminal D1 with respect to the second drain terminal D2 and applying a higher voltage to the gate electrode G than the second drain terminal D2, the first and second n drain regions 39, 40 and n A channel is formed on the side surface of the p offset region 35 interposed between the source regions 34, and current flows from the first drain terminal D1 to the second drain terminal D2. Thus, a bidirectional LMOSFET is obtained.

  On the other hand, by setting the gate terminal G to the same potential as the lower potential of the first and second drain terminals D1 and D2, the channel formed in the p-offset region 35 is extinguished, and the bidirectional LMOSFET is brought into a blocking state. Can be.

7A and 7B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention. FIG. 7A is a plan view of a main part corresponding to FIG. 5B, and FIG. (C) is a cross-sectional view of a main part taken along line X2-X2 in (a) of FIG. Here, a bidirectional LMOSFET will be described as an example.
The difference from FIG. 5 is that a p-base pickup region 46 is formed next to the n-source region 34 below the trench bottom surface 33a, and a pickup electrode 45 is formed so as to be in contact with the n-source region 34 and the p-base pickup region 36. It is. The operation is the same as that described with reference to FIG.
Thus, by forming the p base pickup region 46 and short-circuiting the p base pickup region 46 and the n source region 34 by the pickup electrode 45, the potential of the p offset region 35 is stabilized, and the safe operation of the bidirectional LMOSFET is achieved. The area becomes wider. Others are the same as the third embodiment.

FIG. 8 is a layout view of a main part of a semiconductor device according to a fifth embodiment of the present invention. Here, the power IC mounted on the battery device is shown as an example.
In this power IC, a bidirectional LMOSFET 50, a drive / protection circuit unit 51, and a remaining amount circuit unit 52 are formed on the same semiconductor substrate 91. The drive / protection circuit unit 51 and the remaining amount circuit unit 52 are provided with a voltage of the battery cell 92, a charging current flowing into the battery cell 92 from a charger (not shown), and a discharging current flowing out of the battery cell 92 to a load (eg, a portable device). Is detected by the resistor 93, and the bidirectional LMOSFET 50 is controlled normally, and in the case of an abnormality such as overcharge or overdischarge, a signal for turning off the bidirectional LMOSFET 50 is transmitted to the bidirectional LMOSFET 50. The drive / protection circuit unit 51 includes a charge pump circuit 53, and can apply a voltage higher than the voltages of the first and second source terminals S1 and S2 of the bidirectional LMOSFET 50 to the gate terminal G. ing. The control terminal is a terminal for externally specifying the remaining charge of the battery cell 92.

9A to 9C show a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-type semiconductor substrate 1, a p-offset region 5 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is formed, and an n-well region 2 is formed using an oxide film as a mask. A trench 3 having a width of 1.5 μm is formed, and an n-drain region 4 having a surface concentration of 1 × 10 ¹⁸ cm ⁻³ and a diffusion depth of 1 μm is ion-implanted and heat-treated (drive) from the window of the trench 3 to the bottom surface 3 a of the trench 3. (FIG. 3A). Here, the trench 3 is formed after the well region 2 and the p-offset region 5 are formed, but may be formed after the trench 3 is formed.
Next, ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees in a channel formation portion of the trench side wall 3b at a tilde angle of 45 degrees to form a diffusion layer having a surface concentration of 7 × 10 ¹⁶ cm ⁻³ and a diffusion depth of 0.3 μm. I do. Subsequently, the channel forming portion is cleaned to form a gate insulating film 6 (for example, a gate oxide film) on the inner wall of the trench. On this gate insulating film 6, doped polysilicon serving as a gate electrode 7 is formed to a thickness of 0.3 μm. And the gate electrode 7 is formed by anisotropic etching (FIG. 4B).

  Next, first and second n source regions 9 and 10 are formed in the surface layer of the p offset region 5, and an oxide film is deposited as an interlayer insulating film 8. In this step, the inside of the trench is filled with the interlayer insulating film 8, and the surface of the interlayer insulating film 8 is planarized by etch back. Subsequently, ion implantation for reducing contact resistance is performed on the first and second n source regions 9 and 10, and the first and second source electrodes 11 are formed on the first and second n source regions 9 and 10 with aluminum or the like. 12 is formed. Subsequently, a first source wiring and a second source wiring (not shown) are formed (FIG. 3C).

10A to 10C show a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. FIGS. 10A to 10C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
9 is different from FIG. 9 in that p contact regions 15 and 16 are formed in FIG. 10C and the first and second source electrodes 11 and 12 and the p contact regions 15 and 16 are in contact with each other.

FIGS. 11A to 11C show a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention. FIGS. 11A to 11C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method for manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-type semiconductor substrate 1, a 3 μm wide trench 33 is formed in the n-well region 2 using an oxide film (not shown) as a mask, and a surface concentration of 1 × An n source region 34 of 10 ¹⁸ cm ⁻³ and a diffusion depth of 1 μm is formed by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed, and a p-offset region 35 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is formed on the isolation semiconductor region 61 divided by the trench 33 so as to be in contact with the n-drain region 34. (FIG. 3A).
Next, ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees into a channel formation portion of the trench side wall 33b to form a diffusion layer having a surface concentration of 7 × 10 ¹⁶ cm ⁻³ and a diffusion depth of 0.3 μm. To form Subsequently, the channel formation portion is cleaned, a gate insulating film 36 is formed on the inner wall of the trench, and doped polysilicon serving as a gate electrode 37 is deposited on the gate insulating film 36 to a thickness of 0.3 μm, A gate electrode 37 is formed by etching (FIG. 4B).

  Next, first and second n drain regions 39 and 40 are formed in the surface layer of the p offset region 35, and an oxide film is deposited as an interlayer insulating film 38. In this step, the inside of the wide trench is not filled with the interlayer insulating film 38, and the interlayer insulating film 38 at the bottom of the trench is removed by etching back to expose the surface of the n source region 34. Subsequently, a barrier metal (not shown) is formed on the bottom surface 33 of the trench, and a pickup electrode 45 such as tungsten is buried and flattened. Subsequently, ion implantation for reducing contact resistance is performed on the first and second drain regions 39 and 40, and the first and second drain electrodes 41 and 42 are formed on the first and second n drain regions 39 and 40 with aluminum or the like. 42 is formed. At this time, an aluminum film is also formed on the pickup electrode 45 at the same time. Subsequently, a first drain wiring and a second drain wiring (not shown) are formed (FIG. 3C).

12A and 12B show a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention. FIGS. 12A and 12B are cross-sectional views of a main part manufacturing process corresponding to FIG. 11D and 11D are cross-sectional views of a main part manufacturing step corresponding to FIG. 7 (a) and 7 (c) are cross-sectional views of a main part manufacturing process corresponding to X1-X1 of FIG. 7 (a), and FIGS. 7 (b) and 7 (d) are X2-X2 of FIG. 7 (a). FIG. 13 is a sectional view of a relevant part manufacturing step corresponding to FIG. This is a method for manufacturing the bidirectional LMOSFET of FIG.
11 is different from FIG. 11 in that a p-base pickup region 46 is formed at the bottom of the trench in FIG. 12A, and the pickup electrode 45 is in contact with the p-base pickup region 46 in FIG. 12C. .

13A to 13C show a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention. FIGS. 13A to 13C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a manufacturing method in which the bidirectional LMOSFET and the CMOS shown in FIG. 1 are formed on the same semiconductor substrate. CMOS is a basic element for forming the drive / protection circuit and the remaining amount circuit of FIG.
An n-well region 72 is formed on p-semiconductor substrate 71, a 1.5-μm wide trench 73 is formed in n-well region 72 using an oxide film (not shown) as a mask, and a p-well region 76 is also formed. Then, an n-drain region 74 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is formed on the bottom surface 73a of the trench by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed to form a p-offset region 75 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm (FIG. 7A).

Next, element isolation on the surface is performed by a LOCOS step, and ion implantation for threshold adjustment (not shown) is performed at a tilde angle of 45 degrees into a channel formation portion of the CMOS portion and a channel formation portion of the trench side wall 73b, and a surface concentration of 7 × A diffusion layer having a diffusion depth of 10 ¹⁶ cm ⁻³ and a depth of 0.3 μm is formed. Subsequently, the channel forming portion is cleaned, a gate insulating film 79 is formed on the inner wall of the trench, and doped polysilicon serving as a gate electrode 80 is deposited on the gate insulating film 79 to a thickness of 0.3 μm. A CMOS portion and a gate electrode 80 inside the trench are formed by reactive etching (FIG. 4B).
Next, first and second n source regions 81 and 82 are formed in the surface layer of the p offset region 75, source / drain regions 83 and 84 are formed in the CMOS portion, and an oxide film is deposited as an interlayer insulating film 87. In this step, the inside of the trench is filled with the interlayer insulating film 87, and the surface of the interlayer insulating film 87 is flattened by etch back. Subsequently, contact holes are formed in the interlayer insulating film 87, plug ions are implanted into the openings to reduce the contact resistance, and the first and second n-type source regions 81 and 82 are formed on the first and second n-type source regions 81 and 82 with aluminum or the like. Source electrodes 85 and 86 are formed, and source / drain electrodes 88 and 89 are formed on the source / drain regions 83 and 84 in the CMOS section (FIG. 3C).

  An embodiment which is a semiconductor device different from the semiconductor device of the present invention and includes a gate wiring structure will be described. The gate wiring and the source electrode are simultaneously formed of a metal film. Here, the one connected by the contact hole and arranged immediately above the source region is defined as a source electrode, and the other part is defined as a gate wiring.

14 to 17 show a semiconductor device according to an eleventh embodiment of the present invention, showing a main part configuration including a gate wiring structure. FIG. 14 is a plan view, and FIG. 15 is a line XX of FIG. 16, FIG. 16 is a cross-sectional view taken along line YY in FIG. 14, and FIG. 17 is a cross-sectional view taken along line ZZ in FIG. FIG. 14 is a plan view as viewed from the surface, and a portion hidden by a shadow is indicated by a dotted line. The interlayer insulating film 208a is not shown.
Only the points different from FIG. 1 will be described. In FIG. 1, one first n source region 9 and one second n source region 10 are alternately arranged. In this embodiment, however, the first n source regions 209 are adjacent to each other. A plurality of the second n source regions 210 are formed adjacent to each other. Further, the p offset region 205 is not in contact with the n drain region 204. Further, p contact regions 215 and 216 are formed in each source region as in FIG. A gate wiring structure not shown in FIG. 1 is shown.

When the p-offset region 205 is not in contact with the n-drain region 204, the withstand voltage can be increased and the on-resistance can be reduced as compared with the case where the p-offset region 205 is in contact. However, since the width of the p-offset (the width between the n-well region 202 and the source region 209) is small, high precision is required during manufacturing.
As shown in FIGS. 14 to 17, a first source electrode 211 connected to the first n source region 209 via a contact hole 217 formed in the interlayer insulating film 208a, and a first source electrode connected to the first source electrode 211 The wiring 213 is formed simultaneously with a metal film. In addition, the second source electrode 212 connected to the second n source region 210 via the contact hole 217 formed in the interlayer insulating film 208a and the second source wiring 214 connected to the second source electrode 212 are simultaneously formed of a metal film. It is formed. A space between the adjacent first n source regions 209 and between the second n source regions 210 is filled with a gate electrode 207 formed with a gate insulating film 206 interposed therebetween. The first n source region 209 group and the second n source region 210 group face each other with the interlayer insulating film 208 interposed therebetween. The current capacity can be increased by enlarging the trench outer periphery 203a and alternately arranging a large number of the first n source regions 209 and the second n source regions 210.

The polysilicon forming the gate electrode 207 forms an elongated trench 203b protruding like a cap from the outer periphery 203a of the trench where the n source regions 209 and 210 are formed, and a gate insulating film formed on the inner wall of the trench 203b. Polysilicon wiring 218 is formed via 206, and this polysilicon wiring 218 is also formed on gate insulating film 206 formed on p semiconductor substrate 201. The polysilicon wiring 218 and the gate wiring 219 of a metal film are connected via a contact hole 217 formed in the interlayer insulating film 208a.
As described above, in the above-described semiconductor device of the present invention, since the polysilicon (gate electrode 207) formed over the entire sidewall of the trench outer periphery 203a is connected, only one gate electrode 207 is provided.
FIG. 8 shows an example of an application apparatus using a semiconductor device having a single gate electrode.

FIGS. 18A and 18B are diagrams in which the bidirectional LMOSFET and the drive / protection circuit unit of FIG. 8 are extracted and shown. FIGS. 18A to 18C show the time course when the battery cell is overcharged. FIG.
8A, when charging is performed in a state where a portable device, which is a load (not shown), is connected to the battery cell 92 in FIG. 8, an ON signal is supplied to the gate terminal G to turn on the left and right n-channel MOSFETs. As a result, the charging current I1 flows from the right to the left through the bidirectional LMOSFET 50 in the battery cell 92. At this time, the discharge current I2 is being supplied from the battery cell 92 to the load. That is, the battery cell 92 is discharging while not being charged.
In FIG. 9B, when the battery cell 92 is overcharged, an off signal is supplied to the gate terminal G to turn off the left and right n-channel MOSFETs. When the left and right n-channel MOSFETs are turned off, the load and the battery cell 92 are separated from each other in circuit, the charging current I1 does not flow to the battery cell 92, and the overcharge stops. At the same time, the discharge current I2 is not supplied from the battery cell 92 to the load. If the battery charger of FIG. 8 is unplugged during this overcharge period, no current is supplied to the load, and the load becomes inoperable.

To avoid this, an ON signal is again supplied to the gate terminal G to turn on the bidirectional LMOSFET 50 to supply the discharge current I2 from the battery cell 92 to the load, as shown in FIG. However, since the drive / protection circuit 51 outputs an ON signal by detecting that the voltage of the battery cell 92 has become a normal voltage, a time delay occurs, and during that time, no current is supplied from the battery cell 92 to the load. A state, that is, a momentary interruption occurs.
As a method of solving this, there is a method of using a bidirectional LMOSFET in which a gate electrode is provided for each of the left and right n-channel MOSFETs.
FIG. 19 is an equivalent circuit diagram of a bidirectional LMOSFET having two gate electrodes. This is a diagram corresponding to FIG.
The difference from FIG. 6 is that since there are two gate electrodes, the gate terminal G in FIG. 6 is a first terminal G1 and a second gate terminal G2, and the respective n-channel MOSFETs 331 and 332 are The point is that they can be operated individually, and the point is that the parasitic diodes 333 and 334 of the n-channel MOSFET are used for the operation.

An operation mode using the bidirectional LMOSFET 300 having the two gate electrodes will be described below.
FIG. 20 is a diagram corresponding to FIG. 18, and FIGS. 20A to 20C are diagrams illustrating a lapse of time when the battery cells are overcharged.
In FIG. 7A, an ON signal is given to the first and second gate terminals G1 and G2 from the drive / protection circuit 51, the left and right n-channel MOSFETs 331 and 332 are turned on, and the charging current I1 flows to the battery cell 92. . At this time, the discharge current I2 is being supplied from the battery cell 92 to the load. That is, the battery cell 92 is discharging while not being charged.
In FIG. 6B, when the battery cell 92 is overcharged, an off signal is given to the first gate terminal G1 to stop the charging current I1. At this time, the ON signal is kept applied to the second gate terminal G2. Then, even if the charging current I1 stops, the above-mentioned momentary interruption does not occur because the discharging current I2 flows to the load through the parasitic diode 333 and the n-channel MOSFET 332.

In FIG. 9C, when the battery cell 92 returns to the normal voltage, an ON signal is again supplied to the first gate terminal G1, and the left n-channel MOSFET 331 is turned ON. In this state, the discharge current I2 is supplied to the load via the left and right n-channel MOSFETs 331 and 332, and the operation returns to the normal operation.
As described above, by using the bidirectional LMOSFET 300 having two gate electrodes, the current can be supplied to the load without interruption.
Next, a configuration of a semiconductor device having two gate electrodes is described.

  FIGS. 21 to 25 show a semiconductor device according to a twelfth embodiment of the present invention. FIG. 21 is a plan view of a main part including a gate wiring, FIG. 21 is a plan view, and FIG. 23 is a sectional view taken along line BB of FIG. 21, FIG. 24 is a sectional view taken along line CC of FIG. 21, and FIG. 25 is a sectional view taken along line DD of FIG. It is sectional drawing. FIG. 21 is a plan view as viewed from the surface, where a portion hidden by a shadow is indicated by a dotted line, and the interlayer insulating film 308a is not illustrated. In the trench, there are a plurality of islands 341 and 342, which are the remaining portions of the columnar trenches. And two islands 342 forming gate wiring. On the island 341, a p offset region 305, n source regions 309 and 310, and source electrodes 311 and 312 are formed. The difference from FIGS. 14 to 17 is that the first gate electrode 307a and the second gate electrode 307b whose gate electrodes are respectively surrounded by the interlayer insulating film 308 are independent, and these gate electrodes 307a and 307b The point that the gate electrode 307a and the gate electrode 307b are connected to the metal first gate wiring 319 and the second gate wiring 320 through the polysilicon wiring 318 is separated from the polysilicon 307 on the side wall 303a. is there.

As described above, since the polysilicon 307 formed on the trench outer periphery 303a and the first gate electrode 307a and the second gate electrode 307b are separated by the interlayer insulating film 308, the island 341 on which the first n source region 309 is formed is formed. The distance W1 between the islands 341 where the second n source regions 310 are formed is set to a width that is not filled with polysilicon for forming a gate electrode. On the other hand, the distance Wg1 between the islands 341 forming the first and second n-type source regions 309 and 310 is set to a width that is completely filled with polysilicon forming the gate electrode. The space Wg2 between the island 342 forming the polysilicon wiring 318 for connecting the gate electrodes 307a and 307b to the metal gate wirings 319 and 320 and the island 341 forming the n source regions 309 and 310 are also filled with polysilicon. Therefore, the interval is set to be the same as Wg1.
For example, when the thickness of the polysilicon forming the gate electrode is 0.3 μm, W1 is about 1 μm, and Wg1 and Wg2 are about 0.5 μm. Further, in order to flatten the surface, W1 is preferably set to be equal to or less than the width of the island 341 forming the source region.

  By forming the independent first and second gate electrodes 307a and 307b in this manner, the effect described with reference to FIG. 20 can be obtained.

26 to 29 are views showing a method for manufacturing a semiconductor device according to the thirteenth embodiment of the present invention, and are cross-sectional views of main steps in the order of steps. In each figure, (a) is a cross-sectional view of a portion corresponding to FIG. 22, (b) is a cross-sectional view of a portion corresponding to FIG. 23, and (c) is a cross-sectional view of a portion corresponding to FIG.
In FIG. 26, for example, an n-well region 302 having a surface concentration of 5 × 10 ¹⁶ cm ⁻² and a depth of about 4 μm is formed in a surface layer of a p-type semiconductor substrate 301, and a trench 303 reaching the n-well region 302 from the surface is formed in a mesh shape. Then, a trench-remaining portion, that is, islands 341 and 342 are formed in a columnar shape. The islands 341 and 342 are connected to the island 341 that forms the first and second p-offset regions and the first and second n-source regions in a later step, and the first and second gate electrodes and the first and second gate wirings. The island 342 forms the polysilicon wiring 318.

The distance Wg1 between the islands 341 and the distance Wg2 between the islands 341 and 342 are equal and about 0.5 μm, so that the polysilicon is not separated even by polysilicon etch back (polysilicon patterning). Can be filled with. By setting the distance W1 between the islands 341 and 342 and the side wall of the trench outer periphery 303a and the distance W1 between the islands 341 forming the first source region 309 and the second source region 310 to 1 μm or more, the polysilicon etching is performed. At the back, the polysilicon can be completely separated.
In FIG. 27, a gate insulating film 306 is formed, and an n-drain region 304 is formed at a high concentration of 1 × 10 ¹⁷ cm ⁻³ or more in the n-well region 302 on the bottom of the trench in order to have a withstand voltage of about 30 V to 50 V. Then, a p-offset region 305 is formed apart from the n-drain region 304 (it may be connected). Thereafter, polysilicon, which will be the first and second gate electrodes 307a and 307b and the polysilicon wiring 318, is formed on the entire surface with a thickness of about 0.3 μm, and polysilicon is formed between the islands 341 and between the islands 341 and 342. After completely filling with silicon, patterning is performed.

In FIG. 28, the first and second n source regions 309 and 310 are formed at a high concentration of 1 × 10 ²⁰ cm ⁻³ or more using the first and second gate electrodes 307a and 307b as a mask. A high-concentration p contact region 316 that reaches the p offset region 305 through the regions 309 and 310 is formed, and an interlayer insulating film 308a is formed on the surface.
In FIG. 29, a contact hole 317 is formed in an interlayer insulating film 308a, and first and second metal source electrodes connected to the first and second n source regions 309 and 310 and the p contact regions 315 and 316 in the contact hole 317. 311 and 312, and first and second source wirings 313 and 314 formed simultaneously with the first and second source electrodes 311 and 312, and polysilicon wiring formed simultaneously with the first and second gate electrodes 307a and 307b. Metal first and second gate wirings 319 and 320 connected to 318 are formed.

  When the thickness of polysilicon such as a gate electrode is about 0.3 μm, W1 may be 1 μm or more, and may be smaller than the width of an island to flatten the surface. Further, Wg1 = Wg2 may be set to 0.5 μm or less.

1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view of a main part, FIG. 1B is an enlarged view of a portion A of FIG. 1A, and FIG. Sectional view FIGS. 2A and 2B are diagrams of a configuration different from FIG. 1A, in which FIG. 1A is a diagram in which an n-well region also serves as an n-drain region 4 in FIG. 1C, and FIG. The figure also serving as an n-drain region, and (c) is a view in which an n-drain region 4 is further formed in (b). FIG. 1 is an equivalent circuit diagram of the bidirectional LMOSFET. 2A and 2B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, wherein FIG. 1A is a plan view of a main part corresponding to FIG. 1B, and FIG. 1B is a main part cut along line XX of FIG. Sectional view It is a block diagram of the semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is the B section enlarged view of (a), (c) is XX line of (b). Sectional view Equivalent circuit diagram of the bidirectional LMOSFET of FIG. It is a block diagram of the semiconductor device of 4th Example of this invention, (a) is a principal part plane view corresponding to FIG.5 (b), (b) is a principal part cross section cut | disconnected by X1-X1 of (a). FIG. 3C is a cross-sectional view of a main part taken along line X2-X2 of FIG. Main part layout of a semiconductor device according to a fifth embodiment of the present invention. 14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. 14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. 14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. This is a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention, in which (a) and (b) are cross-sectional views of a main part manufacturing step corresponding to FIG. 11 (a), and FIGS. Sectional manufacturing process sectional view corresponding to c) 14A to 14C are cross-sectional views of a main part manufacturing process shown in the order of processes. Main part plan view of a semiconductor device according to an eleventh embodiment of the present invention. FIG. 14 is a cross-sectional view taken along line XX of FIG. 14. FIG. 14 is a sectional view taken along line YY in FIG. 14. FIG. 14 is a sectional view taken along line ZZ in FIG. 14. FIG. 9 is a diagram in which the bidirectional LMOSFET and the drive / protection circuit unit of FIG. 8 are drawn and omitted, and (a) to (c) are diagrams illustrating a time course when the battery cell is overcharged. Equivalent circuit diagram of a bidirectional LMOSFET having two gate electrodes FIG. 19 is a diagram corresponding to FIG. 18 in the case where a bidirectional LMOSFET having two gate electrodes is used, and (a) to (c) are diagrams illustrating a time course when a battery cell is overcharged. Main part plan view of a semiconductor device according to a twelfth embodiment of the present invention. Sectional drawing cut | disconnected by the AA line of FIG. Sectional drawing cut | disconnected by the BB line of FIG. Sectional drawing cut | disconnected by CC line of FIG. Sectional drawing cut | disconnected by the DD line of FIG. FIGS. 23A and 23B are cross-sectional views of main parts of a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention, in which FIG. 23A is a cross-sectional view of a part corresponding to FIG. (C) is a sectional view of a portion corresponding to FIG. FIG. 27 is a cross-sectional view of a main part step of the method for manufacturing a semiconductor device according to the thirteenth embodiment of the present invention, following FIG. 26, where (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. FIG. 28 is a cross-sectional view of a main part of a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention, following FIG. 27, wherein (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. FIG. 29 is a cross-sectional view of a main part step of a manufacturing method of a semiconductor device according to a thirteenth embodiment of the present invention, following FIG. 28, where (a) is a cross-sectional view of a portion corresponding to FIG. FIG. 24C is a cross-sectional view of a portion, and FIG. Sectional view of main part of conventional bidirectional LIGBT The figure which shows the output characteristic of the bidirectional LIGBT of FIG. Sectional view of main part of another conventional bidirectional MOSFET The figure which shows the output characteristic of the bidirectional LIGBT of FIG.

Explanation of reference numerals

1, 71 201, 301 p semiconductor substrate
2, 72 202, 302 n-well region
3, 33, 73, 203, 303 trench
3a, 33a, 73a Bottom
3b, 33b, 73b Side view
4, 74, 204, 304 n drain region
5, 35, 75, 205, 305 p offset region
6, 36, 79, 206, 306 Gate insulating film
7, 37, 80, 207 Gate electrode
8, 38, 87, 208, 208a, 308, 308a Interlayer insulating film
9, 81, 209, 309 1st n source region 10, 82, 210, 310 2nd n source region 11, 85, 211, 311 1st source electrode 12, 86, 212, 312 2nd source electrode 13, 213, 313 1 source wiring 14, 214, 314 second source wiring 15, 16, 215, 216, 315, 316 p contact region 34 n source region 39 first n drain region 40 second n drain region 41 first drain electrode 42 second drain electrode 43 First drain wiring 44 Second drain wiring 45 Pickup electrode 46 p base pickup area 50, 60 Bidirectional LMOSFET
REFERENCE SIGNS LIST 51 Drive / protection circuit unit 52 Remaining circuit unit 53 Charge pump circuit 61 Divided semiconductor region 70, 90, 91 Semiconductor substrate 83, 84 Source / drain region 88, 89 Source / drain electrode 92 Battery device 203a, 303a Trench outer periphery 203b Projection Trench 307 polysilicon 217, 317 contact hole 218, 318 polysilicon wiring 219 gate wiring 300 bidirectional LMOSFET
307a first gate electrode 307b second gate electrode 319 first gate wiring 320 second gate wiring 331, 332 n-channel MOSFET
333, 334 Parasitic diode 341, 342 Island
S1 First source terminal
S2 Second source terminal
G Gate terminal
G1 First gate terminal
G2 Second gate terminal
D1 first drain terminal
D2 Second drain terminal

Claims (21)

First and second divided semiconductor regions formed by dividing a surface layer of the semiconductor region by a trench formed in the first conductivity type semiconductor region;
A first region of a first conductivity type formed on a bottom surface or a bottom surface and a side wall of the trench;
Second and third regions of the second conductivity type, which are formed in the first and second divided semiconductor regions, respectively, and are in contact with the side wall of the trench and the first region;
A fourth region of a first conductivity type formed in contact with the sidewall of the trench and in contact with the second region, in the first divided semiconductor region;
A fifth region of a first conductivity type formed in contact with the side wall of the trench and in contact with the third region, in the second divided semiconductor region;
A first control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fourth region via a first insulating film;
A second control electrode formed on the trench sidewall of the first divided semiconductor region from the first region to the fifth region via a second insulating film;
A first main electrode formed on the fourth region,
A second main electrode formed on the fifth region,
A bidirectional element having: 2. The device according to claim 1, further comprising a sixth region having a lower impurity concentration than the first region, between the first region and the second region, and between the first region and the third region. 3. Directional element. The bidirectional element according to claim 1, wherein the first control electrode and the second control electrode are electrically connected. 3. The bidirectional device according to claim 1, wherein the first control electrode and the second control electrode are electrically insulated. The bidirectional element according to claim 1, wherein the semiconductor region is a region formed on a surface layer of a semiconductor substrate of the second conductivity type. The bidirectional element according to claim 1, wherein a plurality of the first and second divided semiconductor regions are provided. The bidirectional device according to claim 6, wherein the first divided semiconductor region and the second divided semiconductor region are formed adjacent to each other. A plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider between different divided regions than between the same divided regions. Item 6. The bidirectional element according to any one of Items 1 to 5. The bidirectional element according to claim 1, wherein the first and second main electrodes are electrically connected to the second and third regions, respectively. The bidirectional element according to claim 1, further comprising a conductor that reaches the first region via an interlayer insulating film inside the control electrode. The bidirectional device according to claim 10, further comprising a seventh region of a second conductivity type formed on a bottom surface of the trench, in contact with the second and third regions, and in contact with the conductor. The semiconductor device including the bidirectional element according to claim 1, wherein the bidirectional element and a control circuit for controlling the bidirectional element are formed on the same semiconductor substrate. Forming a diffusion region of the second conductivity type in a surface layer of the semiconductor region of the first conductivity type;
Forming a trench from the surface of the diffusion region and forming first and second divided semiconductor regions surrounded by the trench;
Forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the trench bottom surface;
A fourth region of a first conductivity type is formed in the first divided semiconductor region so as to be in contact with a side wall of the trench from a surface layer of the semiconductor region, the first region, and a second region surrounded by the trench. The process of
A fifth region of the first conductivity type is formed in the second divided semiconductor region from a surface layer of the third region surrounded by the semiconductor region, the first region, and the trench so as to be in contact with a sidewall of the trench. The process of
Forming a first control electrode on the trench side wall of the first divided semiconductor region via an insulating film from the first region to the fourth region;
Forming a second control electrode on the trench sidewall of the second divided semiconductor region via an insulating film from the first region to the fifth region;
Forming a first main electrode on the fourth region;
Forming a second main electrode on the fifth region;
A method for manufacturing a bidirectional device, comprising: 14. The method according to claim 13, wherein the trench is formed to reach the semiconductor region, and the first region is formed inside the semiconductor region. The method according to claim 14, wherein the trench is formed to reach the semiconductor region, and the first region is formed to be connected to the second and third regions. Forming a trench from the surface of the semiconductor region of the first conductivity type and forming first and second divided semiconductor regions surrounded by the trench;
Forming a diffusion region of the second conductivity type in a surface layer of the semiconductor region;
Forming a first region of a first conductivity type connected to the semiconductor region by diffusion from the trench bottom surface;
A fourth region of the first conductivity type is formed in the first divided semiconductor region so as to be in contact with a side wall of the trench from a surface layer of the semiconductor region, the first region, and a second region surrounded by the trench. The process of
A fifth region of the first conductivity type is formed in the second divided semiconductor region from a surface layer of the third region surrounded by the semiconductor region, the first region, and the trench so as to be in contact with a sidewall of the trench. The process of
Forming a first control electrode on the trench side wall of the first divided semiconductor region via an insulating film from the first region to the fourth region;
Forming a second control electrode on the trench sidewall of the second divided semiconductor region via an insulating film from the first region to the fifth region;
Forming a first main electrode on the fourth region;
Forming a second main electrode on the fifth region;
A method for manufacturing a bidirectional device, comprising: 17. The method according to claim 13, further comprising a step of forming an interlayer insulating film between the first control electrode and the second control electrode. Forming an opening reaching the first region in the interlayer insulating film;
Filling the opening with a conductor;
The method for manufacturing a bidirectional element according to claim 17, comprising: 19. The method according to claim 18, further comprising: forming a sixth region of the second conductivity type on the bottom surface of the trench, adjacent to the first region and in contact with the second and third regions. A method for manufacturing a bidirectional element. 19. The method according to claim 13, wherein a plurality of the first and second divided semiconductor regions are formed. The trench between the first divided semiconductor region and the second divided semiconductor region is formed as a first trench, between the first divided semiconductor regions, and between the second divided semiconductor regions. 21. The method according to claim 20, wherein when the trench is a second trench, the width of the first trench is formed wider than the width of the second trench.

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