JP2000243949A - Trenched semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect an insulation film and at the same time reduce an element area by preventing a base region at a position that is not surrounded by a plurality of gate electrodes from being connected to any electrode directly. SOLUTION: A high-concentration N+-type source region 105 is formed in P-type base regions 104, and a U gate electrode 107 is formed on an N-type drain region 103 between the adjacent P-type base regions 104 and on one portion of the P-type base region 104 via a U gate insulation film 106. Then, a source electrode 109 and a drain electrode 110 are formed while being insulated from a U-type gate electrode 107 by a first interlayer insulation film 111, and the source electrode 109 and a second interlayer insulation film 112 are used for insulating, thus forming a second drain electrode 113. At this time, a base region 130 at a position that is not surrounded by each gate electrode 107 is allowed not to be in contact with any electrode directly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench type semiconductor device having a power transistor used for an IPD (Intelligent Power Device) and the like, and more particularly to a device for protecting a gate insulating film from a drain surge voltage and an element. An object of the present invention is to provide a groove type semiconductor device whose area can be reduced.

[0002]

2. Description of the Related Art As a conventional groove type semiconductor device, there has been one having a structure as shown in FIGS. 6 and 7, for example, as disclosed in Japanese Patent Application Laid-Open No. 8-316467. FIG. 6 is a plan pattern layout diagram, and FIG.
FIG. 4 is a cross-sectional structural view corresponding to an AA cross-section in the plan pattern layout diagram shown in FIG.

[0003] First, a cross-sectional configuration of the prior art will be described with reference to FIG. In FIG. 7, an N ⁺ -type buried layer 1002 is formed on one main surface of a P-type substrate 1001, and an N-type drain region 1003 is formed on one main surface of a P-type substrate 1001. A P-type base region 1004 and a high-concentration N ⁺ -type drain extraction region 1008 are formed in the N-type drain region 1003, and the high-concentration N ⁺ -type drain extraction region 1008 reaches the N ⁺ -type buried layer 1002. Is formed.

In the P-type base region 1004, a high concentration N ⁺
Mold source region 1005 is formed, and adjacent P
On the N-type drain region 1003 between the mold base regions 1004 and on a part of the P-type base region 1004, a U-type gate electrode 1007 is formed via a U-gate insulating film 1006. Note that the high concentration N ⁺ type source region 1005
Has a circular shape (a donut shape) with a hole in the center, for example. A P ⁺ high concentration base contact region 1020 is formed in the center of the donut.

A source electrode 1009 and a drain electrode 1010 are formed insulated from the U-shaped gate electrode 1007 by the first interlayer insulating film 1011. Further, a second drain electrode 1013 is formed insulated from the source electrode 1009 by the second interlayer insulating film 1012. As described above, the source electrode 1009 and the second layer drain electrode 101
3 has a so-called two-layer wiring structure having a vertically overlapping portion.

Next, the planar arrangement of the source and drain cell regions will be described with reference to FIG. Note that the cell region is a small region (source cell) and a large region (drain cell) among the region surrounded by the U-shaped gate 1014 formed in a lattice shape on the entire surface.

In the 2 × 2 array at the center of the source cell regions S arranged at a predetermined pitch in a four-row square mesh, one source cell region is replaced with four source cell regions and one space therebetween. A drain cell region D is provided. Therefore, one column of source cell region S surrounds one drain cell region D, and two columns of source cell regions exist between the drain cell regions D. On the basis of this pattern arrangement, a source cell region S and a drain cell region D are repeatedly arranged.

Next, the operation of the prior art will be described. When a voltage equal to or higher than the threshold is applied to the U-type gate electrode 1007 while a positive voltage is applied between the second-layer drain electrode 1013 and the source electrode 1009, the U-type gate electrode 100
The interface of the P-type base region 1004 in contact with 7 is inverted to N-type, and a channel is formed in the vertical direction. On the side of the source cell region S facing the drain cell region D, a current spreads from the high-concentration N ⁺ -type drain lead-out region 1008 into the N-type drain region 1003, and the high-concentration N ⁺ -type source region 1005 Current flows through On the other hand, the side not facing the drain cell region D of the source cell area S, the current high concentration N ⁺ -type drain extraction region 10
08 flows in the vertical direction, subsequently flows in the N ⁺ -type buried layer 1002 in the horizontal direction, further flows in the N-type drain region 1003 in the vertical direction, and the current flows to the high-concentration N ⁺ -type source region 1005 via the channel. Flows.

As described above, in this prior art,
The number of columns of the source cell region S provided between the drain cell regions D is two or more. Via the N-type drain region 1003 or via the N ⁺ -type buried layer 1002 depending on the position of the source cell region S from the drain cell region D. , The number of parallel connections of the resistance path between the drain and the source is increased, so that the on-resistance can be reduced.

[0010]

However, in such a conventional grooved semiconductor device, a high-concentration N ⁺ -type drain lead-out region 1008 is formed by the U gate insulating film 1006.
, The U-gate insulating film 1006 is in direct contact with the N-type drain region 1003. Therefore, when a high surge voltage is applied to the drain, the surge voltage is directly applied to the U-gate insulating film 1006. In this portion, the U gate insulating film may be broken. To protect this portion, the P-type base region 1004 is
^It can be easily extended to the outside of the U gate insulating film 1006 facing the ⁺ drain drain region 1008 to form a P ⁺ high-concentration base contact region 1020 in the same manner as in the source cell region S, and to make it equal to the source potential. Come up with. In this case, the P ⁺ high concentration base contact region 1
Since the lateral distance (distance a in FIG. 7) needs to be sufficiently large so that the device withstand voltage does not decrease between the gate insulating film 1 and the high-concentration N ⁺ -type drain extraction region 1008, the U gate insulating film 1
To protect 006, the element area must be increased.

The present invention has been made in view of such a conventional problem, and it is possible to protect an insulating film and reduce an element area when a high voltage surge is applied to a drain electrode. It is an object of the present invention to provide a grooved semiconductor device that can be used.

[0012]

According to a first aspect of the present invention, a first conductive type drain region is formed on a surface of the drain region. A base region of the second conductivity type, a plurality of grooves formed so as to reach the drain region from the surface of the base region, and a gate electrode formed on the surface of the plurality of grooves via an insulating film; A first conductivity type source region formed at a position in contact with the insulating film on the surface of the base region and surrounded by the gate electrode, and a surface of the drain region different from the base region; A drain-type semiconductor device having a first-conduction-type drain extraction region formed at a position, wherein the drain electrode is connected to the drain extraction region and applies a power supply voltage to the drain extraction region. And a source electrode connected to the source region and applying a ground voltage to the source region. The base region at a position not surrounded by the plurality of gate electrodes is not directly connected to any of the electrodes. Configuration.

According to a second aspect of the present invention, in the trench type semiconductor device according to the first aspect, the drain region is a base region at a position not surrounded by the plurality of gate electrodes. The part opposite to is not directly connected to any of the electrodes.

[0014] Further, a third invention according to a third aspect is characterized in that:
A drain region of the first conductivity type, a substantially linear base region of the second conductivity type formed on the surface of the drain region, and a groove formed from the surface of the base region to reach the drain region; A gate electrode formed on the surface of the trench via an insulating film; a first conductivity type drain lead-out region formed at a position different from the base region on the surface of the drain region; and a surface of the base region. And a first conductive type source region formed at a position in contact with the insulating film and at a position facing the drain lead region with the gate electrode interposed therebetween. A drain electrode connected to the region and applying a power supply voltage to the drain extraction region;
A source electrode that is connected to the source region and applies a ground voltage to the source region, and is formed at a position that is a part of the base region and that faces the drain extraction region without sandwiching the gate electrode. The other portion is not directly connected to any of the electrodes.

[0015]

As described above, according to the present invention, the following effects can be obtained. According to the first aspect of the present invention, in the trench type semiconductor device, since the base region at a position not surrounded by the plurality of gate electrodes is not directly connected to any of the electrodes,
When a voltage equal to or higher than the threshold is not applied to the gate electrode, an inversion layer is formed in a portion near the bottom of the insulating film and in contact with the drain region. As a result, the potential of the base region where the source region is formed on the surface is transmitted through the inversion layer,
The potential of the base region at a position not surrounded by the plurality of gate electrodes is also equal to the potential of the base region where the source region is formed on the surface. Therefore, the voltage applied to the drain electrode is not directly applied to the insulating film, and the insulating film can be protected even when, for example, a high-voltage surge is applied to the drain electrode.

Accordingly, the insulating film can be protected from a high-voltage surge by the above configuration, so that the distance between the base region and the drain extraction region not surrounded by the plurality of gate electrodes can be reduced. As a result, the element area can be reduced.

In a second aspect of the present invention, a portion of the base region which is not surrounded by the plurality of gate electrodes and faces the drain extraction region is directly connected to any of the electrodes. Since it is not connected, the insulating film can be protected even when a high-voltage surge is applied to the drain electrode, and the portion between the base region and the drain extraction region not surrounded by the plurality of gate electrodes can be protected. The distance can be reduced, and the element area can be reduced.

Further, in the third aspect of the present invention, a part of the base, which is formed at a position opposed to the drain extraction region without the gate electrode interposed therebetween, is connected to any of the electrodes. Since it is not directly connected, the insulating film can be protected even when a high-voltage surge is applied to the drain electrode, and the base region and the drain extraction region at positions not surrounded by a plurality of gate electrodes can be protected. Can be reduced, and the element area can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 and 2 are views showing a first embodiment of a groove type semiconductor device according to the present invention, and have a structure corresponding to claims 1 and 2. FIG. FIG.
FIG. 2 is a cross-sectional structure diagram corresponding to the AA cross section of the plan pattern layout diagram shown in FIG. 1. Note that, in the embodiments described below, parts and parts that are the same as or equivalent to those in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description is omitted.

First, the cross-sectional structure of the first embodiment will be described with reference to FIG. In FIG. 2, a P-type substrate 101
N ⁺ type buried layer 102 is formed on one main surface of
N-type drain region 103 is formed on one main surface of mold substrate 101. In the N-type drain region 103, a P-type base region 104 and a high-concentration N ⁺ -type drain lead region 1
08 is formed, and the high-concentration N ⁺ -type drain lead region 108 is formed to reach the N ⁺ -type buried layer 102.

A high-concentration N ⁺ -type source region 105 is formed in the P-type base region 104. The N-type drain region 103 between the adjacent P-type base regions 104 and the P-type
On a part of the mold base region 104, the U gate insulating film 1 is formed.
The U gate electrode 107 is formed with the intermediary of the reference numeral 06. The planar shape of the high-concentration N ⁺ type source region 105 is, for example, a circular shape (a donut shape) having a hole at the center. A P ⁺ high concentration base contact region 120 is formed in the center of the donut.

A source electrode 109 and a drain electrode 110 are formed insulated from the U-shaped gate electrode 107 by the first interlayer insulating film 111. In addition, the source electrode 109
And a second drain electrode 113 is formed insulated by the second interlayer insulating film 112. As described above, the source electrode 109 and the second-layer drain electrode 113 have a so-called two-layer wiring structure having a vertically overlapping portion.

Up to this point, there is no difference from the configuration of the prior art. Characteristically in the embodiment, the closest point to the high-concentration N ⁺ -type drain lead-out region 108 in the U gate insulating film 106, U gate facing the P-type base region 104 at a high concentration N ⁺ -type drain extraction region 108 The point is that a floating P-type base region 130 is formed extending to the outside of the insulating film 106.

Next, the planar arrangement of the source and drain cell regions will be described with reference to FIG. Although it is almost the same as FIG. 7 used in the description of the prior art, the characteristic point is that
U-shaped gate 11 on the outer periphery of drain cell region D (= portion of outer periphery of source cell region S and in contact with drain cell region D)
4 is that a floating P-type base region 130 is formed in a circular shape (a donut shape) having a hole at the center (in this figure, a rectangular hole is formed at the center). Actually, the corners are rounded and almost donut-shaped due to the influence of the resolution of the pattern in the manufacturing process.)

Next, the operation of the first embodiment will be described. The basic operation is the same as the prior art. When a voltage equal to or higher than a threshold is applied to the U-type gate electrode 107 in a state where a positive voltage is applied between the second-layer drain electrode 113 and the source electrode 109, the P-type base region in contact with the U-type gate electrode 107 The interface at 104 is inverted to N-type, and a channel is formed in the vertical direction. On the side of the source cell region S that faces the drain cell region D, a current spreads from the high-concentration N ⁺ -type drain lead-out region 108 into the N-type drain region 103, and passes through the channel to the high-concentration N ⁺ -type source region 105. Current flows through On the other hand, on the side of the source cell region S that does not face the drain cell region D, current flows vertically through the high-concentration N ⁺ -type drain extraction region 108,
Subsequently, it flows laterally through the N ⁺ type buried layer 102,
A current flows vertically through the drain region 103 and flows through the channel to the high-concentration N ⁺ -type source region 105.

As described above, in the first embodiment, the number of columns of the source cell region S provided between the drain cell regions D is two or more, and the number of columns of the source cell region S from the drain cell region D is Accordingly, since the current flows through the current path via the N-type drain region 103 or the N ⁺ -type buried layer 102, the number of parallel connection of the resistance path between the drain and the source increases. The resistance can be reduced.

The operation characteristic of the first embodiment is shown in FIG.
This will be described with reference to FIG. When the gate voltage of the device is equal to or lower than the threshold value, the depletion layer expands between the PN junction formed by the N-type drain region 103 and the P-type base region 104. In the P-type base region 104 between the adjacent U-type gates 114, a PN junction is formed in the vertical direction, so that the depletion layer extends in the horizontal direction. High concentration N ^{+ on the} side of the U gate insulating film 106
The P-type base region 104 extends to the outside of the U gate insulating film 106 in a region facing the drain drain region 108 (here, denoted by 130). The potential of the extended P-type base region 130 is floating.

Since the N-type drain region 103 is at a high voltage and the U-type gate electrode 107 is at 0 V when turned off,
Near the bottom of the gate insulating film 106, the N-type drain region 10
Holes, which are minority carriers for the N-type drain region 103, accumulate on the side in contact with 3 and an inversion layer 140 is formed (in FIG. 3, the inversion layer 140 is drawn thick to be conspicuous, but actually Formed in a very small area of the interface).

As a result, in FIG. 3, the potential of the region indicated by the reference numeral 142 is transmitted through the inversion layer 140 to the P-type base region 13.
P-type base region 1 which propagated to 0 and was floating
30 is fixed to the potential of the region indicated by 142. For example, if the source potential is 0 V and about 50 V can be applied to the drain (applied voltage is equal to or lower than the element withstand voltage), the depletion layer extends between the P-type base region 104 and the N-type drain region 103. The potential of the area indicated by reference numeral 142 is, for example, about 10 to 15 V. Then, the vicinity of the interface of the U gate insulating film 106 in the P-type base region 130 is 10 to 15
V fixed. Therefore, the drain voltage is not directly applied to the U gate insulating film 106.

The depletion layer extending parallel to the horizontal direction maintains continuity in this portion as well, and extends along the floating P-type base region 130 as shown by a broken line 132 in FIG. . Even when a high surge voltage is applied to the drain, the U gate insulating film 106 is protected.

The P-type base region 104 faces the high-concentration N ⁺ -type drain lead-out region 108 and the U gate insulating film 10
6 and extend to P ⁺ as in the source cell region S.
In the case of forming the high-concentration base contact region 120 and keeping it equal to the source potential, the device withstand voltage is not reduced between the P ⁺ high-concentration base contact region 120 and the high-concentration N ⁺ -type drain extraction region 108. Since it is necessary to secure a sufficient lateral distance, the element area has to be increased. In order to realize these operations including the operation at the time of device ON, in the first embodiment,
The element area does not increase. Also, the manufacturing method of the first embodiment is characterized in that there is no additional step from the conventional manufacturing method.

(Second Embodiment) FIGS. 4 and 5 are views showing a second embodiment of a groove type semiconductor device according to the present invention, and have a structure corresponding to claim 3. FIG. FIG. 4 is a plan pattern layout diagram, and FIG. 5 is a cross-sectional structure diagram corresponding to a BB cross section of the plane pattern layout diagram shown in FIG.

First, a plane pattern arrangement according to the second embodiment will be described with reference to FIG. In FIG. 4, an N ⁺ -type drain diffusion layer 301 is formed in a stripe shape at the center. A U-shaped gate electrode 305 is formed in a stripe shape inside the groove via a U-gate insulating film 304 so as to be symmetrical in parallel with the N ⁺ -type drain diffusion layer 301. N ⁺ type drain diffusion layer 301 and U gate insulating film 30
4, an N ⁻ type drain region 302 exists, but a P type floating region 303 is similarly formed in a stripe shape at a portion in contact with the U gate insulating film 304 and the N ⁻ type drain region 302. Left and right U-shaped gate electrodes 305,
Outside the 305, via the U gate insulating film 304, N
⁺ Type source region 306, P ⁺ base contact region 30
7 are each formed in a stripe shape.

Next, a sectional structure of the second embodiment will be described with reference to FIG. An N ⁻ type drain region 302 is formed on P substrate 308. Further, a P-type base region 309 is formed on N ⁻ -type drain region 302.
A P-type floating region 303 is formed opposite to the N ⁺ -type drain diffusion layer 301 and separated from the P-type base region 309 by a U groove. Also, the drain electrode 3
10, a source electrode 311 is formed at the illustrated position.

The operation of the second embodiment will be described. When a voltage equal to or higher than the threshold is applied to the U-shaped gate electrode 305 in a state where a positive voltage is applied between the drain electrode 310 and the source electrode 311, the P
The interface of the mold base region 309 is inverted to N-type, and a channel is formed in the vertical direction. A current spreads from the N ⁺ -type drain diffusion region 301 into the N ⁻ -type drain region 302, and a current flows to the high-concentration N ⁺ -type source region 306 via the channel.

When the device has a gate voltage equal to or lower than the threshold value, the N ⁻ type drain region 302 and the P type base region 3
The depletion layer expands between the PN junctions formed at step 09. In the P-type base region 309, a PN junction is formed in the vertical direction, so that the depletion layer extends in the horizontal direction. U gate insulating film 30
A P-type base region 309 is formed in a region facing the high-concentration N ⁺ -type drain diffusion region 301 on the four side surfaces.
4 (indicated by 303 here).
The potential of the extended P-type base region 303 is floating.

When the N ^- type drain region 302 is
Since the mold gate electrode 305 is at 0 V when turned off,
Holes, which are minority carriers for the N ⁻ -type drain region 302, accumulate near the bottom of the U-gate insulating film 304 in contact with the N ⁻ -type drain region 302, thereby forming an inversion layer.

As a result, as in the first embodiment, P
The potential of the mold base region 309 propagates through the inversion layer to the P-type base region 303, and the floating P-type base region 303 is fixed at the potential. Therefore, the drain voltage is not directly applied to the U gate insulating film 304.

The depletion layer extending parallel to the lateral direction maintains continuity even in this portion, and extends along the floating P-type base region 303. Even when a high surge voltage is applied to the drain, the U gate insulating film 304
Is protected.

The P-type base region 309 is extended to the outside of the U-gate insulating film 304 facing the high-concentration N ⁺ -type drain diffusion region 301 to form a P ⁺ base contact region 307 and keep it equal to the source potential. , This P
^Since it is necessary to secure a sufficient lateral distance between the ⁺ base contact region 307 and the high-concentration N ⁺ -type drain diffusion region 301 so that the breakdown voltage of the device does not decrease, the device area must be increased. In order to realize these operations including the operation when the device is ON, the element area does not increase in the second embodiment. Also, the manufacturing method of the second embodiment is characterized in that there is no additional step from the conventional manufacturing method.

[Brief description of the drawings]

FIG. 1 is a plan pattern layout diagram of a first embodiment of a groove type semiconductor device according to the present invention.

FIG. 2 is a cross-sectional structure diagram showing a cross section of a portion marked by AA in the plane pattern layout diagram (FIG. 1) of the first embodiment.

FIG. 3 is a cross-sectional structural diagram illustrating an operation of the first embodiment.

FIG. 4 is a plan pattern layout diagram of a second embodiment.

FIG. 5 is a cross-sectional structure diagram illustrating a cross-section of a portion marked by BB in the planar pattern layout diagram (FIG. 4) of the second embodiment.

FIG. 6 is a plan pattern layout diagram of a conventional groove type semiconductor device.

FIG. 7 is a plane pattern layout diagram of the prior art (FIG. 6).
FIG. 3 is a cross-sectional structure diagram illustrating a cross section of a portion marked by AA in FIG.

[Explanation of symbols]

Reference Signs List 101 P-type substrate 102 N ⁺ -type buried layer 103 N-type drain region 104 P-type base region 105 High-concentration N ⁺ -type source region 106 U gate insulating film 107 U-type gate electrode 108 High-concentration N ⁺ -type drain lead-out region 109 Source Electrode 110 Drain electrode 111 First interlayer insulating film 112 Second interlayer insulating film 113 Second layer drain electrode 114 U-shaped gate 120 P ⁺ high concentration base contact region 130 Floating P-type base region 132 Depletion layer end 140 Inversion layer 301 High Concentration N ⁺ type drain diffusion region 302 N ⁻ type drain region 303 Floating P type base region 304 U gate insulating film 305 U type gate electrode 306 High concentration N ⁺ type source region 307 P ⁺ base contact region 308 P substrate 309 P type Base region 310 Drain electrode 11 source electrode S source cell region D drain cell area

Claims (3)

[Claims] A drain region of a first conductivity type; a base region of a second conductivity type formed on a surface of the drain region; and a plurality of drain regions formed to reach the drain region from a surface of the base region. A groove, a gate electrode formed on a surface of the plurality of grooves via an insulating film, and a surface of the base region, the position being in contact with the insulating film and formed at a position surrounded by the gate electrode. A drain region of the first conductivity type formed at a position different from the base region on the surface of the drain region, and a drain region of the first conductivity type formed on the surface of the drain region. A drain electrode connected to apply a power supply voltage to the drain extraction region; and a source connected to the source region and applying a ground voltage to the source region. And an electrode, the base region of the position that is not surrounded by said plurality of gate electrodes, a groove-type semiconductor device, characterized in that both said one of the electrodes are not directly connected. 2. The trench-type semiconductor device according to claim 1, wherein a portion of the base region which is not surrounded by the plurality of gate electrodes and faces the drain extraction region is connected to any of the electrodes. A groove type semiconductor device characterized by not being directly connected. 3. A drain region of a first conductivity type, a substantially linear base region of a second conductivity type formed on a surface of the drain region, and a drain region formed from the surface of the base region to reach the drain region. A gate electrode formed on a surface of the groove via an insulating film; a first conductivity type drain extraction region formed at a position different from the base region on the surface of the drain region; A trench-type semiconductor device comprising: a first conductive type source region formed on a surface of a region, at a position in contact with the insulating film, and at a position facing the drain extraction region with the gate electrode interposed therebetween. A drain electrode connected to the drain extraction region and applying a power supply voltage to the drain extraction region; and a drain electrode connected to the source region, A source electrode for applying a ground voltage, and a part of the base region, which is formed at a position facing the drain extraction region without sandwiching the gate electrode, is directly connected to any of the electrodes. A groove type semiconductor device characterized by not being performed.