JP2004247709A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage current flowing through a Schottky junction to a low level and to increase adhesion of a gate electrode to a nitride semiconductor layer. <P>SOLUTION: This semiconductor device has a GaN layer 13 and a gate electrode 16 formed on the GaN layer 13. The gate electrode 16 includes silicon. An Al<SB>2</SB>O<SB>3</SB>film is provided between the GaN layer and the gate electrode 16. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

The present invention relates to a group III nitride semiconductor layer generally represented by (In _x Al _{1 -x} ) _y Ga _{1 -y} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), that is, a so-called gallium nitride-based layer. The present invention relates to a semiconductor device including a compound semiconductor layer and a method for manufacturing the same.

A group III nitride semiconductor, that is, a semiconductor made of GaN, AlN, InN or a mixed crystal thereof is being studied for application to not only short-wavelength light emitting devices but also electronic devices. In particular, Al _x Ga _1-x N (0 ≦ x ≦ 1) In a heterojunction field effect transistor (hereinafter abbreviated as HFET) using a high-concentration two-dimensional electron gas formed at the hetero interface between GaN and GaN, the intrinsic properties of nitride semiconductors Therefore, there is a high possibility that the high withstand voltage and high saturation speed can be sufficiently utilized, and therefore, a heterojunction field effect device is being developed as a high-output high-frequency device.

  Hereinafter, a conventional semiconductor device having a group III nitride semiconductor layer will be described with reference to FIG.

As shown in FIG. 13, a buffer layer 102 is formed on a substrate 101, and a GaN layer 103 is formed on the buffer layer 102. An Al _x Ga ₁ -xN layer 104 is formed on the GaN layer 103, and an ohmic contact 105 is formed on the Al _x Ga ₁ -xN layer 104. A gate electrode 106 is formed on the Al _x Ga ₁ -xN layer 104.

Incidentally, in the HFET, the flow rate of the two-dimensional electron gas flowing through the channel region is generally controlled by the voltage applied to the gate electrode 106 forming a Schottky junction with the surface barrier layer of the Al _x Ga ₁ -xN layer 104. As described above, the gate electrode having a Schottky junction formed on the surface of the nitride semiconductor layer is generally formed by directly depositing a metallic gate electrode material on the surface of the nitride semiconductor layer. In this case, it is necessary to increase the reactivity between the gate electrode material and the nitride semiconductor layer in order to increase the adhesion between the gate electrode material and the nitride semiconductor layer.

  However, increasing the reactivity between the gate electrode material and the nitride semiconductor layer poses a major problem in minimizing the leakage characteristics of the finally formed Schottky junction. That is, in order to suppress the leakage current to a smaller value, generally, a material having low reactivity to the nitride semiconductor layer (for example, Au, Pt, or Pd) may be used for the gate electrode. Since the adhesiveness to the surface of the nitride semiconductor layer is low due to low reactivity to the nitride semiconductor layer, the gate electrode using these materials is easily peeled off from the surface of the nitride semiconductor layer.

  For the problem that a gate electrode using a material such as Au, Pt, or Pd having low reactivity to the nitride semiconductor layer is easily peeled off from the surface of the nitride semiconductor layer, usually, Ti, Ni, or A method of increasing the adhesion of the gate electrode to the nitride semiconductor layer by depositing Si or the like together with Au, Pt, Pd, or the like has been adopted.

However, since Ti, Ni, or Si is a metal having high reactivity to the nitride semiconductor layer, it causes a chemical reaction with the nitride semiconductor layer to induce defects such as nitrogen vacancies in the nitride semiconductor layer. For this reason, the leak current flowing through the formed Schottky junction becomes extremely high.
JP-A-10-223901 JP 2000-150792 A EHRHODERICK and RHWILLIAM., "Metal-Semiconductor Contacts", 2nd Ed.Claredon Press.Oxford 1988 Chap 1-3 Tamotsu Hashizume, Shinya Otomo "Surface Evaluation of GaN and AlGaN and Insulated Gate Structure" TECHNICAL REPORT OF IEICE.ED2002-87, LQ2002-62 (2002-06) Hori, Iwasaki, "Ultra-thin Re-oxidized Nitride-oxides Prepared by Thermal Processing", Technical Digest, 1987, IEDM, pp. 570-573, (1987). Kusunoki, Inuishi, Yamaguchi, Tsukamoto, Akasaka, "Hot-career-resistivity Structure by Re-oxydized Nitrided Oxide Sidewall for Highly Rliable and High Performance LDD MOSFET", Tecnical Digest, 1991, IEDM, pp649-652, (1991).

  By the way, in order to form a Schottky junction capable of reducing the occurrence of a leak current, a gate electrode made of Pd containing a small amount of Si as a material of the gate electrode is formed on the surface of the nitride semiconductor layer to form a nitride. It was confirmed that the adhesion of the gate electrode to the semiconductor layer was improved. However, when the addition amount of Si added as a material of the gate electrode is reduced to the minimum, there is a demand for suppressing mechanical disturbance in a process of manufacturing a semiconductor device after forming the gate electrode (for example, excessive ultrasonic cleaning). Is extremely high. Furthermore, when the addition amount of Si added as a material for the gate electrode is reduced to the minimum, the case where the gate electrode is formed on an incomplete crystalline epitaxial layer having large irregularities on the surface or a high-temperature heat treatment step is performed. In such a case, a new problem that the gate electrode once adhered to the surface of the nitride semiconductor layer is usually peeled off occurs.

  In view of the above, it is an object of the present invention to reduce the leakage current flowing through a Schottky junction and to improve the adhesion of a gate electrode to a nitride semiconductor layer.

  In order to achieve the above object, a semiconductor device according to the present invention includes a group III nitride semiconductor layer and a gate electrode formed on the group III nitride semiconductor layer, wherein the gate electrode is an adhesion promoting element. And a thermal oxide insulating film is interposed between the group III nitride semiconductor layer and the gate electrode.

  According to the semiconductor device of the present invention, the thermal oxidation insulating film is interposed between the gate electrode and the group III nitride semiconductor layer. Since a chemical reaction does not occur directly with the semiconductor layer, generation of a leak current can be suppressed. Further, since the gate electrode causes a chemical reaction with the thermal oxide insulating film but does not directly cause a chemical reaction with the group III nitride semiconductor layer, the content of the adhesion promoting element in the gate electrode is increased to a necessary amount. be able to. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors.

  Note that the adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, and is particularly preferably an element that is easily oxidized, for example, Ti, Si, Ni, Cr, Elements such as Cu, Al, Hf, Zr, Nb, Ta, Nd, Ga, and In. The thermal oxide insulating film is a concept including a pure thermal oxide film and a thermal oxide film containing nitrogen, that is, a thermal oxynitride film.

  In the semiconductor device according to the present invention, when the thermally oxidized insulating film is made of aluminum oxide or silicon oxide, the gate electrode causes a chemical reaction with the thermally oxidized insulating film, and directly between the gate electrode and the group III nitride semiconductor layer. Since no chemical reaction occurs, generation of a leak current can be reliably suppressed. Furthermore, by improving the adhesion of the gate electrode to the nitride semiconductor layer, it is possible to more reliably prevent the gate electrode from peeling off from the nitride semiconductor layer due to external factors.

  In the semiconductor device according to the present invention, the thickness of the thermal oxide insulating film is preferably 0.5 nm or more and 3 nm or less.

  With this configuration, when the thickness of the thermally oxidized insulating film is less than 0.5 nm, the generation of a leakage current is suppressed as in the case where the gate electrode is directly joined to the group III nitride semiconductor layer. Can not. When the thickness of the thermally oxidized insulating film is greater than 3 nm, a function as an insulating film is exhibited and Schottky junction cannot be realized. Therefore, by setting the thickness of the thermally oxidized insulating film in the range of 0.5 nm or more and 3 nm or less, Schottky junction can be realized and the leak current can be suppressed, and further, the gate to the nitride semiconductor layer can be formed. The adhesion of the electrodes can be improved.

  In the semiconductor device according to the present invention, the gate electrode preferably contains Pd.

  By doing so, it is possible to effectively suppress the occurrence of a leak current and to improve the adhesion to the thermal oxide insulating film. Further, the gate electrode containing Pd has excellent heat resistance.

  In the semiconductor device according to the present invention, when the adhesion promoting element is Ti, Ni or Si, the adhesion of the gate electrode to the nitride semiconductor layer is improved.

  In the semiconductor device according to the present invention, when the adhesion promoting element is an element having a property of being easily oxidized, the adhesion of the gate electrode to the nitride semiconductor layer is improved.

  In the semiconductor device according to the present invention, the thermal oxide insulating film is preferably an insulating film formed by thermally oxidizing a group III nitride semiconductor layer.

  In the semiconductor device according to the present invention, the adhesion promoting element is Si, and the weight ratio of Si in the metal constituting the gate electrode is preferably 3% or more and 10% or less.

  In this case, the gate electrode has no or almost no peeling over the entire surface of the wafer, so that the gate electrode has excellent adhesion to the nitride semiconductor layer. In this case, the leakage current can be extremely small or can be suppressed to a small value, so that the gate electrode has excellent electric characteristics.

  In the semiconductor device according to the present invention, the adhesion promoting element is Si, and the weight ratio of Si in the metal constituting the gate electrode is more preferably 4% or more and 7% or less.

  In this case, the gate electrode does not peel off at all over the wafer, so that the gate electrode has extremely excellent adhesion to the nitride semiconductor layer. In this case, the leakage current can be suppressed to a very small value, so that the gate electrode has very excellent electric characteristics.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes the steps of thermally oxidizing a group III nitride semiconductor layer and forming a thermally oxidized insulating film on the surface of the group III nitride semiconductor layer. Forming a gate electrode containing an adhesion promoting element on the thermally oxidized insulating film.

  According to the method for manufacturing a semiconductor device according to the present invention, since the thermal oxide insulating film is interposed between the gate electrode and the group III nitride semiconductor layer, the gate electrode causes a chemical reaction with the thermal oxide insulating film, Since a chemical reaction does not occur directly with the group III nitride semiconductor layer, generation of a leak current can be suppressed. Further, since the gate electrode causes a chemical reaction with the thermal oxide insulating film but does not directly cause a chemical reaction with the group III nitride semiconductor layer, the content of the adhesion promoting element in the gate electrode is increased to a necessary amount. be able to. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors.

  Note that the adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, and is particularly preferably an element that is easily oxidized, for example, Ti, Si, Ni, Cr, Elements such as Cu, Al, Hf, Zr, Nb, Ta, Nd, Ga, and In. The thermal oxide insulating film is a concept including a pure thermal oxide film and a thermal oxide film containing nitrogen, that is, a thermal oxynitride film.

  In the method for manufacturing a semiconductor device according to the present invention, the step of forming a thermal oxide insulating film includes forming an aluminum nitride layer on the group III nitride semiconductor layer, and then thermally oxidizing the aluminum nitride layer to form an aluminum oxide layer. It is preferable to include a step of forming a thermally oxidized insulating film made of the aluminum oxide layer by changing to

  In this case, since the aluminum oxide layer is interposed between the gate electrode and the aluminum nitride layer, the gate electrode causes a chemical reaction with the aluminum oxide layer, while a chemical reaction directly occurs between the gate electrode and the group III nitride semiconductor layer. Since no reaction occurs, generation of a leak current can be suppressed. Furthermore, since the gate electrode chemically reacts with the aluminum oxide layer but does not directly react with the group III nitride semiconductor layer, it is necessary to increase the content of the adhesion promoting element in the gate electrode to a necessary amount. Can be. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors.

  In the method for manufacturing a semiconductor device according to the present invention, the thickness of the aluminum oxide layer is preferably 0.5 nm or more and 3 nm or less.

  In this manner, when the thickness of the aluminum oxide layer is less than 0.5 nm, it is possible to suppress the occurrence of leakage current as in the case where the gate electrode is directly joined to the group III nitride semiconductor layer. Can not. If the thickness of the aluminum oxide layer is greater than 3 nm, a function as an insulating film is exhibited and Schottky junction cannot be performed. Therefore, by setting the thickness of the aluminum oxide layer to a range of 0.5 nm or more and 3 nm or less, Schottky junction can be realized, and generation of a leak current can be suppressed. Of the gate electrode can be improved.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming a thermal oxide insulating film includes, after forming a silicon layer on the surface of a group III nitride semiconductor layer, thermally oxidizing the silicon layer to change it to a silicon oxide layer. Accordingly, the method preferably includes a step of forming a thermal oxide insulating film made of the silicon oxide layer.

  In this case, since the silicon oxide layer is interposed between the gate electrode and the nitride semiconductor layer, the gate electrode causes a chemical reaction with the silicon oxide layer, while the gate electrode directly reacts with the group III nitride semiconductor layer. Since no chemical reaction occurs, generation of a leak current can be suppressed. Furthermore, since the gate electrode causes a chemical reaction with the silicon oxide layer but does not directly cause a chemical reaction with the group III nitride semiconductor layer, the content of the adhesion promoting element in the gate electrode must be increased to a necessary amount. Can be. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors.

  In the method for manufacturing a semiconductor device according to the present invention, the thickness of the silicon oxide layer is preferably 0.5 nm or more and 3 nm or less.

  In this manner, when the thickness of the silicon oxide layer is less than 0.5 nm, it is possible to suppress the generation of the leak current as in the case where the gate electrode is directly joined to the group III nitride semiconductor layer. Can not. Further, when the thickness of the silicon oxide layer is larger than 3 nm, a function as an insulating film is exhibited and Schottky junction cannot be realized. Therefore, by setting the thickness of the silicon oxide layer in the range of 0.5 nm or more and 3 nm or less, Schottky junction can be realized and the occurrence of leak current can be suppressed low. Of the gate electrode can be improved.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, since the thermal oxide insulating film is interposed between the gate electrode and the group III nitride semiconductor layer, the gate electrode reacts chemically with the thermal oxide insulating film. No chemical reaction occurs directly with the group III nitride semiconductor layer, so that the occurrence of leakage current can be suppressed. Further, since the gate electrode causes a chemical reaction with the thermal oxide insulating film but does not directly cause a chemical reaction with the group III nitride semiconductor layer, the content of the adhesion promoting element in the gate electrode is increased to a necessary amount. be able to. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors.

(1st Embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c) and FIG.

  1A to 1C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, after a buffer layer 12 is deposited on a SiC substrate 11, an organic chemical vapor deposition (hereinafter referred to as MOCVD) or a molecular beam epitaxy (hereinafter referred to as MOCVD). An n ⁻ -type GaN layer 13 is formed on the buffer layer 12 by molecular beam epitaxy (hereinafter referred to as MBE method). Next, similarly, an AlN layer 14 having an extremely small thickness of 1.5 nm is formed on the GaN layer 13 by MOCVD or MBE.

Next, as shown in FIG. 1B, the surface of the sample shown in FIG. 1A was heated at 900 ° C. for 5 minutes in an oxygen atmosphere having an oxygen flow rate of 5 mL / min (standard state). Oxidation is performed to form a thermal oxidation insulating film. That is, the AlN layer 14 formed on the GaN layer 13 is thermally oxidized and changes to an extremely thin Al ₂ O ₃ film (thermally oxidized insulating film) 15.

Next, as shown in FIG. 1 (c), Pd in which Si is mixed at a weight ratio of 10% as an adhesion promoting element is vapor-deposited on the Al ₂ O ₃ film 15 and then lift-off is performed. Forms a gate electrode 16 made of Pd mixed at a weight ratio of 10%. Thus, the diode is completed.

Here, the adhesion promoting element will be described with reference to [Table 1]. The adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, and is described in [Table 1] below. As shown in (1), for example, an element having high adhesion, such as Ti, Si, Ni, Cr, or Cu, can be used as the adhesion element.

  Further, the adhesion promoting element is preferably an element having a property of being easily oxidized. This is because a gate electrode containing an element having a property of being easily oxidized has excellent adhesion to a nitride semiconductor layer.

  The following [Table 2] shows the oxides, oxidizability, and heat of oxidation formation for metal elements and Si.

As shown in [Table 2], Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In have high values of heat of oxidation generation, and it is clear that they have high oxidizability. . Thus, each of Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In is easily oxidized, and Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , Ta, respectively. ₂ O ₅ , Nd ₂ O ₃ , SiO ₂ , Ga ₂ O ₃ , and In ₂ O ₃ . On the other hand, it can be seen that Au, Pd and Pt have low oxidizing properties and are not suitable as adhesion promoting elements. Therefore, as shown in [Table 2], it is desirable to use Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In as the adhesion promoting element.

Further, the thickness of the Al ₂ O ₃ film 15 formed between the gate electrode 16 and the GaN layer 13 is preferably 0.5 nm or more and 3 nm or less.

The following Table 3], Al ₂ O ₃ and the thickness of the film 15, Al ₂ O ₃ shots of the gate electrode 16 formed on the film 15 key properties and Al ₂ O ₃ on the surface of the film 15 morphology and Al The relationship with the thickness of the ₂ O ₃ film 15 is shown.

As is evident from Table 3, when the thickness of the Al ₂ O ₃ film 15 is 0.5 nm or more and 3 nm or less, the Schottky characteristics are good. This is because when the film thickness is less than 0.5 nm, the leakage current cannot be suppressed as in the case where the gate electrode 16 is directly joined on the GaN layer 13, while the film thickness is less than 3 nm. If the thickness is too large, the function of the Al ₂ O ₃ film 15 as an insulating film is exhibited, and Schottky junction cannot be performed. That is, when the thickness of the Al ₂ O ₃ film 15 is 0.5 nm or more and 3 nm or less, good Schottky characteristics are realized and the function of the gate electrode is not impaired. Also, when the thickness of the Al ₂ O ₃ film 15 is 0.5 nm or more and 3 nm or less, it can be seen that the morphology of the surface of the Al ₂ O ₃ film 15 is also good. More preferably, when the thickness of the Al ₂ O ₃ film 15 is 0.8 n to ₃ nm, the Schottky characteristics are more excellent and the leak current can be more effectively suppressed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the first embodiment, since the Al ₂ O ₃ film 15 is interposed between the gate electrode 16 and the GaN layer 13, the gate electrode 16 While a chemical reaction occurs with the ₂ O ₃ film 15, a direct chemical reaction does not occur with the GaN layer 13, so that generation of a leak current can be suppressed. Further, while the gate electrode 16 causes a chemical reaction with the Al ₂ O ₃ film 15 but does not directly cause a chemical reaction with the GaN layer 13, the content of Si mixed in the gate electrode 16 is reduced to a necessary amount. Can be enhanced. Therefore, since the adhesion of the gate electrode to the nitride semiconductor layer can be improved, it is possible to prevent the gate electrode 16 from peeling off due to external factors. As a result, in the formation of the gate electrode 16, the gate electrode 16 did not come off at all even if excessive ultrasonic cleaning was performed at the time of lift-off. That is, according to the semiconductor device and the method of manufacturing the same according to the first embodiment, it is possible to realize a very low leak characteristic inherent to Pd constituting the gate electrode 16 and to prevent the gate electrode 16 from peeling off. .

Further, since the Al ₂ O ₃ film 15 interposed between the gate electrode 16 and the GaN layer 13 is a thermal oxide insulating film, the surface levels derived from dangling bonds and the like are small, so that the thermal oxide insulating film is formed. In doing so, electrical stability can be obtained. Therefore, by interposing a thermally oxidized insulating film between the gate electrode 16 and the GaN layer 13, if the insulating film is formed by deposition using a normal CVD method or the like, the surface level derived from dangling bonds or the like can be reduced. It is possible to prevent a leak current generated by electrically activating the electric field.

  FIG. 2 shows the IV characteristics of the gate electrode 16 according to the first embodiment of the present invention. As is apparent from FIG. 2, the semiconductor device according to the first embodiment has good Schottky characteristics. Is realized.

In the first embodiment, the thermal oxide insulating film is a concept including a pure thermal oxide insulating film and a thermal oxynitride insulating film. That is, the concept includes a pure thermal oxide insulating film made of an Al ₂ O ₃ film and a thermal oxynitride insulating film made of an AlON _x film containing nitrogen.

(Second embodiment)
Hereinafter, a semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention will be described with reference to FIGS.

  3A to 3D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

First, as shown in FIG. 3A, a buffer layer 22 made of AlN is deposited on a SiC substrate 21 by MOCVD, and then a GaN layer 23 having a thickness of 1 μm is deposited on the buffer layer 22. I do. Next, an Al _0.25 Ga _0.75 N layer 24 having a thickness of 25 nm is deposited as a surface barrier layer on the GaN layer 23, and a 1 nm extremely thick layer is formed on the Al _0.25 Ga _0.75 N layer 24 by MOCVD. An AlN layer 25 having a small thickness is deposited.

Next, as shown in FIG. 3 (b), the surface of the sample shown in FIG. 3 (a) was heated at 900 ° C. for 10 minutes in an oxygen atmosphere having an oxygen flow rate of 5 mL / min (standard state). Oxidation is performed to form a thermal oxidation insulating film. That is, the AlN layer 25 formed on the outermost surface is thermally oxidized and changes to an Al ₂ O ₃ film (thermally oxidized insulating film) 26 having a thickness of 1.3 nm.

Next, as shown in FIG. 3C, a desired region such as the Al ₂ O ₃ film 26 is removed by etching using the resist pattern as a mask to form a source / drain formation region. Next, after performing metal deposition, lift-off of the resist pattern is performed, and further, annealing is performed on the source / drain regions where the metal is deposited, thereby forming source / drain electrodes 27.

Next, as shown in FIG. 3D, Pd in which Si is mixed at a weight ratio of 5% as an adhesion promoting element is vapor-deposited on the Al ₂ O ₃ film 26, and then lift-off is performed. Forms a gate electrode 28 made of Pd mixed at a weight ratio of 5%. Thus, the transistor is completed.

  Here, the adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, as in the first embodiment. For example, as shown in [Table 1], for example, Elements having high adhesion, such as Ti, Si, Ni, Cr, and Cu, can be used as the adhesion element.

  Further, it is preferable that the adhesion promoting element is an element having a property of being easily oxidized, as in the first embodiment. This is because a gate electrode containing an element having a property of being easily oxidized has excellent adhesion to a nitride semiconductor layer. Specifically, as shown in Table 2 above, it is desirable to use Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In as the adhesion promoting element.

The thickness of the Al ₂ O ₃ film 26 formed between the gate electrode 28 and the Al _0.25 Ga _0.75 N layer 24 is 0.5 nm or more and 3 nm or less, as in the first embodiment. Is preferred.

This is because, as is clear from Table 3, when the thickness of the Al ₂ O ₃ film 26 is 0.5 nm or more and 3 nm or less, the Schottky characteristics are good. That is, when the film thickness is less than 0.5 nm, the leak current cannot be suppressed as in the case where the gate electrode 28 is directly joined on the GaN layer 23, while the film thickness is less than 3 nm. This is because when the thickness is large, the function of the Al ₂ O ₃ film 26 as an insulating film is developed, and Schottky junction cannot be performed. That is, if the thickness of the Al ₂ O ₃ film 26 is 0.5 nm or more and 3 nm or less, good Schottky characteristics are realized and the function of the gate electrode is not impaired. When the thickness of the Al ₂ O ₃ film 26 is 0.5 nm or more and 3 nm or less, the morphology of the surface of the Al ₂ O ₃ film 26 is also good. More preferably, when the thickness of the Al ₂ O ₃ film 26 is 0.8 nm to ₃ nm, the Schottky characteristics are more excellent, and the leak current can be more effectively suppressed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the second embodiment, since the Al ₂ O ₃ film 26 is interposed between the gate electrode 28 and the Al _0.25 Ga _0.75 N layer 24, The electrode 28 causes a chemical reaction with the Al ₂ O ₃ film 26, but does not directly cause a chemical reaction with the Al _0.25 Ga _0.75 N layer 24, so that generation of a leak current can be suppressed. Further, while the gate electrode 28 causes a chemical reaction with the Al ₂ O ₃ film 26 but does not directly cause a chemical reaction with the Al _0.25 Ga _0.75 N layer 24, the content of Si mixed in the gate electrode 28 is reduced. It can be increased to the required amount. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors. As a result, in forming the gate electrode 28, the gate electrode 28 did not come off at all even if excessive ultrasonic cleaning was performed at the time of lift-off. That is, according to the semiconductor device and the method of manufacturing the same according to the second embodiment, it is possible to realize a very low leak characteristic inherent to Pd constituting the gate electrode 28 and to prevent the gate electrode 28 from peeling off. .

Further, since the Al ₂ O ₃ film 26 interposed between the gate electrode 28 and the Al _0.25 Ga _0.75 N layer 24 is a thermal oxide insulating film, the surface level derived from dangling bonds and the like is small, so that the thermal oxidation Electrical stability can be obtained when the insulating film is formed. Therefore, by interposing a thermally oxidized insulating film between the gate electrode 28 and the Al _0.25 Ga _0.75 N layer 24, if the insulating film is formed by deposition using a normal CVD method or the like, it can be used as a dangling bond or the like. It is possible to prevent a leakage current generated by electrically activating a large number of derived surface states.

  FIG. 4 is a diagram showing the IV characteristics of the gate electrode 28 according to the second embodiment. As is apparent from FIG. 4, the characteristics show that the leak current is 3 nA or less up to a reverse bias of 50 V. It can be seen that the semiconductor device according to the second embodiment achieves good Schottky characteristics.

In the second embodiment, the thermal oxide insulating film is a concept including a pure thermal oxide insulating film and a thermal oxynitride insulating film. That is, the concept includes a pure thermal oxide insulating film made of an Al ₂ O ₃ film and a thermal oxynitride insulating film made of an AlON _x film containing nitrogen.

(Third embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS.

  5A to 5C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

First, as shown in FIG. 5A, after a buffer layer 32 having a thickness of 50 nm is deposited on a SiC substrate 31, an n ⁻ -type GaN having a thickness of 1 μm is formed on the buffer layer 32. A layer 33 is deposited.

Next, as shown in FIG. 5 (b), the surface of the sample shown in FIG. 5 (a) was heated at 900 ° C. for 3 minutes under an oxygen atmosphere having an oxygen flow rate of 5 mL / min (standard state). Oxidation is performed to form a thermal oxidation insulating film. That is, the outermost surface of the GaN layer 33 is oxidized and changes to a Ga ₂ O ₃ film (thermally oxidized insulating film) 34 having an extremely small thickness of 1.5 nm.

Next, as shown in FIG. 5 (c), Pd in which Si is mixed at a weight ratio of 5% as an adhesion promoting element is deposited on the Ga ₂ O ₃ film 34, and then lift-off is performed to lift off the Si. Forms a gate electrode 35 made of Pd mixed at a weight ratio of 5%. Thus, the diode is completed.

  Here, the adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, as in the first embodiment. For example, as shown in [Table 1], for example, Elements having high adhesion, such as Ti, Si, Ni, Cr, and Cu, can be used as the adhesion element.

  Further, it is preferable that the adhesion promoting element is an element having a property of being easily oxidized, as in the first embodiment. This is because a gate electrode containing an element having a property of being easily oxidized has excellent adhesion to a nitride semiconductor layer. Specifically, as shown in Table 2 above, it is desirable to use Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In as the adhesion promoting element.

Here, when Si is used as the adhesion promoting element, the concentration (% by weight) of Si in the metal constituting the gate electrode 35, the adhesion of the gate electrode 35 to the Ga ₂ O ₃ film, and the gate. The relationship with the electrical characteristics of the electrode 35 will be described with reference to the following [Table 4].

As shown in Table 4, first, regarding the adhesion of the gate electrode 35 to the Ga ₂ O ₃ film 34, the weight ratio of Si in the metal constituting the gate electrode 35 is 4% or more and less than 13%. In this range, the gate electrode does not peel off at all over the wafer. If the weight ratio of Si in the metal constituting the gate electrode 35 is in the range of 3% or more and less than 4%, the gate electrode hardly peels off over the entire surface of the wafer. If the weight ratio of Si in the metal constituting the gate electrode 35 is in the range of 2% or more and less than 3%, the gate electrode 35 is peeled off at some points on the entire surface of the wafer.

Regarding the electrical characteristics of the gate electrode 35 with respect to the Ga ₂ O ₃ film 34, if the weight ratio of Si in the metal constituting the gate electrode 35 is 4% or more and less than 8%, the leakage current Is very small. Further, when the weight ratio of Si in the metal constituting the gate electrode 35 is 3% or more and less than 4%, and 8% or more and less than 11%, the leak current is small. If the weight ratio of Si in the metal constituting the gate electrode 35 is 2% or more and less than 3% and 8% or more and less than 11%, the leakage current is slightly high, but depending on the application. Can be used.

Therefore, when Si is used as the adhesion promoting element, the weight ratio of Si in the metal constituting the gate electrode 35 is preferably 3% or more and 10% or less. In this manner, the gate electrode 35 has excellent or low adhesion to the Ga ₂ O ₃ film 34 because the gate electrode 35 is not or is hardly peeled over the entire surface of the wafer. In this case, the leakage current can be extremely small or can be suppressed to a small value, so that the gate electrode 35 has excellent electric characteristics.

More preferably, the weight ratio of Si in the metal constituting gate electrode 35 should be 4% or more and 7% or less. In this case, the gate electrode 35 does not peel off at all on the entire surface of the wafer, so that the gate electrode 35 has extremely excellent adhesion to the Ga ₂ O ₃ film 34. Further, in this case, since the leak current can be suppressed to a very small value, the gate electrode 35 has very excellent electric characteristics.

[Table 4] indicates that, when Si is used as the adhesion promoting element, the concentration (% by weight) of Si in the metal constituting the gate electrode 35 and the ratio of the gate electrode 35 to the Ga ₂ O ₃ film are different. The relationship between the adhesion and the electrical characteristics of the gate electrode 35 is shown. In addition to the Ga ₂ O ₃ film, heat represented by the oxides of the highly oxidizable elements in Table 2 above is also used. It is clear that a similar relationship can be obtained even in the case of an oxide insulating film.

As described above, according to the semiconductor device and the method of manufacturing the same according to the _third embodiment, since the Ga ₂ O ₃ film 34 is interposed between the gate electrode 35 and the GaN layer 33, the gate electrode 35 While a chemical reaction occurs with the ₂ O ₃ film 34, a chemical reaction does not occur directly with the GaN layer 33, so that generation of a leak current can be suppressed. Further, while the gate electrode 35 causes a chemical reaction with the Ga ₂ O ₃ film 34 but does not directly cause a chemical reaction with the GaN layer 33, the content of Si mixed in the gate electrode 35 is reduced to a necessary amount. Can be enhanced. Therefore, since the adhesion of the gate electrode to the nitride semiconductor layer can be improved, the gate electrode 35 can be prevented from peeling off due to external factors. As a result, in the formation of the gate electrode 35, the gate electrode 35 did not come off at all even if excessive ultrasonic cleaning was performed at the time of lift-off. That is, according to the semiconductor device and the method of manufacturing the same according to the third embodiment, it is possible to realize a very low leak characteristic inherent to Pd constituting the gate electrode 35 and to prevent the gate electrode 35 from peeling off. .

In the third embodiment, the thermal oxide insulating film is a concept including a pure thermal oxide insulating film and a thermal oxynitride insulating film. That is, the concept includes a pure thermal oxide insulating film made of a Ga ₂ O ₃ film and a thermal oxynitride insulating film made of a GaON _x film containing nitrogen.

(Fourth embodiment)
Hereinafter, a semiconductor device and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS. 6 (a) to 6 (d) and FIG.

  6A to 6D are process cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to a fourth embodiment of the present invention.

First, as shown in FIG. 6A, a buffer layer 42 having a thickness of 50 nm is formed on a SiC substrate 41 by MOCVD, and then a non-doped layer having a thickness of 2 μm is formed on the buffer layer 42. A GaN layer 43 of a mold type is stacked. On the GaN layer 43, an Al _0.25 Ga _0.75 N layer 44 having a thickness of 20 nm is deposited as a surface barrier layer. The Al _0.25 Ga _0.75 N layer 44 is doped with Si, similarly to the modulation doping structure of AlGaAs / GaAs usually used for the HFET.

Next, as shown in FIG. 6B, a Si layer 45 is formed by stacking 5 to 7 atomic layers of Si used as a dopant on the Al _0.25 Ga _0.75 N layer 44. Further, the Si layer 45 having such an extremely small thickness can be formed by using the MOCVD method.

  Next, since the 2 to 3 atomic layers on the outermost surface of the Si layer 45 are naturally oxidized when moving in the atmosphere, the oxidized 2 to 3 atomic layers are removed by HF.

Next, as shown in FIG. 6 (c), in an oxidation furnace, at 750 ° C. for 10 minutes in an atmosphere in which oxygen is 20% (oxygen flow rate is 5 mL / min (standard state)) and nitrogen is 80%. A thermal oxide insulating film is formed by performing a heat treatment on the sample shown in FIG. In this case, the temperature to oxidize very low at 750 ℃, Al _0.25 Ga _0.75 N layer 44 without being oxidized, only Si layer 45 is oxidized, very thin Si0 ₂ film of thickness 1 nm (thermal oxidation (Insulating film) 46.

Next, as shown in FIG. 6D, by etching the SiO ₂ film 46 and the like using the resist pattern as a mask, a desired region of the SiO ₂ film 46 and the like is removed to form a source / drain. Form an area. Next, after metal is deposited on the source / drain formation region, the resist pattern is lifted off, and the source / drain region is annealed to form a source / drain electrode 47.

Next, on the Si0 ₂ film 46, Si as an adhesion-promoting element after depositing the Pd mixed in a weight ratio of 30%, by lift-off, Si is mixed in a weight ratio of 30% Pd A gate electrode 48 is formed. Thus, a transistor is completed.

  Here, the adhesion promoting element is an element that promotes the adhesion of the gate electrode to the nitride semiconductor layer, as in the first embodiment. For example, as shown in [Table 1], for example, Elements having high adhesion, such as Ti, Si, Ni, Cr, and Cu, can be used as the adhesion element.

  Further, it is preferable that the adhesion promoting element is an element having a property of being easily oxidized, as in the first embodiment. This is because a gate electrode containing an element having a property of being easily oxidized has excellent adhesion to a nitride semiconductor layer. Specifically, as shown in Table 2 above, it is desirable to use Al, Hf, Zr, Nb, Ta, Nd, Si, Ga, and In as the adhesion promoting element.

Further, the gate electrode 48 and Al _0.25 Ga _0.75 N Si0 ₂ film 46 thickness formed between the layer 44, as in the first embodiment, it is preferable that the and 3nm or less 0.5nm or more.

The following Table 5], Si0 ₂ film and the film thickness of 46, Si0 ₂ Schottky gate electrode 48 formed on the film 46 properties and Si0 ₂ film on the surface of the film thickness of 46 morphology and Si0 ₂ film 46 Shows the relationship with the film thickness.

As is clear from Table 5, when the thickness of the SiO ₂ film 46 is 0.5 nm or more and 3 nm or less, it is found that the Schottky characteristics are good. This is because when the film thickness is less than 0.5 nm, the leak current cannot be suppressed, as in the case where the gate electrode 48 is directly joined on the Al _0.25 Ga _0.75 N layer 44. If the thickness is greater than 3 nm, the function of the SiO ₂ film 46 as an insulating film is exhibited, and Schottky junction cannot be performed. That is, if the thickness of the SiO ₂ film 46 is 0.5 nm or more and 3 nm or less, good Schottky characteristics are realized and the function of the gate electrode is not impaired. In addition, when the thickness of the SiO ₂ film 46 is 0.5 nm or more and 3 nm or less, it can be seen that the morphology of the surface of the SiO ₂ film 46 is also good. More preferably, if the thickness of the SiO ₂ film 46 is 0.5 nm to 1.5 nm, the Schottky characteristics are more excellent and the leak current can be more effectively suppressed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the fourth embodiment, since the SiO ₂ film 46 is interposed between the gate electrode 48 and the Al _0.25 Ga _0.75 N layer 44, the gate electrode 48 whereas chemically reacts with Si0 ₂ film 46, does not cause a direct chemical reaction between the Al _0.25 Ga _0.75 N layer 44, it is possible to suppress generation of leakage current. Further, while the gate electrode 48 to cause a chemical reaction with Si0 ₂ film 46, does not cause a direct chemical reaction between the Al _0.25 Ga _0.75 N layer 44, the necessary amount of Si to be mixed into the gate electrode 48 Up to the volume. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors. As a result, in forming the gate electrode 48, the gate electrode 48 did not peel off at all even if excessive ultrasonic cleaning was performed at the time of lift-off. That is, according to the semiconductor device and the method of manufacturing the same according to the fourth embodiment, it is possible to realize a very low leak characteristic inherent to Pd constituting the gate electrode 48 and to prevent the gate electrode 48 from peeling off. .

Further, since the SiO ₂ film 46 interposed between the gate electrode 48 and the Al _0.25 Ga _0.75 N layer 44 is a thermal oxide insulating film, since the surface level derived from dangling bonds and the like is small, the thermal oxide insulating film Can be obtained to obtain electrical stability. Therefore, by interposing a thermally oxidized insulating film between the gate electrode 48 and the Al _0.25 Ga _0.75 N layer 44, if the insulating film is formed by deposition using a normal CVD method or the like, it can be used as a dangling bond or the like. It is possible to prevent a leakage current generated by electrically activating a large number of derived surface states.

In the fourth embodiment, the thermal oxide insulating film is a concept including a pure thermal oxide insulating film and a thermal oxynitride insulating film. That is, the concept includes a pure thermal oxide insulating film made of a SiO ₂ film and a thermal oxynitride insulating film made of a SiON _x film containing nitrogen.

  In the fourth embodiment, the Si layer 45 is formed by doping, but the Si layer may be deposited.

Although the case where the Al _0.25 Ga _0.75 N layer 44 is doped with Si has been described, the same effect can be obtained even when the Si is not doped.

  Here, a semiconductor device according to a modification of the fourth embodiment will be described with reference to FIG.

  FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor device according to a modification of the fourth embodiment.

In the semiconductor device shown in FIG. 7, the SiC substrate 41, the buffer layer 42, the GaN layer 43, and the Al _0.25 Ga _0.75 N layer 44 are formed in the same manner as described with reference to FIG. Further, SiON film 81 is formed on the Al _0.25 Ga _0.75 N layer 44, to the Si layer 45 which is formed by the procedure of description with reference to FIG. 6 (b), N ₂ O Alternatively, it is formed by performing a heat treatment in an NO atmosphere to change the outermost surface of the Si layer 45 to an extremely thin silicon oxynitride film. The source / drain electrode 47 and the gate electrode 48 are formed in the same procedure as described with reference to FIG. Thus, a transistor is completed.

According to the modification of the fourth embodiment, since the SiON film 81 is interposed between the gate electrode 48 and the Al _0.25 Ga _0.75 N layer 44, the gate electrode 48 causes a chemical reaction with the SiON film 81. , Al _0.25 Ga _0.75 N layer 44 does not directly cause a chemical reaction, thereby suppressing generation of a leak current. Further, since the gate electrode 48 causes a chemical reaction with the SiON film 81 but does not directly cause a chemical reaction with the Al _0.25 Ga _0.75 N layer 44, the content of Si mixed in the gate electrode 48 is reduced to a necessary amount. Can be increased. Therefore, the adhesion of the gate electrode to the nitride semiconductor layer can be improved, so that the gate electrode can be prevented from peeling off due to external factors. As a result, in forming the gate electrode 48, the gate electrode 48 did not peel off at all even if excessive ultrasonic cleaning was performed at the time of lift-off. That is, according to the semiconductor device and the method for manufacturing the same according to the modification of the fourth embodiment, Pd constituting the gate electrode 48 achieves a very low leak characteristic inherently, and prevents the gate electrode 48 from peeling off. be able to.

As described above, even when the thermal oxynitride insulating film made of the SiON _x film containing nitrogen is used as the thermal oxide insulating film, the same effect as that when the above-described pure thermal oxide insulating film is used can be obtained. it can.

In the first to fourth embodiments, the case where the Al ₂ O ₃ film, the Ga ₂ O ₃ film, and the SiO ₂ film are used as the thermal oxide insulating film has been described. In the case where the HfO ₂ film, the ZrO ₂ film, the Nb ₂ O ₅ film, the Ta ₂ O ₅ film, the Nd ₂ O ₃ film, or the In ₂ O ₃ film among the oxides shown in FIG. Even in this case, the same effect as when the thermal oxidation insulating film is an Al ₂ O ₃ film, a Ga ₂ O ₃ film, or a SiO ₂ film can be obtained.

  In each of the first to fourth embodiments described above, the case where SiC is used as the substrate has been described. However, the present invention is not limited to this, and sapphire, Si, GaN, or the like may be used.

Further, in each of the first to fourth embodiments described above, the case where the base film of the thermal oxide insulating film is a GaN film or an AlGaN film has been described. However, a general film such as an AlN film, an InN film, or a mixed crystal thereof is used. On the group III nitride semiconductor layer represented by (In _x Al _1-x ) _y Ga _{1 -y} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), Similar effects can be obtained even when the thermal oxidation insulating film described in the embodiment is formed.

-Consideration on the operation and effect of the present invention-
Here, as described in the above embodiments, even if an insulating film is interposed between the metal electrode of the gate and the nitride semiconductor layer, by maintaining the thickness of the insulating film at about 1 nm to about 3 nm, It will be described below that the gate electrode in each embodiment has the same Schottky characteristics as when a metal is directly deposited on the surface of the nitride semiconductor layer.

  FIG. 8A is a band diagram of a Schottky junction in which a metal electrode is formed directly on the surface of a nitride semiconductor layer.

  As shown in FIG. 8A, the alignment of the Fermi level between the metal and the nitride semiconductor layer that determines the height of the Schottky barrier is such that the wave function 201 of the electron near the Fermi level of the metal is This is realized by overlapping with the interface state 202. The IV characteristic of this junction is approximately expressed by the following equation according to a thermionic emission model, as shown in FIG.

^{J = A ** T 2 (-qφ} / k B T) {exp (qV / k B T) -1}
Here, J is the current density, A ^** Richardson constant, q is the elementary charge, phi is the Schottky barrier height, k _B T is the Boltzmann constant, T is the absolute temperature, V is representative of the applied voltage.

  9 to 11 are band diagrams in the case where an extremely thin insulating film is interposed between the metal electrode and the nitride semiconductor layer.

  As shown in FIGS. 9 to 11, when the thickness of the insulating film is gradually increased, the degree of overlap between the wave function 301 of electrons near the Fermi level of the metal and the surface level 302 of the nitride semiconductor layer is as follows. It decreases as the thickness of the insulating film increases, and both eventually become uncorrelated (decoupling). When the thickness of the insulating film is extremely thin, 3 nm or less, the degree of overlap between the wave function 301 and the surface level 302 of the nitride semiconductor layer is sufficiently large, and the Fermi level alignment between the metal and the semiconductor surface is This is the same as in the case of a Schottky junction in which a metal is directly deposited on a nitride semiconductor layer, and the obtained IV characteristics are substantially the same.

  FIG. 12 is a diagram showing IV characteristics corresponding to FIGS. 9 to 11, and shows the IV characteristics corresponding to FIGS. 9 to 11 using curves a to c.

  When the thickness of the insulating film exceeds 3 nm, the Fermi level between the metal and the nitride semiconductor layer becomes uncorrelated as shown by the curve c, and a tunnel junction is formed instead of a Schottky junction. In this region, the voltage applied to the gate electrode makes it possible to independently control the Fermi level of the metal with respect to the nitride semiconductor layer, and in particular, at the time of reverse bias, leakage caused by electrons injected by tunneling from the gate. This causes an increase in current. Further, as the thickness of the insulating film increases, the voltage drop in the insulating film also increases, and the controllability of the amount of charge in the nitride semiconductor layer deteriorates. For example, in an HFET, the decrease in transconductance (gm) decreases. Invite.

  On the other hand, when the thickness of the insulating film is extremely thin and is about one or two atomic layers, surface levels due to the nonuniformity of the insulating film on the surface of the nitride semiconductor layer increase, The key characteristics have an adverse effect such as an increase in leakage current (the above-mentioned references "EHRHODERICK and RHWILLIAM.," Metal-Semiconductor Contacts ", 2nd Ed. Claredon Press. Oxford 1988 Chap 1-3).

Here, when an Al ₂ O ₃ film or a SiO ₂ film is used as the insulating film, the aforementioned element Ti, Ni, or Si has extremely high reactivity, so that the adhesion of Pd is improved. However, Si can obtain desired characteristics more electrically than Ti and Ni, which may be excessively diffused into the insulating film during the reaction. Therefore, if a material containing Pd as a main component and a proper amount of Si mixed with the material is used as the gate electrode material, it is extremely adherent to the Al ₂ O ₃ film or SiO ₂ film while making use of the inherently low leak characteristics of Pd. This is a particularly desirable combination of materials in the present invention, because it is possible to form a gate electrode having a high gate electrode.

  As described above, according to the present invention, since the thermal oxide insulating film is interposed between the gate electrode and the group III nitride semiconductor layer, it is possible to suppress the occurrence of a leakage current and to reduce the gate to the nitride semiconductor layer. Since the adhesion of the electrode can be improved, it is useful when a gate electrode is formed on a group III nitride semiconductor layer.

6A to 6C are cross-sectional views showing the steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating an IV characteristic of the gate electrode according to the first embodiment. 7A to 7D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a diagram illustrating an IV characteristic of a gate electrode according to the second embodiment. 7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention. (a)-(d) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment of this invention. FIG. 14 is a cross-sectional view illustrating a structure of a semiconductor device according to a modification of the fourth embodiment of the present invention. (a) is a band diagram of a Schottky junction in which a metal electrode is formed directly on the surface of a nitride semiconductor layer, and (b) is a diagram showing IV characteristics. 3 is a band diagram in a case where an extremely thin insulating film is interposed between a metal electrode and a nitride semiconductor layer. 3 is a band diagram in a case where an extremely thin insulating film is interposed between a metal electrode and a nitride semiconductor layer. 3 is a band diagram in a case where an extremely thin insulating film is interposed between a metal electrode and a nitride semiconductor layer. FIG. 4 is a diagram showing IV characteristics when an extremely thin insulating film is interposed between a metal electrode and a nitride semiconductor layer. FIG. 14 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

Explanation of reference numerals

11, 21, 31, 41 SiC substrate 12, 22, 32, 42 Buffer layer 13, 23, 33, 43 GaN layer 14, 25 AlN layer 15, 26 Al ₂ O ₃ film 16, 28, 35, 48 Gate electrode 24 , 44 Al _0.25 Ga _0.75 N layer 27, 47 Source / drain electrode 34 Ga ₂ O ₃ film 45 Si layer 46 SiO ₂ film 81 SiON film 201, 301 Schematic wave function near metal Fermi level 202, 302 Metal / semiconductor interface Level

Claims (14)

A group III nitride semiconductor layer;
A gate electrode formed on the group III nitride semiconductor layer,
The gate electrode contains an adhesion promoting element,
A semiconductor device, wherein a thermal oxide insulating film is interposed between the group III nitride semiconductor layer and the gate electrode.   2. The semiconductor device according to claim 1, wherein the thermal oxide insulating film is made of aluminum oxide or silicon oxide.   2. The semiconductor device according to claim 1, wherein the thickness of the thermal oxide insulating film is 0.5 nm or more and 3 nm or less.   The semiconductor device according to claim 1, wherein the gate electrode contains Pd.   The semiconductor device according to claim 1, wherein the adhesion promoting element is Ti, Ni, or Si.   2. The semiconductor device according to claim 1, wherein the adhesion promoting element is an element having a property of being easily oxidized.   2. The semiconductor device according to claim 1, wherein the thermal oxide insulating film is an insulating film formed by thermally oxidizing the group III nitride semiconductor layer. The adhesion promoting element is Si,
8. The semiconductor device according to claim 7, wherein a weight ratio of the Si occupying the metal constituting the gate electrode is 3% or more and 10% or less. 9. The adhesion promoting element is Si,
8. The semiconductor device according to claim 7, wherein a weight ratio of the Si occupying the metal forming the gate electrode is 4% or more and 7% or less. 9. Thermally oxidizing the group III nitride semiconductor layer to form a thermal oxide insulating film on the surface of the group III nitride semiconductor layer;
Forming a gate electrode containing an adhesion promoting element on the thermally oxidized insulating film. The step of forming the thermal oxide insulating film includes:
After forming an aluminum nitride layer on the group III nitride semiconductor layer, by thermally oxidizing the aluminum nitride layer to change it to an aluminum oxide layer, the thermal oxide insulating film made of the aluminum oxide layer is formed. The method for manufacturing a semiconductor device according to claim 10, comprising a step.   The method according to claim 11, wherein a thickness of the aluminum oxide layer is 0.5 nm or more and 3 nm or less. The step of forming the thermal oxide insulating film includes:
Forming a silicon layer on the surface of the group III nitride semiconductor layer, and then thermally oxidizing the silicon layer to change it to a silicon oxide layer, thereby forming the thermal oxide insulating film made of the silicon oxide layer. The method for manufacturing a semiconductor device according to claim 10, wherein the method includes: 14. The method according to claim 13, wherein the thickness of the silicon oxide layer is 0.5 nm or more and 3 nm or less.

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