JP2004185375A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: as the number of bus controllers of a transfer source or a transfer destination increases, clock operation is executed even in the absence of a wait state or an access request, to cause wasteful electricity consumption. <P>SOLUTION: This information processor has: the plurality of transfer source bus controllers 19 etc., a plurality of input stages 22 etc. holding access requests, and a plurality of decoding stages 25 etc. deciding access destinations; a detection means 28 detecting congestion of the access requests to the same access destination on the basis of results of the decoding stages; a plurality of mediation stages 29 etc. deciding access rights according to priority order for the congestion; a plurality of output stages 33 etc. each receiving information from the transfer source bus controller acquiring the access right and outputting the information ; the plurality of transfer destination bus controllers 37 etc. receiving the access requests; and a clock control circuit 41 stopping the clocking of the input stage and the decoding stage corresponding to the transfer source bus controller suspending the access request. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock control signal and a bus control in an information processing device.
[0002]
[Prior art]
There are few conventional information processing apparatuses that reduce the power consumption of the information processing apparatus in accordance with the use state of the bus, and almost none of the information processing apparatuses reduce the power consumption of the bus itself. Hereinafter, a conventional information processing apparatus will be described. FIG. 8 is a block diagram showing a configuration of a conventional information processing apparatus.
[0003]
In FIG. 8, reference numerals 1 to 3 denote first to third transfer source bus control devices which issue access requests, and reference numerals 4 to 6 denote first to third input stages which hold access requests of the transfer source bus control devices 1 to 3. , 7 to 9 are first to third decoding stages connected to the transfer destination bus control devices requested by the transfer source bus control devices 1 to 3, and 10 to 13 are transfer source bus control devices to the transfer destination bus control devices 14 to 17. First to fourth output stages 14 to 17 for outputting information from the bus controller, first to fourth destination bus controllers 14 to 17 receiving an access request, and 18 a bus connecting each block.
[0004]
The operation of the information processing apparatus configured as described above will be described below.
[0005]
When an access request is issued from any one of the transfer source bus controllers 1 to 3 to the bus 18, the access request is transmitted to the corresponding one of the input stages 4 to 6. Next, one of the decode stages 7 to 9 connects to one of the transfer destination bus control devices 14 to 17 to which access is requested.
[0006]
An access request from the transfer source bus control devices 1 to 3 may be issued by any one transfer source bus control device to any one transfer destination bus control device. The control device may request access.
[0007]
When a plurality of transfer source bus control devices request access to one transfer destination bus control device at the same time, priority processing is performed. In the plurality of transfer source bus controllers 1 to 3, priorities are determined in advance. Note that this priority is fixed. An output stage corresponding to a certain transfer destination bus control device arbitrates to which transfer source bus control device the access right is given when a plurality of access requests are transmitted to the output stage at the same time. As a result, the priority transfer source bus control device to which the access right has been granted performs information transmission with the transfer destination bus control device, while the transfer source bus control device to which the access right has not been granted enters a wait state, As soon as the information transfer of the priority transfer source bus control device is completed, the process shifts to the information transfer with the transfer destination bus control device.
[0008]
[Patent Document 1]
JP-A-6-43980 (page 4, FIG. 1)
[0009]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, in the plurality of transfer source bus control devices that issue an access request and the plurality of transfer destination bus control devices that receive the access request, the transfer between the transfer source bus control device and the transfer destination bus control device that are not transmitting information is performed. Clock control and bus amplitude control (operated by state transitions unrelated to clock operation) are not addressed, so as the number of transfer source bus control devices and the number of transfer destination bus control devices increase, the transfer source bus control There is a drawback that power is consumed between the transfer source bus control device and the transfer destination bus control device when the device is in a waiting state or when a transfer request is not made.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide an information processing apparatus that reduces the power consumption of a bus according to the usage status of the bus.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the present invention takes the following measures.
[0012]
The information processing apparatus of the present invention is based on the following configuration. That is, a plurality of transfer source bus control devices that issue access requests, a plurality of input stages that hold access requests from the transfer source bus control devices, and an access based on the access requests held by each of the input stages. A plurality of decoding stages for determining destinations; detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage; and an access right according to a priority when the access requests are congested. A plurality of arbitration stages for arbitrating access requests, a plurality of output stages for receiving and outputting information from the transfer source bus control device having the access right, and an access request from each of the output stages. With multiple destination bus controllers receiving the The processing unit is assumed.
[0013]
According to a first aspect of the present invention, in the information processing apparatus having the above-described configuration, the input stage and the decode stage corresponding to the transfer source bus control device whose access request is detected to be suspended by the detection unit are stopped. A clock control circuit. According to this, the bus clock is stopped for the transfer-source bus control device that does not request access, so that the power consumption of the information processing device can be reduced.
[0014]
According to a second aspect of the present invention, in the information processing device having the above-described configuration, the arbitration stage and the output stage corresponding to the transfer destination bus control device that has been detected as not receiving an access request by the detection unit are stopped. A clock control circuit. According to this, since the bus clock is stopped for the transfer destination bus control device that has not received the access request, it is possible to reduce the power consumption of the information processing device.
[0015]
According to a third aspect of the present invention, in the information processing apparatus having the above-described configuration, a transfer which is individually interposed between the decoding stage and the detecting means and which is detected by the detecting means as suspending an access request. The one corresponding to the former bus control device includes a plurality of selectors for switching to selection of fixed information instead of selection of information from the decode stage. According to this, the bus amplitude operation (operated by a state transition unrelated to the clock operation) is stopped for the transfer source bus control device that has not made an access request, so that the power consumption of the information processing device can be reduced. it can.
[0016]
A fourth solution means is the information processing device having the above configuration, wherein the clock control circuit stops the clocks of the input stage and the decode stage corresponding to the transfer source bus control device to which the access right has not been given by the arbitration stage. Is provided. According to this, since the bus clock is stopped for the transfer source bus control device to which the access right has not been given, the power consumption of the information processing device can be reduced.
[0017]
Fifth solution means is the information processing device having the above configuration, wherein the transfer source bus control device which is individually interposed between the decode stage and the detection means and whose access right is not given by the arbitration stage is provided. Are provided with a plurality of selectors for switching to selection of fixed information instead of selection of information from the decode stage. According to this, the bus amplitude operation of the transfer source bus control device to which the access right has not been given is stopped, so that the power consumption of the information processing device can be reduced.
[0018]
According to a sixth aspect of the present invention, in the information processing apparatus having the above configuration, information that does not change during continuous transfer is held in a fixed state in the output stage corresponding to the transfer source bus control device to which the access right has not been given by the arbitration stage. Bus control means for performing the operation. According to this, for the transfer source bus control device to which the access right has not been given, the information that does not change during the continuous transfer is held in a fixed state, so that the power consumption of the information processing device can be reduced.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of an information processing apparatus according to the present invention will be described in detail with reference to the drawings.
[0020]
(First Embodiment)
FIG. 1 is a block diagram showing a configuration of the information processing apparatus according to the first embodiment of the present invention. In FIG. 1, reference numerals 19 to 21 denote first to third transfer source bus control devices which issue an access request, and reference numerals 22 to 24 first to third transfer input and hold access requests from the transfer source bus control devices 19 to 21. Input stages 25 to 27 are first to third decode stages for determining the access destination requested by the transfer source bus control devices 19 to 21, and 28 is for detecting an access status to the same transfer destination bus control device. Detecting circuits 29 to 32 determine first to fourth arbitration stages for determining access rights to transfer destination bus control devices 37 to 40, and 33 to 36 obtain access rights to transfer destination bus control devices 37 to 40. First to fourth output stages 37 to 40, which hold and output information from the transfer source bus control device, are first to fourth transfer destination bus control devices receiving an access request. , The clock control circuit 41, 42 denotes a clock control bus.
[0021]
The first to third transfer source bus controllers 19 to 21 are connected to the detection circuit 28 via input stages 22 to 24 and decode stages 25 to 27, respectively. The detection circuit 28 is connected to first to fourth transfer destination bus control devices 37 to 40 via first to fourth arbitration stages 29 to 32 and output stages 33 to 36, respectively. Further, clock control circuits 41, 41 are attached to each of the input stages 22 to 24 and each of the decode stages 25 to 27, and the detection circuit 28 is connected via a clock control bus 42 to a pair of the input stage and the decode stage. The clock control circuits 41 in the set are configured to be individually controlled.
[0022]
Each of the transfer source bus controllers 19 to 21 receives an address signal, an access request signal, a transfer status signal, a bus status signal, a data transmission / reception signal, a transmission / reception data size signal, a continuous It issues a transfer signal, protection control signal, transmission / reception data signal, and transfer destination fixed signal.
[0023]
Each of the input stages 22 to 24 holds and transfers each signal related to the access request in accordance with the use status of the next and subsequent stages. The decode stages 25 to 27 perform a transfer between the transfer destination bus controllers 37 to 40 based on the address signals of the access destinations issued by the corresponding transfer source bus controllers 19 to 21. Confirm.
[0024]
The detection circuit 28 checks whether or not an access request has been issued from a plurality of transfer source bus controllers simultaneously to the same transfer destination bus control device. A control signal is supplied to the clock control circuits 41, 41 of the input stage and the decode stage corresponding to the device via a clock control bus 42, and the clock control circuits 41, 41 which have received the control signal transmit the control signal to the corresponding input stage. And stopping the clock in the decode stage. As a result, each signal relating to an access request from the transfer source bus control device having no access request is held.
[0025]
Among the arbitration stages 29 to 32, a plurality of arbitration stages related to the simultaneous access request determine an access right to the transfer destination bus control device related to the current simultaneous access request. Each of the transfer destination bus control devices 37 to 40 individually has a rule of priority of which of the plurality of transfer source bus control devices 19 to 21 is given priority and which is given later. The priorities of the transfer destination bus controllers 37 to 40 are independent of each other.
[0026]
According to this priority, the corresponding arbitration stage selects the transfer source bus control device having the highest priority from the plurality of transfer source bus control devices related to the simultaneous access request, and continues the information transmission.
[0027]
The corresponding one of the output stages 33 to 36 outputs information from the transfer source bus control device that has obtained the right to access the transfer destination bus control device to which the current simultaneous access request is to be made to the corresponding transfer destination bus control device. . The corresponding destination bus control device receives each of the above signals.
[0028]
FIG. 2 is a timing chart showing an operation state when a plurality of transfer source bus control devices simultaneously access the same transfer destination bus control device. .., B, B + 4, B + 8... And B, B + 4, B + 8. IDLE indicates the state of the bus transfer source not issuing an access request, NONSEQ indicates the state of the bus transfer source performing discontinuous transfer, and SEQ indicates the state of the bus transfer source performing continuous transfer. With respect to the original transfer information Data0, Data1, and Data2, D, E, F... And DD, EE, FF.
[0029]
The operation of the information processing apparatus configured as described above will be described below.
[0030]
Now, it is assumed that access requests are issued from the first and second transfer source bus controllers 19 and 20 at the same time. It is assumed that the third transfer source bus control device 21 has not made an access request. The input stages 22 and 23 hold respective access requests. Next, the decode stages 25 and 26 determine an access destination to the transfer destination bus control device requested by the transfer source bus control devices 19 and 20 by referring to an address map based on the issued address. Further, the detection circuit 28 checks whether or not there is the same transfer destination bus control device as the access destination. Based on the transfer source address and the transfer status signal, the relationship between the transfer source bus control device having the access request and the transfer destination bus control device is recognized. The detection circuit 28 stops the clock by transmitting a clock stop signal to each of the clock control circuits 41 and 41 of the input stage 24 and the decode stage 27 corresponding to the transfer source bus control device 21 that does not have an access request. In FIG. 2, the source clock CLK2 is stopped, and the source transfer state Trans2 becomes IDLE. Since the operation of the input stage 24 and the decode stage 27 whose clocks are stopped is stopped, low power consumption can be achieved.
[0031]
As described above, according to the present embodiment, the clock stop of the input stage and the decode stage related to the transfer source bus control device that has not issued the access request is performed by the cooperation of the detection circuit 28 and the clock control circuits 41, 41. Is performed, power consumption of the clock control register (input stage, decode stage) can be reduced.
[0032]
In the present embodiment, since clock control is performed in a stage earlier than in a second embodiment described later, power consumption can be reduced at an earlier stage.
[0033]
(Second embodiment)
FIG. 3 is a block diagram showing the configuration of the information processing device according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as in FIG. 1 of the first embodiment denote the same components, and a detailed description thereof will be omitted. Clock control circuits 43 and 43 are attached to the arbitration stages 29 to 32 and the output stages 33 to 36, respectively, and the detection circuit 28 is connected to a clock in a pair of arbitration stage and output stage via a clock control bus 44. The control circuits 43 are individually controlled. Other configurations are the same as those of the first embodiment shown in FIG.
[0034]
The operation of the information processing apparatus configured as described above will be described below.
[0035]
One of the transfer source bus controllers 19 to 21 issues an access request, and a corresponding one of the input stages 22 to 24 holds the access request. Next, the corresponding one of the decode stages 25 to 27 determines the access destination to the transfer destination bus control device requested by the transfer source bus control device by referring to the address map based on the issued address.
[0036]
The detection circuit 28 checks whether an access request has been made to the same transfer destination bus control device at the same time, and if so, first, an arbitration corresponding to the transfer destination bus control device that has not received the access request is performed. A control signal is supplied to the clock control circuits 43 of the stage and the output stage via a clock control bus 44. The clock control circuits 43, 43 that have received the control signal from the detection circuit 28 stop the clock in the corresponding arbitration stage and output stage. Thereby, the operations of the arbitration stage and the output stage relating to the transfer destination bus control device which has not received the access request are stopped.
[0037]
As described above, according to the present embodiment, the clock stop of the arbitration stage and the output stage related to the transfer destination bus control device that has not received the transfer request is performed by the cooperation of the detection circuit 28 and the clock control circuit 43. Therefore, power consumption of the clock control register (arbitration stage, output stage) can be reduced.
[0038]
(Third embodiment)
FIG. 4 is a block diagram showing a configuration of a main part of an information processing apparatus according to the third embodiment of the present invention. The configuration shown in FIG. 4 is different from the configuration shown in FIG. 1 in that selectors 45 to 47 are interposed between decode stages 25 to 27 and detection circuit 28, and from detection circuit 28 via selector control bus 53. The configuration is such that the selectors 45 to 47 are controlled. In FIG. 4, reference numerals 45 to 47 denote first to third selectors for selecting information transmitted from the transfer source bus control devices 19 to 21 and fixed information, and reference numerals 48 to 51 denote transfer destination bus control devices 37 to 40. First to fourth detection stages for detecting an access request, 52 is a terminal for outputting fixed information, and 53 is a selector control bus connecting the detection circuit 28 and the selectors 45 to 47. The detection circuit 28 includes a plurality of detection stages 48 to 51. The configuration of the detection circuit 28 is the same in FIGS. 1, 3, and 5.
[0039]
The operation of the information processing apparatus configured as described above will be described below.
[0040]
One of the transfer source bus controllers 19 to 21 issues an access request, and a corresponding one of the input stages 22 to 24 holds the access request. Next, the corresponding one of the decode stages 25 to 27 determines the access destination to the transfer destination bus control device requested by the transfer source bus control device by referring to the address map based on the issued address.
[0041]
The detection circuit 28 checks whether an access request has been made to the same transfer destination bus control device at the same time, and if so, first, an arbitration corresponding to the transfer destination bus control device that has not received the access request is performed. A control signal is supplied to the clock control circuits 43 of the stage and the output stage via a clock control bus 44.
[0042]
The detection circuit 28 detects the presence or absence of an access request from the transfer source bus control device and the transfer destination bus control device, but controls a selector corresponding to the transfer source bus control device that has not made an access request for a certain period of time. . That is, a switching control signal is transmitted via the selector control bus 53 to the selector corresponding to the transfer source bus control device which has not made an access request among the selectors 45 to 47, and the selector is fixed without bus amplitude operation. Switch to the information 52 side. The bus amplitude operation operates according to a state transition unrelated to the clock operation.
[0043]
As described above, according to the present embodiment, the selectors 45 to 47 that are switched according to the detection result of the detection circuit 28 are provided, and the bus amplitude operation is performed on a signal output in a state transition that is not under clock control. Since the system is configured to be stopped, low power consumption can be achieved.
[0044]
(Fourth embodiment)
FIG. 5 is a block diagram showing a configuration of a main part of an information processing apparatus according to the fourth embodiment of the present invention. 5, the same reference numerals as those in FIG. 1 of the first embodiment denote the same components, and a detailed description thereof will be omitted. In FIG. 5, reference numeral 54 denotes a clock control bus connecting the arbitration stages 29 to 32 and the clock control circuits 41, 41. Other configurations are the same as those in FIG. 1 in the case of the first embodiment.
[0045]
The operation of the information processing apparatus configured as described above will be described below.
[0046]
One of the transfer source bus controllers 19 to 21 issues an access request, and a corresponding one of the input stages 22 to 24 holds the access request. Next, the corresponding one of the decode stages 25 to 27 determines the access destination to the transfer destination bus control device requested by the transfer source bus control device by referring to the address map based on the issued address.
[0047]
The detection circuit 28 checks whether an access request has been made to the same transfer destination bus control device at the same time, and if so, passes the check result to the arbitration circuit 55. The arbitration circuit 55 determines an access right to the transfer destination bus control device, and arbitrates in a plurality of transfer source bus control devices that have issued access requests to the same transfer destination bus control device at the same time. That is, the transfer source having the access right and the transfer source not having the access right are determined. Therefore, a control signal is supplied to the transfer source having no access right, that is, the clock control circuits 41 and 41 of the transfer source in the waiting state via the clock control bus 54, and the clock control circuit receiving the control signal 41, 41 stop the clock in the corresponding input stage and decode stage. As a result, each signal related to an access request from the transfer source bus control device that is not granted the access right is held.
[0048]
As described above, according to the present embodiment, by controlling the clock control circuit 41 from the arbitration circuit 55, the clock of the input stage and the decode stage related to the transfer source bus control device in the transfer waiting state is stopped. Power consumption of the clock control register (input stage, decode stage) can be reduced.
[0049]
(Fifth embodiment)
FIG. 6 is a block diagram showing a configuration of a main part of an information processing apparatus according to the fifth embodiment of the present invention. The configuration shown in FIG. 6 is different from the configuration shown in FIG. 1 in that selectors 45 to 47 are interposed between decode stages 25 to 27 and detection circuit 28 and arbitration circuit 55 is connected to selector control bus 56. The configuration is such that the selectors 45 to 47 are controlled. 4 is different from FIG. 4 of the third embodiment in that the detection circuit 28 or the arbitration circuit 55 is under the control of the selectors 45 to 47. Other configurations are the same as those in FIG. 1 in the first embodiment and FIG. 4 in the third embodiment, and therefore, the same reference numerals are given to the same portions, and description thereof will be omitted.
[0050]
The operation of the information processing apparatus configured as described above will be described below.
[0051]
One of the transfer source bus controllers 19 to 21 issues an access request, and a corresponding one of the input stages 22 to 24 holds the access request. Next, the corresponding one of the decode stages 25 to 27 determines the access destination to the transfer destination bus control device requested by the transfer source bus control device by referring to the address map based on the issued address.
[0052]
The detection circuit 28 checks whether an access request has been made to the same transfer destination bus control device at the same time, and if so, first, an arbitration corresponding to the transfer destination bus control device that has not received the access request is performed. A control signal is supplied to the clock control circuits 43 of the stage and the output stage via a clock control bus 44.
[0053]
The detection circuit 28 checks whether an access request has been made to the same transfer destination bus control device at the same time, and if so, passes the check result to the arbitration circuit 55. The arbitration circuit 55 determines an access right to the transfer destination bus control device, and arbitrates in a plurality of transfer source bus control devices that have issued access requests to the same transfer destination bus control device at the same time. That is, the transfer source having the access right and the transfer source not having the access right are determined. Therefore, the selector controls the selector corresponding to the transfer source bus control device to which the access right is not held. That is, a switching control signal is transmitted via the selector control bus 55 to the selector corresponding to the transfer source bus control device having no access right among the selectors 45 to 47, and the selector is set to the fixed information having no bus amplitude operation. Switch to the side of 52.
[0054]
As described above, according to the present embodiment, the selectors 45 to 47 that are switched by the arbitration processing of the arbitration circuit 55 are provided, and the bus amplitude operation is performed on the signal output in the state transition that is not under the clock control. Since the system is configured to be stopped, low power consumption can be achieved.
[0055]
(Sixth embodiment)
FIG. 7 is a timing chart showing the operation of the information processing apparatus according to the sixth embodiment of the present invention. In FIG. 7, Addr0 is a transfer source address signal, Data0 is a transfer source data signal, WE0 is a data read / write control signal, Trans0 is a transfer status signal, CS0 is a chip select signal, and Size0 is a data transfer width. 57 indicates an uncertain state of the signal.
[0056]
The operation of the information processing apparatus configured as described above will be described below.
[0057]
The transfer source bus control device given the access right by the arbitration circuit 55 continues the information transmission process. When performing continuous data transfer in the information transmission process, an access request from a transfer source having a higher priority is occasionally received even though the values do not change as in the control signal WE0, the chip select signal CS0, and the data transfer width Size0 in FIG. When the values are re-acquired for confirmation, a signal uncertainty state 57 occurs as shown in the figure, which results in wasteful power consumption.
[0058]
Therefore, the output stages 33 to 36 are configured to hold information from the transfer source bus control device having the access right. By holding the information transmission control signal in the register (output stage), the occurrence of the signal indeterminate state 57 can be prevented.
[0059]
As described above, according to the present embodiment, low power consumption is achieved by retaining information that does not change during continuous transfer from the transfer source bus control device that has obtained the access right to the transfer destination bus control device in the output stage. Can be achieved.
[0060]
Note that any one of the first to sixth embodiments may be used in combination.
[0061]
【The invention's effect】
As described above, according to the present invention, a transfer source bus control device that has not made an access request, a transfer destination bus control device that has not received an access request, or a transfer source bus control device that has not been granted an access right has a bus Since the clock is stopped, power consumption of the information processing device can be reduced. Also, by stopping the bus amplitude operation (operating by a state transition unrelated to the clock operation) for a transfer source bus control device that has not made an access request or a transfer source bus control device that has not been granted an access right, Power consumption of the information processing device can be reduced. Furthermore, for the transfer source bus control device to which the access right has not been given, the information that does not change during continuous transfer is held in a fixed state, so that the power consumption of the information processing device can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing an operation of the information processing apparatus according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an information processing apparatus according to a second embodiment of the present invention.
FIG. 4 is a block diagram illustrating a configuration of a main part of an information processing apparatus according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of an information processing apparatus according to a fourth embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a main part of an information processing apparatus according to a fifth embodiment of the present invention.
FIG. 7 is a timing chart showing the operation of the information processing apparatus according to the sixth embodiment of the present invention.
FIG. 8 is a block diagram illustrating a configuration of an information transmission unit of a conventional information processing apparatus.
[Explanation of symbols]
19-21: transfer source bus control device
22-24 ... Input stage
25-27 ... Decoding stage
28 ... Detection circuit
29-32 ... Arbitration stage
33-36 ... Output stage
37-40: Transfer destination bus control device
41, 43 ... Clock control circuit
42, 44, 54: Clock control bus
45-47 ... selector
48 to 51: detecting means
52 ... fixed information output terminal
53, 56 ... selector control bus
55 Arbitration circuit
57: Signal uncertain state

Claims (6)

A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
An information processing apparatus comprising: a clock control circuit that stops the clock of the input stage and the decode stage corresponding to the transfer source bus control device for which the detection unit detects that the access request is suspended. A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
An information processing apparatus comprising: a clock control circuit that stops a clock of the arbitration stage and the output stage corresponding to a transfer destination bus control device that is detected as not receiving an access request by the detection unit. A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
The one corresponding to the transfer source bus control device which is interposed between the decoding stage and the detecting means and which has detected that the access request has been suspended by the detecting means is information from the decoding stage. An information processing apparatus comprising: a plurality of selectors that switch to selection of fixed information instead of selection of a selection. A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
An information processing apparatus comprising: a clock control circuit that stops a clock of the input stage and the decode stage corresponding to a transfer source bus control device to which an access right has not been given by the arbitration stage. A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
The one corresponding to the transfer source bus control device which is individually interposed between the decoding stage and the detecting means and whose access right is not given by the arbitration stage is replaced with the selection of information from the decoding stage. An information processing apparatus comprising: a plurality of selectors for switching to selection of fixed information. A plurality of transfer source bus controllers for issuing access requests;
A plurality of input stages for holding access requests from each of the transfer source bus control device,
A plurality of decoding stages for determining an access destination based on an access request held by each of the input stages,
Detecting means for detecting whether or not access requests to the same access destination are congested based on the result of the decoding stage;
A plurality of arbitration stages to determine the access right according to the priority when the access request is congested and arbitrate the access request,
A plurality of output stages for receiving and outputting information from the transfer source bus control device that has obtained the access right;
A plurality of transfer destination bus control devices receiving an access request from each of the output stages;
An information processing apparatus comprising: a bus control unit that holds information that does not change during continuous transfer in a fixed state in the output stage corresponding to a transfer source bus control device to which an access right has not been given by the arbitration stage.

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