JP2003242102A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of increase of total route length and increase of throughput in data transfer for one time when mediate peripheral devices are increased along a data transfer route. <P>SOLUTION: In this data transfer device, a plurality of peripheral devices are daisy-chain-connected by bidirectional buses to a bus control device 200. The bus control device 200 is provided with a bus arbiter 201 to adjust bus using rights, a route selecting circuit 202 to decide a data transfer route in accordance with position relation between the peripheral device as an origin of data transfer and the peripheral device as a destination, and a direction control circuit 203 to control a data transfer direction based on decision of the route selecting circuit 202. Each peripheral device is provided with direction changing circuits 211, 221, and 231 to change the data transfer direction of connection buses in accordance with direction control signals 250 from the direction control circuit 203. The enhancement of efficiency of data transfer is thus realized, and system performance can be improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for controlling data transfer between a plurality of peripheral devices daisy chained to a bus control device.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration of a conventional data transfer device (see Japanese Patent Laid-Open No. 2-257351). The outline of the data transfer device shown in FIG. 9 will be described below.

Central processing unit 100 and a plurality of peripheral devices 11
0, 120, 130 are bidirectional buses 140, 141, 1
42 and 143 are connected in a daisy chain. The central processing unit 100 includes a communication direction control circuit 101. Each of the peripheral devices 110, 120, 130 switches the communication direction according to the control signal 150 output from the communication direction control circuit 101, and the communication direction switching circuits 111, 1
21 and 131 are provided.

The daisy-chain connection capable of bidirectional communication is that the communication direction is controlled by the communication direction control circuit 101 and the communication direction switching circuits 111, 121, 131 when a failure occurs in any bus on the communication path. This is to reduce the probability of communication failure by switching between.

[0005]

The data transfer apparatus shown in FIG. 9 has a function of switching the communication direction according to a bus failure. However, in determining the data transfer path, the positional relationship between the peripheral device of the data transfer source and the peripheral device of the data transfer destination is not considered. This does not matter whether a bus failure occurs.

Depending on the selected data transfer direction, a large number of peripheral devices may be connected between the data transfer source peripheral device and the data transfer destination peripheral device. In this case, since the number of intermediary peripheral devices increases and the total path length increases, the throughput in one data transfer increases and the system performance deteriorates.

The present invention was devised in view of such circumstances, and an object thereof is to improve system performance by making a device for rationally determining a data transfer route.

[0008]

The present invention solves the above problems by taking the following means.

In the data transfer device of the present invention, a plurality of peripheral devices are daisy-chain connected to the bus control device by a bidirectional bus. In such a data transfer device, the bus control device determines a data transfer path according to a positional relationship between a bus arbiter that arbitrates a right to use the bus and a peripheral device that is a data transfer source and a peripheral device that is a data transfer destination. And a direction control unit for controlling the data transfer direction based on the determination result of the route selection unit. Further, each of the peripheral devices includes a direction switching unit that switches a data transfer direction of a bus connected to the peripheral device according to a direction control signal from the direction control unit. Each of the route selection means, the direction control means, and the direction switching means may be configured by hardware,
It may be configured by software or a combination of hardware and software.

The route selecting means determines the closer data transfer route according to the positional relationship between the peripheral device of the data transfer source and the peripheral device of the data transfer destination. The mutual positional relationship between the plurality of peripheral devices and the bus control device in the daisy chain bus is fixed. By making this positional relationship into a table, for example, the route selection means can determine the optimum data transfer route according to a combination of which peripheral device of the data transfer source is and which peripheral device of the data transfer destination is. It will be possible.

The direction control means determines the data transfer direction (for example, clockwise or counterclockwise) based on the data transfer path determined by the path selection means, and notifies the direction switching means provided in each peripheral device. The direction switching means switches the direction of the bus connected to its own peripheral device according to the direction control signal notified from the direction control means.

According to this, by automatically selecting the optimum data transfer path and transfer direction according to the positional relationship between the peripheral device of the transfer source and the peripheral device of the transfer destination, the throughput in one data transfer Improves the system
Performance can be increased.

According to another aspect of the present invention, in the above structure,
The bus control device further includes route notification means for outputting a route corresponding signal indicating whether or not the peripheral device corresponds to the transfer route determined by the route selection means to each of the peripheral devices. In addition, each of the peripheral devices further includes clock control means for controlling clock supply to its own peripheral device according to the route corresponding signal from the route notification means.
The route notification means and the clock control means may be configured by hardware, software, or a combination of hardware and software.

The route notification means outputs a route corresponding signal to each peripheral device to notify whether or not each peripheral device corresponds to the determined transfer route. The clock control means of each peripheral device stops the supply of the clock to the peripheral device itself when the peripheral device does not exist on the data transfer path. Since the clock supply to the peripheral device not directly related to the data transfer is stopped in this way, the power consumption can be reduced.

In a further aspect of the present invention, in the above configuration, the bus control device further comprises transfer time determining means for determining a time required for data transfer based on a determination result of the path selecting means. I have it. In addition, the bus arbiter is configured to permit the peripheral device of the data transfer source to use the bus for the time determined by the transfer time determining means. The transfer time determining means may be configured by hardware, software, or a combination of hardware and software.

The transfer time determining means determines a time (clock number) required for data transfer on the determined transfer path,
Notify the bus arbiter. The bus arbiter permits the peripheral device of the data transfer source to use the bus only for the time determined by the transfer time determination means. The peripheral device operates for the allowed time, and stops when the time expires. Therefore, the bus arbiter can arbitrate for the bus without waiting for a reception completion signal from the peripheral device to which the data is transferred, and the bus usage efficiency is improved.

In a further aspect of the present invention, in the above configuration, the bus control device further includes a route storage means for storing a route used for data transfer being executed. In addition, the bus arbiter compares the route of the request from the route selecting means with the route being executed stored in the route storing means, and when there is no duplication, the route of the request is stored in the route storing means. After being stored, the peripheral device of the data transfer source is allowed to use the bus.

If the data transfer path determined by the path selecting means does not overlap with any of the paths stored in the path storing means, the bus arbiter gives permission to use the bus to the corresponding peripheral device. Multiple data transfers can be performed simultaneously, improving bus utilization efficiency.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a data transfer apparatus according to the present invention will be described below in detail with reference to the drawings. In the following embodiments, the number of peripheral devices daisy-chained to the bus controller is fixed,
It does not change depending on the situation.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a data transfer apparatus according to Embodiment 1 of the present invention. The bus controller 200 is a bus arbiter 201.
A path selection circuit 202 and a direction control circuit 203. The bus arbiter 201 includes peripheral devices 210 and 22.
In accordance with a bus request signal 271 input from 0, 230, arbitration is performed so that a plurality of peripheral devices do not use the same bus at the same time, and a bus permission signal 272 is output to the peripheral device that requested the bus. Also, the bus arbiter 20
1 is the bus arbitration result (peripheral devices 210, 220, 23
Which peripheral device out of 0 has acquired the bus right) is output to the direction control circuit 203. Route selection circuit 202
Determines the data transfer path according to the transfer destination selection signal 260 input from the peripheral devices 210, 220, 230 and outputs the result to the direction control circuit 203. The direction control circuit 203 determines whether the transfer direction is clockwise or counterclockwise according to the bus arbitration result input from the bus arbiter 201 and the transfer route input from the route selection circuit 202, and controls the data transfer direction. Output a direction control signal 250 to the peripheral devices 210, 220, 230.

The peripheral devices 210, 220 and 230 respectively include direction switching circuits 211, 221, 231. The direction switching circuits 211, 221, 231 are the direction control circuits 2
In accordance with the direction control signal 250 input from 03, the data transfer direction in the bus connected to the peripheral device is switched.

In the above, each signal is set in binary as follows, for example.

(1) Bus request signal 271 0: Request use of bus 1: Do not request use of bus (2) Bus enable signal 272 0: Allow use of bus 1: Not allow use of bus ( 3) Reception completion signal 273 0: Data reception completed 1: Data reception not completed (4) Transfer destination selection signal 260 000: Bus control device 200 001: Peripheral device 210 010: Peripheral device 220 011: Peripheral device 230 (5) direction Control signal 250 0: Clockwise 1: Counterclockwise FIG. 2 shows an example of a table for determining the data transfer direction.

When the data transfer source is the peripheral device 210 and the data transfer destination is the peripheral device 220, there is an interposition of the bus control device 200 and the peripheral device 230 in the clockwise path from the transfer source to the transfer destination. Since the counterclockwise route is direct without any intervention of other devices, the counterclockwise route is set to have a shorter route length.

When the data transfer source is the peripheral device 210 and the data transfer destination is the peripheral device 230, the bus control device 200 intervenes in the clockwise path from the transfer source to the transfer destination, while the counterclockwise path is provided. In peripheral device 22
There is an intervening number of 0, but the transfer speed is set to clockwise, which is faster.

When the data transfer source is the peripheral device 220 and the data transfer destination is the peripheral device 210, the clockwise path from the transfer source to the transfer destination is direct without the intervention of other devices, and on the other hand, Since the peripheral device 230 and the bus control device 200 are present in the counterclockwise route, the route is set to be clockwise with a shorter route length.

When the data transfer source is the peripheral device 220 and the data transfer destination is the peripheral device 230, the peripheral device 210 and the bus control device 200 intervene in the clockwise path from the transfer source to the transfer destination, while Since the counterclockwise route is direct without any intervention of other devices, the counterclockwise route is set to have a shorter route length.

When the data transfer source is the peripheral device 230 and the data transfer destination is the peripheral device 210, the peripheral device 220 is interposed in the clockwise path from the transfer source to the transfer destination, while the counterclockwise path is provided. Is the bus controller 20
There is an intervening value of 0, but it is set counterclockwise, which has a higher transfer rate.

When the data transfer source is the peripheral device 230 and the data transfer destination is the peripheral device 220, the clockwise path from the transfer source to the transfer destination is direct without the intervention of other devices, and Since the bus control device 200 and the peripheral device 210 are present in the counterclockwise route, the route is set to be clockwise with a shorter route length.

For the data transfer operation, the peripheral device 230
Data transfer from the device to the peripheral device 220 will be described as an example.

[Step 1] The peripheral device 230 outputs a bus request signal 271 to the bus arbiter 201 of the bus control device 200 to request the right to use the bus. At the same time, the peripheral device 230 is connected to the route selection circuit 2 of the bus control device 200.
A transfer destination selection signal 260 is output to 02 to notify that the data transfer destination is the peripheral device 220.

[Step 2] A bus requested to use the bus by the bus request signal 271 from the peripheral device 230.
The arbiter 201 confirms that the bus control device 200 and other peripheral devices are not using the bus, and the peripheral device 23
The direction control circuit 203 is notified that 0 is given the right to use the bus. At the same time, the route selection circuit 202 which receives the transfer destination selection signal 260 from the peripheral device 230 is
Determine the data transfer path from 30 to the peripheral device 220,
Notify the direction control circuit 203.

[Step 3] Bus Arbiter 201
Is the peripheral device 230 that is the output source of the bus request signal 271.
A bus permission signal 272 is output to the CPU to give the right to use the bus. At the same time, the direction control circuit 203 determines the data transfer direction based on the transfer route determined by the route selection circuit 202 (clockwise in this example), and the direction control signal 25
0 is generated and output to the direction switching circuits 211, 221, 231 of each of the peripheral devices 210, 220, 230 to notify that the data transfer direction should be switched clockwise.

[Step 4] Each direction switching circuit 211,
221 and 231 switch the data transfer direction clockwise according to the direction control signal 250. Bus permission signal 272
The peripheral device 230, which is permitted to use the bus by the above, starts data transfer to the peripheral device 220. in this case,
Data transfer is performed using the bus 242 which is clockwise.

[Step 5] The peripheral device 220 receives the data from the peripheral device 230, and then the bus arbiter 2
The reception completion signal 273 is output to 01.

By the above procedure, the peripheral device 230
Data transfer from the peripheral device 220 to the peripheral device 220
→ bus 242 → peripheral device 220 is performed in a clockwise route.

According to the present embodiment, with the above configuration, the data transfer path and the transfer direction are selected in consideration of the relative positional relationship between the peripheral devices, thereby improving the data transfer throughput. System performance can be improved.

(Second Embodiment) FIG. 3 is a block diagram showing a configuration of a data transfer apparatus according to a second embodiment of the present invention. The bus controller 300 is a bus arbiter 301.
A route selection circuit 302, a direction control circuit 303, and a route notification circuit 304. The path selection circuit 302 determines a data transfer path in accordance with the transfer destination selection signal 360 input from the peripheral devices 310, 320, 330, and outputs the result to the direction control circuit 303. Further, the route selection circuit 302 outputs information of peripheral devices existing on the determined transfer route to the route notification circuit 304. The route notification circuit 304 outputs a route corresponding signal 380 to each of the peripheral devices 310, 320 and 330 according to the information input from the route selection circuit 302.

Peripheral devices 310, 320 and 330 respectively include direction switching circuits 311, 321, 331 and clock control circuits 312, 322, 332. The clock control circuits 312, 322, 332 are provided in the route notification circuit 304.
The supply of the clock to its own peripheral device is controlled according to the route corresponding signal 380 input from the.

The path-corresponding signal 380 is set in binary as follows, for example.

0: Exists on the data transfer path 1: For the method of determining the data transfer direction that does not exist on the data transfer path, the same table as in FIG. 2 in the first embodiment is applied correspondingly.

FIG. 4 shows an example of a table for determining the information of the peripheral device existing on the data transfer path.

When the data transfer source is the peripheral device 310 and the data transfer destination is the peripheral device 320, since it is counterclockwise according to the table of FIG. 2, only the peripheral device 310 and the peripheral device 320 which are themselves are included. is there.

When the data transfer source is the peripheral device 310 and the data transfer destination is the peripheral device 330, since it is clockwise according to the table of FIG. A peripheral bus controller 300 is included.

When the data transfer source is the peripheral device 320 and the data transfer destination is the peripheral device 310, since it is clockwise according to the table of FIG. 2, only the peripheral device 320 and the peripheral device 310 which are themselves are included. .

In the case where the data transfer source is the peripheral device 320 and the data transfer destination is the peripheral device 330, since it is counterclockwise according to the table of FIG. 2, only the peripheral device 320 and the peripheral device 330 which are themselves are included. is there.

In the case where the data transfer source is the peripheral device 330 and the data transfer destination is the peripheral device 310, since it is counterclockwise according to the table of FIG. 2, the peripheral device 330 and the peripheral device 310 which are themselves are included, and A counterclockwise bus controller 300 is included.

In the case where the data transfer source is the peripheral device 330 and the data transfer destination is the peripheral device 320, the peripheral device 330 and the peripheral device 320, which are themselves, are only included because they are clockwise according to the table of FIG. .

Regarding the data transfer operation, the peripheral device 330
Data transfer from the device to the peripheral device 320 will be described as an example.

[Step 1] Since it is the same as that of the first embodiment, its explanation is omitted.

[Step 2] A bus for which the right to use the bus is requested by the bus request signal 371 from the peripheral device 330.
The arbiter 301 confirms that the bus control device 300 and other peripheral devices are not using the bus, and the peripheral device 33
The direction control circuit 303 is notified that 0 is given the right to use the bus. At the same time, the route selection circuit 302, which receives the transfer destination selection signal 360 from the peripheral device 330, changes the peripheral device 3 to
Determine the data transfer path from 30 to the peripheral device 320,
Notify the direction control circuit 303.

At the same time, the path selection circuit 302 transmits information about the peripheral devices existing on the data transfer path from the peripheral device 330 to the peripheral device 320 (in this example, the peripheral device 320
And peripheral device 330) to the route notification circuit 304.

[Step 3] Bus Arbiter 301
Is the peripheral device 330 that is the output source of the bus request signal 371.
A bus permission signal 372 is output to the CPU to give the right to use the bus. At the same time, the direction control circuit 303 determines the data transfer direction based on the transfer route determined by the route selection circuit 302 (clockwise in this example), and the direction control signal 35
0 is generated and output to the direction switching circuits 311, 321, 331 of the peripheral devices 310, 320, 330 to notify the data transfer direction to be switched clockwise. At the same time, the route notification circuit 304 follows the clock control circuits 312, 32 of the respective peripheral devices according to the information of the peripheral devices existing on the data transfer route input from the route selection circuit 302.
The route corresponding signal 380 is output to 2, 332.

[Step 4] Each clock control circuit 31
2, 322 and 332 are the respective route corresponding signals 380.
According to the control, the clock supply to the peripheral device is controlled.
That is, the clock control circuits 322 and 332 existing on the data transfer path maintain the clock supply to the peripheral devices 320 and 330, but the clock control circuit 312 not existing on the data transfer path supplies the clock to the peripheral device 310. Stop the supply. At the same time, the direction switching circuits 321 and 331 existing on the data transfer path switch the data transfer direction clockwise according to the direction control signal 350. Peripheral device 3 permitted to use the bus by the bus permission signal 372
30 starts data transfer to the peripheral device 320. In this case, data transfer is performed using the clockwise bus 342.

[Step 5] The peripheral device 320 receives the data from the peripheral device 330, and then the bus arbiter 3
The reception completion signal 373 is output to 01.

By the above procedure, the peripheral device 330
Data transfer from the peripheral device 320 to the peripheral device 320
→ bus 342 → performed by the clockwise route of the peripheral device 320.

According to the present embodiment, with the above configuration, it is possible to reduce power consumption by stopping the clock supply to the peripheral device not existing on the data transfer path.

(Third Embodiment) FIG. 5 is a block diagram showing a configuration of a data transfer device according to a third embodiment of the present invention. The bus controller 400 includes a bus arbiter 401.
A path selection circuit 402, a direction control circuit 403, and a transfer time determination circuit 404. Route selection circuit 402
Determines the data transfer direction according to the transfer destination selection signal 460 input from the peripheral devices 410, 420, 430, and outputs the result to the direction control circuit 403. Also,
The route selection circuit 402 outputs information on peripheral devices existing on the determined transfer route to the transfer time determination circuit 404.
The transfer time determination circuit 404 determines the time required for data transfer (the number of transfer cycles) according to the information input from the path selection circuit 402, and outputs it to the bus arbiter 401. The bus arbiter 401 has a transfer time determination circuit 404.
The bus usage right is given to the peripheral device that has requested the bus usage right for the number of transfer cycles input from the.

As for the method of determining the data transfer direction, the same table as in FIG. 2 in the first embodiment is applied correspondingly.

FIG. 6 shows an example of a table for determining the time (cycle number) required for data transfer.

When the data transfer source is the peripheral device 410 and the data transfer destination is the peripheral device 420, they are adjacent to each other.
It is a cycle.

When the data transfer source is the peripheral device 410 and the data transfer destination is the peripheral device 430, it is clockwise according to FIG. 2, and the bus control device 400 is interposed therebetween.
2 cycles.

If the data transfer source is the peripheral device 420 and the data transfer destination is the peripheral device 410, they are adjacent to each other.
It is a cycle.

When the data transfer source is the peripheral device 420 and the data transfer destination is the peripheral device 430, they are adjacent to each other.
It is a cycle.

When the data transfer source is the peripheral device 430 and the data transfer destination is the peripheral device 410, it is counterclockwise according to FIG. 2, and since the bus control device 400 is interposed therebetween, it is two cycles.

If the data transfer source is the peripheral device 430 and the data transfer destination is the peripheral device 420, they are adjacent and therefore 1
It is a cycle.

For the data transfer operation, the peripheral device 430
Data transfer from the device to the peripheral device 420 will be described as an example.

[Step 1] Since it is the same as that of the first embodiment, its explanation is omitted.

[Step 2] The bus for which the right to use the bus is requested by the bus request signal 471 from the peripheral device 430.
The arbiter 401 confirms that the bus control device 400 and other peripheral devices are not using the bus, and the peripheral device 43
The direction control circuit 403 is notified that 0 is given the right to use the bus. At the same time, when the transfer destination selection signal 460 is input from the peripheral device 430, the path selection circuit 402 is
Determine the data transfer path from 30 to the peripheral device 420,
Notify the direction control circuit 403.

At the same time, the path selection circuit 402 provides information on the peripheral device of the data transfer source and the peripheral device of the data transfer destination (in this example, the peripheral device 430 is the data transfer source and the peripheral device 420 is the data transfer destination). Is output to the transfer time determination circuit 404.

[Step 3] Bus Arbiter 401
Is the peripheral device 430 that is the output source of the bus request signal 471.
A bus permission signal 472 is output to the CPU to give the right to use the bus. At the same time, the direction control circuit 403 determines the data transfer direction based on the transfer route determined by the route selection circuit 402 (clockwise in this example), and the direction control signal 45
0 is generated and output to the direction switching circuits 411, 421, 431 of each of the peripheral devices 410, 420, 430 to notify that the data transfer direction should be switched clockwise. At the same time, the transfer time determination circuit 404 determines the time (the number of cycles) required for data transfer according to the information of the peripheral device of the data transfer source and the peripheral device of the data transfer destination input from the route selection circuit 402, Output to the bus arbiter 401.

[Step 4] Each direction switching circuit 411,
421 and 431 switch the data transfer direction clockwise according to the direction control signal 450. At the same time, the peripheral device 430 permitted to use the bus by the bus permission signal 472.
Starts data transfer to the peripheral device 420. The bus arbiter 401 restores the right to use the bus to the peripheral device 430 (disables the use of the bus) after the number of cycles input from the transfer time determination circuit 404 has elapsed.

By the above procedure, the peripheral device 430
Data transfer from the peripheral device 420 to the peripheral device 420
→ Bus 442 → Circular route of peripheral device 420.

According to the present embodiment, with the above configuration, the bus arbiter 401 can arbitrate the bus without receiving the data transfer completion notification from the peripheral device 420, so that the bus usage efficiency is improved. To do.

(Fourth Embodiment) FIG. 7 is a block diagram showing the structure of a data transfer apparatus according to a fourth embodiment of the present invention. The bus controller 500 is a bus arbiter 501.
A path selection circuit 502, a direction control circuit 503, and a path storage circuit 504. The path selection circuit 502 determines the data transfer direction according to the transfer destination selection signal 560 input from the peripheral devices 510, 520, 530, and outputs the result to the direction control circuit 503. The route selection circuit 502 also sends the determined route information to the bus arbiter 50.
Output to 1.

The bus arbiter 501 is the path selection circuit 5
02, the transfer route input from 02 is compared with the route being executed stored in the route storage circuit 504, and if it does not overlap with any stored route information, it is stored in the route storage circuit 504 as a new transfer route. Then, the bus use right is given to the peripheral device related to the bus request.

FIG. 8 shows an example of a table for determining the information of the buses existing on the data transfer path.

Data transfer from the peripheral device 530 to the peripheral device 520 when the buses 541 and 543 are already used by another peripheral device will be described as an example.

[Step 1] The description is omitted because it is the same as that of the first embodiment.

[Step 2] The path selection circuit 502 which receives the transfer destination selection signal 560 from the peripheral device 530,
The data transfer path from the peripheral device 530 to the peripheral device 520 is determined, and the direction control circuit 503 is notified. At the same time, the route selection circuit 502 moves the peripheral devices 530 to 52
Information of the bus existing on the data transfer path to 0 (bus 542 in this example) is output to the bus arbiter 501.

[Step 3] Bus Arbiter 501
Is a bus in use that has already stored the bus input from the route selection circuit 502 in the route storage circuit 504 (in this example, the buses 541 and 543 are stored as buses already in use). Compare and check for duplicates. The bus arbiter 501 stores the bus 542 in the route storage circuit 504 as a newly used bus.

[Step 4] The bus arbiter 501, which has confirmed that data can be transferred from the peripheral device 530 to the peripheral device 520, outputs the bus permission signal 572 to the peripheral device 530 which is the output source of the bus request signal 571. Then
Give the right to use the bus. At the same time, it notifies the direction control circuit 503 that data should be transferred from the peripheral device 530 to the peripheral device 520. The direction control circuit 503 notifies the direction switching circuits 521 and 531 of the peripheral devices 520 and 530 to switch the direction of the bus 542 clockwise by the direction control signal 550.

[Step 5] Direction switching circuits 521, 5
31 switches the transfer direction of the bus 542 clockwise according to the direction control signal 550. At the same time, the peripheral device 530 permitted to use the bus by the bus permission signal 572.
Starts data transfer to the peripheral device 520.

[Step 6] After the completion of data reception from the peripheral device 530, the peripheral device 520 receives the bus arbiter 5
The reception completion signal 573 is output to 01.

By the above procedure, the peripheral device 530
Data transfer from the peripheral device 520 to the peripheral device 520
→ Bus 542 → Peripheral device 520 is performed in a clockwise route.

According to the present embodiment, with the above configuration, it is possible to simultaneously perform a plurality of data transfers in which the data transfer paths do not overlap with each other, and the bus usage efficiency is improved.

[0087]

As described above, according to the present invention, the data transfer path is determined according to the positional relationship between the peripheral device of the data transfer source and the peripheral device of the data transfer destination, and the data transfer direction is switched, thereby The transfer throughput can be improved.

Further, by stopping the clock supply to the peripheral devices not existing on the data transfer path,
Power consumption can be reduced.

Further, in the configuration in which the data transfer is completed without waiting for the reception completion signal from the data transfer destination,
The bus usage efficiency can be improved.

Further, in a configuration in which a plurality of data transfers whose data transfer routes do not overlap are permitted at the same time,
The bus usage efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer device according to a first embodiment of the present invention.

FIG. 2 is an example of a table for determining a data transfer direction in the data transfer device according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a data transfer device according to a second embodiment of the present invention.

FIG. 4 is an example of a table for determining a peripheral device on a data transfer path in the data transfer device according to the second embodiment.

FIG. 5 is a block diagram showing a configuration of a data transfer device according to a third embodiment of the present invention.

FIG. 6 is an example of a table for determining a data transfer time in the data transfer device according to the third embodiment.

FIG. 7 is a block diagram showing a configuration of a data transfer device according to a fourth embodiment of the present invention.

FIG. 8 shows an example of a table for determining a bus on a data transfer path in the data transfer device according to the fourth embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional data transfer device.

[Explanation of symbols]

200,300,400,500 Bus controller 201,301,401,501 Bus Arbiter 202, 302, 402, 502 Route selection circuit 203, 303, 403, 503 Direction control circuit 210, 220, 230 peripheral devices 211,221,231 Direction switching circuit 304 Route notification circuit 310, 320, 330 peripheral devices 311, 321, 331 Direction switching circuit 312, 322, 332 Clock control circuit 404 Transfer time determination circuit 410, 420, 430 peripheral devices 411, 421, 431 Direction switching circuit 504 route memory circuit Peripheral devices 510, 520, 530 511,521,531 direction switching circuit

Claims (4)

[Claims] 1. A data transfer device in which a plurality of peripheral devices are daisy-chained to a bus control device by a bidirectional bus, wherein the bus control device comprises a bus arbiter for arbitrating bus usage rights, Route selecting means for determining a data transfer route according to the positional relationship between the peripheral device of the data transfer source and the peripheral device of the data transfer destination; and direction control means for controlling the data transfer direction based on the determination result of the route selecting means. The data transfer device, wherein each of the peripheral devices includes a direction switching unit that switches a data transfer direction of a bus connected to the peripheral device according to a direction control signal from the direction control unit. 2. The data transfer device according to claim 1, wherein the bus control device further indicates whether or not it is a peripheral device corresponding to the transfer route determined based on the determination result of the route selection means. A route notification unit that outputs a route corresponding signal to each of the peripheral devices is provided, and each of the peripheral devices further includes a clock control unit that controls clock supply to its own peripheral device according to the route corresponding signal from the route notification unit. A data transfer device comprising: 3. The data transfer device according to claim 1, wherein the bus control device further comprises transfer time determining means for determining a time required for data transfer based on a determination result of the path selecting means. The data transfer device, wherein the bus arbiter permits the peripheral device of the data transfer source to use the bus only for the time determined by the transfer time determination means. 4. The data transfer device according to claim 1, wherein the bus control device further includes a route storage unit that stores a route used for data transfer being executed, and the bus arbiter includes: The route of the request from the route selecting unit is compared with the route being executed stored in the route storing unit, and when the route does not overlap, the route of the request is stored in the route storing unit and then the data transfer is performed. A data transfer device characterized by permitting the original peripheral device to use the bus.