JP2004031650A - Leadless package and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a leadless package which can prevent the increase in package thickness and the deterioration in productivity and manufacturing cost while improving heat radiation effect and ensuring proper operational characteristics in a semiconductor chip, and to provide a semiconductor device formed by laminating the same. <P>SOLUTION: The leadless package 22 housing a semiconductor chip 23 comprises a die pad 29 for holding the semiconductor chip 23, and a heat-transfer terminal 28 for communicating with the die pad 29. The semiconductor device 21 is composed of a plurality of leadless packages 22 which are connected with each other via their I/O leads 24 and heat-transfer terminals 28. Heat generation from each semiconductor chip 23 in each layer is transferred in the laminating direction via each die pad 29 and heat-transfer terminal 28. The die pad 29 in the uppermost-layer is used as a heat sink, and the heat-transfer terminal 28 in the lowermost-layer is connected to a heat dissipating land 14 of a printed wiring board 8. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a leadless package and a semiconductor device formed by stacking the same in a plurality of stages, and more particularly, to a leadless package and a semiconductor device that enhance heat dissipation of a semiconductor chip to ensure proper operation characteristics. .
[0002]
[Prior art]
2. Description of the Related Art As electronic devices such as mobile communication devices such as mobile phones and PDAs and notebook personal computers have become smaller and more sophisticated, it is essential to implement high-density mounting of electronic components constituting these devices. Conventionally, high-density mounting of electronic components has been supported by fine pitch of component terminals due to miniaturization of electronic components and miniaturization of wiring patterns of mounting boards.In recent years, semiconductor bare chips and semiconductor package components have been used. Various three-dimensional module structures that are stacked three-dimensionally and have improved mounting efficiency have been proposed.
[0003]
Above all, for example, a structure as disclosed in Japanese Patent Application Laid-Open No. 2001-177005 can use a material / process which has been most commonly used as a semiconductor package technology, and thus realizes a three-dimensional laminated module structure at low cost. It is drawing attention as a possible means.
A conventional semiconductor device having a three-dimensional stacked module structure will be described with reference to FIGS.
[0004]
FIG. 20 shows a conventional semiconductor device 101. The conventional semiconductor device 101 has a structure in which leadless packages 102 shown in FIGS. 21 and 22 are stacked in a plurality of stages.
[0005]
The leadless package 102 includes a semiconductor chip 103, a plurality of leads 104 disposed adjacent to the side of the semiconductor chip 103, bonding wires 105 connecting the semiconductor chip 103 and the plurality of leads 104, and a semiconductor chip 103. And a sealing resin 106 for sealing the bonding wire 105.
[0006]
The respective leadless packages 102 are electrically connected to each other via a conductive bonding material 107 formed on the lead 104, and the lowermost leadless package 102 is connected to the printed wiring board 108 via the bonding material 107. It is connected to the land 109.
[0007]
As shown in FIG. 21, the lead 104 of the leadless package 102 has an upper surface portion 104a, a step portion 104b, and a lower surface portion 104c. The step portion 104b is a portion formed one step lower than the upper surface portion 104a, and is a region where the bonding wire 105 is bonded. The thickness of the leadless package 102 is equal to the thickness of the lead 104, and the top surface 104a and the bottom surface 104c of the lead 104 and the back surface of the semiconductor chip 103 are exposed to the outside as shown in FIGS. ing.
[0008]
23A and 23B show a lead frame 110 for constituting the leadless package 102 shown in FIG. The lead frame 110 includes a lead portion 104 corresponding to a lead of the leadless package 102, and a frame portion 111 supporting the lead portion 104. When the leadless package 102 is manufactured, the lead portion 104 is separated from the frame portion 111.
[0009]
[Problems to be solved by the invention]
By the way, in recent years, the performance of semiconductor devices has been improved in order to respond to higher functions of electronic devices and high-speed signal processing, but the heat generation of the semiconductor devices has been significantly increased. On the other hand, as devices have become thinner and smaller, there has been a problem of a rise in air temperature inside the device and a local rise in temperature of components. In general, if the component temperature exceeds the allowable value, malfunctions such as malfunctions and device destruction are caused, which greatly affects the function and reliability of the product. For this reason, in recent years, heat dissipation measures for component parts have been regarded as important in high-density mounting technology.
[0010]
However, in the conventional semiconductor device 101 having the above-described configuration, a semiconductor chip that consumes a large amount of power and generates a large amount of heat is packaged, particularly, since heat dissipation from the inner package is not sufficiently ensured. In this case, there is a high possibility that the temperature of the semiconductor chip becomes high and the characteristics are affected. That is, with the conventional leadless package 102 having the structure shown in FIG. 21 and the configuration of the semiconductor device 101 in which the package is stacked, it is structurally difficult to ensure efficient heat dissipation from the semiconductor chip 103.
[0011]
When a plurality of semiconductor chips having different functions are stacked, one of the stacked semiconductor chips that generates a large amount of heat is disposed in the uppermost layer having relatively high heat radiation efficiency, or is disposed in the lowermost layer for printed wiring. Although there is a method of adopting a structure in which heat is dissipated to the board side, it is a great limitation in design, and when there are three or more semiconductor chips generating a large amount of heat, application to an inner layer package is inevitable. Problems due to excessive heat generation become apparent.
[0012]
On the other hand, for example, Japanese Unexamined Patent Publication No. Hei 8-236694 discloses a stacked semiconductor device in which the heat dissipation efficiency of the semiconductor chips of each layer is increased by attaching heat sinks to the back surfaces of the semiconductor chips stacked in multiple stages. I have.
[0013]
However, in this configuration, since a heatsink is interposed in each layer, the height of the entire stacked module is increased, and the significance of using a leadless package whose purpose is to reduce the thickness of the package is reduced. . Further, there is a problem that the productivity of the semiconductor device is impaired due to the installation of the heat radiating plate, and the manufacturing cost is increased.
[0014]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has a leadless package capable of avoiding an increase in package thickness, a decrease in productivity and a manufacturing cost, while enhancing a heat dissipation effect of a semiconductor chip and securing appropriate operation characteristics. It is an object to provide a stacked semiconductor device.
[0015]
[Means for Solving the Problems]
In order to solve the above problems, a leadless package according to the present invention includes a semiconductor chip, a plurality of leads arranged on a side of the semiconductor chip, bonding wires connecting the semiconductor chip to the plurality of leads, and a semiconductor chip. A leadless package having a structure in which a top surface and a bottom surface of the lead are exposed to the outside, the die pad portion supporting the semiconductor chip within the thickness range of the lead, and And a heat transfer terminal connected to the die pad portion and having the same thickness as the lead.
[0016]
In the present invention, when the semiconductor device of the present invention is configured by stacking the leadless package by arranging heat transfer terminals for heat radiation connected to the die pad portion together with the signal input / output leads. Even so, a heat radiation path in the stacking direction can be secured. As a result, an operation failure due to heat generated from the semiconductor chip of the leadless package laminated on the inner layer is avoided.
[0017]
The die pad portion and the heat transfer terminal can be integrally formed as a part of a lead frame for forming a lead. For this reason, since it is not necessary to attach a heat radiation member in a subsequent process, it is possible to avoid deterioration in productivity and manufacturing cost.
[0018]
In this case, since the die pad portion and the heat transfer terminal are incorporated as a part of the package together with the leads when the semiconductor chip is packaged, an increase in the package thickness is prevented.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
1 to 9 show a first embodiment of the present invention. 1 is a side sectional view of the semiconductor device 1 according to the present embodiment, FIG. 2 is a plan view of FIG. 1, FIG. 3 is a sectional view taken along the line [3]-[3] in FIG. 2, and FIG. 1 is a rear view of FIG. 5 is a side sectional view of the leadless package 2 constituting the semiconductor device 1, FIG. 6 is a plan view of a lead frame for constituting the leadless package 2, and FIGS. It is a process sectional view explaining a method.
[0021]
The semiconductor device 1 according to the present embodiment is configured by vertically stacking a plurality of (four in the figure) leadless packages 2 of the same configuration each containing a semiconductor chip 3 therein. Hereinafter, details of each unit will be described.
[0022]
As the semiconductor chip 3, for example, a semiconductor memory such as a DRAM or a system LSI in which a logic circuit is mixed therein, or a MPU, a driver circuit for driving various hardware systems, a power supply circuit, a high-frequency signal processing circuit, or the like is incorporated. Are applied.
[0023]
Therefore, the semiconductor device 1 is configured as a three-dimensional module that performs a specific function by being configured of the same type of semiconductor chip, such as increasing the memory capacity by stacking a plurality of semiconductor memories, or It can be configured as a three-dimensional module that performs a systematic function by being configured by different types of semiconductor chips.
[0024]
The leadless package 2 of each stage constituting the semiconductor device 1 includes a semiconductor chip 3, a plurality of signal input / output leads 4 disposed adjacent to the side of the semiconductor chip 3, and a semiconductor chip 3 and a lead 4. , A sealing resin 6 for sealing the semiconductor chip 3 and the bonding wire 5, a die pad portion 11 for supporting the semiconductor chip 3, and a heat transfer terminal 10 arranged at four corners of the package. And a horizontal heat transfer section 12 connecting between the die pad section 11 and the heat transfer terminal 10.
[0025]
As shown in FIG. 5, the semiconductor chip 3 is bonded and fixed to the die pad portion 11 in a face-up manner. A plurality of bonding pads (not shown) are formed at a predetermined pitch on the surface (active surface) of the semiconductor chip 3, and are connected to the leads 4 via bonding wires 5 such as gold wires.
[0026]
As shown in FIG. 5, the lead 4 of the leadless package 2 has an upper surface portion 4a, a step portion 4b, and a lower surface portion 4c. The step portion 4b is a portion where the lead 4 is lowered one step by coining or half etching, and is a region where the bonding wire 5 is bonded. The thickness of the leadless package 2 is equal to the thickness of the lead 4 (for example, 0.2 mm to 0.25 mm), and the upper surface 4a and the lower surface 4c of the lead 4 are exposed to the outside. The thickness (height) of the step portion 4b is, for example, 0.1 mm to 0.125 mm.
[0027]
The die pad portion 11 supports the semiconductor chip 3 within the range of the thickness (height) of the lead 4. In other words, the sizes of the three are selected so that the total of the thickness of the die pad portion 11, the thickness of the semiconductor chip 3, and the loop height of the bonding wire 5 falls within the thickness of the lead 4. Have been.
[0028]
The back surface of the die pad portion 11 belongs to the same plane as the lower surface portion 4c of the lead 4, and the periphery except the back surface is molded with the sealing resin 6 together with the bonding wire 5, thereby forming a QFN (Quad Flat Non-leaded package). ) Type leadless package 2 is constituted.
[0029]
The heat transfer terminals 10 have a function of transmitting heat generated from the semiconductor chip 3 to the outside of the semiconductor chip 3, and are arranged at four corners of the leadless package 2 in the present embodiment. The heat transfer terminal 10 has the same thickness (height) as the lead 4, and is in communication with the die pad portion 11 via the horizontal heat transfer portion 12. Note that the horizontal heat transfer section 12 is formed to have the same thickness as the die pad section 11.
[0030]
The die pad portion 11, the horizontal heat transfer portion 12, and the heat transfer terminal 10 are each formed of the same material as the lead 4. Both the upper and lower surfaces of the lead 4 and the heat transfer terminal 10 and the lower surfaces of the die pad portion 11 and the horizontal heat transfer portion 12, respectively, are exposed to the outside to constitute the outer surface of the leadless package 2 (FIG. 2, FIG. 4). A plating film 13 is formed on these metal surfaces.
[0031]
As shown in FIGS. 1 and 3, the respective leadless packages 2 are connected to each other via a conductive bonding material 7 provided on the leads 4 and the heat transfer terminals 10. The lead 4 is connected to an input / output land 9 of a printed wiring board 8 via a bonding material 7. Further, the heat transfer terminals 10 of the lowermost leadless package 2 are connected to the heat release lands 14 of the printed wiring board 8 via the bonding material 7. As a result, the leadless package 2 of each layer is electrically connected between the layers by the leads 4 and forms a heat dissipation path between the layers via the respective heat transfer terminals 10.
[0032]
The die pad portion 11 of the leadless package 2 located on the uppermost layer has a function as a heat radiating plate for releasing heat from the leadless package 2 of each layer to the outside air or to a radiator attached by a user. Have.
[0033]
On the other hand, FIG. 6 shows a configuration of a lead frame 15 for configuring the leadless package 2 of the present embodiment. In this embodiment, the lead frame 15 is made of a general metal material for forming a lead frame, such as an iron-based alloy or a copper-based alloy. In addition, not only a metal material but also an organic or ceramic base material may be used.
[0034]
As shown in FIG. 6, the lead frame 15 is formed with a plurality of leads (parts) 4 to which one ends of bonding wires are joined and also serves as external terminals at equal intervals along the periphery of the frame part 16. At the tips of the leads 4 are formed step portions 4b lower than the lead upper surface portions 4a by half etching or coining.
[0035]
The “suspend” or “stay” that connects the die pad unit 11 and the frame unit 15 constitutes the above-described horizontal heat transfer unit 12. In the present embodiment, the die pad portion 11 and the horizontal heat transfer portion 12 are formed to have the same thickness as the step portion 4b of the lead 4. On the other hand, the heat transfer terminal 10 is formed to have the same thickness as the lead 4.
[0036]
7 to 9 are process cross-sectional views illustrating a manufacturing process of the leadless package 2 of the present embodiment. Hereinafter, a method of manufacturing the leadless package 2 will be described.
[0037]
An adhesive tape 17 is attached to the lower surface of the lead frame 15 shown in FIG. 6, and the semiconductor chip 3 is bonded to the die pad portion 11 (FIGS. 7A, 7B, and 7C). Next, each electrode pad of the semiconductor chip 3 is connected to the step 4b of the lead 4 of the lead frame 15 by a bonding wire 5 (FIG. 7D).
[0038]
Next, the semiconductor chip 3 and the bonding wires 5 are sealed with a thermosetting sealing resin 6 such as epoxy (FIG. 8E). The sealing resin 6 is formed to have a thickness equal to the thickness of the lead 4, so that the upper surface 4a of the lead 4 and the upper surface of the heat transfer terminal 10 are exposed to the outside (FIG. 4).
[0039]
Subsequently, the adhesive tape 17 is peeled off from the lead frame 15, and plating films 13 are formed on both surfaces of the lead frame 15, respectively (FIGS. 8F and 8G). As the plating film 13, for example, solder plating is applied. Thereafter, the lead frame 15 is cut according to the cut line C indicated by a dashed line in FIG. 6, and the frame portion 16 is removed (FIG. 8H).
[0040]
As described above, leadless package 2 of the present embodiment is substantially manufactured. Here, if necessary, an electrical measurement / screening test is performed to determine the quality.
[0041]
Next, a bonding material 7 for lamination is applied to the upper surface portion 4a of the lead 4 of the leadless package 2 and the upper surface of the heat transfer terminal (FIGS. 9I and 3). In the present embodiment, a solder paste is used as the bonding material 7 and is applied by a screen printing method. Then, the semiconductor device 1 shown in FIG. 1 is obtained by stacking the manufactured leadless package 2 via the lead 4 and the heat transfer terminal 10 in a state where the package is turned upside down (FIG. 9J, FIGS. (Fig. 4).
[0042]
The semiconductor device 1 described above realizes a stacked package by assembling and completing a QFN type semiconductor package and then stacking the individual semiconductor packages individually. Such a stacked semiconductor device can increase the capacity of a memory by being applied to a three-dimensional module of a semiconductor memory typified by a DRAM, for example. Further, a small system module can be formed by applying and stacking different types of chips such as SRAM, flash memory, and logic IC.
[0043]
As described above, according to the present embodiment, heat generated from each semiconductor chip 3 of leadless package 2 stacked in multiple stages is transmitted to heat transfer terminal 10 via die pad portion 11 and horizontal heat transfer portion 12. From there, the heat is transmitted to the die pad portion 11 of the leadless package 2 of the uppermost layer via the heat transfer terminals 10 of each layer, and is radiated. Alternatively, the heat is transmitted to the heat radiation lands 14 of the printed wiring board 8 through the heat transfer terminals 10.
[0044]
As described above, since the heat radiating path of the semiconductor chip 3 is formed in the plane of the leadless package 2 and in the laminating direction thereof, the heat radiating efficiency of the semiconductor device 1 is improved, and the semiconductor chip 3 Operation failure such as characteristic failure and malfunction.
[0045]
In particular, heat generated from the leadless package 2 located in the inner layer passes through the die pad portion (also serving as a heat sink) 11 of the leadless package 2 of the uppermost layer and the heat transfer terminal 10 of the leadless package 2 of the lowermost layer. Since the heat can be radiated to the outside, the reliability of the stacked semiconductor device having a leadless package in which the semiconductor chip 3 generating a large amount of heat is mounted in the inner layer can be improved.
[0046]
Further, according to the present embodiment, the die pad portion 11, the horizontal heat transfer portion 12, and the heat transfer terminal 10 forming the heat dissipation path from the semiconductor chip 3 are integrated as a part of the lead frame 15 forming the lead 4. The heat dissipation path can be built in when the leadless package 2 is manufactured since the leadless package 2 is manufactured, thereby avoiding a decrease in productivity and an increase in manufacturing cost. Further, the thinness of the leadless package 2 can be maintained.
[0047]
(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. Here, FIG. 10 is a side sectional view of the semiconductor device 21 according to the present embodiment, FIG. 11 is a plan view of FIG. 10, and FIG. 12 is a rear view of FIG.
[0048]
The semiconductor device 21 of the present embodiment is configured by vertically stacking a plurality of (four in the figure) leadless packages 22 having the same configuration and incorporating a semiconductor chip 23.
[0049]
The leadless package 22 of each stage constituting the semiconductor device 21 connects the semiconductor chip 23, a plurality of signal input / output leads 24 arranged on the sides of the semiconductor chip 23, and the semiconductor chip 23 and the leads 24. Bonding wire 25, a sealing resin 26 for sealing the semiconductor chip 23 and the bonding wire 25, a die pad portion 29 for supporting the semiconductor chip 23, and a conductive wire having a thickness equal to that of the lead 24 which is in contact with the die pad portion 29. And a heating terminal 28.
[0050]
The die pad portion 29 supports the semiconductor chip 23 within the range of the thickness (height) of the lead 24. In other words, the sizes of the three are selected so that the total of the thickness of the die pad portion 29, the thickness of the semiconductor chip 23, and the loop height of the bonding wire 25 falls within the thickness of the lead 24. Have been.
[0051]
The back surface of the die pad portion 29 belongs to the same plane as the lower surface portion of the lead 24 (the upper surface in FIG. 10), and the periphery except the back surface is molded with the sealing resin 26 together with the bonding wires 25. , QFN type leadless package 22.
[0052]
The heat transfer terminal 28 has a function of transmitting heat generated from the semiconductor chip 23 to the outside of the semiconductor chip 23, and is disposed between the semiconductor chip 23 and the lead 24 in the present embodiment. The heat transfer terminals 28 have the same thickness (height) as the leads 24 and are integrally formed at equal intervals along the periphery of the die pad portion 29. The bonding wires 25 are stretched between the arrangement pitches of the heat transfer terminals 28 so that the heat transfer terminals 28 do not come into contact with the bonding wires 25.
[0053]
Note that the arrangement of the heat transfer terminals 28 does not necessarily have to be as shown in the figure. For example, according to the connection density of the bonding wires 25, the arrangement may be made only at the sparse portions.
[0054]
These heat transfer terminals 28 and die pad portions 29 are each formed of the same material as the leads 24. In particular, although not shown, it is formed integrally with one lead frame. The upper and lower surfaces of the lead 24, the tip of the heat transfer terminal 28, and the back surface of the die pad portion 29 are exposed to the outside to constitute the outer surface of the leadless package 22 (FIGS. 11 and 12). A plating film 30 is formed on these metal surfaces.
[0055]
As shown in FIG. 10, the respective leadless packages 22 are connected to each other via a conductive bonding material 27 provided on the lead 24 and the heat transfer terminal 28, and the leads 24 and the lead 24 of the lowermost leadless package 22 are connected to each other. The heat transfer terminals 28 are connected to the input / output lands 9 and the heat radiating lands 14 of the printed wiring board 8 via bonding materials 27, respectively. Thus, in the leadless package 22 of each layer, electrical connection between the layers is made by each lead 24, and a heat dissipation path between the layers is formed by the heat transfer terminal 28 and the die pad portion 29 of each layer.
[0056]
The die pad portion 29 of the leadless package 22 located on the uppermost layer has a function as a heat radiating plate for releasing heat from the leadless package 22 of each layer to the outside air or to a radiator attached by a user. Have.
[0057]
As described above, according to the present embodiment, the same effects as those of the above-described first embodiment can be obtained. In particular, according to the present embodiment, the heat transfer terminals 28 can be formed not only at the four corners (corner portions) of the leadless package but also at arbitrary positions inside the package, so that the heat radiation paths can be diversified. Thus, the degree of freedom in designing the heat radiation path is increased.
[0058]
(Third embodiment)
FIG. 13 to FIG. 15 show a third embodiment of the present invention. 13 is a side sectional view of the leadless package 32 according to the present embodiment, FIG. 14 is a rear view of FIG. 13, and FIG. 15 is a plan view of FIG.
[0059]
The leadless package 32 of the present embodiment has a structure obtained by combining the above-described first and second embodiments.
[0060]
In other words, the leadless package 32 of the present embodiment includes a semiconductor chip 33, a plurality of signal input / output leads 34 disposed adjacent to the side of the semiconductor chip 33, and the semiconductor chip 33 and the leads 34. It has a bonding wire 35 for connection, a sealing resin 36 for sealing the semiconductor chip 33 and the bonding wire 35, and a die pad portion 39 for supporting the semiconductor chip 33. A heat terminal 38A, a second heat transfer terminal 38B disposed between the semiconductor chip 33 and the lead 34, and a horizontal heat transfer portion 38C connecting the die pad portion 39 and the first heat transfer terminal 38A are formed. Have.
[0061]
The die pad portion 39 supports the semiconductor chip 33 within the range of the thickness (height) of the lead 34. In other words, the three sizes are selected so that the sum of the thickness of the die pad portion 39, the thickness of the semiconductor chip 33, and the loop height of the bonding wire 35 falls within the thickness of the lead 34. Have been.
[0062]
The back surface of the die pad portion 39 belongs to the same plane as the lower surface portion of the lead 34, and the periphery excluding the back surface is molded with the sealing resin 36 together with the bonding wire 35, so that the QFN type leadless package 32 is formed. Be composed.
[0063]
The first heat transfer terminal 38 </ b> A and the second heat transfer terminal 38 </ b> B have a function of transmitting heat generated from the semiconductor chip 33 to the outside of the semiconductor chip 33. The first and second heat transfer terminals 38A and 38B have the same thickness (height) as the lead 34, and the first heat transfer terminal 38A is connected to the die pad portion 39 by a horizontal heat transfer portion 38C. You have contacted via Note that the horizontal heat transfer section 38C is formed to have the same thickness as the die pad section 39. The bonding wires 35 are stretched between the arrangement pitches of the second heat transfer terminals 38B so that the heat transfer terminals 38B do not come into contact with the bonding wires 35.
[0064]
The die pad portion 39, the first and second heat transfer terminals 38A and 38B, and the horizontal heat transfer portion 38C are formed of the same material as the lead 34, respectively. In particular, although not shown, it is formed integrally with one lead frame. Both the upper and lower surfaces of the lead 34 and the first heat transfer terminal 38A, the tip of the second heat transfer terminal 38B, and the back surfaces of the die pad portion 39 and the horizontal heat transfer portion 38C are exposed to the outside. The outer surface of the leadless package 32 is configured (FIGS. 14 and 15). Then, a plating film 40 is formed on these metal surfaces.
[0065]
Although not shown, the leadless package 32 configured as described above is stacked in a plurality of stages via the leads 34 and the first and second heat transfer terminals 38A and 38B, so that a stacked semiconductor device is formed. Can be configured.
[0066]
According to the present embodiment, effects similar to those of the above-described embodiments can be obtained. In particular, according to the present embodiment, since a larger number of heat dissipation paths are formed than in the above-described embodiments, heat dissipation performance is enhanced, and a leadless package stacking a semiconductor chip having an extremely high heat generation amount is stacked. It can be suitably implemented for the structure.
[0067]
(Fourth embodiment)
16 to 19 show a fourth embodiment of the present invention. 16 is a side sectional view of the semiconductor device 41 according to the present embodiment, FIG. 17 is a plan view of FIG. 16, FIG. 18 is a sectional view taken along the line [18]-[18] in FIG. 17, and FIG. FIG. 16 is a rear view of FIG.
[0068]
The semiconductor device 41 according to the present embodiment is configured by vertically stacking a plurality of (four in the figure) leadless packages 42 of the same configuration each containing a semiconductor chip 43.
[0069]
The leadless package 42 of each stage constituting the semiconductor device 1 connects the semiconductor chip 43, a plurality of signal input / output leads 44 arranged on the sides of the semiconductor chip 43, and the semiconductor chip 43 and the leads 44. Bonding wire 45, a sealing resin 46 for sealing the semiconductor chip 43 and the bonding wire 45, a die pad 49 for supporting the semiconductor chip 43, and a conductive wire having a thickness equivalent to that of the lead 44 which is in contact with the die pad 49. And a heat terminal 48.
[0070]
The die pad portion 49 supports the semiconductor chip 3 within the range of the thickness (height) of the lead 44. That is, the three sizes are selected such that the total of the thickness of the die pad portion 49, the thickness of the semiconductor chip 43, and the loop height of the bonding wire 45 falls within the thickness of the lead 44. Have been.
[0071]
The back surface of the die pad portion 49 belongs to the same plane as the lower surface portion of the lead 44 (the upper surface in FIG. 16), and the periphery excluding the back surface is molded with the sealing resin 46 together with the bonding wires 45. , SON (Small Outline Non-leaded package) type leadless package 42 is configured.
[0072]
The heat transfer terminal 48 has a function of transmitting heat generated from the semiconductor chip 43 to the outside of the semiconductor chip 43. In the present embodiment, the heat transfer terminal 48 is provided integrally with the die pad portion 49 on the side surface of the package where the leads 44 are not formed. (FIGS. 18 and 19). The heat transfer terminal 48 has the same thickness (height) as the lead 44, and is formed on the entire area of the side portion of the die pad portion 49.
[0073]
The die pad portion 49 and the heat transfer terminal 48 are formed of the same material as the lead 44, respectively. In particular, although not shown, it is formed integrally with one lead frame. The upper and lower surfaces of the lead 44, the tip of the heat transfer terminal 48, and the back surface of the die pad portion 49 are exposed to the outside to constitute the outer surface of the leadless package 42 (FIGS. 17 and 19). Then, a plating film 50 is formed on these metal surfaces.
[0074]
As shown in FIG. 16, the respective leadless packages 42 are connected to each other via a conductive bonding material 47 provided on the lead 44 and the heat transfer terminal 48, and the lead 44 and the lead 44 of the lowermost leadless package 42 are connected to each other. The heat transfer terminals 48 are connected to the input / output lands 9 and the heat radiating lands 14 of the printed wiring board 8 via bonding materials 47, respectively. Thus, in the leadless package 42 of each layer, electrical connection between the layers is made by each lead 44, and a heat dissipation path between the layers is formed by the heat transfer terminal 48 and the die pad portion 49 of each layer.
[0075]
The die pad portion 49 of the leadless package 42 located on the uppermost layer functions as a heat radiating plate for releasing heat generated from the leadless package 42 of each layer to the outside air or to a radiator attached by a user. Have.
[0076]
According to the semiconductor device 41 of the present embodiment configured as described above, the same effect as that of the above-described first embodiment can be obtained.
[0077]
Although the embodiments of the present invention have been described above, the present invention is, of course, not limited to these, and various modifications can be made based on the technical idea of the present invention.
[0078]
For example, in each of the above embodiments, an example is described in which a leadless package containing the same type of semiconductor chip is stacked in a plurality of stages to form a semiconductor device. However, a leadless package containing semiconductor chips of different types is used. It is also possible to form a semiconductor device by stacking.
[0079]
Further, in each of the above embodiments, the heat radiation path connecting the respective layers of the semiconductor device in the vertical direction is formed linearly. However, the present invention is not limited to this, and the heat radiation path in the vertical direction may be formed in a zigzag shape. is there.
[0080]
Although the number of heat transfer terminals is the same for each layer, if there is at least one heat dissipation path between each layer, the minimum heat dissipation can be ensured. It is also possible.
[0081]
Further, the bonding material for connecting the leadless packages of each layer is not limited to the above-mentioned solder paste, and for example, a plating bump or the like can be applied. In addition, connection between layers may be achieved by using a conductive layer such as a conductive paste or an anisotropic conductive material (ACF / ACP).
[0082]
Furthermore, in each of the above embodiments, an example in which the present invention is applied to a three-dimensional module in which a leadless package having a single semiconductor chip mounted on a single lead frame is stacked in a plurality of stages has been described. The present invention is also applicable to a three-dimensional module including a multi-chip type leadless package in which a plurality of semiconductor chips are mounted on one lead frame.
[0083]
【The invention's effect】
As described above, according to the leadless package of the present invention, since the signal input / output leads and the heat transfer terminals for heat dissipation connected to the die pad portion are arranged side by side, the leadless package is stacked. Even in this case, a heat radiation path in the stacking direction can be secured, and an operation failure due to excessive heat generation can be avoided.
[0084]
Further, if the die pad portion and the heat transfer terminal are integrally formed as a part of a lead frame for forming a lead, it is not necessary to attach a heat radiating member in a later step, thereby improving productivity and manufacturing. Cost deterioration can be avoided. Further, in this case, the die pad portion and the heat transfer terminal can be incorporated as a part of the package together with the lead when the semiconductor chip is packaged, so that an increase in the package thickness can be prevented.
[0085]
On the other hand, according to the semiconductor device of the present invention, it is possible to avoid an operation failure due to heat generated from a semiconductor chip of a leadless package stacked in a plurality of stages, particularly a leadless package located in an inner layer portion. The reliability of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of FIG.
FIG. 3 is a sectional view taken along the line [3]-[3] in FIG.
FIG. 4 is a rear view of FIG. 1;
FIG. 5 is a side sectional view of a leadless package constituting the semiconductor device of FIG. 1;
FIG. 6 is a plan view of a lead frame for constituting the leadless package of FIG. 5;
FIG. 7 is a process sectional view illustrating the method for manufacturing the leadless package of FIG. 5;
FIG. 8 is a process sectional view illustrating the method for manufacturing the leadless package of FIG. 5;
FIG. 9 is a process sectional view illustrating the method of manufacturing the semiconductor device in FIG. 1;
FIG. 10 is a side sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 11 is a plan view of FIG. 10;
FIG. 12 is a rear view of FIG. 10;
FIG. 13 is a side sectional view of a leadless package according to a third embodiment of the present invention.
FIG. 14 is a rear view of FIG.
FIG. 15 is a plan view of FIG.
FIG. 16 is a side sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 17 is a plan view of FIG. 16;
18 is a sectional view taken along the line [18]-[18] in FIG.
FIG. 19 is a rear view of FIG. 16;
FIG. 20 is a side sectional view of a conventional semiconductor device.
FIG. 21 is a side sectional view of a conventional leadless package forming the semiconductor device of FIG. 20;
FIG. 22 is a perspective view showing the entire conventional leadless package, where A is a view from the front side and B is a view from the back side.
23A and 23B are diagrams showing a lead frame for forming a conventional leadless package, wherein A is a plan view and B is a cross-sectional view taken along the line [B]-[B] in A.
[Explanation of symbols]
1, 21, 41 ... semiconductor device, 2, 22, 32, 42 ... leadless package, 3, 23, 33, 43 ... semiconductor chip, 4, 24, 34, 44 ... lead, 5, 25, 35, 45 ... Bonding wire, 6, 26, 36, 46: sealing resin, 8: printed wiring board, 9: input / output land, 14: heat release land, 10, 28, 38A, 38B, 48: heat transfer terminal, 11 , 29, 39, 49: die pad portion, 12, 38B: horizontal heat transfer portion, 15: lead frame.

Claims (7)

A semiconductor chip, a plurality of leads arranged on a side of the semiconductor chip, a bonding wire connecting the semiconductor chip to the plurality of leads, and a sealing resin for sealing the semiconductor chip and the bonding wire. A leadless package having a structure in which an upper surface and a lower surface of the lead are exposed to the outside,
A die pad portion supporting the semiconductor chip within a thickness range of the lead;
A leadless package having a heat transfer terminal connected to the die pad portion and having a thickness equal to that of the lead. The leadless package according to claim 1, wherein the die pad portion and the heat transfer terminal are formed of the same material as the lead. The leadless package according to claim 1, wherein the heat transfer terminal is connected to the die pad portion via a horizontal heat transfer portion. The leadless package according to claim 3, wherein the heat transfer terminals are arranged at four corners of the package. The leadless package according to claim 1, wherein the heat transfer terminal is disposed between the semiconductor chip and the lead. The leadless package according to claim 1, wherein the heat transfer terminal is disposed on a side of the package. A semiconductor device in which a leadless package is stacked in a plurality of stages,
The leadless package includes a semiconductor chip, a plurality of leads arranged on a side of the semiconductor chip, a bonding wire connecting the semiconductor chip and the plurality of leads, and the semiconductor chip and the bonding wire. A sealing resin for sealing, a die pad portion supporting the semiconductor chip within the thickness range of the lead, and a heat transfer terminal having a thickness equivalent to that of the lead in contact with the die pad portion,
A semiconductor device, wherein each of the leadless packages is connected via the lead and the heat transfer terminal.

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