JP2004031640A - Magnetic memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a magnetic memory device wherein density is increased and power consumption is reduced is realized. <P>SOLUTION: On a surface of a silicon substrate 10 wherein an MOS transistor QN is formed, a plurality of TMR(tunneling magnetoresistive) elements VR are stacked being embedded in interlayer insulating films 40. Writing bit lines W-BL and writing word lines W-WL which intersect each other are arranged above and below sandwiching the respective TMR elements VR. Yoke members 51, 52 are formed on surfaces except surfaces facing the TMR elements VR of the writing bit lines W-BL and the writing word lines W-WL. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a magnetic memory device (magnetic random access memory) using a memory cell that stores "1" and "0" information by a tunnel-type magnetoresistance effect.
[0002]
[Prior art]
In recent years, many memories for storing information based on a new principle have been proposed. One of them is Roy Skeuerlein et. Al. For example, there is a memory using a tunneling magnetoresistive (TMR) effect proposed by the company (for example, ISSCC2000 Technical Digest p.128 "A 10 ns Read and Write Non-Joint Monthly Railway International Union of Railways National Railways Monthly Monthly Journal of the United States of America). in each Cell ").
[0003]
A magnetic random access memory (MRAM: Magnetic Random Access Memory) using the TMR effect stores "1" and "0" information by a TMR element. The TMR element has a structure in which an insulating layer (tunnel barrier) 103 is sandwiched between two magnetic layers (ferromagnetic layers) 101 and 102 as shown in FIG. The binary information stored in the TMR element is defined by whether the spin directions of the two magnetic layers 101 and 102 are parallel or antiparallel. Here, “parallel” means that the spin directions (indicated by arrows) of the two magnetic layers 101 and 102 are the same, and “antiparallel” means that the spin directions of the two magnetic layers 101 and 102 are opposite. It means that they are parallel.
[0004]
Usually, one of the two magnetic layers 101 and 102 of the TMR element is called a fixed layer in which a diamagnetic layer is arranged and the spin direction is fixed, and the other is a recording layer in which the spin direction is switched by a current magnetic field. It becomes. As shown in FIG. 35, when the spin directions of the two magnetic layers 101 and 102 become parallel, the tunnel resistance of the insulating layer (tunnel barrier) 103 sandwiched between these two magnetic layers becomes the lowest. This state is, for example, the data “1” state. When the spin directions of the two magnetic layers 101 and 102 are antiparallel, the tunnel resistance of the insulating layer 103 sandwiched between these two magnetic layers becomes the highest. This state is the data "0" state.
[0005]
As shown in FIG. 34, an MRAM using such a TMR element is arranged at the intersection of a write word line (W-WL) and a data selection line (bit line) (BL) that intersect each other. Be composed. Data writing is achieved by applying a current to the write word line W-WL and the data selection line BL, and making the spin directions of the TMR element parallel or anti-parallel using a magnetic field created by the current flowing through both the lines. You.
[0006]
For example, at the time of writing, only a current flowing in one direction flows through the data selection line BL, and a current flowing in a different direction flows through the write word line W-WL in accordance with write data. When a current flowing in the first direction flows through the write word line W-WL, the spin direction of the TMR element becomes parallel ("1" state). When a current flowing in the second direction flows, the spin direction of the TMR element changes. Are antiparallel ("0" state).
[0007]
More specifically, in the TMR element, at the time of writing, a magnetic field Hx in the direction of the easy axis (Easy-Axis) which is the long side direction and a magnetic field Hy in the direction of the hard axis (Hard-Axis) orthogonal thereto. And a combined magnetic field is applied. Thereby, the resistance value of the TMR element changes as shown by the TMR curve in FIG. The vertical axis in FIG. 36 indicates the rate of change in the resistance value of the TMR element, and is called the MR ratio. Although the MR ratio changes depending on the properties of the magnetic layer used, a ratio of about 10% to 50% is obtained.
[0008]
As shown by the solid line and the dotted line in FIG. 36, the magnitude of the magnetic field Hx in the easy axis direction required to change the resistance value of the TMR element also changes according to the magnitude of the magnetic field Hy in the hard axis direction. By utilizing this phenomenon, data can be written only to the TMR element existing at the intersection of the selected write word line W-WL and the selected data selection line BL in the cell array.
[0009]
This situation will be further described using an asteroid curve. The asteroid curve of the TMR element is, for example, as shown in FIG. If the magnitude of the combined magnetic field of the magnetic field Hx in the easy axis direction and the magnetic field Hy in the hard axis direction is outside the asteroid curve (the position of the black circle), the spin direction of the magnetic layer can be reversed. . Conversely, when the magnitude of the combined magnetic field of Hx and Hy is inside the asteroid curve (the position of the white circle), the spin direction of the magnetic layer cannot be reversed.
Therefore, by changing the magnitude of the combined magnetic field of the magnetic field Hx in the direction of the easy axis and the magnetic field Hy in the direction of the hard axis and changing the position of the magnitude of the combined magnetic field in the Hx-Hy plane, the data of the TMR element Writing can be controlled.
[0010]
Data reading can be easily performed by applying a current to the selected TMR element and detecting the resistance value of the TMR element. Specifically, a current path is created by connecting a switch element in series with the TMR element. If only the selected TMR element is turned on and the current flows, the data of the TMR element can be read.
[0011]
FIG. 38 is a cross-sectional view of a memory cell when a MOSFET is applied as a switch element. In this case, the gate electrode of the MOSFET becomes the read word line R-WL. The selected read word line R-WL is set to “H” to turn on the MOSFET, and by reading the magnitude of the current flowing from the selected bit line BL through the TMR element and through the MOSFET, data can be determined. it can.
[0012]
FIG. 39 is a sectional view of a memory cell when a diode is applied as a switch element. In this case, there is no read word line, but if the diode is turned on and off depending on the resistance of the TMR element, data can be determined by detecting the current of the bit line.
Although the spin direction of the TMR element is not shown in FIGS. 38 and 39, the spin direction may be either perpendicular (to the write word line W-WL) or parallel to the bit line (to the bit line BL).
[0013]
[Problems to be solved by the invention]
In the MRAM using the above-described TMR element, in order to realize a large MR ratio difference between the data “1” and “0” with low power consumption, the current magnetic field of the write word line and the bit line is required for the TMR element. Needs to be concentrated efficiently. However, it is not easy to concentrate a current magnetic field on a minute TMR element composed of a thin film. In this regard, it has been proposed that the yoke material be coated on a surface other than the surface of the write word line or the bit line facing the TMR element so that the current magnetic field is concentrated on the TMR element (US Pat. 6, 174, 737).
On the other hand, in the conventionally proposed MRAM using the TMR element, as shown in FIG. 38 or 39, the TMR elements arranged in a matrix are connected between a bit line and a reference potential line via switch elements. You. That is, since one TMR element requires one switch element, it is difficult to reduce the cell area.
[0014]
An object of the present invention is to provide a magnetic memory device that achieves higher density and lower power consumption.
[0015]
[Means for Solving the Problems]
A magnetic memory device according to the present invention includes a semiconductor substrate, a switching element formed on the semiconductor substrate, and a plurality of tunnel magnetoresistors stacked on the semiconductor substrate via an interlayer insulating film and connected to the switching element. An element, a first write wiring buried in the interlayer insulating film so as to pass in the vicinity of each of the tunnel magnetoresistive elements; and A second write wiring buried so as to intersect with the first write wiring and at least one of the first and second write wirings formed on a surface excluding a surface facing the tunnel magnetoresistive element; And a yoke material.
[0016]
According to the present invention, by stacking a plurality of tunnel magnetoresistive elements, it is possible to increase the density of the MRAM. Further, by forming a yoke material on a write wiring for applying a magnetic field for writing data to each tunneling magneto-resistance element, the magnetic field can be concentrated on the tunneling magneto-resistance element, and the write current can be reduced.
[0017]
In the present invention, for example, the first and second write wirings are disposed vertically above and below each tunnel magnetoresistive element, and the yoke material is formed on the side surface of each write wiring and the surface facing the tunnel magnetoresistive element. Formed on the opposite side.
Alternatively, the first and second write wirings can be formed at least partially as shared wiring between vertically adjacent tunneling magneto-resistance elements. In this case, a yoke material is formed on the side surface of the shared wiring.
[0018]
In the present invention, the plurality of stacked tunneling magneto-resistance elements are connected in series to, for example, a switching element. At this time, a data line connected to the terminal electrode of the uppermost tunneling magneto-resistance element is provided above the plurality of tunneling magneto-resistance elements.
[0019]
Further, a plurality of tunneling magneto-resistance elements can be stacked in a parallel connection state. In this case, one terminal electrode of the tunneling magneto-resistance element is commonly connected to the switching element, and the other terminal electrode is commonly connected to a data line provided above the plurality of tunneling magneto-resistance elements.
[0020]
Further, the plurality of tunnel magnetoresistive elements can be stacked in a state where a plurality of sets each connected in parallel are connected in series to the switching element. In this case, a data line commonly connected to the terminal electrodes of the uppermost set of tunneling magneto-resistance elements is provided above the plurality of tunneling magneto-resistance elements.
[0021]
Further, one end of the plurality of tunneling magneto-resistance elements is commonly connected to the switching element, and at the other end, one of the first and second write wirings also serves as a terminal electrode and a current wiring of the tunneling magneto-resistance element. You may make it connected. In this case, the data line may be buried under the plurality of tunneling magneto-resistance elements in the interlayer insulating film so as to be connected to the terminal of the switching element opposite to the connection terminal with the tunneling magneto-resistance element. Good.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
FIG. 1 shows an equivalent circuit of one cell unit of the stacked MRAM. This cell unit is configured such that four TMR elements VR1 to VR4 are connected in series to a MOS transistor QN as one switch element. One terminal electrode of the TMR elements VR1 to VR4 connected in series is connected to a read bit line R-BL which is a data line, and a source of the MOS transistor QN is connected to a source line SL.
[0023]
In the vicinity of each of the TMR elements VR1 to VR4, a write bit line W-BL and a write word line W-WL, which are write wirings crossing each other, are provided to apply a current magnetic field at the time of data writing. The gate electrode of the MOS transistor QN is continuously provided as a read word line R-WL in parallel with the write word line W-WL.
[0024]
In this stacked MRAM, one MOS transistor QN accesses four TMR elements VR1 to VR4. This is because a cell cannot have selectivity in a reading method such as the case of one switching element and one TMR element as in the related art, so that a unique reading method is required. First, one cell unit is selected by selecting a read word line R-WL and a read bit line R-BL. Then, currents flowing through the plurality of TMR elements VR1 to VR4 of the selected cell unit are read by the sense amplifier, and the values are stored.
[0025]
Next, by selecting the write word line W-WL and the write bit line W-BL corresponding to the selected cell, for example, data “1” is written to the selected cell. The read word line R-WL and the read bit line R-BL are selected again, the current flowing through the selected cell unit is read by the sense amplifier, and the value is compared with the value previously sensed and stored. If the values are different, the data of the selected cell is "0", and if the values are the same, it is "1". As described above, the data of the selected cell in the cell unit can be determined. In the case of data "0", destructive reading is performed, so rewriting is performed.
[0026]
FIG. 2 shows a stacked structure of the above stacked MRAM, and FIG. 3 shows a cell layout. FIG. 2 is a cross-sectional view taken along the write bit line W-BL. Actually, as shown in FIG. 3, the TMR elements VR (VR1 to VR4) are formed in the element region where the MOS transistor QN is formed. Are formed at the same time in the element isolation region, and do not appear at the same time in the cross section of FIG. 2, and are shown here as schematic perspective cross sectional views. The same applies to the following embodiments.
[0027]
As shown, a MOS transistor QN is formed in an element region of a silicon substrate 10 surrounded by an element isolation insulating film 11. The gate electrode of the MOS transistor QN is formed continuously in one direction as shown in FIG. 3, and becomes a read word line (R-WL) 12. On the substrate on which the MOS transistor QN is formed, four TMR elements VR separated by an interlayer insulating film 40 are stacked by repeating film deposition and patterning.
[0028]
Specifically, the source 14 of the MOS transistor QN is connected via a contact 21 to a source line SL made of a first layer metal film, and the drain 13 is connected via a contact 31 to a relay electrode 22 made of the same metal film as the source line SL. Connected. Each TMR element VR has a ferromagnetic layer sandwiching a tunnel barrier layer, which is sandwiched between lower metal electrodes 26 (26a to 26d) and upper metal electrodes 28 (28a to 28d).
Write word lines (W-WL) 25 (25a to 25d) buried in the interlayer insulating film 40 and arranged in parallel with the read word lines 12 are provided immediately below each TMR element VR. Write bit lines (W-BL) 30 (30a to 30d) embedded in the interlayer insulating film 40 and intersecting with the read word lines 12 and the write word lines 25 are provided immediately above each TMR element VR. .
[0029]
As shown in FIG. 3, the lower electrode 26 and the upper electrode 28 of each TMR element VR are drawn from the region of the TMR device VR to the region of the drain 13 of the MOS transistor QN. The lower electrode 26 is provided on the drain region 13 via the relay electrode 24 (24a to 24d) patterned with the same metal film as the write word line 25, via the contact plug 31, and the TMR element VR thereunder. The lower electrode 26a of the lowermost TMR element VR1 is sequentially connected to the upper electrode 28, and is connected to the drain 13 via the relay electrodes 24 and 22 and the contact plug 31. Thereby, each TMR element VR is connected in series to the MOS transistor QN.
[0030]
A read bit line (R-BL) 41 which is a data line parallel to the write word line 30 is provided on the uppermost TMR element VR. The read bit line 41 is connected to the upper electrode 28 of the TMR element VR via the contact plug 31.
[0031]
4 and 5 show a structure in which a yoke material is formed around the write bit line (W-BL) 30 and the write word line (W-WL) 25 based on the above laminated MRAM. 4 is a cross section corresponding to FIG. 2, and FIG. 5 is a cross section along a write word line 25 orthogonal to the cross section. As shown in the drawing, a yoke material 51 is formed on the write word line 25 so as to cover the surface (side surface and bottom surface) except the surface facing the TMR element VR. Both open upper ends of the yoke member 51 are located near both short sides of the TMR element VR. Similarly, the yoke material 51 is formed on the surface (side surface and upper surface) of the write bit line 30 except for the surface facing the TMR element VR. As shown in FIG. 5, both open lower ends of the yoke member 52 extend below the bottom surface of the write bit line 30 so as to be located near both long sides of the TMR element VR.
[0032]
As the yoke members 51 and 52, a conductive yoke material such as a Ni—Fe alloy or a Co—Ni alloy is typically used. In addition, Co- (Zr, Hf, Nb, Ta, Ti) -based, (Co, Ni, Fe)-(Si, B)-(P, Al, Mo, Nb, Mn) -based amorphous materials may be used. it can.
[0033]
By forming the yoke material around the write bit line 30 and the write word line 25 in this manner, the magnetic field generated when a write current flows through these can be effectively concentrated on the TMR element VR. This leads to a reduction in the write current of the TMR element. Further, the yoke material on the side surfaces of the write bit line 30 and the write word line 25 functions to suppress the influence of the write magnetic field on the non-selected cells when the adjacent cells are arranged close to each other. It is also advantageous for high density. As described above, a large-capacity MRAM in which the write current and the crosstalk are reduced can be obtained.
[0034]
[Embodiment 2]
FIG. 6 shows an embodiment in which the write bit line (W-BL) 30 is shared by two upper and lower cells based on the stacked structure of FIG. With the sharing of the write bit line 30, the write word line (W-WL) 25 is also shared by the second and third TMR elements VR2 and VR3. A write word line 25d is arranged above the uppermost TMR element VR4, and a write word line 25a is arranged below the lowermost TMR element VR1.
[0035]
FIGS. 7 and 8 show a structure in which a yoke material is formed around the write bit line (W-BL) 30 and the write word line (W-WL) 25 based on the above stacked MRAM. 7 is a cross section corresponding to FIG. 6, and FIG. 8 is a cross section along a write word line 25 orthogonal to the cross section.
[0036]
Since the write word line 25 and the write bit line 30 are shared by the upper and lower TMR elements VR, the yoke members 51 and 52 are arranged only on both side surfaces of these wires. As shown in FIG. 8, the yoke material 52 on the side surface of the write bit line 30 extends from the upper and lower surfaces of the bit line metal film to the vicinity of the TMR element VR, so that the magnetic field can be concentrated by the TMR element VR. Is possible.
[0037]
Accordingly, the same effects as those of the above embodiment can be obtained, and the sharing of the laminated film simplifies the laminated structure and the manufacturing process. Further, by extending the yoke material 52 on the side surface of the write bit line 30 vertically, the write current can be further reduced.
[0038]
[Embodiment 3]
FIG. 9 shows an equivalent circuit of another stacked MRAM. In this stacked MRAM, four TMR elements VR are connected in parallel to a MOS transistor QN, which is one switch element. In each of the TMR elements VR, a write word line W-WL disposed on the lower electrode side and a write bit line W-BL disposed on the upper electrode side are provided to cross each other. One end of each TMR element VR is connected to a source line SL via a MOS transistor QN, and the other end is connected to a read bit line R-BL formed at the top of the stacked structure. The fact that the gate of the MOS transistor QN becomes the read word line R-WL is the same as in the previous embodiment.
[0039]
Although the four TMR elements VR are connected in parallel, the reading method is the same as in the case of the series connection of the above embodiment. That is, the reading of the current of the cell unit, the writing of “1” data to the selected cell, and the reading of the current of the cell unit are performed again, and the data can be determined by comparing the read current twice.
[0040]
FIG. 10 shows a stacked structure of the above stacked MRAM, and FIG. 11 shows a cell layout. FIG. 10 is a cross-sectional view along the write bit line W-BL. As shown in FIG. 11, the TMR elements VR (VR1 to VR4) are separated from the element region where the MOS transistor QN is formed, as shown in FIG. It does not appear at the same time in the cross section of FIG.
[0041]
The source 14 of the MOS transistor QN is connected via a contact 21 to a source line (SL) 23 made of a first-layer metal film, and the drain 13 is connected via a contact 31 to a relay electrode 22 made of the same metal film as the source line SL. Is done. Each TMR element VR is embedded in the interlayer insulating film 40 and sequentially laminated as in the previous embodiment, and is sandwiched between the lower metal electrode 26 (26a to 26d) and the upper metal electrode 28 (28a to 28d). I have. Write word lines (W-WL) 25 (25a to 25d) buried in the interlayer insulating film 40 and arranged in parallel with the read word lines 12 are provided immediately below each TMR element VR. Write bit lines (W-BL) 30 (30a to 30d) embedded in the interlayer insulating film 40 and intersecting with the read word lines 12 and the write word lines 25 are provided immediately above each TMR element VR. .
[0042]
As shown in FIG. 11, the lower electrode 26 and the upper electrode 28 of each TMR element VR are respectively guided to the region of the drain 13 and the region of the source 14 of the MOS transistor QN. Each lower electrode 26 is connected in parallel to the drain 13 via a contact plug 31 via a relay electrode 24 (24a to 24d) patterned with the same metal film as the write word line 25 on the drain region 13. . The upper electrode 28 is connected in parallel via a contact plug 32, and is connected to a read bit line (R-BL) 41 provided at the top.
[0043]
FIG. 12 shows a structure in which a yoke material is formed around a write bit line (W-BL) 30 and a write word line (W-WL) 25 based on the laminated structure of FIG. 10, and FIG. 4 is a cross section taken along a perpendicular write word line 25. As shown in the drawing, a yoke material 51 is formed on the write word line 25 so as to cover the surface (side surface and bottom surface) excluding the surface facing the TMR element VR. Both open upper ends of the yoke member 51 are located near both short sides of the TMR element VR. Similarly, the yoke material 51 is formed on the surface (side surface and upper surface) of the write bit line 30 except for the surface facing the TMR element VR. As shown in FIG. 13, both open lower ends of the yoke member 52 are formed below the bottom surface of the write bit line 30 so as to be located near both long sides of the TMR element VR.
[0044]
By forming the yoke material around the write bit line 30 and the write word line 25 in this manner, the generated magnetic field can be effectively concentrated on the TMR element VR as in the previous embodiment, and the adjacent cell Magnetic field leakage can be suppressed. Therefore, a large-capacity MRAM with a reduced write current and reduced crosstalk can be obtained.
[0045]
[Embodiment 4]
FIG. 14 shows an embodiment in which the write bit line (W-BL) 30 is shared by two upper and lower cells based on the stacked structure of FIG. With the sharing of the write bit line 30, the write word line (W-WL) 25 is also shared by the second and third TMR elements VR2 and VR3. A write word line 25d is arranged above the uppermost TMR element VR4, and a write word line 25a is arranged below the lowermost TMR element VR1. With the sharing of the write bit line 30, the lower electrodes 26a and 26b of the TMR elements VR1 and VR3 and the upper electrodes 28b and 28d of the TMR elements VR2 and VR4 are shared by the diffusion layer 13 and the upper parts of the TMR elements VR1 and VR3. The electrodes 28a and 28c and the lower electrodes 26b and 26d of the TMR elements VR2 and VR4 are commonly connected to a read bit line (R-BL) 41.
[0046]
15 and 16 show a structure in which a yoke material is formed around the write bit line (W-BL) 30 and the write word line (W-WL) 25 based on the above-described stacked MRAM. FIG. 15 is a cross section corresponding to FIG. 14, and FIG. 16 is a cross section along a write word line 25 orthogonal to the cross section.
[0047]
Since the write word line 25 and the write bit line 30 are shared by the upper and lower TMR elements VR, the yoke members 51 and 52 are arranged only on both side surfaces of these wires. As shown in FIG. 16, the yoke material 52 on the side surface of the write bit line 30 extends from the upper and lower surfaces of the bit line metal film to the vicinity of the TMR element VR, thereby concentrating the magnetic field by the TMR element VR. Is possible.
[0048]
Thus, as in the second embodiment, the sharing of the metal film simplifies the laminated structure and the manufacturing process. Further, by extending the yoke material 52 on the side surface of the write bit line 30 vertically, the write current can be further reduced.
[0049]
[Embodiment 5]
FIG. 17 shows an equivalent circuit of one cell unit of another stacked MRAM. In this cell unit, two TMR elements VR1 to VR4 are connected in parallel two by two, and these are connected in series to a MOS transistor QN as one switch element. The terminal electrode of the TMR element VR4 is connected to a read bit line R-BL which is a data line, and the source of the MOS transistor QN is connected to a source line SL.
[0050]
The write word line W-WL is shared between the two TMR elements VR2 and VR3, and is provided independently for the remaining TMR elements VR1 and VR4. The write bit line W-BL is shared between two TMR elements VR1 and VR2, and between VR3 and VR4.
[0051]
FIG. 18 shows a cross section along the write bit line W-BL of the laminated MRAM, and FIG. 19 shows a cell layout thereof. As shown in FIG. 19, the lower electrodes 26a and 26c of the first and third TMR elements VR1 and VR3 and the upper electrodes 28b and 28d of the second and fourth TMR elements VR2 and VR4 have the same pattern of MOS. It is led to the region of the drain 13 of the transistor. Then, on the region of the drain 13, the lower electrode 26a, 26c and the upper electrode 28b, 28d are connected by the contact plug 31, respectively.
[0052]
The upper electrodes 28a and 28c of the first and third TMR elements VR1 and VR3 and the lower electrodes 26b and 26d of the second and fourth TMR elements VR2 and VR4 have the same pattern and extend to the gate region of the MOS transistor. I will On the gate region, the lower electrodes 26b, 26d and the upper electrodes 28a, 28c are connected by contact plugs 32, respectively. The lower electrode 26a of the lowermost TMR element VR1 is connected to the drain 13 via the contact plug 31, and the lower electrode 26d of the uppermost TMR element VR4 is connected to the uppermost read bit line (R- BL) 41.
[0053]
Thus, equivalently, as shown in FIG. 17, a cell unit is formed in which two TMR elements are connected in parallel and two TMR elements are connected in series.
[0054]
20 and 21 show a structure in which a yoke material is formed around the write bit line (W-BL) 30 and the write word line (W-WL) 25 based on the stacked MRAM described above. FIG. 20 is a cross section corresponding to FIG. 18, and FIG. 21 is a cross section along a write word line 25 orthogonal to the cross section.
[0055]
The yoke material 51 is formed on the write word line 25 on the side surface and the bottom surface other than the surface facing the TMR element VR. Similarly, a yoke material 52 is formed on the upper and side surfaces of the write bit line 30 except for the surface facing the TMR element VR.
As shown in FIG. 21, the yoke material 52 on the side surface of the write bit line 30 extends from the upper and lower surfaces of the bit line metal film to the vicinity of the TMR element VR, thereby concentrating the magnetic field by the TMR element VR. Is possible.
[0056]
As described above, similarly to the previous embodiment, the generated magnetic field can be effectively concentrated on the TMR element VR, and the leakage of the magnetic field to the adjacent cell can be suppressed. Therefore, a large-capacity MRAM with a reduced write current and reduced crosstalk can be obtained.
[0057]
Embodiment 6
FIG. 22 shows an embodiment in which the write bit line (W-BL) 30 is shared by two upper and lower TMR elements based on the laminated structure of FIG. With the sharing of the write bit line 30, the write word line (W-WL) 25 is also shared by the second and third TMR elements VR2 and VR3. A write word line 25d is arranged above the uppermost TMR element VR4, and a write word line 25a is arranged below the lowermost TMR element VR1. FIG. 23 shows the cell layout, which is the same as FIG.
[0058]
FIGS. 24 and 25 show a structure in which a yoke material is formed around a write bit line (W-BL) 30 and a write word line (W-WL) 25 based on the laminated MRAM of FIG. FIG. 24 is a cross section corresponding to FIG. 22, and FIG. 25 is a cross section along a write word line 25 orthogonal to the cross section.
[0059]
The write word line 25 has a yoke material 51 formed only on the side surface. Similarly, the yoke material 52 is formed only on the side surface of the write bit line 30. This enables the magnetic field to be concentrated by each TMR element VR.
[0060]
Embodiment 7
FIG. 26 shows an equivalent circuit of one cell unit of another stacked MRAM. In this cell unit, four TMR elements VR1 to VR4 are connected in parallel to a MOS transistor QN as one switch element, but are configured to be independently accessible. That is, one end of the MOS transistor QN is connected to a read bit line R-BL which is a data line, and the write word line W-BL of each TMR element VR is connected to one end of the TMR element VR, respectively. Also serves as current wiring.
[0061]
FIG. 27 is a cross-sectional view along a write bit line showing a stacked structure of the stacked MRAM, and FIG. 28 is a cell layout. The source 14 of the MOS transistor QN is connected via a contact plug 21 to a read bit line (R-BL) 41 which is a first layer metal wiring. The read bit line 41 is drawn out of the region of the MOS transistor as shown in FIG. 28 and is provided in the element isolation region. After the MOS transistors are formed, the TMR elements VR are sequentially stacked. A write bit line (W-BL) 30 is formed also as an upper electrode of each TMR element VR. A write word line (W-WL) 25 is buried below each TMR element VR.
[0062]
As shown in FIG. 28, the lower electrode 26 of each TMR element VR is led up to the region of the drain 13 of the MOS transistor QN, and passes through the relay electrode 24 and the contact plug 31 formed simultaneously with the write word line 25. And is commonly connected to the drain 13.
[0063]
FIGS. 29 and 30 show a structure in which a yoke material is formed around a write bit line (W-BL) 30 and a write word line (W-WL) 25 based on the stacked MRAM of FIG. FIG. 29 is a cross section corresponding to FIG. 27, and FIG. 30 is a cross section along a write word line 25 orthogonal to the cross section.
[0064]
The yoke material 51 is formed on the write word line 25 on the side surface and the bottom surface other than the surface facing the TMR element VR. Similarly, a yoke material 52 is formed on the upper and side surfaces of the write bit line 30 except for the surface facing the TMR element VR.
Thereby, the magnetic field can be concentrated by the TMR element VR. Therefore, as in the previous embodiment, a large-capacity MRAM in which the write current is reduced and the leakage of the magnetic field to adjacent cells is suppressed can be obtained.
[0065]
Embodiment 8
FIG. 31 shows the structure of another stacked MRAM in association with FIG. 27 is different from FIG. 27 in that the write bit line 30 is embedded below each TMR element VR, the write word line 25 is arranged above each TMR element VR, and this write word line 25 is used as a terminal wiring of the TMR element VR. It is that. Therefore, it is equivalent to FIG.
[0066]
FIGS. 32 and 33 show a structure in which a yoke material is formed around the write bit line (W-BL) 30 and the write word line (W-WL) 25 based on the laminated MRAM of FIG. FIG. 32 is a cross section corresponding to FIG. 31, and FIG. 33 is a cross section along a write word line 25 orthogonal to the cross section.
[0067]
In the write word line 25, a yoke material 51 is formed on the side surface and the upper surface excluding the surface facing the TMR element VR. Similarly, a yoke material 52 is formed on the bottom and side surfaces of the write bit line 30 except for the surface facing the TMR element VR. Thereby, the magnetic field can be concentrated by the TMR element VR. Therefore, as in the previous embodiment, a large-capacity MRAM in which the write current is reduced and the leakage of the magnetic field to adjacent cells is suppressed can be obtained.
[0068]
In the above embodiments, when the yoke material is provided, the yoke material is formed on both the write word line and the write bit line. However, the write current reduction effect can be obtained by forming only one of the yoke material and the write bit line.
Although an example using a MOS transistor as the selective switching element has been described, the present invention can be similarly applied to a case where a diode is used.
[0069]
【The invention's effect】
As described above, according to the present invention, high density and low power consumption of a magnetic memory device can be achieved.
[Brief description of the drawings]
FIG. 1 is a diagram showing an equivalent circuit of a stacked MRAM according to an embodiment of the present invention.
FIG. 2 is a schematic sectional view showing a laminated structure of the laminated MRAM.
FIG. 3 is a diagram showing a cell layout of the stacked MRAM.
FIG. 4 is a schematic sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG.
FIG. 5 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 6 is a schematic sectional view of a stacked MRAM according to another embodiment.
FIG. 7 is a schematic cross-sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG.
FIG. 8 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 9 is a diagram showing an equivalent circuit of a stacked MRAM according to another embodiment.
FIG. 10 is a schematic sectional view showing a laminated structure of the laminated MRAM.
FIG. 11 is a diagram showing a cell layout of the stacked MRAM.
FIG. 12 is a schematic sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG. 10;
FIG. 13 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 14 is a schematic sectional view of a stacked MRAM according to another embodiment.
FIG. 15 is a schematic sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG.
16 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 17 is a diagram showing an equivalent circuit of a stacked MRAM according to another embodiment.
FIG. 18 is a schematic sectional view showing a laminated structure of the laminated MRAM.
FIG. 19 is a diagram showing a cell layout of the stacked MRAM.
FIG. 20 is a schematic sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG. 18;
21 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 22 is a schematic cross-sectional view illustrating a stacked structure of a stacked MRAM according to another embodiment.
FIG. 23 is a diagram showing a cell layout of the stacked MRAM.
FIG. 24 is a schematic sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG. 22;
FIG. 25 is a schematic cross-sectional view in a direction orthogonal to FIG.
FIG. 26 is a diagram showing an equivalent circuit of a stacked MRAM according to another embodiment.
FIG. 27 is a schematic sectional view showing a laminated structure of the laminated MRAM.
FIG. 28 is a diagram showing a cell layout of the stacked MRAM.
FIG. 29 is a schematic cross-sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG. 27;
30 is a schematic sectional view in a direction orthogonal to FIG. 29.
FIG. 31 is a schematic sectional view showing a laminated structure of a laminated MRAM according to another embodiment.
FIG. 32 is a schematic cross-sectional view showing a laminated MRAM obtained by improving the laminated MRAM, corresponding to FIG. 31;
FIG. 33 is a schematic sectional view in a direction orthogonal to FIG. 32;
FIG. 34 is a diagram for explaining the principle of writing in the MRAM.
FIG. 35 is a view for explaining the basic structure and operation principle of the TMR element.
FIG. 36 is a diagram showing characteristics of the TMR element.
FIG. 37 is an asteroid curve for explaining the principle of a TMR element.
FIG. 38 is a diagram showing an integrated structure of a TMR element.
FIG. 39 is a diagram showing another integrated structure of the TMR element.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon substrate, 11 ... Element isolation insulating film, 12 ... Read word line (R-WL), 13, 14 ... Drain, source, 21 ... Contact plug, 23 ... Source line (SL), 25 (25a-25d) ... write word line (W-WL), 26 (26a-26d) ... lower electrode, 27 (27a-27d) ... TMR element (VR), 28 (28a-28d) ... upper electrode, 30 (30a-30d) ... Write bit lines (W-BL), 31, 32 contact plugs, 40 interlayer insulation curtains, 41 read bit lines (R-BL), 51, 52 yoke materials.

Claims (7)

A semiconductor substrate;
A switching element formed on the semiconductor substrate,
A plurality of tunneling magneto-resistance elements stacked on the semiconductor substrate via an interlayer insulating film and connected to the switching element;
A first write wiring buried in the interlayer insulating film so as to pass near each of the tunnel magnetoresistive elements;
A second write wiring buried in the interlayer insulating film so as to pass near each of the tunnel magnetoresistive elements and intersect with the first write wiring;
A yoke material formed on a surface of at least one of the first and second write wirings except a surface facing the tunnel magnetoresistive element;
A magnetic memory device comprising: The first and second write wirings are disposed vertically above and below each tunnel magnetoresistive element, and
2. The magnetic memory device according to claim 1, wherein the yoke material is formed on a side surface of each of the write wirings and a surface opposite to a surface facing the tunnel magnetoresistive element. The first and second write wirings are formed at least partially as shared wiring between vertically adjacent tunneling magneto-resistance elements, and
2. The magnetic memory device according to claim 1, wherein the yoke material is formed on a side surface of the shared wiring. The plurality of tunnel magnetoresistive elements are connected in series to the switching element,
2. The magnetic memory device according to claim 1, further comprising a data line disposed above said plurality of tunneling magneto-resistance elements and connected to a terminal electrode of an uppermost tunneling magneto-resistance element. The plurality of tunneling magneto-resistance elements have one terminal electrode commonly connected to the switching element,
2. The magnetic memory device according to claim 1, further comprising a data line commonly connected to the other terminal electrodes of the plurality of tunneling magneto-resistance elements, above the plurality of tunneling magneto-resistance elements. The plurality of tunneling magneto-resistance elements, a plurality of sets connected in parallel each other are connected in series to the switching element,
2. The magnetic memory device according to claim 1, further comprising a data line disposed above the plurality of tunneling magneto-resistance elements and commonly connected to terminal electrodes of the topmost set of tunneling magneto-resistance elements. One end of the plurality of tunneling magneto-resistance elements is commonly connected to the switching element,
One of the first and second write wirings is connected to the other end of each of the corresponding tunneling magneto-resistance elements, also serving as a terminal electrode and a current wiring,
A data line is embedded in the interlayer insulating film below the plurality of tunneling magneto-resistance elements and connected to a terminal of the switching element opposite to a connection terminal with the tunneling magneto-resistance element. The magnetic memory device according to claim 1.

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