JP2001217398A - Storage device using ferromagnetic tunnel junction element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly integrate a storage device (magnetic memory device) which uses a ferromagnetic tunnel junction element and realize the storage of multi- valued information using such a storage device, SOLUTION: Memory elements ME11, ME21, each provided with a ferromagnetic tunnel junction element, are laminated on a semiconductor substrate 1 with a bit line BL1 put between. The memory element ME11 can write information by being applied with a magnetic field caused by currents in a control line CL1 and the bit line BL1. The memory element ME21 can write information by being applied with a magnetic field caused by currents in the bit line BL1 and a control line CL2. By connecting the memory elements ME11, ME21 to transistors Tr11, Tr21 respectively, two cells can be disposed in an area for one memory cell. By connecting the memory elements ME11, ME21 to a common transistor, multi-valued information can be stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device using a ferromagnetic tunnel junction device.

[0002]

2. Description of the Related Art Ferromagnetic tunnel junction devices (MTJ: Magnetic
Tunnel Junction) has a pair of ferromagnetic layers and a tunnel insulating layer (such as an alumina layer) having a thickness of several nm sandwiched between them. When a voltage is applied between the pair of ferromagnetic layers, a tunnel current flows through the tunnel insulating layer. This tunnel current becomes maximum when the magnetic moments of the pair of ferromagnetic layers are parallel, and becomes minimum when the magnetic moments of the pair of ferromagnetic layers are antiparallel. More specifically,
The tunnel current passing through the insulating layer is proportional to the sum of the product of the state density of the up spin of the conduction electrons and the product of the state density of the down spin of the conduction electrons in both ferromagnetic layers. When the magnetic moments are parallel, a large number of spins of conduction electrons of the pair of ferroelectric layers are oriented in the same direction, and the state density thereof is larger than that of the few spins, so that a large tunnel current flows. On the other hand, when the magnetic moment is antiparallel, the majority spins are in opposite directions, so the state density of the majority spins takes a large value in one of the pair of ferromagnetic layers and a small value in the other. Take. Since the same situation occurs for down spin, the tunnel current eventually takes a small value. The above-mentioned effect manifested by the artificial lattice structure of the ferromagnetic material layer / insulating layer / ferromagnetic material layer is obtained by TMR (Tu
nnel MagnetoResistance) effect.

Since the magnetic moment of the ferromagnetic layer can be changed by applying an external magnetic field, a magnetic memory (in particular, an MRAM (Magnetic Random Access Memory)) can be realized using a ferromagnetic tunnel junction device. . If no external magnetic field is applied, the magnetic moment of the ferromagnetic layer does not change, and this can be used to realize a nonvolatile storage function of information. Unlike an ordinary dynamic RAM or the like, an MRAM requires a control line for writing storage contents in addition to a bit line for reading storage contents and a word line for specifying an address of a memory cell.

FIG. 9 shows the structure of a memory element provided in a memory cell of an MRAM. Memory element M
E denotes a ferromagnetic tunnel junction element 10 in which a tunnel insulating layer 13 made of, for example, alumina is sandwiched between a pair of ferromagnetic layers 11 and 12 (made of CoFe, for example), and one of the tunnel junction elements 10 An antiferromagnetic layer 14 (for example, made of MnFe) provided adjacent to the ferromagnetic layer 12 and a lower electrode 15 (for example, , Ti / Pd).
The upper electrode 1 provided in contact with the other ferromagnetic layer 11
6 (for example, composed of Pd / Ti).

A tunnel current flowing through the tunnel insulating layer 13 when a voltage is applied between the upper and lower electrodes 15 and 16 depends on whether the magnetic moment of the pair of ferromagnetic layers 11 and 12 is parallel or antiparallel. It takes two values, large and small. The antiferromagnetic layer 14 has the property of maintaining the direction of the magnetic field regardless of the external magnetic field. Therefore, the direction of the magnetic moment of the ferromagnetic layer 12 adjacent to the antiferromagnetic layer 14 is It is held in one direction regardless of the magnetic field. On the other hand, the magnetic moment of the other ferromagnetic layer 11 can be changed by applying an external magnetic field. The ferromagnetic layer 11 in which the direction of the magnetic moment changes in accordance with the external magnetic field is called a free layer, and the ferromagnetic layer 12 in which the direction of the magnetic moment is maintained regardless of the external magnetic field is called a pinned layer.

FIG. 10 is a schematic sectional view for explaining a cell structure of a magnetic memory using the memory element ME of FIG. The gate of the MOS transistor Tr for selecting a memory cell forms a word line WL. This M
The lower electrode 15 of the memory element ME is connected to the drain of the OS transistor Tr via the node 17 and the like. Then, the upper electrode 1 of the memory element ME
6 is connected to a bit line BL for reading information.

The bit line BL and the word line WL are formed to extend in directions orthogonal to each other. And
A control line CL is provided in parallel with the word line WL. The control line CL is formed at a position where a necessary and sufficient magnetic field can be applied to the memory element ME. For example, it is assumed that the magnetic moment of the pinned layer 12 of the memory element ME is fixed to the right in FIG. Then, a case is considered where the magnetic moment of the free layer 11 is reversed from right to left in FIG. In FIG.
A rightward current is applied to the bit line BL, and a current is applied to the control line CL from the back side to the front side in FIG. Thus, a magnetic field defined by Ampere's law is generated near the free layer 11 of the memory element ME by the current flowing through the bit line BL and the control line CL. More specifically, the magnetic moment of the free layer 11 receives a downward force on the paper surface of FIG. 10 by a magnetic field from the bit line BL, and further, a leftward force of FIG. 10 by a magnetic field from the control line CL. receive. Due to these forces, the magnetic moment of the free layer 11 is caused to change from a rightward state to a rearward state on the paper, and after this state, it is reversed to the left.

Since the magnetic moment of the free layer 11 is stably held to the right or left due to the magnetic anisotropy, the magnetic moment of the free layer 11 after the reversal becomes the value after removing the external magnetic field. Is also stable. In this way, the magnetic moments of the free layer 11 and the pinned layer 12 become antiparallel, and a state in which the tunnel current is small (for example, a state of “0”) can be written. When the magnetic moment of the free layer 11 is set to the right, the direction of the current applied to the control line CL may be set to the reverse of the above case.

At the time of reading information, a voltage is applied to the word line WL, and a MOS connected to the memory element ME is applied.
The transistor Tr is turned on. In this state, when a voltage is applied to the bit line BL and the magnitude of the tunnel current flowing through the memory element ME is detected by a sense amplifier (not shown), the binary data ("" 1 "or" 0 "). That is, if the tunnel current is large, the state of "1" (the state where the magnetic moments of the free layer 11 and the pinned layer 12 are parallel) is read, and if the tunnel current is small, the state of "0" is read. Become.

In this manner, the direction of the magnetic moment of the free layer 11 is controlled by the direction and magnitude of the current flowing through the bit line BL and the control line CL, and the binary information of “0” or “1” is obtained. To remember,
This can be read out. FIG. 11 is an electric circuit diagram for explaining an electric configuration of a conventional MRAM. The plurality of memory cells are arranged in a matrix. Memory cells C11, C12, arranged in the row direction;
The transistors Tr of C21 and C22 are connected to the word line W
L1 and WL2 are shared, and memory cells C11 and C21; C12 and C22 arranged in the column direction are commonly connected to bit lines BL1 and BL2, respectively.

[0011]

An MRAM as described above
Has a bit line BL and a control line CL which are orthogonal to each other above and below the memory element ME.
Need to be placed. Therefore, the memory element M
It is necessary that the control line CL and the node 17 connecting the E and the transistor Tr be formed of the same thin film. For this reason, the density of the memory cells is determined by the pitch of the wiring. Therefore, ultra-fine processing is required for high integration, and further technical development and cost increase are inevitable. Therefore, at present, MRA
There is a problem that high integration of M is difficult.

Further, since the free layer 11 and the pinned layer 12 can only take two states of parallel or anti-parallel, there is a problem that a multilevel memory such as a flash memory cannot be realized. Accordingly, a first object of the present invention is to solve the above-mentioned technical problem and to provide a storage device using a ferromagnetic tunnel junction element having a structure advantageous for high integration. A second object of the present invention is to provide a storage device in which a memory cell structure capable of storing multilevel information is realized by using a ferromagnetic tunnel junction device.

[0013]

According to the first aspect of the present invention, there is provided a ferromagnetic tunnel junction device (10) which is formed by being laminated on a substrate (1). First and second memory elements (ME11, ME21; ME11a, ME11)
b, ME1, ME2) and a first memory element arranged between the first and second memory elements and shared for information rewriting of the first and second memory elements.
And the second memory element disposed on the opposite side of the first memory element from the second memory element and used for rewriting information of the first memory element. Current application line (C
L1, CL1a, CLa) and a third current application disposed on the opposite side of the second memory element from the first memory element and used for rewriting information in the second memory element. Line (CL2, CL
1b, CLb), and a storage device using a ferromagnetic tunnel junction device. However, the alphanumeric characters in the parentheses indicate corresponding components in the embodiments described below for reference. Hereinafter, the same applies in this section.

The ferromagnetic tunnel junction device may have a structure in which a tunnel insulator layer is sandwiched between a pair of ferromagnetic layers. In this case, the memory element includes an antiferromagnetic layer disposed on one ferromagnetic layer side of the ferromagnetic tunnel junction element, and a ferromagnetic layer / tunnel insulating layer / ferromagnetic layer formed in this manner. A configuration may be adopted in which the laminated structure of the antiferromagnetic layer is sandwiched between the upper electrode and the lower electrode. In such a structure, the magnetic moment of the ferromagnetic layer on the antiferromagnetic layer side is held in one direction. This ferromagnetic layer is called a pinned layer. On the other hand, the direction of the magnetic moment of the other ferromagnetic layer changes under the influence of the external magnetic field. This ferromagnetic layer is called a free layer. Accordingly, binary information can be written by applying an appropriate external magnetic field to the memory element and setting the magnetic moment of the free layer to be parallel or anti-parallel to the magnetic moment of the pinned layer. Since the direction of the magnetic moment of the free layer is maintained even after the external magnetic field is removed, nonvolatile storage is achieved. Then, by applying an appropriate read voltage between the upper and lower electrodes and detecting the magnitude of the tunnel current between the ferromagnetic layers, the stored information can be read.

According to the present invention, the first and second memory elements are stacked and arranged on a substrate (for example, a semiconductor substrate), and the first current application line is arranged between the first and second memory elements. Is done. This first current application line can be commonly used for rewriting information stored in the first and second memory elements.
On the other hand, on the opposite side of the second memory element with respect to the first memory element, a second current application line is arranged, and on the opposite side of the first memory element with respect to the second memory element. On the side, a first current application line is arranged.

When a current is applied to the first to third current application lines, a magnetic field corresponding to the magnitude of the current and the distance from the current path is formed according to Ampere's law. Therefore, information can be written to the first memory element by supplying an appropriate current to the first and second current application lines. At this time, the information stored in the second memory element relatively far from the second current application line is not rewritten. Similarly, by supplying an appropriate current to the first and third current application lines, the information stored in the second memory element can be rewritten without affecting the information stored in the first memory element. .

In this manner, 2-bit information can be stored in a memory cell including two memory elements stacked on a substrate. The invention according to claim 2 is
A first read transistor (Tr11) connected to the first memory element for reading stored information of the first memory element; and a first read transistor (Tr11) connected to the second memory element and connected to the second memory element. A second read transistor (Tr2
The storage device according to claim 1, further comprising: (1).

According to this configuration, the information stored in the first and second memory elements is independently read out via the first and second read transistors. Thus, two memory cells capable of storing 1-bit information can be substantially arranged within the occupied area of one memory cell, so that the degree of integration can be improved. Of course, three or more memory elements can be similarly stacked on the substrate, so that three or more memory cells can be substantially arranged in one memory cell arrangement space. Such a configuration is also within the scope of the present invention.

According to a third aspect of the present invention, the first and second memory elements are commonly connected to each other, and the first and second memory elements are connected to each other.
The storage device according to claim 1, further comprising a read transistor (Tr11, Tr) for commonly reading storage information of the second memory element. According to this configuration, the information stored in the first and second memory elements is read out via the common readout transistor.
Bit multivalued information can be stored. That is,
In the first and second memory elements, the magnetic moments of the pinned layer and the free layer can be in a parallel or anti-parallel state, respectively, so that a total of four states can be realized. With the configuration in which the first and second memory elements are commonly connected to the read transistor, four different types of tunnel currents can be detected according to the above four states.

However, if the configurations of the first and second memory elements are the same, the state of the magnetic moment in the first memory element is parallel and the state of the magnetic moment in the second memory element is antiparallel. In some cases, the amount of detected current is equal between the case where the state of the magnetic moment in the first memory element is antiparallel and the state of the magnetic moment in the second memory element is parallel. Therefore, in this case, ternary storage is practically possible.

By making the structures of the first and second memory elements different (especially, by making the area of the ferromagnetic tunnel junction device having the structure of ferromagnetic layer / tunnel insulator layer / ferromagnetic layer different) ) Four values can be stored. The configuration of the third aspect of the present invention may be developed to stack three or more memory elements on a substrate. In this case, a multi-valued memory of 3 bits or more is realized. Such a configuration is also within the scope of the third aspect of the present invention.

According to a fourth aspect of the present invention, the first current application line is shared for reading information stored in the first and second memory elements. The storage device according to any one of the above. In this configuration, since the first current application line is shared between the first and second memory elements not only when information is rewritten but also when information is read, the circuit configuration of the storage device is simplified. Can be.

With such a configuration, for example, one electrode (for example, an electrode on the free layer side) of each of the first and second memory elements is connected to the first current application line, and the first and second memory elements are connected. This is realized by connecting the other electrode of the memory element (for example, the electrode on the pin layer side) to an individual or common read transistor. In this case, the second current application line may be arranged near the other electrode of the first memory element while being insulated from the other electrode. Similarly, the third current application line may be disposed near the other electrode of the second memory element while being insulated from the electrode.

When the first current application line is not used for reading information, the second current application line is connected to the first current application line.
And the third current application line can be used for reading information from the second memory element. In this case, one electrode of the first and second memory elements is connected to the second and third current application lines, respectively, and the other electrodes of the first and second memory elements are individually or commonly read. Connect to transistor. And the first current application line is
It may be provided between the first and second memory elements while being insulated from the other electrode.

According to a fifth aspect of the present invention, there is provided a storage device having a plurality of memory cells arranged in a matrix on a substrate, wherein each memory cell has a first and a second ferromagnetic tunnel junction element. Two memory elements are stacked on the substrate, and the storage device is provided with a plurality of memory cells arranged in a column direction.
And between the second memory element and
A first current application line commonly used for rewriting stored information in the first and second memory elements; and a plurality of memory cells arranged in a row direction, the first current application line being used for the first memory element. A second current application line for rewriting storage information of the first memory element, the second current application line being arranged on a side opposite to the second memory element, and a plurality of memory cells arranged in a row direction. The second memory element is disposed on a side opposite to the first memory element;
Of rewriting the storage information of the memory element of
And a current application line for the ferromagnetic tunnel junction device.

According to the present invention, the memory cell has a structure in which the first and second memory elements are stacked in a direction perpendicular to the substrate, thereby providing a highly integrated storage device using a ferromagnetic tunnel junction device. Can be realized. According to a sixth aspect of the present invention, each memory cell is connected to the first and second memory elements, respectively, and the first and second memory elements are used to read information stored in the first and second memory elements.
And a second read transistor, which is arranged in the row direction with a first word line (WL1) commonly connected to the first read transistor provided in the plurality of memory cells arranged in the row direction. The storage device according to claim 5, further comprising a second word line (WL2) commonly connected to the second read transistor provided in a plurality of memory cells.

According to this configuration, the stored information of the first and second memory elements of each memory cell can be read independently, so that substantially two memory cells are arranged in the area of one memory cell. Can be. By stacking three or more memory elements on a substrate, the degree of integration can be further improved. The invention according to claim 7 is the storage device according to claim 6, wherein the first and second read transistors are formed on the substrate so as to be shifted along the row direction.

According to this configuration, since the first and second read transistors are arranged offset from each other along the word line, the word lines can be easily routed and the storage device can be easily designed. In a preferred embodiment of the present invention, each memory cell is commonly connected to the first and second memory elements and includes a read transistor for commonly reading stored information of the first and second memory elements. The storage device according to claim 5, further comprising a word line (WL1) commonly connected to a gate of said read transistor provided in a plurality of memory cells arranged in a row direction.

With this configuration, a 2-bit multi-valued memory with a high degree of integration can be realized by a structure in which the first and second memory elements are stacked. A multi-valued memory of three bits or more can be realized by stacking three or more memory elements together with the first and second memory elements. According to a ninth aspect of the present invention, the first current application line is a bit line shared for reading information stored in the first and second memory elements. 9. The storage device according to any one of claims 1 to 8,

According to this configuration, the same effect as that of the fourth aspect can be achieved. According to a tenth aspect of the present invention, the third memory element (ME) is provided on the second memory element with the third current application line interposed therebetween.
3) are stacked, and a fourth current application line (BLb) for rewriting the storage information of the third memory element is provided on the opposite side of the third memory element from the second memory element. The storage device according to any one of claims 1 to 9, further comprising:

According to this configuration, since three memory elements are stacked on the substrate, 3-bit information can be stored in the space of one memory cell.
Thereby, the integration degree of the storage device using the ferromagnetic tunnel junction device can be further increased. Writing information to the third memory element is performed by using a third current application line to be shared with the second memory element and a fourth current application line.
By applying an appropriate write current to the current application line. Since the fourth current application line can be arranged sufficiently away from the first and second memory elements, the magnetic field formed by the current applied to this fourth current application line is the first current application line. Alternatively, there is no possibility of rewriting the storage content of the second memory element.

[0032]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an MRAM (magnetic memory device) according to a first embodiment of the present invention.
FIG. 2 is an illustrative sectional view for describing the structure of the memory cell of FIG. 1, and FIG. 2 is an illustrative plan view showing a planar layout thereof. FIG. 1 and FIG. 2 show two memory cells C11 and C21 sharing the bit line BL.

More specifically, a MOS transistor Tr11 for the memory cell C11 and a MOS transistor Tr21 for the memory cell C21 are provided on the semiconductor substrate 1.
Are formed at close positions. The gates of the MOS transistors Tr11, Tr21 are connected to the word lines WL1, W1,
L2. Above the semiconductor substrate 1, a first control line CL1 is formed extending in parallel with the word lines WL1 and WL2 with an interlayer insulating film 2 made of silicon oxide or the like interposed therebetween. Above the first control line CL1, memory elements ME11 and ME21 for the memory cells C11 and C21 are further formed with the interlayer insulating film 3 interposed therebetween. Further, a second control line CL2 is formed above the memory element ME21 so as to extend in parallel with the first control line CL1 with the interlayer insulating film 4 interposed therebetween.

The memory elements ME11 and ME21 are
It has the same structure as the memory element ME shown in FIG. 9 described above. However, the memory element ME21 arranged on the upper side is formed upside down from the case of FIG. In the following, FIG. 9 is referred to as needed. The upper electrodes 16 of the memory elements ME11 and ME21 are commonly connected to the bit line BL1.
The bit line BL1 extends in the left-right direction on the paper surface of FIG. 1, that is, the direction orthogonal to the word lines WL1 and WL2.

On the other hand, the lower electrode 15 of the memory element ME11 is connected to the MOS transistor Tr1
1 connected. Also, the memory element ME21
The lower electrode 15 (located on the upper side in FIG. 1) is connected to the MOS transistor T
r21. The connection portion 5 includes a node 51 formed using the same conductive film when the control line CL1 is formed, and a node 51 and the memory element ME.
11 includes a plug 52 connecting the lower electrode 15 and the plug 51 connecting the node 51 and the drain of the transistor Tr11. The connection portion 6 includes a node 61 formed by using the same conductive film when forming the control line CL2, a node 62 formed by using the same conductive film when forming the bit line BL1, a control line CL1 and a node. 51 and the node 63 formed using the same conductive film when forming 51. The lower electrode 15 of the memory element ME21 and the node 61 are connected by a plug 64, and the node 61 and the node 62
Are connected by a plug 65, the node 62 and the node 63 are connected by a plug 66, and the node 63 and the drain of the transistor Tr21 are connected by a plug 67.

As shown in FIG. 2, the MOS transistors Tr11 and Tr21 are juxtaposed along the extending direction of the bit line BL1. In order to avoid intersection with the bit line BL1, the lower electrode 15 of the memory element ME21 is formed in an L shape. And MO
The connection portion 6 for connecting the S transistor Tr21 and the lower electrode 15 is formed substantially perpendicular to the semiconductor substrate 1 at a position avoiding the bit line BL1.

The plane layout can be changed as required. However, in consideration of the ease of routing the word lines WL1 and WL2, the plane layout shown in FIG. 3 is preferably used. In the layout shown in FIG. 3, the lower electrode 15 of the memory element ME21 is formed in an L shape so as to be drawn out of the position avoiding the bit line BL1, and the transistors Tr11 and Tr21 are connected to the control line C2.
The extending direction of L1 and CL2 (that is, the word line WL
1, WL2). Then, the lead portion 15a of the L-shaped lower electrode 15
Is connected to the MOS transistor Tr21 via the connection section 6.

FIG. 4 is an electric circuit diagram for explaining the electric configuration of the MRAM of this embodiment. Semiconductor substrate 1
At the top, a large number of memory cells are arranged in a matrix, but FIG. 4 shows only four memory cells.
A plurality of memory cells C11 and C12 aligned in the row direction
Is a word line WL1 and a control line CL
Share one. Then, the memory cells C11 and C12
Above the memory elements ME11 and ME12, the memory elements ME21 and ME22 of a plurality of memory cells C21 and C22 also arranged in the row direction are stacked by the structure shown in FIGS. By providing such a structure in a plurality of rows, a large number of memory cells are arranged on the semiconductor substrate 1.

As described above, the memory cells C11,
C21 shares the bit line BL1, and the bit line BL1 has the memory elements ME11, ME
21 are connected. The memory element ME11 is
MOS controlled by a signal from word line WL1
The memory element ME21 is connected to the transistor Tr11, and is connected to the MOS transistor Tr21 controlled by a signal from the word line WL2.

Similarly, the memory cells C12 and C22 share the bit line BL2.
The memory elements ME12 and ME22 are commonly connected to L2 as in the case of the memory elements ME11 and ME21. The memory element ME12 is connected to a MOS transistor Tr12 controlled by a signal from the word line WL1.
Reference numeral 22 is connected to a MOS transistor Tr22 controlled by a signal from the word line WL2.

The write operation for the memory cell C11 will be described. In the memory element ME11 of the memory cell C11, it is assumed that the magnetic moment of the pinned layer 12 is rightward in FIG. The magnetic moment of the free layer 11 is in a state parallel to the magnetic moment of the pinned layer 12 (that is, rightward in FIG. 1; defined as “1” state). A case where the moment is reversed to a state antiparallel to the magnetic moment of the pinned layer 12 (that is, leftward in FIG. 1, defined as “0” state) will be considered.

First, in FIG. 1, a current of, for example, 10 mA is applied to the bit line BL1 rightward. Further, for example, 30 m
The current A is applied in a direction from the back to the front in FIG. At this time, no current flows through the control line CL2. Free layer 11 of memory element ME11
Near the bit line BL1 and the control line CL
1 generates a magnetic field according to Ampere's law. That is, the magnetic moment of the free layer 11 receives a force facing down on the plane of FIG. 1 by the magnetic field from the bit line BL1, and
Due to the magnetic field from L, a leftward force in FIG. 1 is received. Due to these forces, the direction of the magnetic moment of the free layer 11 of the memory element ME11 changes from rightward to rearward to leftward.

Because of the magnetic anisotropy, the magnetic moment of the free layer 11 is stably held in either the rightward or leftward direction in FIG. 1, so that the magnetic moment of the free layer 11 of the memory element ME11 is inverted. Even if the external magnetic field is removed, it is held to the left. As a result, the magnetic moments of the free layer 11 and the pinned layer 12 become antiparallel, and a state where the tunnel current is small, that is, a state of “0” can be written in a nonvolatile manner.

Free layer 11 of memory element ME21
, A magnetic field from the bit line BL1 is applied in the direction of the paper surface of FIG. However, since the free layer 11 is located relatively far from the control line CL1, the magnetic field from the control line CL1 is weak. The magnetic field formed by the current flowing through the control line CL1 is shielded by the pit line BL1. Therefore, the direction of the magnetic moment of the free layer 11 of the memory element ME21 does not reverse. That is, the direction of the magnetic moment of the free layer 11 of the memory element ME21 returns to the original direction after the current application to the bit line BL1 is stopped. Therefore, the information stored in the memory cell C21 does not change.

At this time, no current for writing information is applied to the bit line BL2, so that the memory cell C
12, C22 does not change. When the information to be written to the memory cell C11 is “1”, the direction of the current of the control line CL1 in the above case may be reversed. Next, an operation for reading information stored in the memory cell C11 will be described. In this case, a voltage for turning on the MOS transistor Tr11 is applied to the word line WL1. The word line WL2 is
The voltage is set such that MOS transistor Tr21 can be turned off. In this state, the bit line BL1
Is applied to the bit line B to determine the magnitude of the tunnel current flowing through the memory element ME11 of the memory cell C11.
By detecting with a sense amplifier (not shown) connected to L1, it is possible to identify whether the storage information of the memory cell C11 is "1" or "0". That is,
If the amount of tunnel current is large, the state of "1" is read, and if the amount of tunnel current is small, the state of "0" is read. Note that the bit line BL
Since no voltage for reading information is applied to 2, no information is read from the memory cells C12 and C22.

Since information erasing is achieved by writing an initial value (for example, "0") to each memory cell, no special erasing operation is required. As described above, according to the MRAM of this embodiment, the pair of memory elements ME11 and ME21 are stacked and arranged above and below the bit line BL1, thereby forming the pair of memory elements ME1.
1, the bit line BL1 is shared by ME21. Thereby, the memory elements ME11 and ME21 for two cells can be formed with an area of substantially one cell. Thereby, a large number of memory cells can be integrated on the semiconductor substrate 1 having a small area, so that an MRAM with a very high degree of integration can be realized.

FIG. 5 is an illustrative sectional view for explaining the memory cell structure of the MRAM according to the second embodiment of the present invention. FIG. 6 is a plan view for explaining a planar layout of the memory cell structure shown in FIG. 5 and FIG. 6, parts corresponding to the respective parts shown in FIG. 1 and FIG. 2 described above are denoted by the same reference numerals as in FIG. 1 and FIG. Unlike the case of the first embodiment described above, in the second embodiment,
Two memory elements ME are stored in one memory cell C11.
11a and ME 11b are provided in a stacked manner. Thus, in the MRAM according to the second embodiment, multi-value information can be stored in one memory cell. The memory elements ME11a and 11b have the same structure as the memory element ME in FIG.

The specific configuration will be described. The lower electrodes 15 of the memory elements ME11a and ME11b which are vertically stacked so as to share the bit line BL1 are
Both are connected to the same MOS transistor Tr11. That is, the lower electrode 15 of the memory element ME11a is connected to the MOS transistor Tr1 via the connection portion 5.
1 drain. Similarly, the lower electrode 15 of the memory element ME11b is connected to the drain of the MOS transistor Tr11 via another connection 6.

As shown in FIG. 6, the lower electrode 15 of the upper memory element ME11b is formed in an L-shape and has a lead-out portion 15a drawn to a position avoiding the bit line BL1. ing. The lead portion 15a is connected to the MOS transistor T via the connection portion 6.
It is connected to the drain of r11. The direction of the magnetic moment of each free layer 11 of the memory elements ME11a and ME11b is determined by the direction of the first control line CL1a provided below the memory element ME11a via the interlayer insulating film 3, the bit line BL1, and the memory element ME11b. By individually controlling the current applied to the second control line CL1b provided above via the interlayer insulating film 4, the current can be controlled independently of the free layer 11 of each other memory element.

That is, the second control line CL
1b with no current applied to the bit line BL
By applying an appropriate write current to the first control line CL1a and the first control line CL1a, the direction of the magnetic moment of the free layer 11 of the memory element ME11a can be controlled, and "0" or "1" is applied to the memory element ME11a.
Information can be written. Similarly, when no current is applied to the first control line CL1a,
Bit line BL1 and second control line C
When an appropriate current is applied to L1b, the memory element M
The direction of the magnetic moment of the free layer 11 of E11b can be controlled, and information can be written to the memory element ME11b.

Therefore, memory element ME11
a, ME11b includes (0, 0), (1, 0)
Four types of information (0, 1) and (1, 1) can be written. However, the memory elements ME11a, ME
11b is commonly connected to the MOS transistor Tr11, and can only detect the sum of the tunnel currents of the respective memory elements at the time of reading information. Therefore, after all, three values of “00”, “01”, and “11” can be stored in binary notation.

Memory elements ME11a, ME11b
If the area of the ferromagnetic tunnel junction device 10 is changed,
The tunnel current is supplied to the memory elements ME11a and ME11.
b. This gives (0,
If four kinds of currents can be detected according to four kinds of storage states of (0), (1, 0), (0, 1), and (1, 1), "00" and "01" are represented in binary notation. "10" and "11" can be stored.

FIG. 7 is an electric circuit diagram for explaining an electric configuration of the MRAM according to this embodiment. This FIG.
Although FIG. 1 shows an electrical configuration related to four memory cells, actually, a larger number of memory cells are formed in a matrix on the semiconductor substrate 1. Memory cells C11, C12, C21, C22
Are respectively a pair of memory elements ME11a,
ME11b; ME12a, ME12b; ME21a, M
E21b has ME22a and ME22b. Each pair of these memory elements ME11a, ME11
b; ME12a, ME12b; ME21a, ME21
b; ME22a and ME22b are commonly MOS
Transistors Tr11, Tr12, Tr21, Tr22
It is connected to the. Memory cells C aligned in the row direction
The gates of the transistors Tr11 and Tr12 of the transistors C11 and C12 are commonly connected to the word line WL1, and the gates of the MOS transistors Tr21 and Tr22 of the memory cells C21 and C22 which are similarly arranged in the row direction are commonly connected to the word line WL1. It is connected to the line WL2.

The memory cells C11,
In connection with C21, the first control line CL1a
And a second CL1b is formed in parallel with the word line WL1. The first control line CL2a and the second control line CL2 also relate to the memory cells C21 and C22 which are also aligned in the row direction.
2b are formed parallel to the second word line WL2. When writing information to the memory cell C11, an appropriate write current is applied to the bit line BL1 and the first and second control lines CL1a and CL1b. At this time, no write current is applied to the first and second control lines CL2a and CL2b corresponding to the bit line BL2 and the memory cells C21 and C22. Thus, the direction of the magnetic moment of the free layer 11 of the memory elements ME11a and ME11b is set only in the memory cell C11.

When reading the storage information of the memory cell C11, the memory cells C11 and C1 are connected to the word line WL1.
A read voltage for conducting the two MOS transistors Tr11 and Tr12 is applied. At this time, no read voltage is applied to the other word lines WL2. And
Without applying a voltage to the bit line BL2, the memory cell C1
An appropriate read current is applied only to the bit line BL1 corresponding to 1. Along with this, a sense amplifier (not shown)
Thus, the amount of current flowing through the bit line BL1 is detected.

The amount of current detected at this time is three types (the ferromagnetic tunnel junction device 10) according to the state of the magnetic moment in the memory elements ME11a and ME11b.
If the areas are appropriately different, four values are taken. Note that since no read voltage is applied to the word line WL2, the transistors Tr21 and Tr22 in the memory cells C21 and C22 are kept in the cutoff state. Then, a voltage for reading is not applied to the bit line BL2 corresponding to the memory cell C12. Therefore, when reading the storage information of the memory cell C11, information from another memory cell is not read.

Erasure of information is achieved by writing an initial value (for example, “0”) to each memory cell, and no special erase operation is required. FIG. 8 is an illustrative sectional view for explaining the structure of the MRAM according to the third embodiment of the present invention. FIG. 8 shows four memory elements ME1 and ME1 having the same configuration as memory element ME in FIG.
A structure in which ME2, ME3, and ME4 are stacked in a direction perpendicular to the semiconductor substrate 1 is shown. These four memory elements ME1 to ME4 are commonly connected to a MOS transistor Tr on the semiconductor substrate 1.

Information "0" or "1" can be written in each of the four memory elements ME1 to ME4. As a result, 4-bit information can be stored in the memory cell C. Specifically, the memory element ME
The set of stored values of 1 to ME4 can take the following 16 types of states. (0000) (0001) (0010) (0011) (0100) (0101) (0110) (0111) (1000) (1001) (1010) (1011) (1100) (1101) (1110) (1111) , Multi-value information can be stored in one memory cell C. By arranging a large number of such memory cells C in a matrix on the semiconductor substrate 1, a highly integrated multi-level MRAM can be realized.

However, the four memory elements ME1 to ME1
When the ME 4 has a similar structure, the current value detected when the read operation is performed by turning on the MOS transistor Tr takes five values. Therefore, quinary data can be stored in one memory cell. If the areas of the ferromagnetic tunnel junction elements 10 of the memory elements ME1 to ME4 are made different, the total tunnel current of the four memory elements ME1 to ME4 becomes 16 at the maximum.
Can be changed to the type. Therefore, at most 1
Data up to six values can be stored in one memory cell.

The structure will be described in detail. On the semiconductor substrate 1, one MOS transistor Tr shared by four memory elements ME1 to ME4 is formed. The gate of the MOS transistor Tr is
A word line WL extending in a direction perpendicular to the plane of FIG. 8 is formed. A first control line CLa is formed above the word line WL via an interlayer insulating film 2, and a first memory element ME1 is formed above the word line WL via an interlayer insulating film 3. . Above the first memory element ME1, a second memory element ME2 is stacked via a first bit line BLa. Further, the second memory element ME
A second control line CLb is provided above the second memory element ME via an interlayer insulating film 9 and an interlayer insulating film 4.
3 are stacked. Above the memory element ME3, a fourth memory element ME4 is stacked via the second bit line BLb. Further, a third control line CLc is provided above the fourth memory element ME4 via an interlayer insulating film 10.

First to third control lines CL
a to CLc are formed parallel to the word line WL. On the other hand, the first and second bit lines BLa, BL
b is formed along a direction crossing the word line WL. The first control line CLa is used for rewriting information of the memory element ME1, and is used for the second control line CLa.
Of the memory element ME
2, the third control line CLc is commonly used for rewriting the storage information of ME3, and the third control line CLc is used for rewriting of the storage information of the memory element ME4. The first bit line BLa is connected to the memory element M
E1 and ME2 are commonly used for rewriting the stored information and reading the stored information from these memory elements, and the second bit line BLb is connected to the memory element M
It is commonly used for rewriting the storage information of E3 and ME4 and for reading the storage information from these memory elements.

Each of the lower electrodes 15 of the memory elements ME1 to ME4 is commonly connected to the drain of the transistor Tr through the connection portions 5, 6, 7, and 8, respectively. A voltage can be independently applied to the first to third control lines CLa to CLc. Also,
Similarly, the first and second bit lines BLa and BLb can be independently applied with a voltage. However, the first and second bit lines BLa, BLa,
BLb is used to read information from the memory cell C.
A voltage for reading is commonly applied, and the currents led to the first and second bit lines BLa and BLb are commonly detected by a sense amplifier.

Writing of information to memory element ME1 is achieved by applying a write current to each of first bit line BLa and first control line CLa. At this time, unless a write current is applied to the control line CLb, the direction of the magnetic moment of the free layer 11 of the memory element ME2 does not change. Writing of information to the memory element ME2 is achieved by applying a write current to the first bit line BLa and the control line CLb. At this time, the first control line CLa
If no write current is applied to memory element ME
Writing of information to 1 does not occur. Also, the second
Unless a current for writing is applied to the bit line BLb, writing of information to the memory element ME3 does not occur.

Writing information to memory element ME3 can be performed in the same manner. That is, if a current for writing information is applied to the second control line CLb and the second bit line BLb, respectively, the direction of the magnetic moment of the free layer 11 of the memory element ME3 can be set to a desired direction. At this time, the control line CL
If no write current is applied to the memory element ME
No information writing to 4 occurs. Unless a current for writing is applied to the first bit line BLa, writing of information to the memory element ME2 does not occur.

Further, writing of information to memory element ME4 is achieved by applying a write current to each of second bit line BLb and third control line CLc. At this time, unless a current for writing is applied to the second control line CLb, writing of information to the memory element ME3 does not occur. According to Ampere's law, a strong magnetic field is not formed at a position far enough from the current path,
Since the magnetic field is shielded by bit lines BLa and BLb, for example, memory elements ME1 and ME
4 may be written in parallel. That is, the first and third control lines CLa, C
Lc, and the first and second bit lines BLa,
A write current is applied to BLb. At this time, no write current is applied to the control line CLb. Thereby, the memory elements ME1, M
The direction of the magnetic moment in each free layer 11 of E4 can be set.

As described above, when the configuration of this embodiment is adopted, a multi-valued MRAM capable of storing 5- to 16-value data in one memory cell can be realized. Similarly, if a large number of memory elements are stacked in a direction perpendicular to the semiconductor substrate 1, a multi-valued memory having a larger number of values can be realized.
In the configuration of this embodiment, the bit line and the control line are shared between a pair of adjacent memory elements, so that the number of wirings can be reduced, the configuration is relatively simple, and the integration degree is high. MRAM
Can be achieved.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above-described first embodiment, the bit line BL1 is shared by the pair of memory elements ME11 and ME21 stacked in the direction perpendicular to the semiconductor substrate 1, but the pair of memory elements ME11 , ME21, a control line may be arranged, and this control line may be shared by the memory elements ME11, ME21. In this case, a bit line is connected to the lower end of the memory element ME11 and the memory element ME21 is connected.
Another bit line may be connected to the upper end of the bit line.

Further, in the configuration of FIG. 1, another memory element may be arranged above control line CL2, and this other memory element may be connected to a read transistor provided on semiconductor substrate 1. .
In this case, above the memory element of the third layer,
A bit line connected to the memory element may be provided. Thus, the control line CL2 can be shared for writing information to the memory element ME21 and another memory element. Then, substantially three memory cells can be arranged in the space of one memory cell. Similarly, by arranging four or more memory cells in an area corresponding to one memory cell, a highly integrated MRAM can be realized.

In the above embodiment, the memory element having the configuration shown in FIG. 9 is used. However, another configuration can be adopted for the memory element. For example, instead of alumina, GdO, Ta ₂ O ₅ , HfO ₂ , NiO, Mg
O may be applied, and Co, NiFe, LaSrMn may be used for the ferromagnetic layers 11 and 12 instead of CoFe.
O ₃ and CrO ₂ may be applied.

In addition, various design changes can be made within the technical scope described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view for explaining a structure of a memory cell of an MRAM according to a first embodiment of the present invention;

FIG. 2 is an illustrative plan view showing a layout of the MRAM.

FIG. 3 is an illustrative plan view showing another example of the layout of the MRAM.

FIG. 4 is an electric circuit diagram for explaining an electric configuration of the MRAM according to the first embodiment.

FIG. 5 is an illustrative sectional view for explaining a memory cell structure of an MRAM according to a second embodiment of the present invention;

FIG. 6 is a plan view illustrating a layout of the memory cell structure shown in FIG. 5;

FIG. 7 is an electric circuit diagram for explaining an electric configuration of the MRAM according to the second embodiment.

FIG. 8 is an illustrative sectional view for explaining the structure of an MRAM according to a third embodiment of the present invention.

FIG. 9 is a cross-sectional view for describing a configuration of a memory element of the MRAM.

FIG. 10 is an illustrative sectional view for explaining a memory cell structure of a conventional MRAM.

FIG. 11 is an electric circuit diagram for explaining an electric configuration of a conventional MRAM.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 5 connection portion 6 connection portion 10 ferromagnetic tunnel junction element 11 free layer (ferromagnetic layer) 12 pin layer (ferromagnetic layer) 13 tunnel insulating layer 14 antiferromagnetic layer 15 lower electrode 16 upper electrode BL1 Bit line BL2 Bit line BLa Bit line BLb Bit line C11 memory cell C12 memory cell C21 memory cell C22 memory cell C memory cell CL1 control line CL2 control line CL1a control line CL1b control line CL2a control line CL2b control line CLa control line CLb control line CLc Control line ME11 Memory element ME12 Memory element ME21 Memory element ME22 Memory element Cement ME11a memory element ME11b memory element ME1~ME4 memory element Tr11 transistor Tr12 transistor Tr21 transistor Tr22 transistor Tr transistor WL1 word line WL2 word line WL word line

Claims (10)

[Claims] A first memory element having a ferromagnetic tunnel junction element, the first memory element having a ferromagnetic tunnel junction element, and a first memory element having a ferromagnetic tunnel junction element. A first current application line shared for rewriting information of first and second memory elements; and a first current application line disposed on a side opposite to the second memory element with respect to the first memory element; A second current application line used for rewriting information of the memory element, and a second current applying line disposed on a side opposite to the first memory element with respect to the second memory element; And a third current application line used for rewriting. A memory device using a ferromagnetic tunnel junction device, comprising: 2. The semiconductor device according to claim 1, wherein said first memory element is connected to said first memory element.
A first read transistor for reading the storage information of the first memory element; and a second read transistor connected to the second memory element for reading the storage information of the second memory element. 2. The method of claim 1, further comprising:
A storage device as described. 3. The semiconductor device according to claim 1, further comprising a read transistor commonly connected to said first and second memory elements, for reading out common information stored in said first and second memory elements. Item 2. The storage device according to Item 1. 4. The device according to claim 1, wherein said first current application line is shared for reading stored information of said first and second memory elements. Storage device. 5. A storage device comprising a plurality of memory cells arranged in a matrix on a substrate, wherein each memory cell includes first and second memory elements each having a ferromagnetic tunnel junction element. The storage device is stacked on a substrate, and the storage device is disposed between the first and second memory elements provided in a plurality of memory cells aligned in a column direction, and the first and second storage elements are arranged. A first current application line commonly used for rewriting storage information in a second memory element; and a second memory element with respect to the first memory element in a plurality of memory cells arranged in a row direction. And a second current application line for rewriting the storage information of the first memory element, and a plurality of lines arranged in the row direction. And a third current application line for rewriting storage information of the second memory element, the memory cell being disposed on the memory cell through a side opposite to the first memory element with respect to the second memory element. A storage device using a ferromagnetic tunnel junction device. 6. A memory cell connected to the first and second memory elements, respectively, and a first memory cell for reading information stored in the first and second memory elements.
A first word line commonly connected to the first read transistor provided in a plurality of memory cells aligned in the row direction; and a plurality of memories aligned in the row direction. The storage device according to claim 5, further comprising a second word line commonly connected to the second read transistor provided in the cell. 7. The memory device according to claim 6, wherein said first and second read transistors are formed on said substrate so as to be shifted along said row direction. 8. Each of the memory cells further includes a read transistor commonly connected to the first and second memory elements, and commonly reading storage information of the first and second memory elements. 6. The storage device according to claim 5, further comprising a word line commonly connected to gates of said read transistors provided in a plurality of memory cells arranged in a row direction. 9. The system according to claim 1, wherein the first current application line is
9. The storage device according to claim 5, wherein the storage device is a bit line shared for reading storage information of the second memory element. 10. A third memory element is further laminated on the second memory element with the third current application line interposed therebetween, wherein the third memory element is stacked on the second memory element. The storage device according to any one of claims 1 to 9, wherein a fourth current application line for rewriting information stored in the third memory element is provided on a side opposite to the memory element. .