JP2003100905A - Mask pattern, evaluation sample manufacturing method for semiconductor device, and evaluation method for semiconductor evaluation sample - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the manufacturing of an evaluation sample easily and in a short time, to enable the execution of reliable evaluation, and to enable the easy identification of a defect. SOLUTION: Storage node contacts are formed in checkers on a silicon substrate by mask patterns 101 disposed in checkers. Thereafter, by storage node patterns 102, storage nodes are disposed on the whole surface like an ordinary cell array. The storage nodes are alternately conducted to the silicon substrate through the storage node contacts. When the evaluation sample is observed by SEM, it is seen a contrast difference by the storage node conducted to the substrate and the storage node being open.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a mask pattern,
The present invention relates to a method for preparing an evaluation sample for a semiconductor device and an evaluation method for a semiconductor evaluation sample.

[0002]

2. Description of the Related Art In the development of semiconductor devices, DRA
In the case of repeated patterns of the same shape such as M cells, it is necessary to evaluate contact openness, short-circuiting defects with adjacent patterns, etc. in a number barrier manner.

[0003]

By the way, in the above-described semiconductor device evaluation method, for example, in the case of a short between storage nodes, there is the following evaluation method.

Electrical Evaluation As shown in FIG. 5, the pattern of the storage node layer 1 is formed in a comb shape, and the presence or absence of a short circuit is determined by the value of the current flowing through the adjacent line 2. In this case, there is a problem that a long line pattern collapses as the cell size decreases. Further, since the actual storage node pattern and the line pattern have different taper shapes and different diameters / spaces, there is a problem that accurate evaluation cannot be performed.

Further, as shown in FIG. 6, the storage node 3 is dropped to a comb-shaped bit line 5 or a diffusion layer via a node contact 4, and a short circuit between the storage nodes 3 is evaluated in the form of a short circuit between these wirings. There is a way to do it. In this case, a defective element other than the storage node, such as a bit line 5 or a diffusion interlayer short circuit, is also included. Therefore, there is a problem that a short circuit in the direction along the bit line 5 or the diffusion layer cannot be detected. Also, if the wiring resistance is large (especially in a large capacity cell array),
There is a problem that it is difficult to distinguish the leakage current between open storage nodes. In addition, in the electrical evaluation according to the related art, there is a problem that a defective portion (defective bit) cannot be specified.

Evaluation from shape In the evaluation method of directly observing the array pattern optically,
It is possible to specify a defective portion and a defective factor such as dust. However, there is a problem that the space between the storage nodes becomes difficult to recognize as the cell size decreases. In addition, when the surface roughness of the storage node is increased by using HSG or the like for expanding the cell capacity, it is more difficult to identify the cause of the defect due to light scattering. The evaluation method of observing by SEM solves the problems in the evaluation method of optically observing as described above. However, when the storage node becomes high, the bottom part becomes difficult to see, which causes a problem that accurate evaluation becomes difficult.

As described above, the conventional method for evaluating a semiconductor device has a problem that it takes a long time for trial manufacture, an accurate evaluation result cannot be obtained, and a defective portion cannot be specified.

Therefore, according to the present invention, an evaluation sample can be easily prepared in a short time, a reliable evaluation can be made, and a defective portion can be easily specified. An object of the present invention is to provide a method and a method for evaluating a semiconductor evaluation sample.

[0009]

In order to achieve the above object, the mask pattern according to the invention of claim 1 is a mask pattern used when an evaluation sample of a semiconductor device is formed, and a node contact is formed on a substrate. It is characterized in that the node contact patterns of the node contact mask used when performing are arranged in a checkered pattern.

As a preferred embodiment, for example, as in claim 2, in the mask pattern according to claim 1, a node pattern of a node pattern mask used when forming a node located in an upper layer of the node contact pattern. May be arrayed on the entire surface.

In order to achieve the above object, in the method for preparing an evaluation sample for a semiconductor device according to the invention of claim 3, the node contacts are formed in a checkered pattern on the substrate, and the array is formed on the entire upper surface of the node contacts. It is characterized by forming arranged nodes.

As a preferred aspect, for example, as described in claim 4, in the method for preparing an evaluation sample for a semiconductor device according to claim 3, the node is electrically connected to the substrate through the node contact. Good.

In order to achieve the above object, the semiconductor evaluation sample evaluation method according to the invention of claim 5 is an evaluation sample in which node contacts are formed in a checkered pattern on a substrate and nodes are formed on the node contacts. Is evaluated by the difference in the contrast of the images observed by the scanning electron microscope.

In the present invention, the node contact patterns of the node contact mask used when forming the node contacts on the substrate are arranged in a checkered pattern. As a result, every other storage node is electrically connected to the silicon substrate via the storage node contact. Therefore, the evaluation sample can be easily created in a short time. In addition, this evaluation sample is SEM
When observed with, it is observed as a difference in contrast between the storage node electrically connected to the substrate and the open storage node, so it is possible to make a reliable evaluation and easily identify the defective part. .

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a mask pattern of a storage node contact and a storage node pattern used in the semiconductor device evaluation method according to the embodiment of the present invention. As shown in FIG. 1, the mask pattern 101 of the storage node contact is arranged in a checkered pattern. Storage node pattern 102 on it
Are arranged on one surface like a normal cell array. Using this mask pattern 101, an evaluation sample as described below is formed.

First, as shown in FIG. 2A, an insulating film 202 (for example, L
P-TEOS: 300 nm) is formed. Next, FIG.
As shown in (b), the mask pattern 101 shown in FIG.
Patterning is performed to open a contact hole, and a conductive film (for example, Phos dopedP) is used.
The contact 203 is formed by embedding poly-Si).

Next, as shown in FIG. 2C, a core film 204 (for example, LP-T) which becomes a core of the storage node is formed.
EOS 1000 nm) is formed. After that, patterning is performed using the storage node pattern 102 in FIG. 1 to open the core film 204 in the portion where the storage node is to be formed.

Next, a conductive film (for example, Phos doped Poly-Si: 5) to be the storage node 205 is formed.
0 nm) is deposited and the upper part is removed by, for example, CMP,
By removing the core film 204 (for example, etching by DHF), the capacitor portion of the DRAM as shown in FIG. 2D is formed.

At this time, the storage node contact 2
Another storage node adjacent to the storage node 205 electrically connected to the silicon substrate 201 via 03 is
It is open because there is no storage node contact 203 at the bottom.

When this evaluation sample is observed by SEM,
As shown in Fig. 3, there is a difference in contrast between the storage node conducting to the substrate and the open storage node due to the difference between the emitted electrons leaving the substrate and the ones charged in the node. To be

Here, the one conducting to the substrate is "black",
If the person who is open is looking at "white",
When there is a short circuit defect between the adjacent storage nodes, the node (open), which should be originally observed as “white”, conducts to the substrate. Therefore, as shown in FIG.
It is observed by reversing to "black". On the contrary, if there is an open defect in the node conducting to the board,
What should be "black" is observed as "white".

As described above, according to the present embodiment, by using the zigzag arrangement pattern, there is no need for an electrical evaluation, which takes a long time for trial production, has uncertain results, and cannot identify a defective portion, as has been conventionally done. , SEM observation only makes it possible to find open / short defects and identify the location. Further, by using the automatic defect inspection apparatus by SEM, it is possible to further reliably perform defect evaluation in a large-scale array in a short time.

[0023]

According to the first aspect of the present invention, since the node contact pattern of the node contact mask used when forming the node contact on the substrate is arranged in a checkered pattern, one storage node is provided. In addition, it will conduct to the silicon substrate through the storage node contact. Therefore, there is an advantage that the evaluation sample can be easily prepared in a short time. Further, when this evaluation sample is observed by SEM, it is observed as a difference in contrast between the storage node electrically connected to the substrate and the open storage node, so that a reliable evaluation can be made and the defective portion can be easily identified. The advantage is that it can be done.

According to the second aspect of the invention, the node patterns of the node pattern mask used when forming the nodes located in the upper layer of the node contact pattern are arrayed on the entire surface. There are advantages that the sample can be easily created in a short time, the reliable evaluation can be made, and the defective portion can be easily specified.

According to the third aspect of the invention, the node contacts are formed in a checkered pattern on the substrate, and the nodes arranged in an array are formed on the entire surface of the upper layer of the node contacts. The advantages are that an evaluation sample can be easily created in a short time, a reliable evaluation can be made, and a defective portion can be easily specified.

According to the invention described in claim 4, the node is electrically connected to the substrate through the node contact, so that an evaluation sample can be easily prepared in a short time, and the evaluation sample can be surely obtained. It is possible to make various evaluations, and it is possible to easily identify a defective portion.

Further, according to the invention of claim 5, the evaluation sample in which the node contacts are formed in a checkerboard pattern on the substrate and the nodes are formed on the node contacts is observed by a scanning electron microscope. Since the evaluation is performed based on the difference between, the advantages that the evaluation sample can be easily prepared in a short time, the reliable evaluation can be made, and the defective portion can be easily specified can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a storage node contact mask pattern and a storage node pattern used in a semiconductor device evaluation method according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a procedure for manufacturing an evaluation sample according to the present embodiment.

FIG. 3 is a schematic diagram showing a state of SEM observation of an evaluation sample according to the present embodiment.

FIG. 4 is a schematic view showing a state of SEM observation when there is a defect in the evaluation sample according to the present embodiment.

FIG. 5 is a schematic diagram showing a pattern of a storage node for performing conventional electrical evaluation.

FIG. 6 is a schematic diagram showing a pattern of a storage node for performing conventional electrical evaluation.

[Explanation of symbols]

101 ... Mask pattern (node contact mask node contact pattern), 102 ... Storage node pattern (node pattern mask node pattern), 201 ... Silicon substrate (substrate), 202 ... Insulating film, 203 ... Contact, 204 ... Core film, 20
5 ... Storage node

Claims (5)

[Claims] 1. A mask pattern used when forming an evaluation sample of a semiconductor device, wherein the node contact patterns of a node contact mask used when forming node contacts on a substrate are arranged in a checkered pattern. Mask pattern to be used. 2. The mask pattern according to claim 1, wherein a node pattern of a node pattern mask used for forming a node located in an upper layer of the node contact pattern is arrayed on the entire surface. 3. A method for preparing an evaluation sample for a semiconductor device, comprising forming node contacts in a checkerboard pattern on a substrate, and forming nodes arranged in an array on the entire surface of an upper layer of the node contacts. 4. The method for producing an evaluation sample for a semiconductor device according to claim 3, wherein the node is electrically connected to the substrate through the node contact. 5. An evaluation sample in which node contacts are formed in a checkerboard pattern on a substrate and the nodes are formed on the node contacts are evaluated by a difference in contrast of an observation image by a scanning electron microscope. Evaluation method of semiconductor evaluation sample.