CN220439615U - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 238000012360 testing method Methods 0.000 claims abstract description 236
- 229910052751 metal Inorganic materials 0.000 claims abstract description 211
- 239000002184 metal Substances 0.000 claims abstract description 211
- 239000010410 layer Substances 0.000 claims abstract description 156
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 25
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 33
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 description 33
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 description 33
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 description 13
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 13
- 101150092599 Padi2 gene Proteins 0.000 description 13
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 description 13
- 238000010894 electron beam technology Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000523 sample Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 239000007769 metal material Substances 0.000 description 4
- 238000013102 re-test Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The present utility model relates to a semiconductor device. The semiconductor device comprises a semiconductor substrate, a first interlayer dielectric layer formed on the semiconductor substrate, a plurality of contact plugs and at least one through hole test structure, wherein the through hole test structure comprises at least one first test through hole electrically connected with a first metal pad, the through hole test structure is isolated from other electrical components above the semiconductor substrate, the structure of the first test through hole can be arranged according to the requirement, and the through hole test structure can be designed into a large test structure to cover a larger area by adjusting the number of the test through holes of each layer, so that the cost is low and the influence of other processes on the semiconductor substrate is not easy to occur.
Description
Technical Field
The present utility model relates to the field of integrated circuit fabrication, and more particularly, to a semiconductor device.
Background
In the fabrication of semiconductor devices, after electronic components (e.g., transistors) are formed on the surface of a substrate, a multi-layered electrical interconnect structure is typically formed over the substrate, including multiple patterned conductive layers separated by dielectric materials and metal vias (via) connecting adjacent conductive layers, with the lowermost conductive layer being connected to the substrate by a contact plug (contact).
Along with the development of the semiconductor technology node to the smaller and smaller direction, the distance between the conductive layers in the multi-layer electrical interconnection structure is reduced, the size of the metal through hole is also reduced, in order to form the metal through hole, the difficulty of etching to form a high aspect ratio through hole and filling metal in the through hole is increased, and the connectivity of the formed metal through hole needs to be detected in time in the process, so that the problems existing in the manufacturing process can be found as soon as possible, and the loss is reduced.
The prior art adopts WAT (wafer acceptance test) to detect connectivity of the metal through holes, but WAT cannot carry out selective inspection on the metal through holes when the metal through holes are in layers, so that the time efficiency is poor, the WAT has higher requirements on test patterns and test flows, the cost is high, the WAT is easily influenced by other processes on a substrate, in addition, the testing process has destructiveness, and the retest difficulty is high.
Disclosure of Invention
In order to solve the problems in detecting metal via connectivity in the prior art, the present utility model provides a semiconductor device having a test structure for detecting metal via connectivity.
The semiconductor device provided by the utility model comprises:
a semiconductor substrate;
the first interlayer dielectric layer is formed on the semiconductor substrate;
at least one contact plug penetrating through the first interlayer dielectric layer, wherein the contact plug is electrically connected with the semiconductor substrate; and
at least one via test structure, each via test structure comprising a first metal pad and at least one first test via formed on and electrically connected to the first metal pad, the first metal pad being electrically connected to the semiconductor substrate through a corresponding contact plug, the via test structure being isolated from other electrical components above the semiconductor substrate.
Optionally, at least one of the via test structures includes:
and at least one second metal pad is formed on the first test through holes in a one-to-one correspondence manner, and each second metal pad is electrically connected with the corresponding first test through hole.
Optionally, the first test through hole and the corresponding second metal pad are integrally formed with a conductive block.
Optionally, at least one of the via test structures includes:
n layers of test vias stacked in a direction away from the semiconductor substrate, wherein a first layer of the test vias closest to the semiconductor substrate is the first test via electrically connected to the first metal pad, an mth layer of the test vias including at least one mth test via located above an (M-1) th layer of the test vias; and
and N layers or (N+1) layers of metal pads are stacked along a direction far away from the semiconductor substrate, wherein the first layer of metal pad closest to the semiconductor substrate is the first metal pad, the Mth layer of metal pad comprises at least one Mth metal pad positioned above the (M-1) th layer of metal pad, and the Mth metal pad is arranged between the (M-1) th layer of test through hole and the Mth layer of test through hole and electrically connected with an (M-1) th test through hole and an Mth test through hole, M and N are integers, and M is equal to or less than 2 and M is equal to or less than N.
Optionally, the mth layer of the test through holes includes a plurality of mth test through holes, and the width of each mth test through hole is the same or not the same.
Optionally, the (n+1) th layer of the metal pads includes at least one (n+1) th metal pad located on the N-th layer of the test vias, each (n+1) th metal pad is electrically connected to an N-th test via of the N-th layer of the test vias, and the (n+1) th metal pad and the N-th test via electrically connected are integrally formed conductive blocks.
Optionally, the number of the metal pads in the (n+1) th layer is the same as the number of the nth test vias in the nth layer.
Optionally, the semiconductor device further includes:
a metal interconnection structure including a first metal interconnection layer and a first metal interconnection via formed on and electrically connected to the first metal interconnection layer, the first metal interconnection layer being electrically connected to the semiconductor substrate through the corresponding contact plug; the first metal interconnection layer and the first metal pad are formed on the surface of the first interlayer dielectric layer and are isolated from each other.
Optionally, the metal interconnection structure comprises N layers of metal interconnection layers stacked along a direction away from the semiconductor substrate, wherein a first layer of the metal interconnection layer closest to the semiconductor substrate is the first metal interconnection layer, and two adjacent layers of the metal interconnection layers are connected through metal interconnection through holes.
Optionally, the mth layer of the metal pad in the via test structure and the mth layer of the metal interconnect layer in the metal interconnect structure are located at the same height position on the semiconductor substrate and are isolated from each other.
The semiconductor device provided by the utility model comprises a semiconductor substrate, a first interlayer dielectric layer formed on the semiconductor substrate, a plurality of contact plugs and at least one through hole test structure, wherein the through hole test structure comprises at least one first test through hole electrically connected with a first metal pad, the through hole test structure is isolated from other electric components above the semiconductor substrate, the number of the first test through holes can be set according to requirements, the cost is low, the first test through holes are not easily influenced by other processes on the semiconductor substrate, and because the first test through holes are electrically connected to the semiconductor substrate through the first metal pad and the corresponding contact plugs, connectivity can be tested by using a conductivity detection means after the layer is finished, timeliness is good, the readability is realized, problems in the manufacturing process can be found as early as possible, and loss is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a test structure for detecting metal via connectivity using WAT.
Fig. 2 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the present utility model.
Fig. 3 is a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present utility model.
Fig. 4 is a schematic partial cross-sectional view of a semiconductor device according to still another embodiment of the present utility model.
Fig. 5 is a schematic plan view of a through hole test structure according to an embodiment of the utility model, where fig. 5 (1), fig. 5 (2), fig. 5 (3), fig. 5 (4) and fig. 5 (5) are schematic plan views of through hole test structures according to different embodiments.
Fig. 6 is a schematic partial cross-sectional view of a semiconductor device according to still another embodiment of the present utility model.
Detailed Description
The semiconductor device of the present utility model will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present utility model will become more apparent from the following description. It should be understood that the drawings in the specification are in a very simplified form and are all to a non-precise scale, simply to facilitate a clear and thorough description of the embodiments of the utility model. It should be noted that the order of steps in the methods presented herein is not necessarily the only order in which the steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the method. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the structure in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term "above … …" may also include "below … …" and other orientations.
Fig. 1 is a schematic cross-sectional view of a test structure for detecting metal via connectivity using WAT. Referring to fig. 1, a test structure for detecting connectivity of metal VIAs using WAT includes a first conductive layer 110 and a second conductive layer 120 formed on a semiconductor substrate 100, a plurality of metal VIAs VIA interposed between the first conductive layer 110 and the second conductive layer 120, and a first probe metal pad 11 and a second probe metal pad 12 connected to the two metal VIAs VIA, respectively, wherein the conductivity between the first probe metal pad 11 and the second probe metal pad 12 is tested by a probe to determine the connectivity of each metal VIA at the time of WAT detection. However, the first and second probe metal pads 11 and 12 are generally formed after the back-end process is completed, and it is difficult to test connectivity of the metal VIA before forming the first and second probe metal pads 11 and 12. Furthermore, WAT is highly demanding in terms of test patterns and test flows, costly and susceptible to other processes on the semiconductor substrate 100, and the testing process is destructive and difficult to retest.
The embodiment of the utility model relates to a semiconductor device, which comprises at least one through hole test structure, has good timeliness and retest compared with the detection of the connectivity of a metal through hole by adopting WAT, is beneficial to finding out the problems existing in the manufacturing process as early as possible and reduces the loss. The following is a detailed description.
Referring to fig. 2, a semiconductor device according to an embodiment of the present utility model includes a semiconductor substrate 100, a first interlayer dielectric layer 101, at least one contact plug CT, and at least one via test structure.
Semiconductor fabrication processes generally include front-end processes, which mainly refer to processes for forming electronic components (e.g., transistors) on a substrate surface, and back-end processes, which refer to multilayer wiring processes after forming the electronic components. The semiconductor substrate 100 may be understood as a substrate structure obtained after the front-end process is completed.
The semiconductor base 100 may include a semiconductor substrate having electronic components formed on a surface thereof. The semiconductor substrate may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a group iii-v compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates known to those skilled in the art for carrying electronic components, and may have doped regions and/or isolation structures formed therein. As an example, the semiconductor substrate is a silicon wafer. The electronic components formed on the surface of the semiconductor substrate may include active or passive circuit elements, such as memory cells and/or logic circuits.
A connection member for connecting the via test structure is formed in the semiconductor base 100, and may include at least one of a doped region formed in the semiconductor substrate, a metal silicide layer formed on the semiconductor substrate, a polysilicon layer, and a metal layer. The via test structure is grounded, for example, by connecting the semiconductor substrate 100.
The first interlayer dielectric layer 101 is formed on the semiconductor substrate 100. The first interlayer dielectric layer 101 may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogen doped Silicon Carbide ), and may further include borophosphosilicate glass (BPSG), undoped Silicate Glass (USG), spin-on glass (SOG), or Tetraethylorthosilicate (TEOS).
At least one contact plug CT is formed penetrating the first interlayer dielectric layer 101, and the contact plug CT is electrically connected to the semiconductor substrate 100. The contact plug CT may include a metal material (e.g., tungsten or copper) filled in a via hole penetrating the first interlayer dielectric layer 101. Each of the contact plugs CT is used to connect a via test structure or a metal interconnection structure located on the first interlayer dielectric layer 101.
The via test structures are formed on the first interlayer dielectric layer 101, and the number of the via test structures in the semiconductor device may be set as required. In this embodiment, each of the VIA test structures includes a first metal PAD1 and at least one first test VIA1 formed on the first metal PAD1 and electrically connected to the first metal PAD1, wherein the first metal PAD1 is electrically connected to the semiconductor substrate 100 through the corresponding contact plug CT, and the VIA test structure is isolated from other electrical components on the semiconductor substrate 100. Optionally, at least one of the VIA test structures may include a plurality of the first test VIAs VIA1, and the widths of the plurality of first test VIAs VIA1 may be the same or not the same, and when the widths of the plurality of first test VIAs VIA1 are not the same, the first test VIAs VIA1 with different aspect ratios may be obtained and detected.
The via test structure is used for testing connectivity of the test vias therein, and the number of layers and the number of the test vias in the via test structure can be set as required, as shown in fig. 2 for three via test structures. In this embodiment, the first test VIA1 is formed, for example, by a single damascene process, specifically, after the first metal PAD1 is formed, the second interlayer dielectric layer 102 covering the first metal PAD1 may be formed first, the second interlayer dielectric layer 102 is etched to form a VIA hole exposing the first metal PAD1, and then a metal material (such as electroplated copper) is filled in the VIA hole, and the metal pillar filled in the VIA hole is the first test VIA hole VIA1.
As an example, in testing connectivity of a first test VIA1 formed using a specific process, after forming the first test VIA1, the layer test can be started, since the first test VIA1 is electrically connected to the semiconductor substrate through the first metal PAD1 and the corresponding contact plug CT, the conductivity of the conductive paths formed by the first test VIA1, the first metal PAD1, the contact plug CT, and the semiconductor substrate 100 may be tested and determined by a conductivity detection means such as electron beam scanning (E-beam) after the completion of the layer to detect the connectivity of the first test VIA1. The via test structure is low cost and is not susceptible to other processes on the semiconductor substrate 100.
In the VIA test structure, when more than one, i.e., more than two, first test VIAs VIA1 are formed on the first metal PAD1, each first test VIA1 may be electrically connected to the semiconductor substrate 100 through the first metal PAD1 and the corresponding contact plug CT, and, since each first test VIA1 shares only the first metal PAD1, the conductive path of each of the first test VIAs VIA1 to the semiconductor substrate 100 is independent of whether or not the other first test VIAs VIA1 are connected, so that the connectivity of each of the first test VIAs VIA1 can be independently tested.
Electron beam scanning (E-beam) is a detection method that determines whether an irradiated material is conductive by irradiating an electron beam to the surface of the material, receiving Secondary Electrons (SE) and back-emitted electrons (BSE) of the surface of the material with corresponding sensors, and imaging. In the present embodiment, as an example, in detecting connectivity of the first test VIA1 using electron beam scanning, the top surface of the first test VIA1 may be scanned using an electron beam scanning device, and a corresponding image is obtained, the brightness of the image is detected, when the image of the first test through hole VIA1 is a white point similar to the conducting structure, it can be determined that the first test VIA1 communicates with the first metal PAD1, and further communicates to the semiconductor substrate 100 (potential ground), when the image of the first test VIA1 is a dark spot similar to the non-conductive structure, it may be determined that the first test VIA1 is not connected to the first metal PAD1 or the connectivity is not acceptable.
Referring to fig. 3, alternatively, in another embodiment, the VIA test structure in the semiconductor device includes, in addition to a first metal PAD1 and at least one first test VIA1 formed on the first metal PAD1 and electrically connected to the first metal PAD1, the semiconductor device further comprises at least one second metal PAD PAD2, wherein the second metal PADs PAD2 are formed on the first test through holes VIA1 in a one-to-one correspondence manner, and each second metal PAD PAD2 is electrically connected with the corresponding first test through hole VIA1. In this embodiment, each of the second metal PADs PAD2 is connected to the semiconductor substrate 100 through a single one of the first test VIAs VIA1, thus detecting the conductivity of the second metal PAD2, i.e. the connectivity of the corresponding first test VIA1. Detecting the conductivity of the second metal PAD2 may employ electron beam scanning (E-beam).
The first test VIA1 and the corresponding second metal PAD2 are, for example, integrally formed conductive blocks, which may be formed by the same metal material filling process. Illustratively, the first test VIA1 and the corresponding second metal PAD2 are formed using a dual damascene process. For example, after the first metal PAD1 is formed, the second interlayer dielectric layer 102 covering the first metal PAD1 may be formed first, then the second interlayer dielectric layer 102 is etched to form a VIA hole exposing the first metal PAD1, then the top of the VIA hole is etched to form a groove, then the VIA hole and the groove are filled with a metal material (such as electroplated copper), the metal block portion in the VIA hole is the first test VIA hole VIA1, and the metal block portion in the groove is the second metal PAD2.
In order to obtain connectivity of the metal vias after the multi-layer stacking, in an embodiment of the present utility model, the via test structure may further include a test via further located above the second metal PAD2.
In particular, at least one of the via test structures may include N layers of test vias stacked in a direction away from the semiconductor substrate 100 and N layers or (n+1) layers of metal pads stacked in a direction away from the semiconductor substrate 100; wherein the first layer of the test VIA closest to the semiconductor substrate 100 is a first test VIA1 electrically connected to the first metal PAD1, and the mth layer of the test VIA includes at least one mth test VIA located above the (M-1) th layer of the test VIA; the first metal PAD closest to the semiconductor substrate 100 is the first metal PAD1, the mth metal PAD includes at least one mth metal PAD located above the (M-1) th metal PAD, the mth metal PAD is disposed between the (M-1) th test via and the mth test via and electrically connects a (M-1) th test via and an mth test via, M and N are integers, and M and N are equal to or less than 2M is equal to or less than N.
Optionally, in the N layers of the test vias in the via test structure, the mth layer of the test vias includes a plurality of mth test vias, and the width of each mth test via is the same or not the same. When the widths of the M test through holes are not completely the same, the M test through holes with different depth-to-width ratios can be obtained and detected.
Referring to fig. 4, in one embodiment, N is 2, the VIA test structure includes two layers of the test VIAs and two layers of the metal PAD stacked in a direction away from the semiconductor substrate 100, the second layer of the test VIAs includes at least one second test VIA2 located on the first layer of the test VIAs, the second layer of the metal PAD comprises at least one second metal PAD2 positioned above the first layer of the metal PAD, wherein the second metal PAD2 is electrically connected with a second test through hole VIA2 and a first test through hole VIA1, and the connectivity of the second test through hole VIA2 can be detected after the layer is formed.
When the through hole test structure comprises an (n+1) th layer of the metal pads, the (n+1) th layer of the metal pads comprises at least an (n+1) th metal pad positioned on the N th layer of the test through holes, each (n+1) th metal pad is electrically connected with an nth test through hole in the N th layer of the test through holes, and the (n+1) th metal pad and the N th test through holes electrically connected are integrally formed conductive blocks. The number of the metal pads in the (n+1) -th layer of the metal pads is, for example, the same as the number of the nth test vias in the nth layer of the test vias. Referring to fig. 4, in another embodiment, the VIA test structure includes two layers of the test VIA and three layers of the metal pad stacked in a direction away from the semiconductor substrate 100, wherein a third layer of the metal pad includes at least one third metal pad (not shown) located on a second layer of the test VIA (i.e., on the second test VIA 2), each of the third metal pads is electrically connected with a second test VIA2 and both are, for example, integrally formed conductive blocks.
When the topmost part of the through hole test structure is an Nth test through hole, the conductivity of the Nth test through hole can be directly detected, and when the topmost part of the through hole test structure is an (N+1) th metal pad, the conductivity of the Nth test through hole below can be detected by detecting the conductivity of the (N+1) th metal pad.
Fig. 5 is a schematic plan view of a via test structure in an embodiment of the utility model. Referring to fig. 5, one or more of the via test structures may be provided in the same semiconductor device, wherein:
as shown in fig. 5 (1), in one embodiment, at least one VIA test structure is a stand-alone structure, the VIA test structure includes one test VIA electrically connected to a first metal PAD1 and a corresponding contact plug CT, there are no other metal VIAs in a certain range around the test VIA to be tested (e.g., in a radius range of 5 times the width of the test VIA), and the semiconductor device exposes the top surface of the test VIA to be tested for connectivity testing;
as shown in fig. 5 (2), in one embodiment, at least one VIA test structure is a stand-alone structure, the VIA test structure including one test VIA electrically connected to a first metal PAD1 and corresponding contact plug CT, the semiconductor device does not expose the top surface of the test VIA to be tested, but exposes the top surface of the metal PAD covering the test VIA to be tested;
as shown in fig. 5 (3), in one embodiment, a plurality of VIA test structures are arranged in a density, each of the VIA test structures includes one test VIA electrically connected to a first metal PAD1 and a corresponding contact plug CT, and the semiconductor device exposes a top surface of the test VIA to be inspected for connectivity test;
as shown in fig. 5 (4), in one embodiment, a plurality of VIA test structures are arranged at a density, each of the VIA test structures including one test VIA electrically connected to a first metal PAD1 and a corresponding contact plug CT, the semiconductor device exposes a top surface of the metal PAD covering the test VIA to be tested for connectivity testing;
as shown in fig. 5 (5), in one embodiment, at least one VIA test structure includes a plurality of test VIAs VIA electrically connected to a PAD1 and corresponding contact plugs CT, and the semiconductor device exposes a top surface of each test VIA to be tested in the VIA test structure for connectivity testing.
It should be noted that the structure and arrangement of the via test structures shown in fig. 5 are only examples, and the structure and arrangement of the via test structures in the semiconductor device may be set as required, for example, may be arranged in a manner of greater density than that shown in (3) of fig. 5.
Fig. 6 is a schematic partial cross-sectional view of a semiconductor device according to still another embodiment of the present utility model. Referring to fig. 6, in an embodiment of the present utility model, the semiconductor device may further include a metal interconnection structure in addition to the semiconductor substrate 100, the first interlayer dielectric layer 101, the at least one contact plug CT, and the at least one via test structure, the metal interconnection structure may be electrically connected to and may form interconnections between electronic components formed on the semiconductor substrate 100.
Specifically, the metal interconnection structure may include a first metal interconnection layer M1 and a first metal interconnection via V1 formed on the first metal interconnection layer M1 and electrically connected to the first metal interconnection layer M1, the first metal interconnection layer M1 being electrically connected to the semiconductor substrate 100 through the corresponding contact plug CT; the first metal interconnection layer M1 and the first metal PAD1 are formed on the surface of the first interlayer dielectric layer 101 and are isolated from each other. In addition, the metal interconnection structure further includes a second metal interconnection layer M2 located above the first metal interconnection via V1 and connected to the first metal interconnection via V1, where the first metal interconnection via V1 and the second metal interconnection layer M2 are formed by, for example, a dual damascene process, and are, for example, integrally formed conductive blocks.
The first metal PAD1 in the via test structure may be formed through the same process as the first metal interconnection layer M1. The first metal interconnection layer M1 and the first metal PAD1 are embedded on the surface of the first interlayer dielectric layer 101 or are located on the surface of the first interlayer dielectric layer 101, for example. In addition, the first test VIA in the VIA test structure may be formed through the same process as the first metal interconnection VIA V1, and, by reasonably setting the size of the first test VIA, the connectivity performance of the first metal interconnection VIA V1 may be obtained by detecting the connectivity of the first test VIA.
The metal interconnection structure may include N metal interconnection layers stacked in a direction away from the semiconductor substrate 100, the first metal interconnection layer closest to the semiconductor substrate 100 is the first metal interconnection layer M1, two adjacent metal interconnection layers may be electrically connected through a metal interconnection via, and N is an integer greater than or equal to 2. For example, the second metal interconnection layer M2 and the first metal interconnection layer M1 are electrically connected through the first metal interconnection via V1.
The metal pad of the mth layer in the via test structure and the metal interconnect layer of the mth layer in the metal interconnect structure are located at the same height position on the semiconductor substrate 100 and are isolated from each other (M is an integer and 2+.m+. N). For example, the first metal interconnection layer M1 is located at the same height position on the semiconductor substrate 100 as the first metal PAD1 in the via test structure and is isolated from each other, and the second metal interconnection layer M2 is located at the same height position on the semiconductor substrate 100 as the second metal PAD2 in the via test structure and is isolated from each other. The M-th layer of the metal pad in the through hole test structure and the M-th layer of the metal interconnection structure can be formed synchronously, and the M-th layer of the test through hole in the through hole test structure and the M-th layer of the metal interconnection structure can be formed synchronously.
The semiconductor device described in the above embodiment includes a semiconductor substrate 100, a first interlayer dielectric layer 101 formed on the semiconductor substrate 100, a plurality of contact plugs CT, and at least one VIA test structure, wherein, the VIA test structure comprises at least one first test VIA1 electrically connected to the first metal PAD1, the VIA test structure being isolated from other electrical components above the semiconductor substrate 100, the structure of the first test VIA1 being configurable as desired, by adjusting the number of test VIAs of each layer, the VIA test structure can be designed into a large-scale test structure to cover a larger area, has low cost and is not easily affected by other processes on the semiconductor substrate 100, and since the first test VIA1 is electrically connected to the semiconductor substrate through the first metal PAD1 and the corresponding contact plug CT, the connectivity of the VIA can be tested by using a conductivity detection means such as electron beam after the layer is completed, the VIA test structure has good timeliness, can retest, is beneficial to finding problems existing in the manufacturing process as early as possible, and reduces loss.
The foregoing description is only illustrative of the preferred embodiments of the present utility model, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present utility model using the method and technical content disclosed above without departing from the spirit and scope of the utility model, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present utility model fall within the scope of the technical solution of the present utility model.
Claims (10)
1. A semiconductor device, comprising:
a semiconductor substrate;
the first interlayer dielectric layer is formed on the semiconductor substrate;
at least one contact plug penetrating through the first interlayer dielectric layer, wherein the contact plug is electrically connected with the semiconductor substrate; and
at least one via test structure, each via test structure comprising a first metal pad and at least one first test via formed on and electrically connected to the first metal pad, the first metal pad being electrically connected to the semiconductor substrate through a corresponding contact plug, the via test structure being isolated from other electrical components above the semiconductor substrate.
2. The semiconductor device of claim 1, wherein at least one of the via test structures comprises:
and at least one second metal pad is formed on the first test through holes in a one-to-one correspondence manner, and each second metal pad is electrically connected with the corresponding first test through hole.
3. The semiconductor device of claim 2, wherein the first test via and the corresponding second metal pad are integrally formed conductive blocks.
4. The semiconductor device of claim 1, wherein at least one of the via test structures comprises:
n layers of test vias stacked in a direction away from the semiconductor substrate, wherein a first layer of the test vias closest to the semiconductor substrate is the first test via electrically connected to the first metal pad, an mth layer of the test vias including at least one mth test via located above an (M-1) th layer of the test vias; and
and N layers or (N+1) layers of metal pads are stacked along a direction far away from the semiconductor substrate, wherein the first layer of metal pad closest to the semiconductor substrate is the first metal pad, the Mth layer of metal pad comprises at least one Mth metal pad positioned above the (M-1) th layer of metal pad, and the Mth metal pad is arranged between the (M-1) th layer of test through hole and the Mth layer of test through hole and electrically connected with an (M-1) th test through hole and an Mth test through hole, M and N are integers, and M is equal to or less than 2 and M is equal to or less than N.
5. The semiconductor device according to claim 4, wherein the mth layer of the test via holes includes a plurality of the mth test via holes, and a width of each of the mth test via holes is the same or not the same.
6. The semiconductor device of claim 4, wherein the (n+1) th layer of metal pads comprises at least one (n+1) th metal pad located on the N-th layer of the test vias, each of the (n+1) th metal pads is electrically connected to an nth one of the N-th layer of the test vias, and the (n+1) th metal pad is an integrally formed conductive block with the N-th test via electrically connected thereto.
7. The semiconductor device of claim 5, wherein the number of metal pads in the (n+1) th layer of the metal pads is the same as the number of nth test vias in the nth layer of the test vias.
8. The semiconductor device according to any one of claims 4 to 7, further comprising:
a metal interconnection structure including a first metal interconnection layer and a first metal interconnection via formed on and electrically connected to the first metal interconnection layer, the first metal interconnection layer being electrically connected to the semiconductor substrate through the corresponding contact plug; the first metal interconnection layer and the first metal pad are formed on the surface of the first interlayer dielectric layer and are isolated from each other.
9. The semiconductor device of claim 8, wherein the metal interconnect structure comprises:
and N layers of metal interconnection layers are stacked along the direction away from the semiconductor substrate, wherein the first layer of metal interconnection layer closest to the semiconductor substrate is the first metal interconnection layer, and two adjacent layers of metal interconnection layers are electrically connected through metal interconnection through holes.
10. The semiconductor device of claim 9, wherein an mth layer of the metal pad in the via test structure and an mth layer of the metal interconnect layer in the metal interconnect structure are located at a same height on the semiconductor substrate and are isolated from each other.
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