JP2003179138A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a high-concentration Ge layer is formed on the surface of an impurity diffusion layer in contact with a wiring layer. <P>SOLUTION: A Si substrate has a first impurity diffusion layer which is formed in a specified surface layer region of a crystal region of the first conductivity type and has the opposite conductivity to the first conductivity, a second impurity diffusion layer which is formed in another specified surface layer region of the crystal region and has the same conductivity as the first conductivity, a first wiring layer which is formed for connecting the first impurity diffusion layer and a second wiring layer which is formed for connecting the second impurity diffusion layer. In this case, the surface of both the first and second impurity diffusion layers of the Si substrate which are connected to the first and second wiring layers is etched and Ge is added to the surface layer part of the first and second impurity diffusion layers. The concentration of Ge is distributed in such a way that it is almost the highest on the surface and is continuously reduced in the direction of the depth. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus in which the contact resistance between an impurity diffusion layer formed on a semiconductor substrate and a wiring layer is reduced.

[0002]

2. Description of the Related Art The integration of semiconductor devices involves miniaturization of device patterns. Accordingly, the contact area between the impurity diffusion layer formed on the semiconductor substrate and the wiring layer connected to the impurity diffusion layer must be miniaturized. The miniaturization of the contact area leads to an increase in contact resistance, which imposes a burden on the device.
Therefore, new measures for reducing the contact resistance have become necessary.

Generally, the contact resistance value ρ _c and the contact resistance value R _C between the impurity diffusion layer and the wiring layer are given by the following two equations.

[0004]

[Equation 1] ρ _c ∝ exp {4π (ε _c · m ^* ) ^1/2 · Φ _B
/ ((N _D ) ^1/2・ q ・ h)}

[0005]

[Number 2] R _C = ρ _c / A _C In the above formula, [Phi _B is the height of the Schottky barrier between the semiconductor forming the metal and the impurity diffusion layer is a wiring material, N
_D is the carrier concentration, m ^* is the effective mass of the carrier, ε _c is the relative dielectric constant of the semiconductor, h is the Planck's constant, and A _C is the contact area.

From the above equation 2, in order to reduce the contact resistance value R _C , 1) increase the contact area A _C , 2) decrease the Schottky barrier height Φ _B , and 2) increase the carrier concentration N _D. It is possible to take measures such as

The contact area A _C tends to decrease as miniaturization progresses. Considering that there is a limit to the concentration of impurities that form a solid solution in the Si substrate, and that the impurity diffusion layer is shallowed due to miniaturization and that the process temperature is lowered, the solid solution limit of impurities is further reduced. However, it cannot be expected that the carrier concentration N _D will be increased.

As a method of reducing the Schottky barrier height Φ _B , it can be considered to select a metal material having a small Φ _B as the wiring material. However, in general, in the case of metal, a material having a small Schottky barrier for an n-type semiconductor is p
Conversely, it tends to have a high Schottky barrier for semiconductors of the type. This property is due to the relationship between the metal and the semiconductor shown by the following equation.

[0009]

In Equation 3] Eg ≒ Φ _Bn + Φ _Bp above equation, Eg is the semiconductor bandgap, [Phi _Bn is the value of the Schottky barrier to n-type semiconductor, [Phi _Bp represents the value of the Schottky barrier to the p-type semiconductor.

Since the wiring layer is connected to the impurity diffusion layer containing Si, Eg in the above equation has a value almost close to the band gap of Si of 1.12 eV. For example, if Pt, which has a small value of Φ _Bn of 0.2 eV, is selected as the wiring material,
Eg is 1.05 eV and Φ _Bp is 0.85 eV. When Ti is selected, Eg is 1.10 eV and Φ _Bn is 0.
50 eV, Φ _Bp becomes 0.60 eV (EHRhoderick,
Metal Semiconductor Contacts, Oxford Press, Londo
n, 1980).

In many cases, both p-type and n-type impurity diffusion layers are present on the device. In order to make Φ _B small for each conductivity type, it is necessary to select different wiring materials for each conductivity type. But,
From the viewpoint of improving the efficiency of the process, it is desired to select one material that can support both conductivity types.

The band gap of Ge is 0.67 eV, which is considerably smaller than that of Si. Therefore,
Both Φ _Bn and Φ _Bp can be reduced by sandwiching Ge, which is a semiconductor, on the connection surface between the wiring material and the impurity diffusion layer. That is, the use of Ge makes it possible to reduce the contact resistance for both conductivity types.

In the case of using Ge in the contact portion between the semiconductor layer and the wiring layer so far, a single layer film of Ge is formed on the impurity diffusion layer by sputtering or CVD (vapor phase growth method). There was a way to do it. However, G on the Si film
The deposition of the single-layer film of e may generate a defect portion that causes a current leak at the interface due to the mismatch of lattice constants.

Therefore, it is also considered to use the SiGe layer by adjusting its composition stepwise and continuously instead of using Ge alone. To adjust the composition of Si / Ge, C
Although it is possible to use the VD method or the sputtering method, it is easier to use the ion implantation method, and the continuous G
A SiGe layer with varying e / Si ratio can be formed.

When the ion implantation method is used, Ge ions are implanted into the impurity-diffused Si layer to form SiG on the surface layer.
e layer is formed. It also has the advantages that the implantation layer can be selectively formed using a mask and that the ion implantation depth can be adjusted with good controllability by adjusting the dose amount, ion acceleration voltage, and the like.

[0016]

A SiGe layer is formed on the surface of an impurity-diffused Si layer into which Ge is ion-implanted. In order to reduce the contact resistance with the wiring, it is desirable to increase the Ge concentration on the contact surface as much as possible. S
This is because the band gap can be reduced and the Φ _B value can be reduced as the ratio of Ge to i is increased.

However, in the Ge ion-implanted layer formed by the ion-implantation method, the concentration distribution in the depth direction changes depending on the conditions such as the ion acceleration voltage and the dose amount. Shows a Gaussian concentration distribution with a high concentration peak. Also, depending on the conditions,
The Ge concentration on the surface of the impurity diffusion layer may be considerably low.

An object of the present invention is to provide a semiconductor device in which a high concentration Ge layer is surely formed on the surface of an impurity diffusion layer connected to a wiring layer.

[0019]

According to one aspect of the present invention, a conductivity type opposite to a first conductivity type formed in a predetermined surface region of a crystal region having a first conductivity type of a Si substrate is provided. A first impurity diffusion layer having the same, a second impurity diffusion layer having the same conductivity type as the first conductivity type formed in another predetermined surface layer region of the crystal region, and the first impurity diffusion layer In a configuration having a first wiring layer formed so as to be connected and a second wiring layer formed so as to be connected to the second impurity diffusion layer, the first and second wiring layers are The S connected
The surfaces of both the first and second impurity diffusion layers of the i substrate are etched, and Ge is added to the surface layer portions of the first and second impurity diffusion layers to obtain a Ge concentration distribution. Is almost the highest at the surface, and the semiconductor device is continuously reduced in the depth direction.

[0020]

The ion-implanted Ge has a concentration distribution close to a Gaussian type in the depth direction, so that a Ge layer of higher concentration can be exposed on the surface by etching to an appropriate position. When Ge is implanted in the Si crystal region, the higher the Ge / Si ratio, the smaller the band gap of SiGe and the lower Φ _B can be. Further, the shape of the connection surface can be made concave by etching, and the contact area can be effectively expanded by the side surface portion. They are,
Both reduce the contact resistance between the impurity diffusion layer and the wiring layer.

Further, the Ge ion implantation performed before the impurity ion implantation makes the implanted region amorphous. Since impurity ion implantation is performed on this amorphous layer, channeling is suppressed and the impurity diffusion layer can be formed shallowly.

When a Ge single layer film is used as the first wiring layer, the contact resistance between the impurity diffusion layer and the wiring layer can be further reduced.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. First, a method of forming the first embodiment will be described by taking out the n-channel portion of the CMOS semiconductor device.

First, B is about 3 × 10 ¹⁵ atoms / cm 3.
³ Prepared p-type Si substrate 1 having a plane orientation (100). As shown in FIG. 2A, after the SiO ₂ film 2 having a thickness of about 30 nm is formed on the surface of the substrate by thermal oxidation, B ions are implanted. Ion implantation conditions at this time are
The conditions under which the ion-implanted layer 3'can be formed by penetrating the layer of the SiO ₂ film 2, for example, the ion acceleration voltage of 30 KeV and the dose amount of 1.5 × 10 ¹³ ions / cm ² are used.

After that, heat treatment is performed at 1150 ° C. for 240 minutes, for example, to activate the ion-implanted layer and deeply diffuse (drive-in) the implanted B. This diffusion layer forms the p-type well 3 shown in FIG. Incidentally, S
The iO ₂ film 2 is a p-type well and is not shown in the drawing.
It is used as an ion implantation mask when forming the mold well.

Next, a first SiO ₂ film 2 is etched, SiO new about 15nm and again thermally oxidized substrate ₂
The film 2a is formed. A SiN _x film having a thickness of about 140 nm is formed on the SiO ₂ film 2a by the CVD method (vapor phase growth method). A resist film is formed on the entire surface of the SiN _x film, exposed,
A resist mask 5 is formed through development. The SiN _x film is etched using the resist mask 5 as an etching mask to form the SiN _x film pattern 4.

As shown in FIG. 2B, B ions are implanted using the SiN _x film pattern 4 and the resist mask 5 as an ion implantation mask to form an ion implantation layer 6 for forming a channel stop region. For example, ion acceleration voltage 1
00 KeV, dose 1.5 × 10 ¹³ ions / cm ²
The condition of is used. After that, the resist mask is removed.

Next, using the SiN _x film pattern 4 as a mask, thermal oxidation is performed to obtain a thickness of about 40 as shown in FIG. 2 (C).
A field oxide film 7 of 0 nm is formed. In this thermal oxidation step, the ion implantation layer 6 is activated and a high concentration p-type channel stop region 8 is formed under the field oxide film.
After that, the SiN _x film pattern 4 is removed by etching.

As shown in FIG. 2C, field oxidation is performed.
Ion implantation of B is performed using the film 7 as an ion implantation mask,
The ion implantation layer 9 is formed. Ion implantation conditions at this time
Is thin SiO₂Membrane 2a passes, but thick field
The condition that the oxide film 7 cannot be exceeded is selected. example
For example, ion acceleration voltage 15 KeV, dose amount 1.5 × 10
¹²ions / cm²Is the condition. This ion injection
The entrance layer 9 does not function as a threshold voltage control.
It

Next, the gate electrode is formed. A two-layer film of a polycrystalline Si film and a WSi film is deposited on the entire surface of the substrate by sputtering, for example, each having a thickness of 150 nm. The structure of such a two-layer film in which metal silicide is formed on the polycrystalline Si film is called a polycide structure. The resist film is WSi
A resist mask pattern is obtained by forming on the entire surface of the film and exposing and developing.

[0031] The resist mask as an etching mask, Cl _2, O _2, He gas mixture or, HBr, S
Using a mixed gas of F ₆ and the polycide layer and SiO ₂
The film 2a is dry-etched. When the unnecessary resist is removed, the gate electrode 11 shown in FIG. 3D is obtained.

Next, as shown in FIG. 3E, P ions are ion-implanted using the field oxide film 7 and the gate electrode 11 as an ion implantation mask, and the ion-implanted layer 1 is formed in an extremely shallow region.
Form 2. For example, the ion implantation conditions at this time are as follows: ion acceleration voltage 80 KeV, dose amount 4.0 × 10.
^{Use 13} ions / cm ² and an injection angle of 45 degrees. The ion implantation layer 12 forms an LDD (Lightly doped drain) region.

Then, a Si film having a thickness of about 200 nm is formed on the entire surface by a CVD method using TEOS (tetraethoxysilane).
An O ₂ film is formed. RIE (reactive ion etching)
This SiO ₂ film is etched by using
As shown in, the SiO ₂ region 13 is formed only on the side wall of the gate electrode 11. This SiO ₂ region 13 is generally called a side spacer or a side wall oxide.

Next, the step of implanting Ge ions will be described. Conventionally, the Ge layer or the SiGe layer formed for the purpose of reducing the contact resistance between the impurity diffusion layer and the wiring layer has been formed after the formation of the impurity diffusion layer. In this embodiment, as described below, Ge ion implantation is performed before the impurity ion implantation step which is the step of forming the impurity diffusion layer.

As shown in FIG. 4G, Ge ions are ion-implanted by using the field oxide film 7, the gate electrode 11 and the side spacers 13 formed on both walls thereof as a mask to form an implantation layer 21. The ion implantation conditions are set so that the Ge distribution range is shallower than the impurity distribution depth obtained by the impurity ion implantation performed after this step. For example, an ion acceleration voltage of 30 to 150 KeV and a dose amount of 5.0 × 10 ^{13 to} 5.0 × 10 ¹⁵ ions / cm.
² Ion acceleration voltage 30 to 80 KeV, dose amount 1.0 to 5.0 × 10 ¹⁴ ions / cm ² More preferably, ion acceleration voltage 30 KeV, dose amount 2.0 × 1
0 ¹⁴ conditions are selected.

Subsequently, as shown in FIG. 4H, P ions, which are ions that impart conductivity, are ion-implanted to form an ion-implanted layer 22. Ion implantation conditions at this time are, for example, an ion acceleration voltage of 20 KeV and a dose of 5.0.
When the ion implantation conditions of × 10 ¹⁵ ions / cm ² and 45 ° are used, an impurity distribution having a depth of about 0.12 μm is obtained immediately after the ion implantation.

After this, RTA (rapid thermal annealin
g) Using the device, the substrate is 800 to 800 in 10 seconds in N ₂ atmosphere.
Annealing is performed under the condition that the temperature is raised to 1000 ° C. and this temperature is maintained for 10 seconds. The impurities in the ion-implanted layer 22 are activated, and the implanted layer is recrystallized to form the impurity-diffused layer 23 shown in FIG. 4 (I).

The Ge ion implantation performed before the ion implantation of impurities as in the present embodiment is not only for forming a Ge mixed layer in the surface region of the impurity diffusion layer, but also as described below. This brings about the effect of shallowing the impurity diffusion layer (junction).

FIG. 6 shows the impurity distribution in the depth direction of the impurity diffusion layer. The horizontal axis represents depth and the vertical axis represents the concentration of impurities that impart conductivity. As devices are highly integrated, it is desired that the impurity distribution width be as shallow as possible from the background that impurity diffusion layers, so-called junctions are required to be shallow. The solid line shows the impurity concentration distribution immediately after the impurity ion implantation when Ge ion implantation is performed before the impurity ion implantation corresponding to this embodiment. The impurity concentration distribution when the impurity ions are directly implanted into the crystal substrate without the Ge ion implantation is shown by a broken line. By performing the Ge ion implantation in advance, the impurity concentration distribution width becomes considerably shallow.

When the impurity ions are directly ion-implanted into the crystal substrate, channeling occurs in which the implanted ions penetrate deeply into the substrate through the gaps in the substrate crystal lattice without causing a large collision with the substrate atoms. However, the Ge ion implantation with an atomic weight of 16 or more performed before the impurity ion implantation can amorphize the substrate surface. Since there is no regular crystal lattice in the amorphous layer, the channeling of impurities ion-implanted into the amorphous layer is suppressed. As described above, in the present embodiment, Ge ion implantation suppresses P channeling, and a shallow junction as shown in FIG. 6 can be formed.

Next, the steps after forming the impurity diffusion layer will be described. As shown in FIG. 4I, atmospheric pressure CVD is used to form a two-layer film of a PSG film (phosphosilicate glass) having a thickness of about 100 nm and a BPSG film (boron phosphosilicate glass) having a thickness of about 600 nm. The interlayer insulating film 24 is formed on the entire surface.

After that, a resist film is formed on the interlayer insulating film 24, and a resist mask is formed by exposure and development.
By using this resist mask as an etching mask and performing etching, a contact hole for connecting the impurity diffusion layer and the wiring layer is formed in the interlayer insulating film 24.
The resist film is removed at this point or after the subsequent step of etching the impurity diffusion layer.

Further, as shown in FIG. 5 (J), with the interlayer insulating film 24 having the contact hole formed as a mask, a high Ge concentration region is exposed on the exposed surface of the impurity diffusion layer. Etching. As for the etching conditions, for example, a parallel plate type reactive ion etching apparatus is used, and trench etching is possible, for example, HBr is 10 to 15 sccm, preferably 12 sccc.
m, Cl ₂ is 25 to 30 sccm, preferably 27 sc
cm mixed gas, pressure 100-150 mtor
r preferably 125 mtorr, RF output 300-50
It is performed at 0 W, preferably 400 W.

FIG. 7 shows the Ge concentration distribution in the depth direction before and after the step of etching the surface of the impurity diffusion layer. FIG. 7A shows Ge just before etching.
The concentration distribution of is shown. It has a Gaussian concentration distribution having the highest concentration Cmax at the depth of Dc from the substrate surface.

The etching depth is most preferably the depth Dc at which the Ge concentration is highest. In the case of dry etching, for example, the etching depth can be controlled by monitoring the emission spectrum of Ge and ending the etching at the point where the emission intensity is highest. It is also possible to measure the Ge impurity distribution and the etching rate in advance and manage the etching time.

When the surface of the impurity diffusion layer is etched to the ideal depth Dc in this way, a region having the highest Ge concentration may be brought to the surface of the impurity diffusion layer as shown in FIG. 7B. it can. As will be described later, this etching process can be performed on the p-channel as well as the n-channel. Both channels can bring a region having the highest Ge concentration on the surface of the impurity diffusion layer.

Further, as shown in FIG. 5 (J), the surface portion of the etched impurity diffusion layer has a concave shape. With this shape, the contact area can be effectively expanded, and the contact resistance can be further reduced.

Thereafter, as shown in FIG. 5K, a so-called barrier metal layer 31 such as a TiN or WSi film is formed by sputtering to a thickness of about 50 nm. Subsequently, an Al alloy layer 32 having, for example, an Al-Si-Cu3 composition is formed by sputtering to have a thickness of about 800 nm.

A resist film is formed on the entire surface of the substrate, and a resist mask having an electrode / wiring pattern is formed by exposure and development. The barrier metal layer 31 and the Al alloy layer 32 are etched using this resist mask as an etching mask. The unnecessary resist is removed, and desired wiring is formed as shown in FIG. Further, using plasma CVD on the entire surface of the substrate, a PSG film having a film thickness of 100 to 500 nm, preferably 150 nm, and 500 to 1500 are used.
A continuous film passivation film 33 made of a SiN _x film having a thickness of preferably 1000 nm is formed.

A resist film is formed on the entire surface of the substrate, and a resist mask having openings corresponding to bonding pads, scribe lines, etc. is formed by exposure and development. Using this resist mask as an etching mask, the passivation film is etched, and windows are opened for bonding pads and the like for drawing out wiring. Incidentally, this window opening is omitted in the drawing.

Finally, the substrate is annealed in a hydrogen atmosphere at 400 ° C. for about 30 minutes to neutralize the charges generated in the gate oxide film due to damage in various steps. In the above embodiment, only the process of forming the n-channel portion of the CMOS transistor has been described, but of course the p-channel is also formed in the CMOS manufacturing process. CMO with both channels
A sectional view of the S semiconductor device is shown in FIG. Si crystal substrate 1
N formed by the above-described process on the upper p-type well 3
A p-channel is formed on the channel and the n-type well 41, respectively. When forming a p-channel, a portion such as an n-channel region that is unnecessary for the process is covered with a resist mask and ion implantation or the like is performed. As the conductivity-imparting ions, for example, B or BF ₂ is selected and implanted. Ge ion implantation,
Since the steps such as etching of the impurity diffusion layer and the like are common to both channels, they can be performed simultaneously.

Next, the forming method of the second embodiment will be described. The second embodiment differs from the first embodiment in the step of etching the surface of the impurity diffusion layer. The process up to the step of annealing the impurity diffusion layer is the same as that of the first embodiment.
The steps after forming the impurity diffusion layer will be described below with reference to FIG.

As shown in FIG. 8A,
Through similar steps, p-type well layer 3 and field oxide film
7, channel stop region 8, gate electrode 11, impure
SiO is formed on the entire surface of the substrate on which the object diffusion layer 23 and the like are formed.₂Membrane C
It is formed by VD or sputtering. Cashier
Stroke film is formed on the entire surface, exposed and developed, and then resist
Form a mask. Etch this resist mask
This SiO as a disc ₂Dry etch the film. C
It may be wet etching.

Thus, the etching mask 51 of the SiO ₂ film is formed on the portion other than the impurity diffusion layer, especially on the gate electrode. The material of the etching mask may be a SiN _x film or the like.

Next, as shown in FIG. 8B, dry etching is performed on the entire surface of the substrate using a mixed gas of Cl ₂ , O ₂ , SF ₆ , HBr and the like. The entire surface of the impurity diffusion layer not covered with the etching mask is etched. Similar to the first embodiment, etching is performed to a depth where the Ge concentration is almost the highest.

As shown in FIG. 8C, an interlayer insulating film 24 is formed on the entire surface of the substrate. Since the etching mask 51 is made of the same material as the interlayer insulating film, it need not be removed by etching. Subsequent steps of forming contact holes, wiring layers, passivation films, and the like use the same process conditions as those in the first embodiment. Of course, the etching of the impurity diffusion layer performed after forming the contact hole in the interlayer insulating film in the first embodiment is omitted because it has already been performed in the above process. FIG. 9 shows a sectional view of the n-channel portion of the CMOS semiconductor device which has undergone the final step.

As described above, in the second embodiment, when the impurity diffusion layer is etched, a relatively wide area is etched. Therefore, the etching condition is not limited to the trench etching condition, but an isotropic etching condition is used. be able to.
Therefore, wet etching can be performed.

As shown in FIG. 8B, when the entire surface of the impurity diffusion layer is etched, the connection portion of the wiring layer is also flat, but only the connection portion of the impurity diffusion layer and the wiring is opened. If the etching mask is used, a concave etching shape can be formed in the connection portion as in the first embodiment, and the contact area can be expanded.

The etching may be carried out immediately after the impurity ion implantation. In this case, the ion implantation layer is annealed after the etching is completed. A third embodiment will be described. The CM in Figure 10
3 is a cross-sectional structural view of an n-channel portion of an OS semiconductor device.
Under the barrier metal layer 31, as a first layer of the wiring layer,
It has a Ge single layer film 61. The forming method is similar to the forming method of the first embodiment described above, but a step of forming a single-layer thin film of Ge of several tens to several hundred Å by sputtering or CVD is added before the barrier metal forming step. . In this embodiment, a Ge layer having a small band gap can be reliably formed at the connecting portion between the impurity diffusion layer and the wiring layer.

The fourth embodiment will be described with reference to FIG. As shown in FIG. 11, the CMO already shown in FIG.
On both sides of the n-channel portion and the p-channel portion of the S semiconductor device, so-called well contacts are formed to sandwich the field oxide film and connect each well to the wiring layer (portion indicated by α in the figure). Also in this well contact portion, a low resistance connecting portion can be formed by the same method as the connecting portion between the source / drain portion and the wiring layer shown in the first embodiment.

For example, Ge is implanted into the surface layer portion of each well. After that, ion doping of impurities of the same conductivity type as that of each well is performed, and further annealing treatment is performed. Thus, the impurity diffusion layer 71 having a higher concentration than the surrounding well concentration is formed in the well surface layer. After that, the surface portion of the well is etched to expose a high Ge concentration region on the surface. The wiring layer is connected to the surface layer of high concentration Ge through the contact hole.

The well contact is formed in parallel with the source and drain portions of the first embodiment, and those which can be formed at the same time are formed at the same time. Therefore, the specific manufacturing conditions such as the ion implantation conditions, the impurity material, and the wiring material may be the same as those in the first embodiment.

Although the four embodiments have been described above, each wiring forming step may be combined with a flattening step such as Al reflow using a high temperature sputtering method or W film formation by a CVD method. The present invention is not limited to the above embodiment. For example, it will be apparent to those skilled in the art that various materials can be changed, improved, combined and the like.

[0064]

According to the present invention, the contact surface of the impurity diffusion layer in the Si substrate and the wiring layer has a high Ge / Si ratio, that is, Φ.
_Bn and Φ _Bp can be reduced. In addition, the contact surface can be concave so that the contact area can be effectively expanded. Due to these effects, the contact resistance between the impurity diffusion layer and the wiring layer can be reduced.

At the same time, the Ge ion-implanted layer can suppress channeling that occurs at the time of implanting impurity ions, and can make the depth of the impurity-diffused layer shallow.

[Brief description of drawings]

FIG. 1 is a sectional view showing a CMOS semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a CMOS semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of the CMOS semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of the CMOS semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of the CMOS semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a graph showing the concentration distribution of impurities in the impurity diffusion layer in the depth direction.

FIG. 7 is a graph showing the concentration distribution of Ge in the impurity diffusion layer in the depth direction.

FIG. 8 is a cross-sectional view showing a manufacturing process of a CMOS semiconductor device according to a second embodiment.

FIG. 9 is a sectional view showing a CMOS semiconductor device according to a second embodiment.

FIG. 10 is a sectional view showing a CMOS semiconductor device according to a third embodiment.

FIG. 11 is a sectional view showing a CMOS semiconductor device according to a fourth embodiment.

[Explanation of symbols]

1 ··· Si substrate, 2,2a ··· SiO ₂ film, 3 '-
..Ion-implanted layer, 3 ... P-type well, 4 ... Si
_Nx film pattern, 5 ... Resist mask, 6 ... Ion implantation layer, 7 ... Field oxide film, 8 ... Channel stop region, 9 ... Ion implantation layer, 11 ...
-Gate electrode, 12 ... Ion implantation layer, 13 ... Side spacer, 21 ... Ion implantation layer, 22 ... Ion implantation layer, 23 ... Diffusion layer, 24 ... Interlayer insulating film, 31 ... Barrier metal, 32 ... Al alloy, 3
3 ... passivation film, 41 ... n-type well,
51 ... Etching mask, 61 ... Ge film, 71
... Impurity diffusion layer, α ... Well contact.

Continued front page    F term (reference) 5F033 HH03 HH04 HH09 HH19 HH28                       HH33 JJ01 JJ03 JJ09 JJ19                       JJ28 JJ33 KK01 MM07 MM08                       MM13 NN06 NN07 NN13 PP06                       PP15 PP18 QQ07 QQ08 QQ09                       QQ10 QQ11 QQ13 QQ16 QQ18                       QQ19 QQ37 QQ58 QQ61 QQ65                       QQ73 QQ75 QQ82 RR04 RR06                       RR14 RR15 SS04 SS08 SS11                       SS12 SS15 TT02 TT08 XX01                       XX03 XX09                 5F048 AA01 AC03 BA14 BB05 BB08                       BC01 BC06 BC15 BD04 BE03                       BF01 BF02 BF11 BF16 BG12                       BH07 DA25                 5F140 AA10 AA13 AA28 AB03 BA01                       BC06 BE07 BF04 BF11 BF18                       BG08 BG12 BG38 BG52 BG53                       BH07 BH08 BH13 BH15 BH19                       BH22 BH43 BJ04 BJ08 BJ10                       BJ11 BJ16 BJ18 BJ20 BK02                       BK13 BK14 BK21 BK22 BK23                       BK25 BK29 BK30 CB01 CB02                       CB08 CC01 CC05 CC07 CC08                       CC12 CC13

Claims (3)

[Claims] 1. A first impurity diffusion layer having a conductivity type opposite to the first conductivity type formed in a predetermined surface layer region of the crystal region having the first conductivity type of the Si substrate, and the crystal region of the first impurity diffusion layer. A second impurity diffusion layer having the same conductivity type as the first conductivity type formed in another predetermined surface layer region, and a first wiring layer formed so as to be connected to the first impurity diffusion layer. A second wiring layer formed so as to be connected to the second impurity diffusion layer, the first of the Si substrate being connected to the first and second wiring layers.
The surfaces of both the first and second impurity diffusion layers are etched, and Ge is added to the surface layer portions of the first and second impurity diffusion layers, and the Ge concentration distribution is almost the most on the surface. A semiconductor device that is high and decreases continuously in the depth direction. 2. The semiconductor device according to claim 1, wherein the surfaces of the first and second impurity diffusion layers to which the first and second wiring layers are connected are concavely etched. 3. The semiconductor according to claim 1, wherein the first layer of the first and second wiring layers on the side connected to the first and second impurity diffusion layers is a Ge single layer film. apparatus.